2007_Yue_Rodwell_CSIC_short_course

Yue & Rodwell, IEEE CSIC Short Course, Nov.
2006
IEEE CSIC Short Course, RF and High Speed CMOS, Nov. 12, 2006, San Antonio, Texas
mm-Wave IC Design:
The Transition from III-V
III V to CMOS Circuit
Techniques
Patrick Yue, Mark Rodwell, UCSB

Yue & Rodwell, IEEE CSIC Short Course, Nov. 2006
Outline
• Background
– Emerging mm-wave applications
– Open design issues for mm mm-Wave
Wave CMOS
• CMOS for mm-wave design
– Optimizing CMOS device performance – layout & bias
– On-chip
On chip inductors in CMOS
– Cell-based device modeling and design methodology
– State of the art CMOS mm-Wave design examples
• mm-Wave design techniques
– Device characterization issues
– Unconditionallyy stable,, g
gain-matched amplifier
p design
g pprocedure
– Tuned amplifier, power amplifier design examples
– On-chip transmission line design
• Summary
• References
Emerging mm-Wave Wireless Applications

(~10 dB/km at sea level)
• Unlicensed 60-GHz band for Gbit wireless link:

– Outdoor, point-to-point wireless link Questions:
– Wireless High-Definition Multimedia Interface (HDMI) C we leverage
Can l scaled
l d
CMOS to produce more
• Licensed point-to-point wireless link in E-band cost-effective products
(71-76, 81-86 GHz, and 92-95 GHz) and enable new markets?
• Vehicular radar at 76-77 GHz
• 94-GHz band for high-resolution imaging
Recent Evolution for CMOS RF
RF
Lower power, Front-end
cost and size
Baseband DSP
(D. Su, et al. ISSCC 2002.) (S. Mehta, et al. ISSCC 2005.)
0.25-μm CMOS • 0.18-μm CMOS
5-GHz RF transceiver • RF + baseband DSP
But difficult to migrate below 0.18μm even for RF SoC...
State of the Art mm-Wave IC: 330 GHz 16-Finger Power Amp
designs in progress: Michael
Mi h l JJones
device: 5 V, 650 GHz fmax InP DHBT
wiring: thin film microstrip with 2 um BCB
Challenges:
line losses are very high
lines > 60 Ω are not feasible → increases Q of output tuning
lines of required impedance are narrow → limits on DC current
small unmodeled parasitics will de-tune design

....must maintain microstrip environment to device vias
with negligible lengths of unmodeled random interconnects
Open Design Issues
• RF CMOS design are by and large lumped circuits

• mm-Wave
mm Wave design are traditionally distributed circuits
• How will mm-Wave CMOS be designed?
– Assuming that we will integrate an entire transceiver,
transceiver
should each block be impedance-matched?
– Do we need new design flow / methodology?
– Should all interconnect be modeled as T-line and be
impedance-controlled?
– Do
D we need
d a well-controlled
ll t ll d global
l b l ground
d (plane)?
( l )?
• How to optimize CMOS device performance?
CMOS Device Parameter Scaling Trend

Challenges for RF/mm-Wave in 0.13-μm CMOS and Beyond
• High mask cost ($0.5M – $1M)

– only makes sense if integration level increases,
e g RF + large DSP
e.g. DSP, or mm-wave
mm wave transceiver
• Lack of a streamline RF/mm-wave design flow
• Negative impact of technology scaling
– Device
• Process variations Strongly depend
• Model uncertainty on layout
l t
• Interconnect parasitic variations
– Circuit
• Low voltage headroom due to reduced Vdd
Î Develop a parasitic-aware design methodology

Î Explore low-voltage circuit techniques
High Frequency Figures of Merit
• Minimize Rg, Rs, and Rsub for better performance

• Layout and biasing are both critical
• Minimize Rg, Rs, and Rsub for better performance

• Layout and biasing are both critical
Complete Macro Model

• Core model (baseline BSIM model)
• Interconnect RC (3D EM field solver)
• Gate and substrate
s bstrate resistances (physical
(ph sical model)
Drain
Core
Rd
Model
Rsub1
Cgd_ext
Gate Rds Bulk
Rg Cds ext
Cgd_ext Rsub2
Rs
Source
Gate Resistance Components
Ref. 16
Gate Electrode Resistance
Ref. 16 & 18
Channel Conductance
Gch = Gst + Ged

L
∝
W
(ac effect – channel charge distribution modulated by gate voltage,

Ref. 16 derived based on diffusion current)
Layout Guideline for Gate Resistance

• M
Multi-finger
lti fi llayoutt in
i RF MOSFET iis common tto minimize
i i i R Rgate
t
(at the expense of more parasitic capacitance)
• Typical finger width for 0.25um device is about 5 um whereas in 0.13um CMOS
i 1.5
is 1 5 um
• Total gate width ranges from a few 10’s of micron for LNA, mixer & VCO
to a few millimeters for PA
• Reltd (poly resistance) scales with 1/n2
• External portion of Rgeltd (contact resistance) scale with 1/n
• Rch is
i independent
i d d t off n to
t th
the fi
firstt order
d
Substrate Resistance Model
Active Region STI

Region
(R. Chang, et al. TED 2004.)
• Active and STI regions have different sheet resistances

• Resistances in x and y directions modeled as parallel resistors
Analytical Model of Substrate Resistance
Ref. 17
Optimization of Substrate Resistance
Ref. 17
Interconnect RC Modeling Using 3D Field Solver
Source
Gate
Drain
Bottom view showing

Top view substrate taps
Width (μm) nf Cgs_wire (fF) Cgd_wire (fF) Cds_wire (fF)

2.0 4 2.42 1.61 1.41
• Wire capacitance
p per
p finger
g is extracted
RF Macro Model vs. Measurement (16 x 2μm/0.12 μ m)
Core Model Core Model

Macro Model 575 19 Macro Model
15
Measurement Measurement
hm]
m]
Rin [Ohm
S]
Gm [mS
550 18
Rout [Oh
10
525 17
Core Model
5
500 Macro Model 16
Measurement
0 475 15
5 6 7 8 9 10 0 2 4 6 8 10 0 2 4 6 8 10
Frequency [GHz] Frequency [GHz] Frequency [GHz]
Core Model Core Model

50 Macro
ac o Model
ode Macro
ac o Model
ode
40 15
Measurement Measurement
Cout [fF]
45
Cfb [fF]
Cin [fF]
35 10
40
Core Model
30 5
35 Macro Model
Measurement
30 25 0
0 2 4 6 8 10 0 2 4 6 8 10 0 2 4 6 8 10
Frequency [GHz] Frequency [GHz] Frequency [GHz]
Rg = 9.8 Ω, Rsub = 475 Ω, Cgs_ext= 4 fF, Cgd_ext= 2.9 fF, Cds_ext= 5.2 fF
Optimized Layout for fT, fmax and NF
• Parallel Rg improves fmax and NFmin

• Gate connected at both ends
• Source drain metals do not overlap
• Bulk contacts surround device
Optimal Finger Width for fT

(L.Tiemeijer, et al. IEDM 2004.) (E. Morifuji, et al. VLSI 1999.)
fT (GHz)
Finger width (μm)
• fT approaches
h vsatt / L deep
d iin Finger width È
velocity saturation
ÖNo. of fingers Ç
ÖCapacitance Ç
ÖfT È
Optimal Finger Width for fmax

(E Morifuji,
(E. M if ji et al.l VLSI 1999
1999.)) (L Ti
(L.Tiemeijer,
ij ett al.l IEDM 2004
2004.))
fmax (GHz)
fmaax (GHz)
Finger width (μm) Finger width (μm)
• Reducing Rg vs. increasing Cgg

• For 0.13-μm, optimal finger width is ~2 μm
• Optimal finger width decreases with device scaling
Optimal Finger Width for NF
Finger width (um) Finger width (um)
Noise due to Rg and Rsub can be minimized through layout

optimization
Ref. 11
Optimal Biasing for fT, fMAX and NFMIN
• Peak fT, fMAX and NFMIN characteristic current densities largely

unchanged across technology nodes and foundries
• NFMIN (0.15mA/µm)
(0 15mA/µm) and peak fMAX (0.2mA/µm)
(0 2mA/µm) are close Æ
LNAs simultaneously optimized for noise and high gain
• In CMOS PAs optimum current swing when biased at
0.3mA/µm
10%
degradation
in fMAX
Optimum
Current Swing
Bias
Source: Yao, RFIC 2006. - U. of Toronto

Frequency Response of On-Chip Inductor Q

First Patterned Ground Shield (PGS)
• Inserted between the

inductor and substrate
• PGS fingers
g connected in
a “star” shape
• Terminates
e ates tthee E field
ed
• No effect on the H field
• Improves
I isolation
i l ti
Self-Shielded Stacked Inductors for high SRF

• Self-shielded layout can effectively boost-strap
the overlap capacitance *
25 μm • 1-nH inductor can be achieved in 25x25 μm2
0 13 μm CMOS 8-metal
using M5 through M8 in a 0.13-μm 8 metal
process
* C.-C. Tang, JSSC, April 2002.
Top view 4 layer (M5-M8)

3 layer (M6-M8)
2 llayer (M7
(M7-M8)
M8)
Bottom view
Systematic mm-wave Design with P-Cells
• Stand-alone single device model is insufficient

• Interconnect model accuracy limited by digital RC extraction
• Test structure layout ≠ actual circuit layout
Design Flexibility Design Automation
Model Scalability Model Accuracy
Scalable
Sub--Circuit P
Sub P--Cells
Leverage the insight to device layout optimization

Exploit the modularity at the sub-circuit level
Sample P-Cell Layouts and Circuit Models
Diff Pair Cross-Coupled Cascode

Pair
D1 D2 D
D1&G2
G2
SS SS
G1
D2&G1 S
G1 G2 B
Sub-Circuit Cell Library for mm-wave Design
Inductor and transformer PCell

D
D
G2 G2
G1
G1
S
Two transistor sub

sub-circuit
circuit PCell
Tuned IF Amplifier 7 μm 7 μm 7 μm
2.71 μm 5 μm
Routing interconnect PCell
A unified design and modeling framework

Each sub-circuit
sub circuit P-Cell
P Cell has its scalable circuit model
mm-wave P-Cell Characterization Test Structures
• Measured S-parameters to validate macro models

• UMC 0.13-μm CMOS with 8 copper layers
Outline
• Background
– Emerging mm-wave applications
– Open design issues for mm mm-Wave
Wave CMOS
• CMOS for mm-wave design
– Optimizing CMOS device performance – layout & bias
– On-chip
On chip inductors in CMOS
– Cell-based device modeling and design methodology
– State of the art CMOS mm-Wave design examples
• mm-Wave design techniques
– Device characterization issues
– Unconditionallyy stable,, g
gain-matched amplifier
p design
g pprocedure
– Tuned amplifier, power amplifier design examples
– On-chip transmission line design
• Summary
• References
140-220 & 220-330 GHz On-Wafer Network Analysis
• HP8510C VNA,
Oleson Microwave Lab mm-wave
Extenders
• coplanar wafer probes made by:

GGB Industries, Cascade Microtech
•connection via short length of

waveguide
GGB Wafer
W f Probes
P b
330 GHz available with bias Tees
• Internal bias Tee’s in probes for biasing
active devices
•measurements to 100 GHz

can be in coax.
High Frequency Device Gain Measurements : Standard Pads
Measuring wideband transistors is very hard ! Much harder than measuring amplifiers.
amplifiers
Determining fmax in particular is extremely difficult on high-fmax or small devices
Standard "short pads"

must strip pad capacitance
must strip pad inductance--or ft will be too high !
cal can be bad due to substrate coupling
make pads small
small, and shield them from substrate
cal can be bad due to probe coupling
use small probe pitch, use well-shielded probes
35
35
30 U
30 h
21
25
25 Gains (dB)
MAG/MSG
dB)
20
20
Gains (d
15 2 15 A = 0.6 x 4.3 um
2
A = 0.6 x 4.3 um jbe
jbe
10 I = 20.6 mA, V = 1.53 V
10 I = 20.6 mA, V = 1.53 V c ce
c ce 2
2
J = 8.0 mA/um , V = 0.6 V J = 8.0 mA/um , V = 0.6 V
5 e cb 5 e cb
f = 450 GH
GHz, f = 490 GH
GHz f = 450 GHz,
GHz f = 490 GHz k
t max
t max
0 0
9 10 11 12
10
9
10
10
10
11
10
12 10 10 10 10
Frequency (Hz) Frequency (Hz)
High Frequency Measurements : On-Wafer LRL

Extended Reference planes CPW
transistors placed at center of long on-wafer line
LRL standards placed on wafer
large probe separation → probe coupling reduced
still should use the best-shielded probes available
Problem: substrate mode coupling

method will FAIL if lines couple to substrate modes
→ method works very poorly with CPW lines
need on wafer thin-film
thin film microstrip lines
Unilateral Power Gain

1) Cancel device feedback with external lossless feedback
→ Y12 = S12 = 0
2) Match input and output
Resulting power gain is Mason
Mason' s Unilateral Gain
Y21 − Y12
2
U=
4(G11G22 − G21G12 )
Monolithic amplifiers are not easily made unilateral

30
→ U mostly of historical relevance to IC design U
25
For simple BJT model, U rolls off at - 20 dB/decade
20
→ U useful for extrapolation to find f max
AG, dB
MSG/MA 15 Common emitter
Common base
In III - V FETs, U shows peak from Cds - Rs - Rd interaction
10
→ U hard to use for f max extrapolation
Common Collector
5
For bulk CMOS, Cds is sheilded by substrate 0

→ U should be OK for f max extrapolation 10 100 1000
Frequency, GHz
Design Tools: Power Gain Definitions

Transducer Gain Available Gain Insertion Gain
Zs=Zo
Zs ZL=Zo
Sij Zs Sij Sij
ZL ZL=Zout*
V
Vgen V
Vgen Vgen
GT = Pload / Pav , gen G A = Pav ,a / Pav , gen S21 = Pav ,a / Pav , gen
2
load power power available from amplifier power delivered to Z o load

= = =
power available from generator power available from generator power available from Z o generator
= general - case gain = gain with output matched = gain in a 50 Ohm enviroment
Operating Gain Maximum Available Gain After impedance-matching:

Sij,matched
Zs=Zo
Zs=Zin* Sij Zs=Zin* Sij ZL=Zo
match Sij,raw match
ZL=Zout*
ZL
Vgen Vgen
Vgen
GMax = Pav ,a / Pgen ,delivered
GP = Pload / Pgen ,delivered
power available from amplifier
load power = S21,matched
2
= Gmax,raw
= power delivered from generator h d
power delivered from generator
= gain with both ports matched S11,matched = S22,matched = 0
= gain with input matched
...MAG may not exist...
....but only if unconditionally stable...
Design Tools: Stability Factors, Stability Circles

S12 S21 S12 S21
Γin = S11 + ΓL Γout = S22 + ΓS
1 − S22 ΓL 1 − S11ΓS
S21 S21 Unconditionally stable
(stable with all (ΓL , ΓS ) if :
S11 S22 ΓL ΓS S11 S22
S12 S12 K = Rollet stability factor
1 − S11 − S22 + det 2 [S ]
2 2
= >1
Load Stability Circle Source Stability Circle 2 S21S12
and B = stability measure
= 1 − S11 − S22 − det 2 [S ] > 0
2 2
Values of ΓL which make Values of ΓS which make

Γin = 1 → beyond lies negative Rin Γout = 1 → beyond lies negative Rout
Negative port impedance→ negative-R oscillator

Tuning for highest gain→ infinite gain (oscillation)
Design Tools: Maximum Stable Gain

Maximum
i stable i = MSG
bl gain SG circles at 50 GHz
S21 Y21 Z
= = = 21
S12 Y12 Z12
17 Ω circle
stabilization
t bili ti
17 Ω
methods Sij Sij
~50 Ω
Sij Sij
75 Ω
~75
~5-10 Ω
MSG
results
MAG 50 GHz
Adding series/shunt resistance

excludes source or load
from unstable regions → stabilizes
Design Procedure: Simple Gain-Matched Amplifier

First:
stabilize at the design frequency
---device is potentially unstable

at 100 GHz design frequency
source stability circle: S_StabCircle1

~5 Ohm on input will
overstabilize the device
After stabilizing
(slightly over-stabilizing)

available g
gain operating
p gggain
Second:
Determine required interface impedances
The Ga & Gp circles define the

source & load impedances
which the transistor must see
...it is necessary to OVERSTABILIZE ΖS,opt ΖL,opt

th device
the d i tto move th the G
Ga & Gp
G circles
i l
towards the Smith chart center
Third:
Thi d ...added
dd d tto d
device,
i th
the amplifier
lifi iis nott yett
Design Input & Output Tuning Networks complete...
...to provide these impedances...

source & load stability circles & 10,20,...,100 GHz
Forth:
Add out-of-band stabilization
potentially unstable
below 75 GHz
with frequency-selective
series stabilization
...caused only slight mistuning

& slight gain drop @ 100 GHz
...and is unconditionally
stable
t bl above
b 10 GH
GHz
Design Procedure: Effect of Line Losses

Finally:
adjusting for line losses
high line skin effect losses → reduced gain
but line losses also increase stability factor
loss in gain are partly recovered

b reducing
by d i stabilization
t bili ti resistance
i t &
line losses
re-tuning the design
--no analytical procedure; just component tweaking
line losses have severe impact

...in
i VLSI wiring
i i environment
i t
...particularly at 50 + GHz
...particularly with high-power amplifiers
Tuned Amplifier Examples

20
3-stage cascode in 180 nm CMOS 15
10
5
0
-5
-10
-15
-20
30 35 40 45 50
III-V HBT small-signal amplifiers 6
4
S21, dB
2
-2
2
-4
140 150 160 170 180 190 200 210 220
Frequency, GHz
10
0
gain, dB
B
-10
-20
-30
140 150 160 170 180 190 200 210 220
Frequency (GHz)
Note: simple gain-tuned amplifiers → limited applications

Transmitters need power amplifiers: need output loadline-match, not gain-match
Receivers need low-noise amplifiers: need input noise-match, not gain-match
Power Amplifier Design (Cripps method)

100
For maximum saturated output power, P = (1 8)(V
max max − Vmin )I max
& maximum efficiency 80
Current, mA
device intrinsic output must see breakdown
60
optimum loadline set by: 200 mW
breakdown maximum current,
breakdown, current maximum power density.
density 40
20
100 mW
0
0 1 2 3 4 5 6 7 8
V or V (V)
ce ds
parasitic C's and R's represented

by external elements...
ammeter monitors intrinsic

junction current
without including
capacitive currents
...(Vcollector-V
Vemitter )
measures voltage
internal to series parasitic
resistances...
Power Amplifier Design (Cripps Method)
Design steps are

1) input stabilization (in-band)
2) output tuning for correct load-line
3) input tuning (match)
4) out-of-band stabilization
Example: 60 GHz, 30 mW PA, 130 nm BiCMOS

Design: Multi-Finger Power Amplifiers: Even-mode method
Even-mode equivalent circuit
-- Most
M multi-finger
l i fi amplifiers
lifi do
d not use Wilkinson
Wilki combiners:
bi lilines are too llong
Even-mode equivalent circuit maps combined design into single-device design
Final design tuning (E&M simulation) with full circuit model
This method explicitly models all feed parasitics in a large multi-finger transistor
MUCH more reliable than using single lumped model for multi-finger device
Design: Multi-Finger Amplifiers: spatial mode instabilities
If each transistor finger is individually stabilized, high-order modes are stable.

Amplifier layout usually does not allow sufficient space for this.
All spatial modes must then be stabilized.
Stabilization method: bridging resistors → parallel loading to higher-order modes

Select so that (ZS , ZL) presented to device lie in the stable regions
etc...
Design: Multi-Finger Amplifiers: Layout Examples
W-band InP HBT power amplifier - UCSB
mm-wave InP HBT power amplifier - Rockwell
mm-wave InP HBT power amplifier - Rockwell

Low-Noise Amplifier Design-- device model

B i model
Basic d l : Van
V der
d Ziel
Zi l SVV,Rg
G Rg Cgd gmVg’s’ Gds Sii,channel
SVV ,Rg = 4kTRg (V / Hz ) 2
SVV,Ri
SVV ,Ri = 4kTRi (V / Hz )
2
Ri
D
SVV ,Rs = 4kTRs (V / Hz )

2
Cgs Vg’s’
Cdb
S II ,channel = 4kTΓg m ( A2 / Hz )
Rs
⎧2/3 : long channel,
channel constant mobility
Γ=⎨
⎩ > 2/3 under high field SVV,Rs
Csb
Cross spectral - densities can be neglected S
(B Hughes,
(B. Hughes IEEE Trans MTT)
SVV,Rin
Rin
G Cgd gmxVg’s’ G
Simplified noise model dsx Sii,channel
D
SVV ,Rin = 4kTRin (V 2 / Hz
H )
S II ,channel = 4kTΓ ' g m Cgsx Vg’s’ Cdb
Γ' → Γ as g m Rs → 0
Γ' → 1 as g m Rs → ∞ Csb
S
Low-Noise Amplifier Design-- sketch of steps in Fmin calculation

Total inputp noise voltage
g & current spectal
p densities :
S En ( f ) = 4kTRin +
4kTΓ
gm
(
1 + (2πfC gs ) Rin2 (V 2 / Hz )
2
)
4kTΓ
S In ( f ) = (2πfCgs )2 ( A2 / Hz )
gm
4kTΓ
S En I n ( f ) =
gm
(1 + j 2πfC gs Rin )( j 2πfC gs ) (V × A / Hz )
*
Noise figure with a particular source impedance :

( )
Zs
S En + Z s S I n + 2 ⋅ Re
2
R Z s*S En I n
F = 1+ Vgen
4kT Re(Z s )
Minimum noise figure
Fmin = 1 +
1 ⎡
4kT ⎢⎣
( [
2 S En S I n − Im S En I n ]) 2
[
+ 2 Re S En I n ⎤
⎥⎦
]
[ ]⎞⎟ [ ]
2 Zopt
S En ⎛ Im S En I n Im S En I n Zs=Z
Zo
Z opt = Ropt + jX opt = −⎜ −j
S I n ⎜⎝ S I n ⎟
⎠ SIn noise
match
→ Fukui Expression (rough)

Vgen
⎛f ⎞
Fmin ~ 1 + 2 Γ( Rs + Rg + Ri ) g m ⋅ ⎜⎜ signall ⎟⎟
⎝ fτ ⎠
Rs + Rg + Ri ⎛ fτ ⎞ 1
Z opt ~ ⋅⎜ ⎟+
⎜ ⎟
Γg mx ⎝ f signal ⎠ j 2πf signal C gs
Low-Noise Amplifier Design
Design steps are Zs

Zs=Zo
1) output stabilization (in-band) noise
2) input tuning for Fmin match
3) output tuning (match)
4) out-of-band stabilization Vgen
Discrepancy in input noise-match & gain-match

can be reduced by adding source inductance (R. Van Tuyl)
Example: 60 GHz, LNA, 130 nm BiCMOS
gain & noise circles after input matching

note compromise between gain & noise tune
III-V MIMIC Interconnects -- Classic Substrate Microstrip

W
Zero ground Brass carrier and
assembly ground
IC with backside
ground plane & vias
Thick Substrate inductance interconnect
substrate
→ low skin loss in package
No ground plane
1 H breaks in IC
α skin ∝ IC vias
ε r1 / 2 H near-zero
eliminate
on-wafer
ground
ground-ground loops
inductance
kz
High via TM substrate
inductance mode coupling
12 pH for 100 μm substrate -- 7.5 Ω @ 100 GHz Strong coupling when substrate approaches ~λd / 4 thickness
lines must be ground vias must be

widely spaced widely spaced
Line spacings must be ~3*(substrate thickness) all factors require very thin substrates for >100 GHz ICs
→ lapping to ~50 μm substrate thickness typical for 100+ GHz
Coplanar Waveguide
No gground vias Hard to g
ground IC
No need (???) to to package
thin substrate +V +V +V
0V
Parasitic microstrip mode
ground plane breaks → loss of ground integrity III-V:

substrate mode coupling semi-insulating
substrate→ substrate
or substrate losses kz mode coupling
-V 0V +V Silicon
conducting substrate
→ substrate
conductivity losses
0V
Parasitic slot mode
Repairing ground plane with ground straps is effective only in simple ICs
In more complex CPW ICs, ground plane rapidly vanishes poor ground integrity
→ common-lead inductance → strong circuit-circuit coupling
loss of impedance control
ground bounce
coupling, EMI, oscillation

40 Gb/s differential TWA modulator driver 35 GHz master-slave latch in CPW 175 GHz tuned amplifier in CPW
note CPW lines, fragmented ground plane note fragmented ground plane note fragmented ground plane
III-V MIMIC Interconnects -- Thin-Film Microstrip
narrow line spacing → IC density
no substrate radiation, no substrate losses
fewer breaks in ground plane than CPW
... but ground breaks at device placements
InP mm-wave
mm wave PA
still have problem with package grounding (Rockwell)
...need to flip-chip bond W
ηo ⎛ H ⎞
thin dielectrics → narrow lines Zo ~ ⎜ ⎟
→ high line losses ε r1 / 2 ⎝ W + H ⎠ H
→ low current capability
→ no high-Zo lines
III-V MIMIC Interconnects -- Inverted Thin-Film Microstrip
Some substrate radiation / substrate losses
No breaks in ground plane
... no ground breaks at device placements
InP 150 GHz master-slave latch

still have problem with package grounding
...need to flip-chip bond
thin dielectrics → narrow lines

→ high line losses
InP 8 GHz clock rate delta-sigma ADC
If It Has Breaks, It Is Not A Ground Plane !
signal line
line 1
“ground” “ground”
signal line line 2
ground plane
common-lead inductance
coupling / EMI due to poor ground system integrity is common in high-frequency systems
whether on PC boards
...or on ICs.
No clean ground return ? → interconnects can't be modeled !
35 GHz static divider

interconnects have no clear local ground return
interconnect inductance is non-local
interconnect inductance has no compact model
8 GH
GHz clock-rate
l k t delta-sigma
d lt i ADC
thin-film microstrip wiring
every interconnect can be modeled as microstrip
some interconnects are terminated in their Zo
some interconnects are not terminated
...but ALL are precisely modeled
InP 8 GHz clock rate delta-sigma ADC

VLSI mm-Wave Interconnects with Ground Integrity
no substrate radiation, no substrate losses
negligible breaks in ground plane
negligible ground breaks @ device placements
still have problem with package grounding
...need to flip-chip bond
thin dielectrics → narrow lines

→ high line losses
Example: 150 GHz Master-Slave Latch

Device
D i TTechnology:
h l
500 nm InP HBT
Interconnects :
inverted thin-film microstrip
Design:
All lines modeled as microstrip lines
representative lines simulated in Agilent / Momentum
fit to simple lossy line model (loss, Zo, velocity)
20
er (dBm)
10
0
Minimum input powe
-10
-20
-30
-40
0 20 40 60 80 100 120 140 160
frequency (GHz)
Example: 20 GHz DDFS Design (Rockwell)

designs in progress: MJ Choe
design target:
20 GHz clock rate
circuit topology:
ECL
device technology:
350 GHz (500 nm) InP HBT (Rockwell)
Interconnect technology gy:
inverted thin-film microstrip throughout
→ all lines are controlled-impedance
shorter lines:
unterminated,, but modeled
longer lines:
modeled and
terminated
Summary
• At 90-nm or below, CMOS can be a cost-effective choice for

highly integrated mm-wave circuits
• Consideration for optimizing device layout and biasing are
very similar for mm-wave and RF
• Pre-characterized
e c a acte ed cecell-based
based mm-wave
a e des
design
g flow
o will be a
key enabler
References on other mm-Wave CMOS Efforts

• P
Prof.
f BB. B
Brodersen
d and
d Prof.
P f A.A Niknejad
Nik j d – “Design
“D i considerations
id ti for
f 60 GHz
GH
CMOS radios,”
IEEE Communications Magazine, Dec. 2004.
• Prof
Prof. A.
A Hajimiri – “A
A fully integrated 24-GHz phased-array transmitter in
CMOS,” IEEE JSSC, Dec. 2005.
• Prof. B. Razavi – “A 60-GHz CMOS receiver front-end” IEEE JSSC, Jan. 2006.
• Prof. F. Chang – “A 60GHz CMOS VCO using on-chip resonator with embedded
artificial dielectric for size, loss, and noise reduction,” 2006 ISSCC.
• Prof. J. Laskar – “60-GHz direct-conversion gigabit modulator/demodulator on
li id
liquid-crystal
t l polymer,”
l ” IEEE TMTT,
TMTT Mar.
M 2006
2006.
In case
off questions
q ti

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Yue & Rodwell, IEEE CSIC Short Course, Nov.

Patrick Yue, Mark Rodwell, UCSB

Emerging mm-Wave Wireless Applications

• Unlicensed 60-GHz band for Gbit wireless link:

Recent Evolution for CMOS RF

small unmodeled parasitics will de-tune design

Open Design Issues

• RF CMOS design are by and large lumped circuits

CMOS Device Parameter Scaling Trend

Challenges for RF/mm-Wave in 0.13-μm CMOS and Beyond

• High mask cost ($0.5M – $1M)

Î Develop a parasitic-aware design methodology

High Frequency Figures of Merit

• Minimize Rg, Rs, and Rsub for better performance

• Minimize Rg, Rs, and Rsub for better performance

Complete Macro Model

Gate Resistance Components

Gate Electrode Resistance

Gch = Gst + Ged

(ac effect – channel charge distribution modulated by gate voltage,

Layout Guideline for Gate Resistance

Substrate Resistance Model

Active Region STI

• Active and STI regions have different sheet resistances

Analytical Model of Substrate Resistance

Optimization of Substrate Resistance

Interconnect RC Modeling Using 3D Field Solver

Bottom view showing

Width (μm) nf Cgs_wire (fF) Cgd_wire (fF) Cds_wire (fF)

RF Macro Model vs. Measurement (16 x 2μm/0.12 μ m)

Core Model Core Model

Core Model Core Model

Optimized Layout for fT, fmax and NF

• Parallel Rg improves fmax and NFmin

Optimal Finger Width for fT

Optimal Finger Width for fmax

• Reducing Rg vs. increasing Cgg

Optimal Finger Width for NF

Finger width (um) Finger width (um)

 Noise due to Rg and Rsub can be minimized through layout

Optimal Biasing for fT, fMAX and NFMIN

• Peak fT, fMAX and NFMIN characteristic current densities largely

Source: Yao, RFIC 2006. - U. of Toronto

Frequency Response of On-Chip Inductor Q

First Patterned Ground Shield (PGS)

• Inserted between the

Self-Shielded Stacked Inductors for high SRF

* C.-C. Tang, JSSC, April 2002.

Top view 4 layer (M5-M8)

Systematic mm-wave Design with P-Cells

• Stand-alone single device model is insufficient

• Test structure layout ≠ actual circuit layout

Design Flexibility Design Automation

Model Scalability Model Accuracy

 Leverage the insight to device layout optimization

Sample P-Cell Layouts and Circuit Models

Diff Pair Cross-Coupled Cascode

Sub-Circuit Cell Library for mm-wave Design

Inductor and transformer PCell

Two transistor sub

Routing interconnect PCell

 A unified design and modeling framework

mm-wave P-Cell Characterization Test Structures

• Measured S-parameters to validate macro models

Noise due to Rg and Rsub can be minimized through layout

Leverage the insight to device layout optimization

A unified design and modeling framework