MB L3_2

MB L3 Training Materials
CMTR3-2
REV 1.0
ASUS Confidential
Overview
Chapter 1. MB Frame Structure……….……P5~P14
Chapter 2. Voltage..............................P15~P39
Chapter 3. Clock…..……………………….....P40~P51
Chapter 4. Power On Sequence.……..….P52~P60
Chapter 5. PS/2………………………………..P61~P74
Chapter 6. USB…………………………………P75~P87
Chapter 7. Com Port……………………….P88~P100
Chapter 8. Print Port……………………..P101~P121
Chapter 9. FDD………………………….....P122~P131
Chapter 10. IDE……………….…………...P132~P142
ASUS Confidential 2
Overview
Chapter 11. SATA…..….....................P143~P153
Chapter 12. RAID………………………….P154~P173
Chapter 13. AGP ………..………………..P174~P193
Chapter 14. Onboard VGA……………..P194~P202
Chapter 15. Audio…………………………P203~P219
Chapter 16. Game Port………………….P220~P231
Chapter 17. PCI…………………………….P232~P254
Chapter 18. PCI-E………………………….P255~P273
Chapter 19. LAN…………………………...P274~P298
Chapter 20. 1394………………………....P299~P322
ASUS Confidential 3
Overview
Chapter 21. Memory…..….................P323~P364
Chapter 22. Battery Circuit……………..P365~P373
Chapter 23. Hardware Monitor ……….P374~P391
Chapter 24. BIOS…………………………..P392~P405
Chapter 25. SMBUS……………………….P406~P424
Chapter 26. POST Code………………….P425~P464
ASUS Confidential 4
MB Frame Structure
ASUS Confidential
INTEL P4 Frame Structure (865 + ICH5)
Intel
IntelPentium
Pentium44
Northwood/Prescott
Northwood/Prescott
CPU
CPU
533/800 MB/s FSB
Intel
Intel 22channel
channel
AGP 4x / 8x 266/333/400 MHz DDR
DDRSDRAM
SDRAM
82865PE
82865PE 44xxDIMMs
DIMMs
(North
(NorthBridge)
Bridge) 128 bit
5 x PCI Slots
HubLink Bus
PCI BUS 266MB/s
33MHz 2 IDE Ports
(Ultra ATA 66/100)
Intel
IntelICH5R
ICH5R
Marvell 2 Serial ATA Ports
Marvell (South Bridge)
(South Bridge)
Gbit
Gbit
(10/100Mbit)
(10/100Mbit) Audio
AudioCodec
Codec USB USB USB USB
ADI
ADI
1980
1980 AC97 USB USB USB USB
VIA
VIA6307
6307 LPC BUS USB1.1/2.0 Port x8
(P1394) Winbond
(P1394) 4M
4M Winbond
83627HF
BIOS 83627HF
BIOS Supper
SupperI/O
I/O
FWH
FWH
Promise 1xParallel, Floppy
Promise
R20276 Support 2xSerial,
R20276
KB,MS,Game Port,
RAID0/RAID1 HW monitor
ASUS Confidential 6
VIA K7 Frame Structure (KT600+VT8237)
Athlon
AthlonXP/Thoroughbred/
XP/Thoroughbred/
Barton
BartonCPU
CPU
266 / 333/400 MHz

8X AGP
32-bit 200/ 266/333/400
66MHz KT600
KT600 64-bit DDR
DDRSDRAM
SDRAM
AGP Slot (3
(North
(NorthBridge)
Bridge) (3xxDIMMs)
DIMMs)
266MHz 8 bit
Vlink Bus
PCI PCI BUS

5*PCI Slots
33MHz
Codec
Codec
AD1980
AD1980 VT8237
VT8237
CNR (South
(SouthBridge)
Bridge)
AC' 97 USB USB USB USB
Realtek
Realtek USB USB USB USB
VIA
VIA6307
6307
(P1394) 10/100
10/100Mb
Mb USB1.1/2.0 Port x8
(P1394) MII
LPC Bus
BIOS
BIOS ITE
Flash ITE
8712 1xParallel,Floppy
Flash 8712
ROM
ROM Super
SuperI/O
I/O 2xSerial, KB,MS, SIR
Gameport
ASUS Confidential 7
SIS P4 Frame Structure (SiS648 +963)
Intel
Intel
Pentium-4
Pentium-4
FSB 400/533/667/800 Mb/s
Scalable bus
AGP 8x 533 MHz SiS DDR

DDRSDRAM
SiS648FX
648FX 266/333/400 MHz SDRAM
33xxDIMMs
slot (North DIMMs
(NorthBridge)
Bridge) 64 bit
5 x PCI Slots MuTIOL Bus

PCI BUS 1 GHz Data
33MHz
SATA/RAID
SATA/RAID
SiS
SiS SiS
SiS963L
963L USB USB USB
180 6 USB/
180 (South Bridge)
(South Bridge) USB 2.0
USB USB USB
Gbit
GbitLAN
LAN Realtek Ports
Wireless
Wireless Realtek
3COM/Marvell
3COM/Marvell PHY
Module
Module PHY 1394 1394
3C940-MV00
3C940-MV00 RTL8801B
(optional)
(optional) RTL8801B
(optional)
(optional) (optional)
LPC BUS (optional)
AC97 Super
SuperI/O
I/O
MII Winbond
Winbond ISA Bus
Realtek ADI W83697HF BIOS
BIOS
Realtek ADI W83697HF Flash
PHY
PHY Codec
Codec Flash
RTL8201BL AD1980 1xParallel, ROM
ROM
RTL8201BL AD1980 2xSerial, SIR
10/100M Lan 6ch Audio KB,MS,Game Port,
Floppy
ASUS Confidential 8
NVIDIA K7 Frame Structure (IGP +MCP2)
Athlon/Athlon
Athlon/AthlonXP
XP
CPU
CPU
8X AGP 266 MHz

32-bit S2K bus
AGP Slot/ 533MHz 333 MHz 184pin
184pinDIMM
DIMM
DVI/TV nForce
nForceCRUSH17
CRUSH17 (2x
(2xDIMMs)
DIMMs)
IGP
64/128 bit DDR
VGA port IGP 184pin
184pinDIMM
DIMM
(1
(1xxDIMMs)
DIMMs)
5 x PCI Slots
266 MHz
LDT Link
PCI BUS 133MHz
33MHz
6 USB
MCP-2/-2H
MCP-2/-2H USB USB Ports
1394a 480Mb/s USB USB USB USB
LAN
10/100 Mbit AC97 LPC Bus
PHY
MII interface 12MHz 33MHz
ALC 650 LPC BIOS
BIOS
6CH Codec LPC Flash
Flash
Super
SuperIO
IO ROM
ROM
1xParallel,
ACR Slot
2xSerial, CIR
KB,MS
ASUS Confidential 9
VIA K8 Frame Structure (K8T400+8237)
AMD
AMD
K8 - CrawHammer
K8 - CrawHammer DDR
DDRSDRAM
SDRAM
266/333 Mb/s 33xxDIMMs
CPU
CPU DIMMs
64 bit
800 Mb/s HyperTransport
AGP 8x VIA
VIA
533 Mb/s
slot K8T400M
K8T400M
(North
(NorthBridge)
Bridge)
533 Mb/s Via Link
5 x PCI Slots 2 SATA Ports
RAID
RAID
(RAID)
VIA
VIA
VT6410
VT6410
VT
VT8237
8237 USB USB USB USB
PCI BUS IEEE1394
IEEE1394 (South
VIA (SouthBridge)
Bridge) USB USB USB USB
33MHz VIAVT6307
VT6307
Wireless
Wireless Gbit
GbitLAN
LAN
AC97
Module
Module Codec
3COM/Marvell
3COM/Marvell Codec
3C940-MV00 ADI
ADI
3C940-MV00 LPC BUS AD1980
AD1980
Super
SuperI/OI/O BIOS
BIOS
ITE Flash
Flash 6ch Audio
10/100M ITE
10/100MPHY
PHY IT8705F
IT8705F
ISA Bus ROM
ROM
VIA
VIA 1xParallel,
VT6103
VT6103 2xSerial, KB,MS,
Game Port,Floppy
ASUS Confidential 10
Intel P5 Frame Structure (915 +ICH6)
Intel
IntelPentium
Pentium44
Socket
Socket775
775
Prescott/Tejas
Prescott/Tejas
CPU
CPU
533/800 MB/s FSB
Intel 22channel
channel
Intel DDR
DDRSDRAM
SDRAM
PCI-E X16 Slot 8 GB/s Grantsdale-P 333/400 MHz 44xxDIMMs
Grantsdale-P DIMMs
(North
(NorthBridge)
Bridge) 128 bit
PCI-E X16
Marvell
Marvell
88E8052(Gbit)
88E8052(Gbit)
DMI Bus
2GB/s
3 x PCI-E X1 Slots 500MB/s
PCI-E X1 1 IDE Ports
3 x PCI Slots Intel (Ultra ATA 66/100)
IntelICH6R
ICH6R
PCI BUS 33MHz (South
(SouthBridge)
Bridge)
4 Serial ATA Ports
Audio
AudioCodec
Codec USB USB USB USB
ITE
ITE8212
8212 Realtek azalia
RealtekALC861
ALC861 USB USB USB USB
LPC BUS
Winbond
Winbond USB1.1/2.0 Port x8
83627EHF
83627EHF
4M
4M Supper
BIOS SupperI/O
I/O
BIOS
FWH
FWH 1xParallel, Floppy
2xSerial,
KB,MS,Game Port,
HW monitor
NVIDIA K8 Frame Structure (CK804 Integrated)
AMD
AMD939
939 DDR ECC
Athlon
Athlon64FX/64
64FX/64
CPU
CPU 333/400 MHz
Hyper-Transport 800/1000 MHz

2 x PCI-E*1 Slots 2 IDE Ports
(Ultra ATA 66/100/133)
PCI-E*1 Slots
2 x PCI-E*16 Slots
SATA
nVIDIA
nVIDIA 4x Serial ATA Ports
RAID
RAID
3 x PCI Slots
PCI BUS PCI BUS Sil
Sil3114
3114
33 MHz CK804
CK804 33 MHz
4x Serial ATA 150 Ports
TI
TI1394a
1394a
TS43AB22A
TS43AB22A 10x USB1.1 / USB 2.0 Ports
Marvell
MarvellPCI
PCI
Gbit
GbitLAN
LAN
88E8001
88E8001 Gb MII
AC97
Marvell
MarvellPHY
PHY Audio Codec
Audio Codec
Gbit LPC BUS BIOS
GbitLAN
LAN Realtek
Realtek BIOS
Flash
88E1111 ALC FlashROM
ROM
88E1111 ALC850
850
FLOPPY ITE
ITE KB MS
IT8712F-A
IT8712F-AIXIX
3 * FAN (Speed Sense) Supper
SupperI/O
I/O Serial port
(Chassis/CPU/SPS)
3 * TEMPERATURE Parallel port

(CPU/MB/SPS)
INTEL P5 Frame Structure (955 + ICH7)
Intel
IntelLGA775
LGA775
Pentium
Pentium44
Prescott
Prescott/ /Cedar
CedarMill
Mill/ /Smithfield
Smithfield DDR2 x 2
3.8GHz+
3.8GHz+CPU
CPU
FSB 533/800/1066 MHz DDR2 533/667
Per dir Intel ECC
Intel82955X
82955X
4Gbytes/s MCH
PCI-EX x16 Slot MCH
Glenwood
Glenwood
8 ch ALC882 (North
(NorthBridge)
Bridge)
ALC882
Audio DDR2 x 2
DMI bus Per-dir
PCI-EX x16 Azalia 10Gb/s
slot 1x ATA100 port
PCI-EX x1 PCI-EX x4 ATA100
slot PCI-EX x1
Intel
Intel82801G
82801G SATA II 4x SATA300 ports
ICH7R
ICH7R
(South
(SouthBridge)
Bridge)
USB 8x USB2.0 ports
GBE
GBE
PCI Bus Marvell
Marvell
33MHz 88E8001
88E8001
3x PCI slot
LPC Bus
BIOS 1x Parallel
BIOS LPC
Flash
Flash LPCI/O
I/O 1x Floppy
ATA133 ROM
ROM Winbond
Winbond 1x Serial
IDE
IDE (FWH) W83627EHG
ITE8211 ATA133 (FWH) W83627EHG KB & MS
ITE8211
1x Game Ports
2x ATA133
port
Q & A (Repair Experience)
1. A8,K8 series (AMD 64bit) memory is

connect to CPU not connect to North Bridge.
2. P5 series (Intel 915,925,945…...) have
PCI-EX16 connect to North Bridge & PCI-EX1
connect to South Bridge.
Voltage
ASUS Confidential
Outline
Voltage Distribution –Intel 915 (925) series
Voltage Distribution –Intel P4 (Old models)
Voltage Distribution Detail Sample-P4S800D
Linear & Switch Regulator
Vcore Multi-Phase Architecture
Vcore Multi-Phase Controller Sample ADP3180
Vcore Problem Debug Procedure
Voltage Distribution Sample [Intel 915 (925)]
+12V_4P VCORE +12V
+12V_4P Switch CPU +5V HDD/ODD
+12V VTT_CPU
+12V
Power +5V +1. 5V +5V SATA
GMCH
Supply +3V Switch +3V-DUAL VTT_CPU +12V
+5VSB Lin. R. +3VSB Switch +2. 5V(1.8V)-DU +5V FLOPPY
-12V +1. 5V +3V
VTT_CPU
+3V-DUAL Lin. R. +2.5VDUAL (+2.5V) +3VSB SUPER IO
+3V ICH V-BAT
+3V Lin. R. VTT_DDR +5V
+3VSB +5V-DUAL PS2 KB/MS
+3V Lin. R. +2. 5V
V-BAT +12V
+5V(3V) Switch +1. 5V Lin. R. VTT_CPU +2. 5V(1.8V)-DU
DDR +5V SERIAL
+5V Switch (1.8VDU) Lin. R. (VTT_DDR) VTT_DDR
-12V
+3VSB +3V CLOCK
Lin. R. +2.5VSB +3VSB +5V PARALLEL
(+2.5VSB) LAN +12V
(+1.2VSB) +3V
Lin. R. +1.2VSB PCI-E +5V-DUAL USB PORT
+5VA +3VSB
AUDIO +12V +3V BIOS
+3V
+3V
+12V Lin. R. +5VA +5V PCI +12V FAN
+3V 1394 +3VSB
ASUS Confidential 17 -12V
Voltage Distribution Sample [Old P4 MB]
Voltage distribution sample-P4S800D
Q57
+3VSB +5VSB
HJ882P
ATXPWR1
D12 +12V
BATT PSON# +5V
SIS964
+3V
U15 -5V
Q49 Q42 U17

+3VSB +2.5VSB_LAN +1.5VSB_LAN
HM882 HM882 PCI GB
LAN
3C940
Q32 Q36 Q31

+3V +3V_DUAL
AP9918H AP9918H AP9918H
Q38
+3VSB +2.5V_DUAL
AP2301N
U7
Q7
+3V VTT_DDR
HJ882P
SIS655FX
GND
HM772
Q9
Q30 U7 Q33 U7
+3VSB +1.8VSB SIS655FX +3V +1.5V
MMB2222A AP9915H SIS655FX
SIS964 AGP
U15 U7
Q35
+3V +1.8V SIS655FX
AP9915H
SIS964 U15
SIS180 U23
Socket478
+12V_4P Vcore
ADP3180
CPU
3-phase
Switch
regulator U7
SIS655FX
Linear Regulator
INPUT OUTPUT
REF
• Advantages - +
• Simple
• Low Cost
• Issues
• Power Dissipation
Switching Regulator
VCC VCC
VIN VIN
UGATE UGATE
PHASE VOUT PHASE VOUT
PWM PWM
CONTROLLER CONTROLLER
LGATE
FB GND FB PGND
GND
STANDARD BUCK CONVERTER SYNCHRONOUS BUCK CONVERTER
Synchronous Buck Converter is More Efficient
Multiple Output Controller
VIN 1 VIN 1
Integrated linear and

VOUT 1 PMW1
PMW1
CONTROL
switching regulator
CONTROL
PMW2
CONTROL
VOUT 2 Up to 4 outputs regulated
from single IC
VIN 2 MULTI-
OUTPUT
CONTROLLER VIN 2 Support microprocessor
core and
LINEAR1
CONTROL
LINEAR1
CONTROL
motherboard peripherals
VOUT 3
VOUT 4
Vcore Architecture
+5V
0 (Low Level) ：0V
1 (High Level) ：5V 1K
10K
VID4
VID3
Vcore
Switching
CPU VID2
Regulator
VID1
VID0
Multi-Phase Operation
Channel 1
IL1
UGATE
Drive
IL1
LGATE
• Multiple Channels
IO
I L2 Converter
Channel 2 • Synchronous-Rectified
UGATE • Ripple Cancellation
Drive
IL2 • Low Ripple Voltage
LGATE I L3
• Small Inductors
Channel 3
UGATE Io
Drive
IL3
LGATE
Multi-Phase Solution
+12V
Modular Power Partition BOOT
Simplifies Component
VCC
z UGATE
Placement PWM
Drive
HIP6601
PHASE
z Regulates Channel Current LGATE
Controller IC
z Regulates Output +12V
Voltage
z Senses Current in Lower +5V
BOOT
+Vcore
MOSFET
VCC
UGATE
VFB VCC COMP
Ripple Frequency
PWM1 PHASE
VSEN
z PWM Drive
HIP6601
Multiplying Clock
PWM2
PGOOD LGATE
Main PWM3
z Controls 2, 3, or 4 Power Control
HIP6301
Channels VID ISEN1
Driver IC
ISEN2
+12V
ISEN3
z Drives Synchronous- FS
BOOT
Rectified Buck MOSFETs

GND
VCC
UGATE
z Adaptive Shoot-through VCC

PWM
Drive PHASE
Protection
HIP6601
LGATE
Controller IC
PGOOD VCC
VSEN
VSEN +
Integrated Soft-Start
UV POR
x 0.90 - OV
LATCH
S Tristate
No External Capacitor
+
• -
OVP
x 1.15
Power Good Monitor OSCILLATOR FS/EN
PWM
Protection SOFT
START
+
-
PWM
PWM1
• Current Limit VID COMP

+
PWM2
PWM
• Over-Voltage VID0
VID1
-
+
PWM3
VID2 D/A PWM
VID3 -
VID4
+
E/A +
PWM4
FB - PWM
-
CURRENT
CORRECTION
#PH CHANNEL
DETECTOR
ISEN
FB I_TOT
ISEN1
+ ISEN2
OC I_Trip ISEN3
-
ISEN4
GND
Building Block
+12V
VCC
BOOT
UGATE
Output filter and
PWM
Drive PHASE load
HIP6601
Compensation components
LGATE
+12V
+5V
+Vcore
BOOT
VFB VCC COMP VCC
UGATE
VSEN PWM1
Drive PHASE
PWM HIP6601
PWM2
PGOOD
LGATE
Main PWM3
Control
HIP6301
VID ISEN1
ISEN2
+12V
ISEN3
FS
GND BOOT
VCC
UGATE
VCC Drive PHASE

PWM HIP6601
PWM (Pulse-width LGATE
modulating) switching
and control
Protection Component
+12V
Components BOOT
VCC
responsible for over- UGATE
Drive PHASE
voltage protection PWM HIP6601

LGATE
+12V
+5V
+Vcore
BOOT
VFB VCC COMP VCC
UGATE
VSEN PWM1
Drive PHASE
PWM HIP6601
PWM2
PGOOD
LGATE
Main PWM3
Control
HIP6301
VID ISEN1
ISEN2
+12V
ISEN3
FS
GND BOOT Components

VCC
responsible for over-

UGATE
VCC Drive PHASE

PWM HIP6601
LGATE
current protection
Current Sense Resistor
+12V
BOOT
VCC
UGATE
• Current-sense resistors set the
Drive PHASE
PWM HIP6601
LGATE
over-current threshold
R DS,ON ⋅ IFL
+12V
R ISEN =
+5V
+Vcore
BOOT
------Formula (C)
−6
n ⋅ 50 × 10
VFB VCC COMP VCC
UGATE
VSEN PWM1
Drive PHASE
PWM HIP6601
PWM2
PGOOD
LGATE
Main PWM3
Control
HIP6301
VID ISEN1
ISEN2
ISEN3
+12V RISEN IO
FS n
GND BOOT
VCC
UGATE IO
RDS,ON
VCC
PWM
Drive
HIP6601
PHASE
n
LGATE
Vcore Control IC—ADP3180
Pin Description—ADP3180
Pin Description—ADP3180
ADP3180 Output Voltage V.S. VID code
Vcore Problem Debug Procedure (1)
If no Output
z Check if both 5V and 12V are OK
z Check POWER MOSFET (both UGATE/ LGATE) are
not short
z Check all VIDs of Power Regulator are not high
z Check EN/FS of Power Regulator is not zero Volt
Vcore Problem Debug Procedure (2)
If the output voltage wrong
z Check if VIDs of Power Regulator are wrong
setting
z Check if the feedback resistor divider is wrong
z Check if UGATE and LGATE of Power Regulator
with wrong voltage level
z Check if POWER MOSFET failure
Clock
ASUS Confidential
Outline
Diagram
Signal Description
Repair Flow Chart
Repair Technique
CLOCK Generator Distribution Diagram
CPUHCLK
CPUHCLK# CPU
66M_MCH
MCHHCLK
MCHHCLK# MCH
100M_CK_HL_NB
66M_AGP
AGP
PCLK_SIO
48M_SIO S I/O
PCLK_SLOT1
PCI 1
PCLK_AS007
CLK AS007S
PCI 2~5
PCLK_FWH
Generator 14M_ICH
FWH
48M_ICH
66M_ICH ICH5
100M_CK_HL_SB
PCLK_1394 TSB43AB22 24.576Mhz
(1394) Crystal
24.576Mhz
Realtek
PCLK_LAN BCM5702 25Mhz Crystal ALC650
(LAN)
Crystal (Audio)
PCLK_RAID PDC 20378 20Mhz

20Mhz
(RAID) Crystal
ASUS Confidential 42 Crystal
Clock Generator Distribution—P4S800D Sample-1
ICS952018AF
CPUCLK
44 CPU
43 CPUCLK# FSB
100/133/200MHz
40 NBHCLK
39 NBHCLK#
SIS655FX
Mutiol Bus
10 NBZCLK 133 MHz
31 NBAGPCLK
30 AGPCLK AGP AGP Bus

66 MHz
9 SBZCLK
47 SATACLKT SIS964 SATA controller
46 SATACLKC 100MHz
ICS952018AF
PCLKS964
PCI Bus
22 SIS964 33.3 MHz
PCLKS1~S6
16 PCI Raid SATA1_X1
17 PCLKSATA 25M
20 PCI1~5 SIS180 Crystal
21
15
WIFI
PCLKS1394 PCI 1394 1394_XIN 24.576M
VT6307 Crystal
PCLKASIC
14 AS007
PCLKSIOBO
12 LPC flash PCLKLAN PCI LAN 940_XIN 25M
3C940 Crystal
SIO
Deluxe feature
ICS952018AF
22
14.318MHz
14M964 MIICLKIN 25M
3 Crystal
SIS964
PH25M1 25M
Phy Crystal
24MHz
IO48M Deluxe feature
26 SIO
14.318MHz
14M1980
2 AD1980
Repair Flow Chart
START
Visual Inspection NG Change damaged CLK OK

check CLK Gen. and related small
components are ok Gen.& NG components
OK NG
Check CLK Vcc 3V & Fix any trace open and OK
NG
Measure CLK Gen. Voltage Input related trace change any NG RLC
component component
OK NG
Check X’TAL & OK
NG Change NG X’TAL or
Measure X’TAL 14.318Mhz is ok related two Capacitors
Capacitor
are ok
NG
OK
Trace the circuit, Fix any trace open and OK
NG
Check which CLK signal is wrong check related trace & change any NG RLC
resistor, capacitor component
OK NG
Change CLK Generator Finished

Repair Technique-Visual Inspection
Visual Inspection to check

Clock Generator and related
small components are not
damaged.
Repair Technique-Measure Vcc_CLK
Use Multi-Meter or Oscilloscope

to measure Clock voltage 3.3V is
ok.
Repair Technique-Measure CLK X’TAL
Use Oscilloscope to measure

Clock X’TAL 14.318Mhz is ok.
3-1
3-2
Repair Technique-Check Individual NG signal

every individual CLK signal.
If find error please trace the
circuit to find it’s connection.
If related RLC components

4 are ok but CLK still is NG
please try to change CLK
generator at last.
Power On Sequence
ASUS Confidential
Outline
General Power On Sequence
Power On Sequence with Reset (General)
Power On Sequence with Reset (W/ASUS ASIC)
Power On Sequence with Reset (P5GD1 Sample)
Power On Sequence with Reset (P4P800 Sample)
No Power Problem Debug Point
General Power On Sequence
ATX
TOP VIEW
+5 + 12 PWRBTN PANNEL
5VSB to 3VSB Cap./ 3VSB
+5 5VSB
Linear Reg. Res. 1/0
-5 PWOK 5VSB 1
GND GND 1
GND +5
GND GND
PG1 Power OK
0 Circuit
PSON + 5
GND GND
- 12V + 3V
+ 3V + 3V
PSON Pull low circuit

PSON PWRBTN
0 0
Power On Sequence with Reset (General)
+5 + 12
+5 5VSB CPU SOCKET
-5 PWOK
(2)
CPURST (5)
GND GND
PG1
GND + 5
IDERST
GND GND
Circuit IDE SLOT
PSON + 5 PGOOD (4)
(3) PCIRST
GND GND
PCI SLOT
- 12V + 3V North Bridge
+ 3V + 3V
Circuit
PSON
South Bridge
(1)
PANNEL
PWRBTN
Power On Sequence with Reset (W/ASUS ASIC)
+5 + 12
+5 5VSB
PG1
-5 PWOK
GND GND (2) CPU
GND + 5
GND GND CPURST (6)
PSON + 5
PGOOD (3)
GND GND
- 12V + 3V North Bridge
+ 3V + 3V
PSON
PCIRST (5)
(1)
PCIRST (4)
PWRBTN
IDE SLOT
PCI SLOT
South
Bridge
PANNEL RSTCON
Power On Sequence with Reset (P5GD1 Sample)
CPURST# PLTRST#
(10) (8)
GMCH
User press
Ctrl+Alt+Del PWROK Power
(7)
PSON
User press (6)
Power button PWRBTN#
Super IO IDE
PLTRST#_Buf_Out
(3)
(9)
PWRBTN#_SB
RSMRST# IO_PWRBTN#
SLP_S3# SLP_S4# PWROK
(2) (4)
(5) (5) (7)
PCIRST#
User press RSTCON#_SB
(8)
Reset button ICH6 PCI
User Clear
CMOS RTCRST#
(1)
RSTCON#
CPUPWRGD
PLTRST#
CPU (8)
GB Lan PCI-EX16
1. When +5VSB is good, SIO send out RSMRST#. FWH PLTRST#_Buf_Out
(9)
2. When RSTCON#_SIO is sent, SIO send
PWRGD/PWROK to notice SB.
1394 PCI-EX1
3. When SLP_S3# is sent by SB, SIO will drive PSON#
High, then Power Supply will cut off main power.
ASUS Confidential RAID
57
Power On Sequence with Reset (P4P800 Sample)
RST#_NB RST#_AGP
GMCH
Power Supply
PWROK RST#CPU AGP
PSON CPU
PWROK_CPU
SIO
PWROK Wireless
PWRBTN#
RST#_PCI_
SLOT
Power PWRBTN#
Button _SB RST#
ICH5
RESET
PSTCON
Button
AC97_RST
RST_RTC_SB#
Battery
RST#IDE
AC97 FWH AS007 LAN SIO 1394 RAID
Resum RST_RSM_SB# IDE
Reset PDRVRST#
SDRVRST#
IDE
ASUS Confidential 58 RAID

No Power Problem Debug Point
POWER UP PROBLEM
1. Check if any burned components or traces

2. Check no voltages short with GND such as +5,
+12 , +5VSB, +3, -12, +3VSB, VCORE 1.5V, 2.5V
3. Check Battery voltage
4. Check X’tal 32.768 KHz
5. Check 5VSB ,3VSB, PWRBTN#
6. Check PSON signal & related circuit
PS/2
ASUS Confidential
Outline
Diagram
Signal Description
Repair Flow Chart
Repair Technique
PS/2 Diagram
Signal Description (PS/2 Mouse)
Pin Define Signal Description

1 Data Data signal
2 N/C Not connection
3 GND Ground signal
4 VCC Power signal (+5VDC)
5 CLK Clock signal
Signal Description (PS/2 KB)

1 Data Data signal
3 GND Ground signal
4 VCC Power signal (+5VDC)
5 CLK Clock signal
Theorem (Receiving Data)
Next page describes the typical

sequence of events when the
system is receiving data from the
auxiliary device.
Receiving Data (Curve Description)
The following describes the typical sequence of events when
the system is receiving data from the auxiliary device.
1. The auxiliary device checks the 'clock' line. If the line is

inactive, output from the device is not allowed.
2. The auxiliary device checks the 'data' line. If the line is
inactive, the controller receives data from the system.
3. The auxiliary device checks the 'clock' line during the
transmission at intervals not exceeding 100 microseconds. If
the device finds the system holding the 'clock' line inactive, the
transmission is terminated. The system can terminate
transmission anytime during the first 10 clock cycles.
4. A final check for terminated transmission is performed at
least 5 microseconds after the 10th clock.
5. The system can hold the 'clock' signal inactive to inhibit the
next transmission.
6. The system can set the 'data' line inactive if it has a byte to
transmit to the device. The 'data' line is set inactive when the
start bit (always 0) is placed on the 'data' line.
7. The system raises the 'clock' line to allow the next
transmission.
Theorem (Sending Data)
Next page describes the typical

sequence of events when the
system is receiving data from the
auxiliary device.
Sending Data (Curve Description)
The following describes the typical sequence of events when the system is
sending data from the auxiliary device.
1. The system checks for an auxiliary device transmission in process. If a

transmission is in process and beyond the 10th clock, the system must receive
the data.
2. The auxiliary device checks the 'clock' line. If the line is inactive, an I/O
operation is not allowed.
3. The auxiliary device checks the 'data' line. If the line is inactive, the system
has data to transmit. The 'data' line is set inactive when the start bit (always 0)
is placed on the 'data' line.
4. The auxiliary device sets the 'clock' line inactive. The system then places the
first bit on the 'data' line. Each time the auxiliary device sets the 'clock' line
inactive, the system places the next bit on the 'data' line until all bits are
transmitted.
5. The auxiliary device samples the 'data' line for each bit while the 'clock' line is
active. Data must be stable within 1 microsecond after the rising edge of the
'clock' line.
6. The auxiliary device checks for a positive-level stop bit after the 10th clock. If
the 'data' line is inactive, the auxiliary device continues to clock until the 'data'
line becomes active. Then it clocks the line-control bit and , at the next
opportunity, sends a Resend command to the system.
7. The auxiliary device pulls the 'data' line inactive, producing the line-control bit.
8. The system can pull the 'clock' line inactive, inhibiting the auxiliary device.
Repair Flow Chart
START
Visual Inspection NG Change NG PS2 Connector, OK

Check Connector. RLC components RLC components,
& PS2 Jumper and Mount PS2 Jumper
OK NG
NG Check PS2 Jumper is ok, Change NG PS2 Jumper,

Measure PS2 5V_Dual trace is not open, fix the open trace or
5V_Dual is correct inductor is ok. change NG inductor OK
OK NG
Measure the bias value of Change NG RLC

Measure PS2 CLK
CLK & DATA signals, trace components or fix any
& Data signal is OK
NG signal’s connection. pcb open OK
NG
Change Super I/O or SB
Finished
Visual Inspection check PS/2 connector

is no damaged or bent pin.
1-1
Check RLC components near PS/2

connector is no damaged.
1-2
Repair Technique-Check 5V_Dual
Use Multi-meter to check 5V_Dual for

PS/2 is OK, if NG check KBPWR
Jumper is mounted, then check
Inductor & Fuse are OK, PCB trace is
not open.
Repair Technique-Measure PS/2 CLK/DATA
Check K/B CLK, Data & Mouse

CLK, Data. Use multi-meter to
connect GND & check point, then
measure the bias voltage value. If
the value is low please check
capacitor and RLC component is no
short, if the value is high check
inductor. resistor & trace is no open.
3-1
If the problem is still existing please

change Super I/O or South Bridge
at last. Exchange I/O or SB depends
on PS/2 CLK, Data connect to
which component.
3-2
1. Some chipset PS/2 CLK & Data is just connect to
South Bridge not Super I/O like VIA 686A, 8237R or
SIS 630,730,960,961,962,963,964…
USB
ASUS Confidential
Outline
Diagram
Signal Description
Repair Flow Chart
Repair Technique
USB Diagram
Signal Description

1 VBUS Power signal
2 D- Data signal
3 D+ Data signal
4 GND Ground signal
Theorem
Power-on and Connection events timing
Curve Description
Δt1 : This is the amount of time required for the hub port power switch to operate. This
delay is a function of the type of hub port switch. Hubs report this time in the hub descriptor ,
which can be read via a request to the Hub Controller. If a device were plugged into a
nonswitched or already-switched on port, Δt1 is equal to zero.
Δt2 : (TSIGATT) This is the maximum time from when VBUS is up to valid level (4.01 V)
to when a device has to signal attach. Δt2 represents the time required for the device’s
internal power rail to stabilize and for D+ or D- to reach VIH (min) at the hub. Δt2 must be
less than 100 ms for all hub and device implementations. (This requirement only applies if
the device is drawing power from the bus.)
Δt3 : (TATTDB) This is a debounce interval with a minimum duration of 100 ms that is
provided by the USB System Software. It ensures that the electrical and mechanical
connection is stable before software attempts to reset the attached device. The interval starts
when the USB System Software is notified of a connection detection. The interval restarts if
there is a disconnect. The debounce interval ensures that power is stable at the device for at
least 100 ms before any requests will be sent to the device.
Curve Description
Δt4 : (T2SUSP) Anytime a device observes no bus activity, it must obey the rules of going
into suspend.
Δt5 : (TDRST) This is the period of time hubs drive reset to a device.
Δt6 : (TRSTRCY) The USB System Software guarantees a minimum of 10 ms for reset
recovery. Device response to any bus transactions addressed to the default device address
during the reset recovery time is undefined.
Repair Flow Chart
START
Visual Inspection
OK
Check Change Defect
Connector & Pins No Connector
Damaged.
NG
Check USB 5V Jumper, OK

Check USB 5V (SB) Change Defect
Related Trace, Fuse,
--VBUS(USB Vcc) Component
Inductor.
NG
Check 48 Mhz OK
Check USB 48Mhz at Change Defect
Related CLK Gen,
Clock Generator Component
Resistor, Trace
NG
Check USB-,USB+ OK
Check USB-, USB+ Change Defect
Related SB, Resistor,
Signals Component
Capacitor, Trace
Finished
Visual inspection check

USB connector appearance
and inside pins no damaged,
USB 5V(SB) jumper is
mounted.
Repair Technique-Check USB 5V_Dual
Use Multi-meter to check USB 5V Vcc

(5V_Dual) is correct.
Repair Technique-Check CLK_USB
Check USB CLK 48Mhz from

CLK Generator.
3-1
3-2
Repair Technique-Measure USB-,USB+
Use Multi-meter to measure USB-,

USB+ bias voltage value. The value
should be the same. If you find the
value is high, please check related
resistor or inductor is ok & trace is
not open. If the value is low please
check there’s no component short or
4-1 SB short.
If the problem is still existing after

you check above, please try to change
South Bridge.
4-2
Most of USB problems caused by USB 5V

Vbus (Vcc) is not correct. Sometimes we can
find inductor bad, trace burned or forgot to
mount USB jumper.
If You’ve checked USB 5V, 48Mhz, USB- &
USB+ signals but can’t find unusual root
cause, please try to change South Bridge.
COM Port
ASUS Confidential
Outline
Diagram
Signal Description
Repair Flow Chart
Repair Technique
COM1 Diagram
COM2 Diagram
Signal Description
9 Pins
Signal Description
1. Carrier Detect - Determines if the modem is connected to a
working phone line.
2. Receive Data - Computer receives information sent from the
modem.
3. Transmit Data - Computer sends information to the modem.
4. Data Terminal Ready - Computer tells the modem that it is
ready to talk.
5. Signal Ground - Pin is grounded.
6. Data Set Ready - Modem tells the computer that it is ready to
talk.
7. Request To Send - Computer asks the modem if it can send
information.
8. Clear To Send - Modem tells the computer that it can send
information.
9. Ring Indicator - Once a call has been placed, computer
acknowledges signal (sent from modem) that a ring is detected.
Theorem
Serial ports, also called communication (COM) ports, are bi-
directional. Bi-directional communication allows each device to
receive data as well as transmit it. Serial devices use different
pins to receive and transmit data -- using the same pins would
limit communication to half-duplex, meaning that information
could only travel in one direction at a time. Using different pins
allows for full-duplex communication, in which information can
travel in both directions at once.
Repair Flow Chart
START
Visual Inspection
Check Connector & NG Change NG connector Ok
& damaged RLC
RLC components
components
Ok
Enable Com port
NG Ok
Check Bios setting , setting in the Bios,
COM Port is enable make sure there is no
conflict.
Ok
Measure COM controller NG Check +5V, +12V,- Change NG R.L.C. Ok

NG
Power included+5V, +12V, 12V trace is not open, components. Fix any pcb
-12V is correct inductor is OK trace open
Ok Ok
Use meter to measure Check NG signal Change NG NG Change Ok

Signal’s bias voltage value NG connect to which array COM
is ok array capacitor capacitor controller
Ok
Finished
Visual Inspection check

COM connector and related
R.L.C. components. COM
controller (75232) & trace is
not damaged.
1-1
1-2
Repair Technique-Check Bios setting
Check COM port setting is

enable in the BIOS.
Repair Technique-Measure Voltage
Measure COM controller

(GD75232) voltages:
Pin 1: +12V
Pin 10: -12V
Pin 11: GND
Pin 20: +5V
Repair Technique-Measure COM signals
Use multi-meter to measure COM

port signal’s bias voltage value. If the
value is NG please trace it to connect
which array capacitor. If the value is
low please change related array
resistor, if high please check circuit is
no open.
4-1
If the problem is still existing

please change COM controller
(75232) or Super I/O.
4-2

Print Port
ASUS Confidential
Outline
Diagram
Signal Description
Repair Flow Chart
Repair Technique

Diagram

Signal Description
Pin Function Direction
1 Strobe I/O
2 Data Bit 0 I/O
3 Data Bit 1 I/O
4 Data Bit 2 I/O
5 Data Bit 3 I/O
6 Data Bit 4 I/O
7 Data Bit 5 I/O
8 Data Bit 6 I/O
9 Data Bit 7 I/O
10 Acknowledge IN
11 Busy IN
12 Paper End IN
13 Select IN
14 Autofeed OUT
15 Error IN
16 Init. Printer OUT
17 Select Input OUT
18 - 25 Signal Ground ---

Signal Description (SPP Mode)
Standard Parallel Port

Signal Description (EPP Mode)
Enhanced Parallel Port

Signal Description (ECP Mode)
Extended Capabilities Parallel Port

Data Write Cycle

Address Write Cycle

Data Read Cycle

Address Read Cycle

Data Cycle for ECP

Command Cycle for ECP

Data Cycle for ECP

Command Cycle for ECP

Repair Flow Chart
START
Visual Inspection
NG Change NG connector OK
Check Connector &
& damaged RLC
RLC components
components
OK NG
Check Bios setting , NG Enable LPT port & OK

LPT Port is enable change to “EPP”mode
to EPP mode in the Bios.
OK NG
NG Check inductor & Change NG inductor & OK

Measure LPT
power 5V is correct
fuse is ok, trace is not fuse. Fix any open trace.
open.
OK NG
Check NG signal
Use meter to measure NG Change NG NG OK
connect to which Change
Signal’s bias voltage value array capacitor
array capacitor & Super I/O
is ok & resistor
resistor
OK
Finished

RLC connector and RLC
component is no damaged
and trace is no open.
1-1
1-2

Check LPT port setting is

enable to “EPP mode” in the
BIOS.

Check LPT voltage (+5V) is

OK, if NG check related
components is ok & trace is no
open.

Repair Technique-Measure LPT signals
Use multi-meter to measure LPT

port signal’s bias voltage value. If
the value is NG please trace it to
connect which array capacitor &
resistor. If the value is low please
check related array capacitor, if
high please check resistor & circuit
4-1 is not open.

please change Super I/O (Some
models without I/O just connect to
South Bridge like “VIA 686A.”
4-2
1. Please make sure your LPT is enable to

“EPP mode” in the bios before testing.
2. Some models use VIA Southbridge need to
plug +12V /5V power to LPT tester.

FDD
ASUS Confidential
Outline
Diagram
Signal Description
Repair Flow Chart
Repair Technique

Diagram
1 3 5……………………… 33 GND
2 4 .……………………… 34 Pin8,26,28,30,34
…
+5V
Super I/O
Clock RN

Signal Description
Head-34
1 2 DENSEL 1:High Density (500Kbps, 1Mbps, 2Mbps)
3 4 0:Low Density (250Kbps, 300Kbps)
5 DRATE0 Additional FDC data rate signal
INDEX#
MOTOR0#
DRIVE1#
DRIVE0#
MOTOR1#
DIR
GND SETP# Step Motor control
WRITE DATA#
WRITE GATE#
TRACK0#
WRITE PROTECT#
READ DATA#
HEAD SELECT
33 34 DISK CHANGE#

Signal Description
DREQ2 HOLD
DACK2 DMA Controller
Super I/O HLDA
TC (SB)
STEP:Step output pulses.This active low open drain output produces a pulse to move the
head to another track.
WE#:Write Enable.
DIR#:Direction of the head step motor.An open drain output.
HEAD#:Head select.This open drain output determines which disk drive head is active.
WD#:Write data.This logic low open drain writes pre-compensation serial data to move the
head to another track.
DSKCHG#:Diskette change.
INDEX#:This Schmitt-triggered input from the disk drive is active low when the head is
positioned over the beginning of a track marked by an index hole.
DSA#:Drive select A.
DSB#:Drive select B.
RDATA#:The read data input signal from the FDD.
WP#:Write protected.

Repair Flow Chart
START
Visual Inspection to check NG Change NG connector,

OK
Connector is no damaged, re-solder NG soldering
Soldering is ok. point, test again
OK
Load set up default/ Load bios default OK

NG
check FDD item is enable /Enable FDD setting
in the bios in the bios, test again
OK NG
Use meter to measure NG If find improper signal, Try to find out if there
OK
signals bias voltage value trace the circuit is any trace open or
Compare with good MB connection to I/O. short, if not, change I/O
OK
Change Super
I/O, SC
ASUS Confidential Finished 127

Visual Inspection to check FDD

connector is no damaged,
soldering points are ok.
1-1
1-2
Load Bios setup default,

enable FDD setting to
1.44M, 3.5in in the Bios.

Repair Technique-Measure FDD signals
Use multi-meter to measure signals

bias voltage value, compare with good
MB.
If you find the value is improper, trace

the circuit connection to super I/O.
3 If there’s trace open or short, try to fix
it.
If you still can’t find any clue, try to

change I/O and South Bridge.

1. Before test FDD function, confirm your

FDD & FDD cable is ok.
2. Make sure you already put a good 1.44MB
disk (disable the write protection) into FDD.

IDE
ASUS Confidential
Outline
Diagram
Signal Description
Repair Flow Chart
Repair Technique

Diagram
Register
Network Super I/O
IDE Reset Circuit
Pin1 : Reset Signal

Signal Description
DD0-DD15 Data Bus bit 1-15
CSEL Cable Select Ground 40 39 DASP-
CS1- 38 37 CS0-
CS0-CS1- Chip Select 0-1 DA2 36 35 DA0
DA0-DA2 Device Address bit 0 -2 PDIAG 34 33 DA1
Reserved 32 31 INTRQ
DMARQ DMA Request 29 DMACK-
Ground 30
DMACK DMA Acknowledge CSEL 28 27 IORDY/DDMARDY/DSTROBE
Ground 26 25 DIOR/HDMARDY/HSTROBE
INTRQ Interrupt Request
Ground 24 23 DIOW- / STOP
DASP- Device Active/Slave Present Ground 22 21 DMARQ
PDIAG Passed Diagnostics KEY(Empty) 19 Ground
DD15 18 17 DD0
Reset Reset
DD14 16 15 DD1
DIOW- I/O Write DD13 14 13 DD2

STOP Stop during UDMA data bursts DD12 12 11 DD3
DD11 10 09 DD4
DIOR- I/O Read
DD10 08 07 DD5
HDMARDY- DMA Ready during UDMA data in burst
DD09 06 05 DD6
HSTROBE Data Strobe during UDMA data out burst
DD08 04 03 DD7
IORDY I/O Ready
DDMARDY- DMA Ready during UDMA data out burst Ground 02 01 Reset-
DSTROBE DMA Strobe during UDMA data in buurst

Theorem
tcycle
Ultra DMA Data In/Out

Ultra DMA Mode 5
1/30ns = 33MHz
30 ns 30 ns
Ultra ATA / 66
Strobe
DATA DATA DATA
1/20ns = 50MHz
20 ns 20 ns 20 ns
Ultra ATA / 100
Strobe
DATA DATA DATA DATA
2 Bytes 50MHz X 2Bytes= 100MB/sec

Repair Flow Chart
START
Visual Inspection to check NG Change NG connector, OK

Connector is no damaged, re-solder NG soldering
Soldering is ok. point, test again
OK NG
Load set up default NG Load setup default and

OK
in the bios/ update bios update to latest bios if
to latest version can’t detect new HDD.
NG
OK
Use meter to measure NG Trace NG signals, check Change NG

OK
signal’s bias voltage value, compare the trace & related resistor, fix any
with good MB. resistors are ok trace open or short.
NG NG
Change SB


IDE connector is no damaged,
soldering points are ok.
1-1
1-2
Repair Technique-Check Bios
Load Bios setup default,

update to the latest Bios
version before testing.

Repair Technique-Measure IDE signals
Use multi-meter to measure

signal’s bias voltage value.
Compare with good MB.
If the value is high please check
related trace is not open, related
resistor is ok & SB is not poor
soldering.
If the value is low check the trace
3 is not short, the resistor is ok &
SB is not short.
If above way is not the real root

cause please try to change SB.

Some MB used SIS 96X series South Bridge, if

forget to mount USB 5V Dual jumper or
jumper is NG will cause IDE2 not detected.

SATA
ASUS Confidential
Outline
Diagram
Signal Description
Repair Flow Chart
Repair Technique

Diagram
C C C C
Pin3 Pin5
Pin2 Pin6
Pin1
Pin4 Pin7

Signal Description
Pin1……………Pin4……………….Pin7
S1 Gnd
Signal Segment
S2 A+ Signal line(pair A)
S3 A- Signal line(pair A)
S4 Gnd
S5 B+ Signal line(pair B)
S6 B- Signal line(pair B)
S7 Gnd
TX/RX

OOB Signal
106.7 ns 106.7 ns
Connector
Serial ATA OOB
Controller
Connector
106.7 ns
320 ns
Device Connector
Serial ATA OOB
Controller
Device Connector

Repair Flow Chart
START
Visual Inspection to NG Change NG connector, OK

check SATA connector is
no damaged Test again
NG
OK
Check CLK CK_SATA_SB, NG If no CLK check CLK OK

CK_SATA_SB# from Generator & related
Clock generator trace. resistors.
NG
OK
Use meter to measure Trace to check related OK

NG
signal’s bias voltage value, compare R.L.C. components
with good MB. and circuit trace.
NG
OK
Change SB


SATA connector is not
damaged.

Repair Technique-Measure SATA CLK
Measure SATA CLK from

CLK Generator.
2-1
2-2
Repair Technique-Measure SATA signals
Use Multi-meter to measure SATA

signals (A+ & A- , B+ & B-)
Trace the circuit to SB if any signal
is error. If there is no trace short or
open please try to change SB.

Q & A ( Repair Experience)

RAID
ASUS Confidential
Outline
Diagram
Signal Description
Repair Flow Chart
Repair Technique

Raid Diagram
3V
IT7212F
PCI Bus
33.3Mhz

ITE 8212F Diagram

Pinout

Pin Description-1

Pin Description-2

Pin Description-3

Pin Description-4

Pin Description-5

Initial UDMA

Transfer to/from device

Initial UDMA data-out

Repair Flow Chart
START
Visual Inspection NG OK
Change any damaged
check Raid connector & controller are
Not damaged. connector or controller
OK NG
NG Enable Raid setting in OK

Check Bios setting
the Bios
OK NG
NG Check Raid 3V is ok if Fix any trace open or OK
Measure Raid Voltage
NG trace the circuit. RLC damaged
OK NG
NG Check Raid CLK Fix any trace or RLC

OK
Measure Raid Clock 33.3Mhz if NG trace damaged/ Change
the circuit. NG CLK Generator
OK NG
NG Measure AD signals Fix any trace/ remove OK
Measure PCI AD signals
compare with good MB any NG PCI device
OK NG
OK
Change Raid Chip
NG
Change SB Finished

Raid connector, chip and
related trace, component is
not damaged.

Check Raid setting is enable in

the Bios.

Repair Technique-Measure Raid Voltage
Use Multi-Meter to measure

Raid voltage.

Repair Technique-Measure Raid Clock

Raid clock (33.3Mhz).
4-1
4-2

Repair Technique-Measure other signals

Raid AD signals bias voltage
value.
Due to Raid AD signals are
connect to “PCI” AD signals, we
can also use PCI signal measure
card to measure AD signals will
5-1
be easier (Fig. 3-2).
If still cannot find any abnormal

please try to change Raid
controller and check other
device under PCI bus.
after change Raid controller
please change SB at last.
5-2


AGP
ASUS Confidential
Outline
Diagram
Signal Description
Repair Flow Chart
Repair Technique

AGP Diagram
HOST BUS
AGP 8X MCH
AGP BUS

AGP Clock
R
RAGP66M AGPCLK
B7
Clock
66MHz
Gen. C C
AGP Slot

Signal Description

Signal Description

Signal Description

Signal Description

Signal Description

Signal Description

Signal Description

Voltage and Clock
1.Check Voltage： 2.Check Clock：
Pin# Voltage Pin# Voltage Pin# Frequency
A1 +12V B24 3Vaux B7 66MHz
A9 VCC3.3V B25 VCC3.3V
A16 VCC3.3V B28 VCC3.3V
A25 VCC3.3V B34 Vddq1.5V
A28 VCC3.3V B40 Vddq1.5V
A34 Vddq1.5V B47 Vddq1.5V
A64 Vddq1.5V
B2 +5V
B3 +5V
B9 VCC3.3V A mean “Left”, B mean “Right”
B16 VCC3.3V

Resistor of AD Signal
Pin Name Pin# Pin Name Pin#
AD[00] A65 AD[16] A39
AD[01] B65 AD[17] B38
AD[02] A63 AD[18] A38
AD[03] B63 AD[19] B36
AD[04] A62 AD[20] A36
AD[05] B62 AD[21] B35
AD[06] A60 AD[22] A35
AD[07] B60 AD[23] B33
AD[08] B57 AD[24] A30
AD[09] A56 AD[25] B30 A mean “Left”,

B mean “Right”
AD[10] B56 AD[26] A29
AD[11] A54 AD[27] B29
AD[12] B54 AD[28] A27
AD[13] A53 AD[29] B27
AD[14] B53 AD[30] A26
AD[15] A51 AD[31] B26

Control Signal
1.Check Control Signal：
Pin Name Pin#
FRAME# A41
IRDY# B41
TRDY# A46
STOP# A47
DEVSEL# B46 A mean “Left”, B mean “Right”
RST# A7

Repair Flow Chart
START
NG Check AGP slot no pin Change NG AGP slot, fix

Visual Inspection
bent, pcb trace no burn any trace if burn out
OK NG OK
NG Check 1.5 V, 3.3V ,5 Trace error voltage to

Measure Voltage change any NG regulator.
V ,12 V is correct
OK NG OK
NG If no AGP CLK or Trace error CLK to

Measure AGP CLK-
error, trace the change NG CLK Gen. or
66Mhz
connection to CLK gen. resistor near the CLK.
OK NG OK
NG Check AD bias voltage Trace error signal to

Measure Address/Data
value & control signals find out any trace open,
Control signals
are ok fix it
OK
OK NG
Change NB Finished

Visual Inspection to check there

is no bent pin inside AGP slot.
Check the trace is not open
near AGP slot and back side.

Check AGP voltage is ok included

in 1.5V, 3.3V, 5V, 12V.
Pin# Voltage
A1 +12V
B2 +5V
A9 VCC3.3V
A34 Vddq1.5V

Repair Technique-Measure CLK
Use oscilloscope to check AGP

CLK 66Mhz is correct, if NG
trace the circuit to CLK
Generator.
3-1
Pin# Frequency
B7 66MHz
3-2

Repair Technique-Measure AGP signals
Use Multi-meter to check

address / data line (AD) &
control signals (refer to P13,14) ,
if find error please trace the
circuit to North Bridge.
If the trace is no open or short,

4 try to change North Bridge.

1. Some models 1.5Vddq error cause AGP no

display (like P4P800 series).
2. Sometimes if no 12V on AGP slot we’ll find
AGP fan is not rotating.
3. Some AGP no display problem caused by
NB poor soldering, we can try to press NB
and confirm again.

On Board VGA
ASUS Confidential
Outline
Diagram
Signal Description
Repair Flow Chart
Repair Technique

Clock Diagram
+1.8V
RED
+1.8V
GREEN
+1.8V
BLUE

Signal Description
1 ~ 5
116 ~ 15 10

Repair Flow Chart
Visual Inspection
NG Change NG component OK
START check VGA connector
no damaged
OK
Clear CMOS, NG Clear CMOS or change OK
Load Default/ Bios change bios to test again
OK
NG
Confirm the problem
RGB color error problem Is color error or No display /other problem
No display
Use multi-meter to measure Use multi-meter to measure

which color signal is error. onboard VGA CLK/DATA,
Trace the connection. HSYNC/ VSYNC signals.
Confirm the problem is Confirm the problem is

caused by RLC components Change NB caused by RLC components
Or NB Or NB
Change NG RLC Change NG RLC or

components.
Finished related 74XX logic IC


VGA connector is no pin bent,
the connector is no damaged.

Repair Technique-Load Default / Check Bios
If onboard VGA is no display, please

clear CMOS, load Bios default at
first. If no use, please try to change
Bios.

Repair Technique-Measure VGA signals
Check the problem belongs to (i) RGB
color error problem (ii) No display or
display error problem.
(i) RGB color error problem please use

multi-meter to measure which color
(R.G.B.) signal is error. Trace the
connection to confirm related
inductor or capacitor is ok. If it’s not
3-1
caused by R.L.C.Q. small components
please change NB.
(ii) No display or display error (not

included color error). Use the meter
to measure bias voltage value on VGA
CLK & DATA , VSYNC & HSYNC.
Trace the connection to confirm
related R.C.L.Q. and 74xx logic IC is
ok. If all check items are no problem
3-2 please change NB.

Audio
ASUS Confidential
Outline
Diagram
Signal Description
Repair Flow Chart
Repair Technique

Diagram
AC97 codec
5-pin serial data transaction :

BIT_CLK, SYNC, RESET,
SDATA_IN, SDATA_OUT

H/W Architecture (1)
AC-Link bus is the pathway that codec communicate with controller.

H/W Architecture (2)
Riser can support modem, LAN or DSL function.

AC-Link Bus
AC-link bus is a 5-wire digital serial interface.
The codec derives its clock internally from an externally
attached 24.576MHz crystal.
The codec drives the BIT_CLK with 12.288MHz (half of
24.576MHz).
The clock of SYNC signal, driven by the controller, is 48kHz
(BIT_CLK/256).
SDATA_IN and SDATA_OUT are used to transfer digital audio
data between controller and codec.
RESET# is an asynchronous master reset signal for codec driven
by controller (# means active if driving low).

AC-link Protocol
AC-link protocol is a bi-directional, fixed clock rate, and serial
digital stream.
The audio frames, which contain digital audio samples, are
transmitted on SDATA_OUT and SDATA_IN and synchronized
with SYNC signal.
Audio frames are divided into 12 slots with 20-bit sample
resolution.
DRA (double rate audio) : Optional 88.2 or 96kHz on L, C and R
channels.
VRA (variable rate audio) : FIFO on both sides of the AC-link
enables the support of variable rate audio.

AC-link Protocol
Data is transitioned on AC-link on every rising edge
of BIT_CLK and subsequently sampled on the
receiving side of AC-link on each immediately
following falling edge of BIT_CLK.

Package and Pinout
The standard industry package for AC’97 is 7mm x
7mm 48-pin LQFP.

The Difference between AC97 & HD AUDIO

Repair Flow Chart
START
Visual Inspection fix any trace or OK

check no phys. damaged damaged component
OK NG
Check Audio setting in the Enable Audio setting in Bios/ OK
Bios /check jumper Confirm jumper setting
OK NG
Check +5VA & +3V Fix or change any R.C. OK
Check Audio Voltage
are ok L.Q. related to Voltage
OK NG
Check Audio CLK Change any component OK
Check Audio Clock
24.576Mhz or 14.3M related to CLK
OK NG
Use meter to compare Change any component OK
Measure other Audio signals
other Audio signals related to NG signal
OK NG
OK
Change Audio chip
NG
ASUS ConfidentialChange SB 213Finished
Visual Inspection to check Audio

connector, Audio chip & nearby
related components are not damaged.

Repair Technique-Check Bios & Jumper setting
Check Audio setting is

enable in the Bios.
2-1
Make sure Audio Jumper

is mounted properly.
2-2
Repair Technique-Measure Audio Voltage
Use Multi-Meter to measure AUD

+5V & 3.3V.
P.S. Audio +5V is transferred by

small regulator like 78L05 (+12V to
3-1 AUD+5V)
3-2
Repair Technique-Measure Audio Clock

Audio CLK 24.576Mhz (from
X’TAL) or 14.318Mhz (from
CLK Generator)
4-1
4-2
Repair Technique-Measure Audio signals
Use Multi-Meter to measure other

Audio signals’ bias voltage value.
(This method should be compared
with good MB)
If the symptom is still existing
please try to change Audio chip.
After change Audio chip the
5 problem is still constant please try
to change SB at last.
P.S.
AC97 Audio chip through AC97
link connect to SB.
HA Audio chip through Azalia
link connect to SB.


Game Port
ASUS Confidential
Outline
Diagram
Signal Description
Repair Flow Chart
Repair Technique

Diagram
Super I/O
+5V
Pin 3,4,12,13

Pin Description
Pin # Signal Description

Pin8…………..……... Pin1 1 VCC +5 volts DC
2 B1A Button 1, joystick A
3 XA X axis resistance, joystick A
4 GND Ground
5 GND Ground
6 YA Y axis resistance, joystick A
7 B2A Button 2, joystick A
8 VCC +5 volts DC
Pin15…………….. Pin9 9 VCC +5 volts DC
10 B1B Button 1, joystick B
Pin2………………………….. Pin14 11 XB X axis resistance, joystick B

12* GND Ground
13 YB Y axis resistance, joystick B
14 B2B Button 2, joystick B
15* VCC +5 volts DC
* On sound cards with a combination

Pin1 Pin3………………………….. Pin15 joystick/MIDI connector, pin 12 is MIDI Out and
pin 15 is MIDI In.
Signal Description (Winbond W83627 series)

Power Pin (Winbond W83627 series)

Repair Flow Chart
START
Visual Inspection NG Change the OK

check Game connector is no connector if there is
Damaged. any damaged.
OK NG
NG Enable Game / MIDI OK

Check Bios Setting is ok
setting in the Bios.
OK NG
NG Check 5V related OK
Check Game +5Vcc is ok Inductor, Fuse is ok.
Change NG components.
OK NG
NG Trace NG signals OK
Use meter to measure
connection, fix any
Other Game signals
trace open or damaged.
OK NG
Change Super I/O

Finished
(Game/ MIDI controller)

Game port connector & small
components around the
connector.

Repair Technique-Check Bios Setting
Some models need to enable

Game /MIDI setting in the Bios
before testing.

Repair Technique-Measure Game +5Vcc

Game +5Vcc .

Repair Technique-Measure other Game signals

other Game signals. Compare
with good MB & trace the
connection to I/O (Game
controller).
If cannot find any abnormal
4 please try to change Super I/O
(Game controller).


PCI
ASUS Confidential
Outline
Diagram
Signal Description
Repair Flow Chart
Repair Technique

PCI System Block Diagram
RAID TV
1394
Card
PCI Local Bus #0
LAN SCSI PCI to PCI

Bridge
PCI Local Bus #1

PCI Diagram
PCI BUS
South
Bridge
Clock Signal
Clock
Gen.
PCI SLOT

PCI Diagram
RN
PCLK1 B76
PCLK2 B76
PCLK3 B76
Clock
Gen.
C C C
Clock Circuit PCI 1 PCI 2 PCI 3

Signal Description
AD[31:0] AD[63:32]
Address & Data C/BE[3:0] C/BE[7:4]#
PAR PAR64
FRAME# REQ63#
IRDY# ACK64#
Interface TRDY# LOCK#
Control STOP#
PCI INTA#
DEVSEL# INTB#
IDSEL
Compliant
INTC#
PERR# Device INTD#
Error Reporting
SERR# SBO#
REQ# SDONE
Arbitration
GNT# TDI
CLK# TDO
System
RST# TCK
TMS
ASUS Confidential 237 TRST#
(1)System Pins
CLK
All other PCI signals, except RST#, INTA#, INTB#, INTC#, and INTD#,
are sampled on the rising edge of CLK and all other timing parameters
are defined with respect to this edge.
RST#
Anytime RST# is asserted, all PCI output signals must be driven to their
benign state. RST# may be asynchronous to CLK when asserted or
deasserted.

(2) Address and Data Pins
AD[31::00]
A bus transaction consists of an address phase followed by one
or more data phases. PCI supports both read and write bursts.
C/BE[3::0]#
During the address phase of a transaction, C/BE[3::0]# define
the bus command. During the data phase, C/BE[3::0]# are used
as Byte Enables.

(3)Interface Control Pins
FRAME# (Cycle Frame)
Driven by the current master to indicate the beginning and duration of an access.
IRDY# (Initiator Ready)
Indicates the initiating agent’s (bus master’s) ability to complete the current data
phase of the transaction.
TRDY# (Target Ready)
Indicates the target agent’s (selected device’s) ability to complete the current data
phase of the transaction.
DEVSEL# (Device Select)
Indicates the driving device has decoded its address as the target of the current
access.
STOP#
Indicates the current target is requesting the master to stop the current transaction.
IDSEL (Initialization Device Select)
Chip select during configuration read and write transactions.

(4)Arbitration Pins
REQ#
Indicates to the arbiter that this agent desires use of the bus. This is a
point-to-point signal. Every master has its own REQ#.
GNT#
Indicates to the agent that access to the bus has been granted. This is
a point-to-point signal. Every master has its own GNT#.

(5)Interrupt Pins
Interrupts on PCI are optional and defined as

“level sensitive”, “active low”,using open drain
output drivers.
INTA# : Interrupt A is used to request an interrupt.
INTB~D# : Interrupt B~D are used to request an
interrupt and only has mean on a multi-function device.

Basic Arbitration
CLK
1 2 3 4 5 6 7 8 9
FRAME#
REQ#a
REQ#b
GNT#a
GNT#b
Address Data Address Data

Basic Read
CLK
1 2 3 4 5 6 7 8 9
FRAME#
AD Address Data-1 Data-2 Data -3
C/BE# Bus CMD
IRDY#
TRDY#
DEVSEL#
Address Data Data Data

phase phase phase phase
ASUS Confidential
Bus 244
Transaction
Basic Write
CLK
1 2 3 4 5 6 7 8 9
FRAME#
AD Address Data-1 Data-2 Data -3
C/BE# Bus CMD BE#-1 BE#-2 BE#-3
IRDY#
TRDY#
DEVSEL#
Address Data Data Data

phase phase phase phase
ASUS Confidential
Bus 245
Transaction
Voltage and Clock
1.Check Voltage： 2.Check Clock：
Pin# Voltage Pin# Voltage Pin# Frequency
A2 +12V B1 -12V B16 33MHz
A5 +5V B5 +5V
A8 +5V B6 +5V
A10 +5V(I/O) B19 +5V(I/O)
A16 +5V(I/O) B25 +3.3V
A21 +3.3V B31 +3.3V
A27 +3.3V B36 +3.3V
A33 +3.3V B41 +3.3V
A39 +3.3V B43 +3.3V
A45 +3.3V B54 +3.3V
A53 +3.3V B59 +5V(I/O)
A59 +5V(I/O) B61 +5V A mean “Left”, B mean “Right”
A61 +5V B62 +5V
A62 +5V

AD Signal
Pin Name Pin# Diode Mode Pin Name Pin# Diode Mode
Sample Sample
AD[00] A58 .317 AD[16] A32 .317
AD[01] B58 .319 AD[17] B32 .319
AD[02] A57 .321 AD[18] A31 .321
AD[03] B56 .318 AD[19] B30 .318
AD[04] A55 .319 AD[20] A29 .319
AD[05] B55 .321 AD[21] B29 .322
AD[06] A54 .319 AD[22] A28 .319
AD[07] B53 .317 AD[23] B27 .318
AD[08] B52 .319 AD[24] A25 .317
AD[09] A49 .321 AD[25] B24 .319
AD[10] B48 .317 AD[26] A23 .321
AD[11] A47 .319 AD[27] B23 .323
AD[12] B47 .321 AD[28] A22 .319
AD[13] A46 .323 AD[29] B21 .321
AD[14] B45 .318 AD[30] A20 .319
AD[15] A44 .317 AD[31] B20 .318

Control Signal
1.Check Control Signal：
Pin Name Pin#

FRAME# A34
IRDY# B35
TRDY# A36
STOP# A38
DEVSEL# B37
IDSEL A26
A mean “Left”, B mean “Right”

Repair Flow Chart
START
Change any damaged
check PCI pin is not bent or
PCI connector
damaged.
OK
NG Check PCI Voltage Fix any trace open or OK

Measure PCI Voltage
12V.-12V.5V.3V.3VSB RLC damaged
OK NG
NG Fix any trace or RLC

Check PCI CLK OK
Measure PCI Clock damaged, change NG
33Mhz
CLK Generator
OK NG
NG Check AD0~31, Fix any trace open or OK
compare with good MB RLC damaged
OK NG
NG Check RST#,FRAME#, Fix any trace open or OK
Measure PCI control signals
DEVSEL#,IRDY#..... RLC damaged
OK NG
Remove NG Device under
Finished
PCI /Change SB
Visual Inspection to check the

PCI connector is no pin bent or
broken.

Repair Technique-Measure PCI Voltage

PCI related voltages (+12V,
-12V,5V,3.3V)

Repair Technique-Measure PCI Clock

PCI Clock =33Mhz
3-1
3-2
Repair Technique- Measure PCI other signals
Use Multi-Meter to measure other

PCI signals:
AD0~AD31(refer to P16)& control
signals ( FRAME#, IRDY#,
TRDY#.......(refer to P17)
4
Compare with good MB. If find
error trace the connection to find
any trace open or short. If cannot
find the root cause please try to
remove other component under
PCI bus and change PCI
controller-SB.


PCI-E
ASUS Confidential
Outline
Diagram
Signal Description
Repair Flow Chart
Repair Technique

PCI-E X16 Diagram-1
B8,A9,A10 +3V
North B10 +3VSB

Bridge
B1,B2,B3,A2,A3 +12V
PCI-E *16 SLOT

PCI-E X16 Diagram-2
R
Clock+ A13
Clock- A14
Clock
Gen.
Clock Circuit PCI-E *16

PCI-E X1 Diagram
+12V (B1,B2,B3) +12V (A2,A3)
+3VSB (B10) +3V (A9,A10)
+3V (B8)
Clock (A13,A14)
South Bridge
PCIE*1

PCI-E X16 Pin Out & Description-1
PCI-Express 16x PinOut
Pin Side B Connector Side A Connector
# Name Description Name Description
1 +12v +12 volt power PRSNT#1 Hot plug presence detect
2 +12v +12 volt power +12v +12 volt power
3 RSVD Reserved +12v +12 volt power
4 GND Ground GND Ground
5 SMCLK SMBus clock JTAG2 TCK
6 SMDAT SMBus data JTAG3 TDI
7 GND Ground JTAG4 TDO
8 +3.3v +3.3 volt power JTAG5 TMS
9 JTAG1 +TRST# +3.3v +3.3 volt power
10 3.3Vaux 3.3v volt power +3.3v +3.3 volt power
11 WAKE# Link Reactivation PWRGD Power Good

Mechanical Key
12 RSVD Reserved GND Ground
13 GND Ground REFCLK+ Reference Clock
14 HSOp(0) Transmitter Lane 0, REFCLK- Differential pair
15 HSOn(0) Differential pair GND Ground
16 GND Ground HSIp(0) Receiver Lane 0,
17 PRSNT#2 Hotplug detect HSIn(0) Differential pair
19 HSOp(1) Transmitter Lane 1, RSVD Reserved
22 GND Ground HSIn(1) Differential pair
23 HSOp(2) Transmitter Lane 2, GND Ground

30 RSVD Reserved HSIn(3) Differential pair
31 PRSNT#2 Hot plug detect GND Ground
32 GND Ground RSVD Reserved


48 PRSNT#2 Hot plug detect HSIn(7) Differential pair


81 PRSNT#2 Hot plug present detect HSIn(15) Differential pair
82 RSVD#2 Hot Plug Detect GND Ground

PCI-E X1 Pin Out & Description
1 +12v +12 volt power PRSNT#1 Hot plug presence detect
2 +12v +12 volt power +12v +12 volt power
3 RSVD Reserved +12v +12 volt power
5 SMCLK SMBus clock JTAG2 TCK
6 SMDAT SMBus data JTAG3 TDI
7 GND Ground JTAG4 TDO
8 +3.3v +3.3 volt power JTAG5 TMS
9 JTAG1 +TRST# +3.3v +3.3 volt power
10 3.3Vaux 3.3v volt power +3.3v +3.3 volt power
11 WAKE# Link Reactivation PWRGD Power Good
Mechanical Key
12 RSVD Reserved GND Ground
13 GND Ground REFCLK+ Reference Clock
14 HSOp(0) REFCLK- Differential pair
Transmitter Lane 0,
17 PRSNT#2 Hotplug detect HSIn(0) Differential pair
ASUS Confidential 18 GND Ground 267 GND Ground

Repair Flow Chart
START
Change any damaged
check PCI-E pin is not bent or
in PCI-E connector
damaged.
OK
NG Check PCI Voltage Fix any trace open or OK

Measure PCI-E Voltage
12V.3V.3VSB RLC damaged
OK NG
NG Check PCI-E CLK Fix any trace or RLC OK

Measure PCI-E Clock damaged, change NG
100Mhz
CLK Generator
OK NG
NG OK
Check TX /RX signals, Fix any trace open or
Measure PCI-E TX /RX signals
compare with good MB RLC damaged
NG
OK
OK
Change NB(PCI-EX16) or
SB(PCI-EX1)
Finished
Visual Inspection to check PCI-

E connector is not damaged or
bent pin inside.
1-1
1-2

Repair Technique-Measure PCI-E Voltage

PCI-E working Voltages—12V,
3V, 3VSB.
2-1
P.S. We can use PCI-E X16

Signals Pin Out card to
measure.
P/N: 08-900036900
Name: ENG_PCI-E PIN
NAME R1.00
2-2
Repair Technique- Measure PCI-E Clock

PCI-E CLK =100Mhz
3-1
3-2

Repair Technique-Measure PCI-E TX/RX signals

PCI-E TX/RX signals,
compare with good MB.
If find error please trace the
circuit to check related trace &
RLC components.
4-1
If still can’t find any abnormal
please try to change NB (PCI-
E X16 controller) or SB (PCI-
E X1 controller).
4-2

LAN
ASUS Confidential
Outline
Diagram
Signal Description
Repair Flow Chart
Repair Technique

Diagram
(2.5VSB/
South Bridge 3VSB 1.2VSB)
Reset
Controller
IC
SMBus
3VSB
EEPROM

Lan Head Signal Description

Lan Chip Structure Diagram

Sample-Realtek 8100C Pin Assignment Diagram

Pin Description-1

Pin Description-2

Pin Description-3

Pin Description-4

Pin Description-5

EEPROM Pinout
AT24C08N

AT24C08N Operation-1
CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an
external device. Data on the SDA pin may change only during SCL low time
periods Data changes during SCL high periods will indicate a start or stop
condition as defined below.

START CONDITION: A high-to-low transition of SDA with SCL high is a start
condition which must precede any other command.
STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop
condition. After a read sequence, the stop command will place the EEPROM in
a standby power mode.

ACKNOWLEDGE: All addresses and data words are serially transmitted to and
from the EEPROM in 8-bit words. The EEPROM sends a zero to acknowledge
that it has received each word. This happens during the ninth clock cycle.
STANDBY MODE: The features a low-power standby mode which is enabled:
(a) upon power-up and (b) after the receipt of the STOP bit and the completion
of any internal operations.
MEMORY RESET: After an interruption in protocol, power loss or system reset,
any 2-wire part can be reset by following these steps:
1. Clock up to 9 cycles.
2. Look for SDA high in each cycle while SCL is high.
3. Create a start condition.

What is MAC Address?
Each device connected to a standard LAN needs a Data Link Layer

address (or called hardware address), providing a means of unique
identification.
Each NIC has its unique, hard-coded MAC (Media Access Control)
address. It is a 48 bits (6 bytes) address written in a hexadecimal
format. The first 3 bytes represents for vendor ID and the remaining 3
bytes are serial number.
MAC: 000C6E 7D3D0F

Vender ID Serial Number

What is IP Address?
z Internet Protocol Address
z IP address = Network and Host ID Number
– An IP address is a unique software, logical address
assigned to each machine on an IP network.
– It was designed to allow a host on one network to
communicate with a host on a different network,
regardless of the type of LANs the hosts are
participating in.
z Two major categories of IP address type : 192.168.0. 3

– Static (Fixed) IP and Dynamic IP
– Real IP and Private IP Network Host
Address Address
192.168.0. 2
Network Host
Address Address

Repair Flow Chart
START
Change damaged
check Lan connector & related components
are not damaged. connector / component
OK
NG Check Lan Voltage Change NG transistor (Q) OK
Measure Lan Voltage
3VSB, 2.5VSB, 1.2SB.... or fix any trace open
OK NG
NG Check Lan 25Mhz Change NG X’TAL /CLK OK
Measure Lan Clock
& PCI CLK 33Mhz Gen. Fix any trace open
OK NG
NG OK
Check AD0~31, Fix any trace / remove
Measure Lan AD signals
OK NG
NG Change NG OK
Measure Lan Transformer
Transformer
OK NG
OK
Change Lan Chip
NG
ASUS Confidential Change SB 291Finished
Repair Flow Chart (Lan Mac ID error)
START
No Yes
Mac ID error
Mac can be Check ?
NG Re-write Mac ID OK
Check Lan EEPROM 3VSB
Re-check Mac ID again
Check & fix any
3VSB trace open NG
OK
OK
NG OK
Change EEPROM /
Change EEPROM / Re-Write Mac again
NG Re-Write Mac again
NG
Go to check Lan
OK
(refer to previous Go to check Lan
page) (refer to previous page)
Finished
Visual Inspection to check Lan

connector & related components
are not damaged or burned.
1-1
1-2

Repair Technique-Measure Lan Voltage
Measure Lan working voltage

3VSB, 2.5VSB,1.2VSB…

Repair Technique-Measure Lan Clock
Use Oscilloscope to check Lan

X’TAL 25Mhz & 33.3Mhz
(synchronization with PCI) are
ok.
3-1
3-2

Repair Technique-Measure AD signals
Use Multi-Meter to measure Lan

AD signals bias voltage value.
Due to Lan AD signals are
be easier (Fig. 4).
4
If still cannot find any
abnormal please try to check
other device under PCI bus.

Repair Technique-Measure Transformer Signals

Transformer signals. Some
signals should be connected
together (Show as Fig.5-2, the
signals marked orange color)
If Transformer NG, please
change it .
5-1

please change Lan controller first.
If change Lan controller is NG
5-2

IEEE 1394
ASUS Confidential
Outline
Diagram
Signal Description
Repair Flow Chart
Repair Technique

IEEE 1394 Diagram
X’TAL24.576Mhz
South Bridge 3V
Controller 1394
IC Connector
33.3Mhz
SMBus
3V
EEPROM

IEEE1394 Introduction
A very fast external bus standard that
supports data transfer rates of up to
400Mbps (in 1394a) and 800Mbps (in 1394b).
also called FireWire (Apple), iLink (Sony)
A single 1394 port can be used to connect
up 63 external devices.
supports isochronous data -- delivering data at a
guaranteed rate. This makes it ideal for devices that
need to transfer high levels of data in real-time,
such as video devices.
What devices are using 1394 interface?
z digital cameras, camcorders, printers, TVs, network cards
and mass storage devices.
Comparison Table
Meaning Transfer rate Interface
IEEE1394 Apple: FireWire
Sony: iLink
100Mbps / 200Mbps /
400Mbps
USB Universal Serial Bus Low Speed Mode: 1.5Mbps

Full Speed Mode: 12Mbps
High Speed Mode: 480Mbps

1394a
It’s called FireWire in 1986 (by Apple computer)
It’s called I.Link in 1995 (by Sony)
Features: (IEEE 1394a)
z Scalable Performance (S100,S200,S400,etc.)
– S100=100Mbps; S200=200Mbps; S400=400Mbps

z Hot Plug
z Plug & Play
z Support for 63 Devices
z Peer-to-Peer Transfer
z Maximum Cable Length: 4.5m

1394a Connector
6 Pin
4 Pin

1394b
Features: (IEEE 1394b)

z Compatible with IEEE 1394a
z Scalable Performance
– 800Mbps
– 1.6Gbps
z Add a plug for 9 pin
z Cables Defined
– 9 pin to 9 pin
– 9 pin to 6 pin
– 9 pin to 4 pin
z Cable material
– POF (Plastic Optic Fiber) 塑膠光纖
– GOF (Glass Optical Fiber) 玻璃光纖
z Scalable Cable Length
– 4.5m
– 50m
– 100m
1394b Connector
9 Pin

1394 chip –TSB43AB22A Diagram

Pin Out

Pin Description-1

Pin Description-2

Pin Description-3

Pin Description-4

Pin Description-5

Pin Description-6

Repair Flow Chart
START
Change any damaged
check 1394 connector & controller are
not damaged. connector or controller
OK NG
NG Enable 1394 setting in OK

Check Bios setting
the Bios
OK NG
NG Check 1394 3V(5V) if Fix any trace open or OK
Measure 1394 Voltage
NG trace the circuit. RLC damaged
OK NG
NG Fix any trace or RLC OK

Check 1394 CLK
Measure 1394 Clock damaged/ Change
24.576&33.3Mhz
NG X’TAL/CLK Gen.
OK NG
NG Measure AD signals Fix any trace/ remove OK
OK NG
OK
Change 1394 Chip
NG
Change SB Finished
Visual Inspection to check 1394

connector, controller & related
small component is not damaged.

Check 1394 setting is enable

in the Bios.

Repair Technique-Measure 1394 Voltage

1394 working voltage 3V,5V
(depends on different chip)

Repair Technique-Measure 1394 Clock
Use Oscilloscope to check 1394

X’TAL 24.576Mhz & 33.3Mhz
(synchronization with PCI) are
ok.

Repair Technique-Measure AD signals

1394 AD signals bias voltage
value.
Due to 1394 AD signals are
be easier (Fig. 5).
5
If still cannot find any abnormal

please try to change 1394
controller and check other device
under PCI bus.
after change 1394 controller,


Memory
ASUS Confidential
Outline
Introduction
1.SDRAM
2.DDR
3.DDR II
Repair Flow Chart
Repair Technique

Introduction
What is memory anyway?
All computer functions have common features
z Data processing (CPU, GPU….)
z Data storage (CDR, HDD, Memory…)
z Data movement (FSB, PCI-E, USB….)
z Control (North Bridge, South Bridge…)
Why memory improve performance?
z CPU runs much more faster than HDD.
If all data & application were stored in HDD.
CPU will always wait for HDD to pass data.
z Bottle neck in HDD, CPU idle most of the time
z Memory enhance the usage of CPU.

Diagram
Memory Module (SDR)
North
Bridge
Type 1
Main Clock Gen.
Memory Module (DDR)
North
Bridge
Main Clock Gen. Type 2

DDR Clock Gen.
Memory Module (DDR, DDR2)

North
Bridge
Type 3
Main Clock Gen.
RAM Family
Static RAM (SRAM)
z Faster, more expensive
z Need not to be recharged regularly like DRAM
z Cache
Dynamic RAM (DRAM)
z Less expensive, need to be refreshed
z DRAM subtypes to be introduced
– Synchronous DRAM (SDRAM)
– Double Data Rate Synchronous DRAM (DDR)
– Double Data Rate 2 Synchronous DRAM (DDR2)
– Rambus DRAM(RDRAM)

DRAM Family

Performance release terms
Performance related terms

z Access Time (Nano seconds)
9 measuring from when the memory module receives a
data request to when that data becomes available.
9 lower numbers indicate faster speeds.
z CAS latency
9 the number of clock cycles it takes before a column can
be addressed on the DRAM chip.
9 Latency is a measure of delay
z Dual channel mode

please refer to the picture next page.

Other important terms
z MEMORY BANKS
Most computer systems have two or more memory
banks – usually called bank A, bank B
z Error Correction Code (ECC)
data integrity checking method used primarily in high-
end PCs and file servers.
z Serial Presence Detect (SPD)
store information about the memory module.

SDR
ASUS Confidential
SDRAM Basic
Short for Synchronous DRAM, a type of DRAM that can run at

much higher clock speeds than conventional memory. SDRAM
actually synchronizes itself with the CPU's bus and is capable of
running at 100/133 MHz

Clock cycle for SDRAM

SDRAM
CLK
Address RA CA
Control
Active
Signals# Active
RAS# Active
Low
Active
CAS# Low
DQ0-16 DQ0 DQ1 DQ2
READ command
SPD
SPD (Serial Presence Detection) :

- EEPROM.
- Store certain information of DIMM
module .
Serial EEPROM
Motherboard north-bridge chipset will 256 Bytes
read the content of SPD via the System
Management Bus, i.e. SM bus (I2C Bus),
and set proper timing for DIMM module.

SDR Pinout

Pin Description-1

Pin Description-2

DDR
ASUS Confidential
DDR Basic
Short for Double Data Rate-Synchronous

DRAM, a type of SDRAM that supports data
transfers on both edges of each clock cycle
(the rising and falling edges), effectively
doubling the memory chip's data throughput.
DDR-SDRAM also consumes less power,
which makes it well-suited to notebook
computers. DDR-SDRAM is also called SDRAM
II and DDRAM.

DDR Naming
Naming conventions and theoretical bandwidths of DDR SDRAM

SDRAM v.s. DDR
SDRAM:
Data transfer along the memory bus can be triggered on either the
rising edge or falling edge of the clock signal.
DDR SDRAM:
Both the rising and falling edges of the clock to trigger data transfer.
This technology, known as double transition clocking

Throughput
DDR 266 operating clock is 266MHz，if the data bus

width is 64bit，in other word it’s 8bytes，thus DDR
266 memory bandwidth is 266MHz x 8=2100MB/s，
i.e. PC 2100.
Clock Freq. Data Freq.

133MHz 266 MHz
Double Data Rate
X2
266 MHz
64 bit = 8bytes 266 x 8= 2100MB/s

Throughput
PC1600 (DDR200)
z 100(MHz)×2×8(Byte) = 1.6GB/S
PC2100 (DDR266)
z 133(MHz)×2×8(Byte) = 2.1GB/S
PC 2700 (DDR333)
z 166(MHz)x2x8(Byte) = 2.7GB/S
PC 3200 (DDR400)
z 200(MHz)x2x8(Byte) = 3.2GB/S
Data strobe signal

(Double Data Rate) 200 / 266 / 333 / 400 MHz
100 / 133 / 166 / 200MHz

DDR Pinout

Pin Description-1

Pin Description-2

DDR II
ASUS Confidential
DDR2 Basic
DDR2 SDRAM (Double Data Rate Two Synchronous

Dynamic Random Access Memory)
The advantage of DDR2 over DDR SDRAM is its
ability to run at much higher clock speeds due to an
improved electrical interface.
Like DDR, DDR2 will transfer data on every rising
and falling edge of the clock (double pumped),
achieving an effective rate of 200 MHz with the same
clock frequency

DDR2 Basic count.
DDR2 DIMM memory modules are not backward-compatible

with DDR DIMM , due to incompatible pin configurations, core
voltage, and memory chip technology.
DDR2 modules are designed with a different "key" in the edge
connector to prevent insertion into incompatible memory
sockets such as DDR motherboard. A DDR2 SDRAM DIMM will
not fit into a standard SDRAM DIMM socket or a DDR DIMM
socket.
DDR2 modules use a 1.8V power supply, providing a big power
saving over the 2.5V DDR modules.

DDR v.s. DDR II
DDR DDR II
Frequency Specs
200/266/333/400
Data Rate 400/533/(667) Mbps*
Mbps*
Bus Frequency 100/133/166/200 MHz 200/266/(333) MHz
DRAM Core Frequency 100/133/166/200 MHz 100/133/(166) MHz
Prefetch Size 2 bit 4 bit

Burst Length 2/4/8 4/8**
Differential Strobe: DQS,
Data Strobe Single DQS
/DQS***
CAS Latency 1.5, 2, 2.5 3+, 4, 5
Write Latency 1T Read Latency-1

DDR v.s. DDR II count.
Power Specs
Core Voltage (VDD) 2.5V++ 1.8V
I/O Voltage (VDDQ) SSTL_2 (2.5V) SSTL_1.8 (1.8V)
Format
Packaging TSOP (II), TBGA FBGA
Compatibility With DDR I
Command Set Same as DDR I
Basic Timing Parameters Same as DDR I
Bus Utilization and Signal Integrity
ODT
OCD-calibration
New Features
Posted CAS
Additive Latency+++

Dual Channel
The two channels handle memory-processing more

efficiently by utilizing the theoretical bandwidth of the
two modules, thus reducing system latencies, the
timing delays that inherently occur with one memory
module.
Rules to Enable Dual Channel Mode
Matched DIMM configuration in each channel

Same Density (128MB, 256MB, 512MB, etc.)
Same DRAM technology (128Mb, 256Mb, or 512Mb)
Same DRAM bus width (x8 or x16)
All either single-sided or dual-sided
DDR2 Pinout

DDR2 Pinout

Pin Description-1

Pin Description-2

Repair Flow Chart
START
Change any damaged
check memory slot is no bent pin
memory slot
or damaged.
NG
OK
Check memory Fix any voltage
NG OK
Measure memory Voltage Voltage 2.5V (1.8 or 3V) regulator or small
dual & Vtt inductor../trace open
OK NG
Fix any trace or RLC

NG Check memory CLK OK
Measure memory Clock damaged, change NG
100/133/166..Mhz CLK Generator
OK NG
Measure memory DQ / NG Compare with good Fix any trace open or OK

Address,RAS#,CAS#,WE# MB, trace NG signal resistor damaged
OK NG
Change NB
Finished
Visual Inspection to check memory

slot is not damaged or bent pin
inside.

Repair Technique-Measure Memory Voltage
Use Multi-Meter or Oscilloscope

to measure Memory Voltage.
2-1
Memory Voltage:
SDRAM: 3V Dual
DDR :2.5V Dual, 1.2Vtt_DDR
DDR2: 1.8 Dual, 0.8Vtt_DDR
2-2
Repair Technique-Measure Memory Clock

Memory Clock (100Mhz or
133Mhz, 166Mhz…depends on
different chipset & memory)
3-1
3-2
Repair Technique-Measure Memory Signals
Plug Memory measure card into slot.

Use Multi-Meter to measure memory
signals’ bias voltage value. Compare
with good MB if you find any
unusual.
4-1
1. ENG_RIMM R1.00 (SDRAM)

P/N: 08-900019700
2. ENG-DDR-DIMM184 TEST (DDR)
P/N: 08-900019900
3. ENG_DDR2 PIN NAME 1.01(DDR2)
4-2 P/N: 08-900037800

Repair Technique-DDR measure
*Special Hint when we measure DDR signals*
When we use DDR measure tool to

measure DDR signals, need to add an
extra voltage. We can use one 9V
battery across each probe (Red
connect +, Black connect--). The
reason is there are pull high array
resistors between North Bridge &
DDR slot. If without extra voltage is
not able to measure the signals from
slot to NB.

1.AMD A7 series with socket 462 are easy to

cause CID case. We can check the resistor ,
array resistor & trace between memory slot &
CPU socket if find MB hangs on memory
problem.

Battery Circuit
ASUS Confidential
Outline
Diagram
Signal Description
Repair Flow Chart
Repair Technique

Function of Battery
ACPI G3 State
• ATX unpluged
• Battery power only
• All power is shut off except for RTC
• No wake events are possible
Function of Battery Power are:
• CMOS SRAM
• Real Time Clock
• AC Power Loss Restart

BATTERY CIRCUIT Diagram
32.7 KHz
ASUS Super
ASIC I/O South Bridge
3VSB
Battery
+ VBATT
CLR *Current Leakage measure:

1kohm CMOS
Use multi-meter to measure the 1kohm,
the value between 1mV~10mV is ok, out
Of this range is NG.
According to Ohm theory: I=V/R, the
Current leakage should be 1uA~10uA.

Repair Flow Chart
START
Use Multi-meter to measure

Current Leakage value
Change Battery, ok
The value is out NG Check Battery ok
Measure the C.L.
of range Power is 3V
value is OK.
ok NG
Change diode,
Check Diode ok ok
Measure the C.L.
RB715 is OK
value is OK
NG
Change I/O, ASIC,
Check Vbatt related ok ok
Measure the C.L.
Components I/O,ASIC
value is OK
NG
Change SB
ok
Finished
Repair Technique- Measure Current Leakage
1. Use multi-meter to measure 1k

ohm near the battery circuit, the
value between 1mV~10mV is ok, out
Of this range is NG.
(According to Ohm theory: I=V/R,

the Current leakage should be
1uA~10uA.)
1

Repair Technique-Check Battery, Diode..
2. If the value is NG, check the

battery voltage is 3V. If not, change
battery and measure the leakage
current again.
3. If the value is still NG, check the

diode (RB715F) near battery is ok. If
NG, please try to change it and
measure again.
3
Repair Technique-Check Vbatt connection
4. If the value is still NG, check which

component use Vbatt. Most MB
Vbatt connect to SB, I/O and ASUS
ASIC. We can strip up the Vbatt pin
of I/O and ASIC to confirm which
component is NG.
5. If it’s not I/O or ASIC problem

finally please try to change SB.

1. Some MB small diode RB715 burn will

cause MB no power. (ex: A7V333)

Hardware Monitor
ASUS Confidential
Outline
Diagram
Signal Description
Repair Flow Chart
Repair Technique

Diagram

Clock Diagram (for super I/O)
Clock Signal R Clock Signal
??MHz C R
Clock Super I/O

Gen.
Clock Signal2 R
Clock Signa2l
??MHz C
Depends on difference chip

Signal Description

Theorem (Temp. Sense)
CPU Temperature
Super IO BIOS Menu
Super I/O
Motherboard Temperature
ASUS PC Probe
Diagram Sample ( Temp. Sense)

Repair Flow Chart (Temp. Sense)
START
Confirm CPU fan Change NG CPU fan

NG OK
Check real CPU/ MB temp. is ok attached on the CPU or any NG R.C.L.Q.
is good, rotation is ok. for fan power circuit
OK NG
NG Change Bios if Bios is OK

Check Bios is ok
NG
OK
Check VREF related Change any NG R.C.
NG OK
Check VREF is ok circuit, R.C. components
components are good
OK NG
Check Temp. sense
Check Temp. sense related NG Change any NG R.C. OK
related circuit, R.C.
circuit is ok components
components are good
OK NG
Change I/O (H.M.

Finished
controller)
Repair Technique (Temp. Sense)
1. Check real CPU or MB temperature is ok or

not, if ok change bios first; if NG check CPU
fan rotation and contact is good.
2. Check VREF (Reference Voltage). If NG check
VREF related resistor & capacitor(104P).
3. Check Temp. Sense signal (TR CPU or TR MB).
If NG check related resistor & capacitor.
4. If check above signals there’s nothing
abnormal, please try to change super I/O
(Hardware Monitor controller).

Theorem (Fan Sense)
Chassis FAN
Super IO BIOS Menu
Power FAN
Super I/O
CPU FAN
ASUS PC Probe
Diagram Sample (Fan Sense)

Repair Flow Chart (Fan Sense)
START
NG Check fan power 12V Change NG transistor OK

Check real fan rotation is ok
is ok for 12 V fan power
NG
OK
NG Change Bios if Bios OK

Check Bios is OK
cause Fan RPM error
NG
OK
NG Check Fan sense OK

Check Fan sense related Change any NG R.C.
circuit is ok related circuit, R.C.
components
components are good
OK NG
Change I/O (H.M.

controller)
Finished
Repair Technique (Fan Sense)
1. Check real fan rotation is ok or not, if NG

check fan 12V related circuit. Especially check
fan transistor which provides fan 12V.
2. Check Bios is ok or not.
3. Check Fan Sense signal (CPU Fan, Chassis Fan,
Power Fan). If NG check related resistor &
capacitor.
4. If check above signals there’s nothing
abnormal, please try to change super I/O
(Hardware Monitor controller).

Theorem (Voltage Sense)
Super IO BIOS Menu
Super I/O
Power Supply
5V、12V、3.3V ASUS PC Probe

Diagram Sample (Voltage Sense)

Repair Flow Chart (Voltage Sense)
START
Check Vcore circuit, Change NG power OK

Check real voltage is ok NG power supply and supply. Cable or Vcore
(Vcore,3, 5, 12 V)
power cable is ok. related NG component
OK NG
Change Bios if Bios OK
Check Bios is OK NG cause voltage detect
error
OK
NG Check VREF related Change any NG R.C.

OK
Check VREF is OK circuit, R.C. components
components are good
OK NG
NG Check Voltage sense Change any NG R.C.

Check Voltage sense related OK
circuit is ok related circuit, R.C. components cause
components are good voltage detect error
OK
NG
Change I/O (H.M.
Finished
controller)
Repair Technique (Voltage Sense)
1. Check real voltage (Vcore, 3.3V, 5V ,12V )is ok or not,
if ok change bios first; if NG check Vcore related
circuit or check power supply (power supply cable also
included) is good.
2. Check VREF (Reference Voltage). If NG check VREF
related resistor & capacitor(104P).
3. Check Voltage Sense signal (12Vin, 5Vin, 3Vin..).
If NG check related resistor & capacitor.
4. If check above signals there’s nothing abnormal,
please try to change super I/O (Hardware Monitor
controller).


BIOS
ASUS Confidential
Outline
Diagram
Signal Description
Repair Flow Chart
Repair Technique

Diagram
Pin1,25,27,32 :+3V
Pin31 : Clock
Pin2 : Reset
BIOS LPC Bus
SIO
SB

Signal Description-1



Reset Operation
1. If RST# is asserted when the WSM is not busy (RY/BY# = .1.), the reset will complete within
100ns.
2. A reset time, tPHAV, is required from the latter of RY/BY# or RST# going high until outputs are
valid.

Bios Pin Definition (Intel Sample)

Repair Flow Chart
START
Visual Inspection Check Bios no pin is Change NG Bios or

NG OK
check bios pin no damaged, damaged. Check the NG socket. Make sure
socket is ok sock connection is ok. the connection is ok
OK NG
Check Bios Voltage NG Check Bios voltage Trace 3.3V voltage, fix OK
is ok 3.3V related circuit. any trace open.
OK NG
NG Check Bios PCLK Change NG CLK Gen, OK

Check Bios CLK
33Mhz and related fix any trace open or
is ok
circuit. component damaged.
OK NG
Measure other control NG Trace NG signal’s Fix any trace open or OK

Signals & LPC AD signals
are ok connection component damaged.
NG
OK
Change I/O,ASIC (bios
Finished
controller) or SB.
Visual Inspection to check Bios

& the socket is not damaged.


Bios (PLCC) Voltage 3.3V .

Repair Technique-Measure Bios PCLK

Bios PCLK (33Mhz)
P.S. Not every model pin31

3-1 connect to PCLK, other
models use for FWE#.
3-2

Repair Technique-Measure other Bios signals

other Bios signals( DQ.A…)
compare with good MB.
If find error trace the connection

4 to I/O (Bios Controller), ASUS
ASIC or SB. Try to change NG
component.


SMBUS
ASUS Confidential
Outline
Diagram
Signal Description
Repair Flow Chart
Repair Technique

Clock Diagram
South
Bridge
SMBUS ( I2C )
CLK
Gen SPD SPEECH IC

Signal Description
System Management Bus

z Connect between IC (Integrated Circuit) chips
z Multiple chips can be connected to the

same bus and each one can act as
a master by initiating a data transfer
Two Wires communication
z Data line
z Clock line

Theorem
SM Bus
• SMBus topology
• SMBus V1.1 uses fixed voltage levels of 0.8 and 2.1 Volts to define
the logic “ZERO” and logic “ONE” on the bus respectively.

SM Bus
• Input and Output stage

I2C
• I2C topology

Data Transfer on SM Bus
• Byte format
• Acknowledge (ACK) and not acknowledge

Arbitration and clock generation
• Synchronization
A situation may occur that more than one master is trying to place
clock signals on the bus at the same time.

Bus Protocols
• Quick Command
• Send Byte
• Receive Byte
• Write Byte/Word
• Read Byte/Word
• Process Call
• Block Read
• Block Write

Bus Protocols
• Quick Command
0 : Write
1 : Read

Bus Protocols
• Send Byte
The least significant bit of command code would tell the device to turn
the feature on or off.

Bus Protocols
• Receive Byte

Bus Protocols
• Write Byte/Word

Bus Protocols
• Read Byte/Word

Repair Flow Chart
START
Visual Inspection NG Check SMBUS jumper setting OK

check SMBUS jumper is good.
mount is ok Change jumper if it’s oxidized
NG
OK
Check NG signal’s connection,

Use meter to measure NG
use elimination way to find out OK
the voltage of SMBUS CLK /Data,
Compare with good MB. which related component is
N.G. and change it.
OK
Finished


SMBUS jumper setting is ok.
1-1
1-2

Repair Technique-Measure SMBUS signals
Use Multi-meter to measure

SMBUS CLK & SMBUS DATA,
the voltage should be 3.3V.
If the value is error, try to trace the

connection and check one by one.
2 Most MB SMBUS signals connect

to CLK generator, Memory &
South Bridge.
If you have checked CLK

generator and other related
component but still NG. Please try
to change SB at last.


POST Code
ASUS Confidential
Overview
What is POST Code

Using POST Code to Debug
Appendix:
(1) Award Bios Code Definition
(2) AMI Bios Code Definition
(3) Phoenix Bios Code Definition

What is POST Code
POST : Power On Self Test
z The tag thrown out by BIOS
– Usually, BIOS would output some number
through 80ports. Using I/O access card (debug
card), user could read those number.
– The POST codes used by Award, Phoenix, and
AMI are different.
– These numbers mean something was executing
in the system.

What is POST Code
POST Code as BIOS executing process
z Standard POST Code
– These numbers were used as standard process.
z BIOS Debug Code
– These numbers depend on various project.

POST “00”, “FF”
POST Code “00”,”FF” or Debug card shows all dots(……) / all 00
(1)Check Voltage:
a)V_core,if no V_core check from power block circuit diagram
b)1.5v,if no 1.5v check from power block circuit diagram
c)2.5v,if no 2.5v check from power block circuit diagram
d)3.3v,if no 3.3v check from power block circuit diagram
e)check for N/B,S/B voltage is ok or not
(2)Check CLK:
a)CPU CLK,if no CPU CLK check from CLK gen. circuit diagram
b)N/B CLK,if no N/B CLK check from CLK gen. circuit diagram
c)S/B CLK,if no S/B CLK check from CLK gen. circuit diagram
d)14.318MHz,if no 14.318MHz check from CLK gen. circuit diagram
e)CLK generator.if all no CLK,change 14.318MHz,and then change
CLK gen. Before must check any open or short

(3)Check Power ok & Reset
a)H/W reset,if low voltage check circuit diagram, normal is capacitor bad
b)power supply power ok,if low voltage,normal is capacitor bad
c)CPU power ok,if low voltage check circuit diagram,and above signal
d)PCI reset,if low voltage check above signal and for S/B CLK,voltage
e)CPU reset,if low voltage check above signal and for N/B CLK,voltage
f)Check boot up sequence.
(4)Check control signal:

a)Check CPU control signal(ADS#,BRDY#…) is ok or not
b)Check PCI control signal(FRAME#,IRDY#,TRDY#…) is ok or not
c)Check others control signal is ok or not
(5)Check Jumper setting:

a)Check USB jumper setting is ok or not
b)Check JEN jumper setting is ok or not
C)Check all jumper setting is ok or not
00(no data)
(1)Change BIOS
(2)Check bios voltage
(3)Check BIOS CLK
(4)Check LAD0~3
(5)Check BIOS control signal
(6)Check CPU control signal
00(Have address & data)

(1)CPU ÅÆN/B:HD0~63,HA3~HA31,control signal open or short
(2)N/BÅÆS/B:PCI BUS(AD0~AD31,CBE0~CBE3) or HUB
Link(HL0~HL10) or V_link or LDT BUS open or short
(3)S/BÅÆBIOS:ISA BIOS(SA0~SA19,SD0~SD7) or LPC BUS
(LAD0~LAD3) open or short

POST “C0”, “D0”
C0 (Award)
D0 (AMI)
(1)Change BIOS
(2)Check HD0~63 signal open or short
(3)Check HA3~31 signal open or short
(4)Check AD0~31 signal open or short
(5)Check SM BUS is ok or not
(6)Check all Voltage is ok or not ,especially 2.5V,3V dual
(7)Check all CLK is ok or not
(8)Check jumper setting is ok or not
(9)Check SB, especially for Intel ICH4, 5

POST “C1”, “9F”, “D3”, “EF”….
C1, E1, 9F, 99, Ad (Award)
D3, D4, E0, E5, A4 (AMI)
EF, EE, 28 (Phoenix)
(1)Change BIOS
(2)Check Memory CLK is ok or not
(3)Check Memory voltage is ok or not, especially 2.5V, 3Vdual,
1.25Vtt
(4)Check SM BUS is ok or not
(5)Check MA,MD,CAS,RAS,CKE… signal is Open or Short
(6)DIMM socket not clean or bad
(7)Check HA,AD,CPU control signal is open or Short

POST “C3”, “C5”, “C7”, “05”
C3 (Award)
(1)Change BIOS
(2)Check memory problem
(3)Check frequency problem
C5 (Award)
(1)Change BIOS
(2)Check memory problem
(3)Check HA3~31 is open or short
(4)Change super I/O
C7 (AMI)
(1) Check K/B +5Vdual
05 (Award)
(1)Check super I/O CLK is ok or not
(2)Check super I/O voltage is ok or not
(3)Check super I/O address,data,control signal is open or short
(4)Change super I/O
POST “0B”, “13”, “20”
0B (Award)
(1)Change BIOS
(2)Check battery is ok or not
(3)Check all CLK signal(14.318MHz,25MHz,40MHz….)
(4)Check all voltage is ok or not
(5)Check INIT,TRDY#,RADY signal… is open or short
(6) Check C/BE0~3 is short or not
(7)Check all control signal(CPU,PCI,AGP) is open or short
13 (AMI)
(1) Check 1.5Vcc to NB ,especially Intel 865,875 series.
20 (AMI)
(1) Check 2.5V dual, 1.25Vtt
(2) Check Memory problems
(3) Check AGP signals

POST ”18”, “31”,”3D”,”41”
18 (Award)
(1)Check D/C# is Open or Short
(2)Check HITM# is Open or Short
(3)Check NMI# is Open or Short
(4)Check INTR,LOCK is open or short
(5)Check LINT0,1 is open or short
31,3D (Award)
(1)Check super I/O CLK is ok or not
(2)Check K/B problem
(3)Check CPU control signal(HITM#,ITIN,ITNK#…)is open or short
(4)Check N/B control signal… is open or short
41 (Award)
(1)Change BIOS
(2)Check SA0~SA16 is Open or short
(3)Check MEMR#,MEMW# is open or short
(4)Check HA3~31 is open or short
POST “4E”, “61”, “85”
4E (Award)
(1)Check TRDY#,DEVSEL# is open or short
(2)Check K/B problem
61 (Award)
(1)Check Cache problem
(2)Check CPU control signal is ok or not
(3)Check N/B control signal is ok or not
85 (AMI)
(1) Check Bios
(2) Check NB (No display problem)

AWARD Bios Code Definition-1
Post (HEX) Descriptions
1.Turn off OEM specific cache, shadow.....
2.Initialize all the standard devices with default values
Standard devices includes:
C0 • DMA controller (8237)
• Programmable Interrupt Controller (8259)
• Programmable Interval Timer (8254)
• RTC chip
C1 Auto detection of onboard DRAM & Cache
1.Test the first 256K DRAM
C3 2.Expand the compressed codes into temporary DRAM area including the compressed
system BIOS & Option ROMs
C5 Copy the BIOS from ROM into E000-FFFF shadow RAM so that POST will go faster
01-02 Reserved
03 Initialize EISA registers (EISA BIOS only)
04 Reserved
1.Keyboard Controller Self-Test
05
2.Enable Keyboard Interface
06 Reserved
07 Verifies CMOS's basic R/W functionality
BE Program defaults values into chipset according to the MODBINable Chipset Default Table

1.Program the configuration register of Cyrix CPU according to the
09 MODBINable Cyrix Register Table
2.OEM specific cache initialization
1.Initialize the first 32 interrupt vectors with corresponding interrupt handlers

Initialize INT No. from 33-120 with Dummy(Spurious) interrupt handler
0A
2.Issue CPUID instruction to identify CPU type
3.Early Power Management initialization (OEM specific)
1.Verify the RTC time is valid or not

2.Detect bad battery
3.Read CMOS data into BIOS stack area
0B 4.PnP initializations including (PnP BIOS only)
• Assign CSN to PnP ISA card
• Create resource map from ESCD
5.Assign IO & Memory for PCI devices (PCI BIOS only)
0C Initialization of the BIOS data area (40:0-40:FF)
1.Program some of the chipset's value according to setup.(Early setup value

program)
0D 2.Measure CPU speed for display & decide the system clock speed.
3.Video initialization including Monochrome, CGA, EGA/VGA.
If no display device found, the speaker will beep.

1.Initialize the APIC (Multi-Processor BIOS only)
2.Test video RAM (If Monochrome display device found)
3.Show message including:
0E • Award logo, Copyright string, BIOS date code & Part No.
• OEM specific sign on messages
• Energy Star logo (Green BIOS only)
• CPU brand, type & speed
0F DMA channel 0 test
10 DMA channel 1 test
11 DMA page registers test
12-13 Reserved
14 Test 8254 timer 0 counter 2
15 Test 8259 interrupt mask bits for channel 1
16 Test 8259 interrupt mask bits for channel 2
17 Reserved
19 Test 8259 functionality
1A-1D Reserved
1E If EISA NVM checksum is good, execute EISA initialization(EISA BIOS only)
1F-29 Reserved
30 Get base memory & extended memory size

1.Test base memory from 256K to 640K
31
2.Test extended memory from 1M to the top of memory
1.Display the Award Plug & Play BIOS extension message(PnP BIOS only)
32 2.Program all onboard super I/O chips(if any) including COM ports, LPT ports, FDD port... according to
setup value
33-3B Reserved
3C Set flag to allow users to enter CMOS setup utility
1.Initialise keyboard
3D
2.Install PS2 mouse
Try to turn on level 2 cache
3E Note: Some chipset may need to turn on the L2 cache in this stage. But usually, the cache is turn on later
in Post 61h
3F-40 Reserved
1.Program the rest of the chipset's value according to setup(Later setup value program)
BF 2.If auto configuration is enabled, programmed the chipset with pre-defined values in the MODBINable
Auto-Table
41 Initialize floppy disk drive controller
42 Initialize hard drive controller
43 If it is a PnP BIOS, initialize serial & parrallel ports
44 Reserved
45 Initialize math coprocessor

46-4D Reserved
If there is any error detected(such as video,KB....), show all the error messages on the screen &
4E
wait for user to press <F1> key
1.If password is needed, ask for password
4F
2.Clear the Energy Star logo (Green BIOS only)
50 Write all the CMOS values currently in the BIOS stack ares back into the CMOS
51 Reserved
1.Initialize all ISA ROMs

2.Later PCI initializations(PCI BIOS only)
• assign IRQ to PCI devices
• initialize all PCI ROMs
3.PnP initializations (PnP BIOS only)
assign IO, Memory, IRQ & DMA to PnP ISA devices
52
•
• initialize all PnP ISA ROMs

4.Program shadow RAM according to setup settings
5.Program parity according to setup setting
6.Power Management initialization
Enable/Disable global PM .
APM interface initializtion
1.If it is not a PnP BIOS, initialize serial & parallel ports

53
2.Initialize time value in BIOS data area by translate the RTC time value into a timer tick value
54-5F Reserved

60 Setup virus protection (Boot sector protection) functionality according to setup setting
1.Try to turn on level 2 cache

Note:If L2 cache is already turned on in post 3D, this part will be skipped
2.Set the boot up speed according to setup setting
61
3.Last chance for chipset initialization
4.Last chance for Power Management initialization (Green BIOS only)
5.Show the system configuration table
1.Setup daylight saving according to setup values

62
2.Program the NUM lock, typmatic rate & typmatic speed according to setup setting
1.If there is any changes in the hardware configuration, update the ESCD information (PnP BIOS
only)
63
2.Clear memory that have been used
3.Boot system via INT 19h
FF System booting. This means that the BIOS already pass the control right to the operating system

AMI Bios Definition-1
01 Processor register test about to start,
and NMI to be disabled.
02 NMI is Disabled.
Power on delay starting.
03 Power on delay complete.
Any initialization before keyboard BAT is in progress.
04 Any initialization before keyboard BAT is complete.
Reading keyboard SYS bit, to check soft reset/ power-on.
05 Soft reset/ power-on determined.
Going to enable ROM. i.e. disable shadow RAM/Cache if any.
06 ROM is enabled. Calculating ROM BIOS checksum, and
waiting
for KB controller input buffer to be free.
07 ROM BIOS checksum passed, KB controller I/B free.
Going to issue the BAT command to keyboard controller.
08 BAT command to keyboard controller is issued.
Going to verify the BAT command.
09 Keyboard controller BAT result verified.
Keyboard command byte to be written next.
0A Keyboard command byte code is issued.
Going to write command byte data.
0B Keyboard controller command byte is written.
Going to issue Pin-23,24 blocking/unblocking command.
0C Pin-23,24 of keyboard controller is blocked/ unblocked.
NOP command of keyboard controller to be issued next.
0D NOP command processing is done.
CMOS shutdown register test to be done next.
0E CMOS shutdown register R/W test passed.
Going to calculate CMOS checksum, and update DIAG byte.
0F CMOS checksum calculation is done, DIAG byte written.
CMOS init. to begin (If "INIT CMOS IN EVERY BOOT IS SET").
10 CMOS initialization done (if any).
CMOS status register about to init for Date and Time.
11 CMOS Status register initialized.
Going to disable DMA and Interrupt controllers.
12 DMA controller #1,#2, interrupt controller #1,#2
disabled.
About to disable Video display and init port-B.
13 Video display is disabled and port-B is initialized.
Chipset init/ auto memory detection about to begin.
14 Chipset initialization/ auto memory detection over.
8254 timer test about to start.
15 CH-2 timer test halfway.
8254 CH-2 timer test to be complete.
16 Ch-2 timer test over.
17 CH-1 timer test over.
18 CH-0 timer test over.
About to start memory refresh.

19 Memory Refresh started.
Memory Refresh test to be done next.
1A Memory Refresh line is toggling.
Going to check 15 micro second ON/OFF time.
1B Memory Refresh period 30 micro second test complete.
Base 64K memory test about to start.
20 Base 64k memory test started.
Address line test to be done next.
21 Address line test passed.
Going to do toggle parity.
22 Toggle parity over.
Going for sequential data R/W test.
23 Base 64k sequential data R/W test passed.
Any setup before Interrupt vector init about to start.
24 Setup required before vector initialization complete.
Interrupt vector initialization about to begin.
25 Interrupt vector initialization done.
Going to read I/O port of 8042 for turbo switch (if any).
26 I/O port of 8042 is read.
Going to initialize global data for turbo switch.
27 Global data initialization is over.
Any initialization after interrupt vector to be done next.
28 Initialization after interrupt vector is complete.
Going for monochrome mode setting.

29 Monochrome mode setting is done.
Going for Color mode setting.
2A Color mode setting is done.
About to go for toggle parity before optional rom test.
2B Toggle parity over. About to give control for any
setup required before optional video ROM check.
2C Processing before video ROM control is done.
About to look for optional video ROM and give control.
2D Optional video ROM control is done. About to give control
to do any processing after video ROM returns control.
2E Return from processing after the video ROM control.
If EGA/VGA not found then do display memory R/W test.
2F EGA/VGA not found.
Display memory R/W test about to begin.
30 Display memory R/W test passed.
About to look for the retrace checking.
31 Display memory R/W test or retrace checking failed.
About to do alternate Display memory R/W test.
32 Alternate Display memory R/W test passed.
About to look for the alternate display retrace checking.
33 Video display checking over. Verification of display
type with switch setting and actual card to begin.
34 Verification of display adapter done.
Display mode to be set next.
35 Display mode set complete.
BIOS ROM data area about to be checked.
36 BIOS ROM data area check over.
Going to set cursor for power on message.
37 Cursor setting for power on message id complete.
Going to display the power on message.
38 Power on message display complete.
Going to read new cursor position.
39 New cursor position read and saved.
Going to display the reference string.
3A Reference string display is over.
Going to display the Hit <ESC> message.
3B Hit <ESC> message displayed.
Virtual mode memory test about to start.
40 Preparation for virtual mode test started.
Going to verify from video memory.
41 Returned after verifying from display memory.
Going to prepare the descriptor tables.
42 Descriptor tables prepared.
Going to enter in virtual mode for memory test.
43 Entered in the virtual mode.
Going to enable interrupts for diagnostics mode.
44 Interrupts enabled (if diagnostics switch is on). Going
to initialize data to check memory wrap around at 0:0.
45 Data initialized. Going to check for memory wrap around
at 0:0 and finding the total system memory size.
46 Memory wrap around test done. Memory size calculation
over. About to go for writing patterns to test memory.
47 Pattern to be tested written in extended memory.
Going to write patterns in base 640k memory.
48 Patterns written in base memory.
Going to find out amount of memory below 1M memory.
49 Amount of memory below 1M found and verified.
Going to find out amount of memory above 1M memory.
4A Amount of memory above 1M found and verified.
Going for BIOS ROM data area check.
4B BIOS ROM data area check over. Going to check <ESC>
and to clear memory below 1M for soft reset.
4C Memory below 1M cleared. (SOFT RESET)
Going to clear memory above 1M.
4D Memory above 1M cleared. (SOFT RESET)
Going to save the memory size.
4E Memory test started. (NO SOFT RESET)
About to display the first 64k memory test.
4F Memory size display started. This will be updated during
memory test. Going for sequential and random memory test.
50 Memory test below 1M complete.
Going to adjust memory size for relocation/ shadow.
51 Memory size adjusted due to relocation/ shadow.
Memory test above 1M to follow.
52 Memory test above 1M complete.
Going to prepare to go back to real mode.
53 CPU registers are saved including memory size.
Going to enter in real mode.
54 Shutdown successful, CPU in real mode. Going to restore

ASUS Confidential registers saved during
449 preparation for shutdown.
55 Registers restored.
Going to disable gate A20 address line.
56 A20 address line disable successful.
BIOS ROM data area about to be checked.
57 BIOS ROM data area check halfway.
BIOS ROM data area check to be complete.
Going to clear Hit <ESC> message.
59 Hit <ESC> message cleared. <WAIT...> message displayed.
About to start DMA and interrupt controller test.
60 DMA page register test passed.
About to verify from display memory.
61 Display memory verification over.
About to go for DMA #1 base register test.
62 DMA #1 base register test passed.
About to go for DMA #2 base register test.
63 DMA #2 base register test passed.
About to go for BIOS ROM data area check.
About to program DMA unit 1 and 2.
66 DMA unit 1 and 2 programming over.
About to initialize 8259 interrupt controller.
67 8259 initialization over.
About to start keyboard test.
80 Keyboard test started. clearing output buffer, checking
for stuck key, About to issue keyboard reset command.
81 Keyboard reset error/stuck key found. About to
issue keyboard controller interface test command.
82 Keyboard controller interface test over.
About to write command byte and init circular buffer.
83 Command byte written, Global data init done.
About to check for lock-key.
84 Lock-key checking over.
About to check for memory size mismatch with CMOS.
85 Memory size check done. About to display soft error
and check for password or bypass setup.
86 Password checked.
About to do programming before setup.
87 Programming before setup complete.
Going to CMOS setup program.
88 Returned from CMOS setup program and screen is cleared.
About to do programming after setup.
89 Programming after setup complete.
Going to display power on screen message.
8A First screen message displayed. About to display
<WAIT...>message
8B <WAIT...> message displayed.
About to do Main and Video BIOS shadow.

8C Main and Video BIOS shadow successful.
Setup options programming after CMOS setup about to start.
8D Setup options are programmed, mouse check and init
to be done next.
8E Mouse check and initialization complete.
Going for hard disk, floppy reset.
8F Floppy check returns that floppy is to be initialized.
Floppy setup to follow.
90 Floppy setup is over.
Test for hard disk presence to be done.
91 Hard disk presence test over.
Hard disk setup to follow.
92 Hard disk setup complete.
About to go for BIOS ROM data area check.
Going to set base and extended memory size.
95 Memory size adjusted due to mouse support, hdisk type-47.
Going to verify from display memory.
96 Returned after verifying from display memory.
Going to do any init before C800 optional ROM control
97 Any init before C800 optional ROM control is over.
Optional ROM check and control will be done next.
98 Optional ROM control is done. About to give control to do
any required processing after optional ROM returns control.

99 Any initialization required after optional ROM test over.
Going to setup timer data area and printer base address.
9A Return after setting timer and printer base address.
Going to set the RS-232 base address.
9B Returned after RS-232 base address.
Going to do any initialization before Co-processor test
9C Required initialization before co-processor is over.
Going to initialize the coprocessor next.
9D Coprocessor initialized.
Going to do any initialization after Co-processor test.
9E Initialization after co-processor test is complete.
Going to check external keyboard, keyboard ID and num-lock.
9F External keyboard check is done, ID flag set. num-lock
on/off. Keyboard ID command to be issued.
A0 Keyboard ID command issued.
Keyboard ID flag to be reset.
A1 Keyboard ID flag reset.
Cache memory test to follow.
A2 Cache memory test over.
Going to display any soft errors.
A3 Soft error display complete.
Going to set the keyboard typematic rate.
A4 Keyboard typematic rate set.
Going to program memory wait states.
A5 Memory wait states programming over.
Screen to be cleared next.
A6 Screen cleared.
Going to enable parity and NMI.
A7 NMI and parity enabled. Going to do any
initialization required before giving control
to optional ROM at E000.
A8 Initialization before E000 ROM control over.
E000 ROM to get control next.
A9 Returned from E000 ROM control. Going to do any
initialization required after E000 optional ROM
control.
AA Initialization after E000 optional ROM control is over.
Going to display the system configuration.
00 System configuration is displayed.
Going to give control to INT 19h boot loader.

Phoenix Bios Code Definition-1
02h confirms the true way
03h removes MNI to establish
04h obtains CPU type
06h initializes the hardware in the system
08h initializes chipset with POST initial value Flag
09h establishes POST course is marked
0Ah initializes the register within CPU
0Bh can cause the register within CPU
0Ch initializes Cache with POST initial value
0Eh initializes the part related to I/O
0Fh initializes IDE equipment
10h initializes the power and manages worker's function
11h load a register POST initial value to make
12h is warm while starting the machine, resume control word yard of
CPU
13h initializes the top management device on PCI bus
14h initializes the keyboard controller
16h checks checksum value within BIOS
17h is established mainly before the capacity of the storing device
automatically, initializes cache first
18h initializes 8254 time-recorders
1Ah initializes 8237DMA controller
1Ch can reset the procedure cuts off the controller (PIC)
20h tests refresh function of DRAM
22h tests 8742 keyboard controllers
24h establishes the temporary device of ES sector to 4GB
26h can cause A20 control the line
28h mainly establishes the capacity of the storing device automatically
(autosize)
29h initial POST course storing device managing device
2Ah removes 512K content value of the storing device basically
2Ch, as detect and examine 512K RAM mistake, then Hao shows
corresponding address line xxxx
2Eh Hao shows wrong low-order district (low bytes of storing device
Materials line xxxx
2Fh duplicates BIOS to shadow RAM, initializes cache first
30h shows the wrong low high-order district (high-bytes ) of storing
device Materials line xxxx
32h tests the pulse frequency when CPU bus

33h initializes Phoenix materials and assigns administrators
36h starts the machine and is over warmly
38h duplicates BIOS to shadow RAM
3Ah establishes cache capacity automatically (auto size)
The register enters the configuration of the steps to establish inside chip group
3Ch
3Dh value in CMOS is loaded another register
42h initializes and cuts off the vectorial form
45h initializes POST component
46h checks the copyright statement within ROM
48h checks the configuration value of video-information
49h initializes PCI bus and device
4Ah initializes all video-information adapters in the system
4Bh get up sound the attitudes start the machine (/optional)
4Ch duplicates video BIOS to shadow
4Eh shows the copyright statement of BIOS
50h shows CPU type and speed
51h initializes EISA Board
52h tests the keyboard
54h establishing
58h tests the sudden signal of cutting off
59h initializes POST video-information service function
5Ah shows information Press F2 to enter SETUP Cache in
5Bh Disable CPU
5Ch tests 512KB 5Ch 640KB storing device
60h tests and extends the storing device (extended memory )
62h tests and extends the storing device address line
64h jumps to user patch 1
66h is established into the steps cache register
67h initializes APIC of many processors
68h can cause CPU / cache outside
69h establishes the systematic management style area (SMM )
6Ah shows outside L2 Cache Size of CPU
6Bh is loaded BIOS value that the user establishes
6Ch Hao shows the information of shadow sector
6Eh Hao shows the high address which resumes UMB
70h shows wrong information
72h checks the configuration mistake
76h checks the mistake of the keyboard
7Ch establishes the vector quantity in the hardware
7Eh is initialized in coordination with the processor (if the words existing)
Super-IO and IRQ 80h Disable onboard One section of POST components
initializes

81h It is examined and installed that 82h is detected to the outside
RS232 port 82h is detected to the outside RS232 port
83h organizes non-MCD IDE controller, it is examined and installed that
84h is detected to the parallel port of outside
85h initializes ISA device of PnP
86h initializes on-board IO port again
87h can organize on the host computer board the organization
component
88h initializes BIOS materials area
89h Enable Non-maskable interrupts(NMI)
The rose can be unable to interdict to cut off the vector quantity
8Ah initializes the BIOS materials area of extension
8Bh tests and initializes PS2 Genius mouse
8Ch initializes FDC
8Fh confirms ATA equipment's figure
90h initializes the hard disk controller
91h initializes the regional hard disk controller
92h jumps to userpatch2
93h sets up Mptable (there are many processor host computer boards)
Installation CD-ROM
95h enables starting the machine
96h removes ES sector register content
97h select / arrange for Mptable (whether large processors choose
form)
98h searches having and ROM, there is and checksum mistake, a two
long short humming
99h checks whether there is SMART device
9Ah and ROM duplicate to shadow RAM
9Ch establishes the functions of management of power
9Dh initializes the safe functions of management
9Eh starts the hardware and cuts off the function
9Fh determines ATA and SCSI device figure
A0h sets for date
A2h checks key-lock function
A4h initializes the keyboard and reflects the speed
A8h dispels F2 and points out number
AAh scans F2 key and is struck down
ACh prohibits entering SETUP
AEh removes and starts the machine the flag is marked

B0H checks whether there is any mistake
B2h POST finished planning to start the machine with the operating system
procedure
The buzzer is loud before
B4h operating system starts the machine A short
B5h discontinues the static behavior and starts the machine (option )
B6h checks the password to establish (option )
B9h plans to start the machine
BAh initializes DMI parameter
BBh initialize and type PnP ROM
BCh is removed with the location location detector
BDh shows that start the machine and choose the form again more
Beh removes the screen (optional)
BFh checks the virus
C0h tries to start the machine with INT19
C1h initializes the wrong administrator of POST (PEM)
C2h initializes the wrong log-in function
C3h initializes wrong Hao and shows the function
C4h initializes the wrong processor
C5h PnP CMOS
C6h initializes the note type computer dock function
C7h initializes the note type working speed of computer dock
C8h Force checking Extending type checksum inspection of C9h
D2h checking and cutting off unidentifiedly
E0h initializes the chip group
E1h initializes the north and south bridge
E2h initializes CPU
E3h initializes the systematic time-recorder
E4h initializes systematic IO
Function that E5h checks and resumes starting the machine by force
E6h calculates checksum of BIOS ROM
E7h is moved to BIOS
E8h establishes the large sector
E9h initializes many processors
EAh initializes OEM special yard
EBh initializes PIC and DMA
ECh initializes the modelling of the storing device to establish
EEh initializes the size of the storing device to establish
EDh starts the machine in the area to duplicate to Shadow RAM
EFh system storing device tests

F0h initializes and cuts off the vectorial form
F1h initializes RTC (Run Time Clock)
F2h initializes the video-information function
F3h initializes the systematic management style
A loud a short before F4h starts the machine
F5h starts the machine to small-scale DOS system
F6h removes the large sector content
F7h starts the machine to DOS
If BIOS is it examine get mistake yards of 2C to detect, 2E or 30
(mainly 512K mistake of storing etc. basically ), it will show 4 is it
show which one address line lose efficiency to come at the same
time, for example " 2C 0002 " expresses the address bit1 mistake,
2E, 1020 " express materials location bit5, 12 wrong BIOSs will
send off corresponding wrong location line to PORT80 LED card
and show that it will show first then 2C shows 00 high bytes, low
byte is 02, regard the covering as equally important and show
finally.


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MB L3 Training Materials

266 / 333/400 MHz

PCI PCI BUS

AGP 8x 533 MHz SiS DDR

5 x PCI Slots MuTIOL Bus

8X AGP 266 MHz

533/800 MB/s FSB

Hyper-Transport 800/1000 MHz

3 * TEMPERATURE Parallel port

 1. A8,K8 series (AMD 64bit) memory is

Q49 Q42 U17

Q32 Q36 Q31

STANDARD BUCK CONVERTER SYNCHRONOUS BUCK CONVERTER

Synchronous Buck Converter is More Efficient

 Integrated linear and

 Modular Power Partition BOOT

z Regulates Channel Current LGATE

Rectified Buck MOSFETs

z Adaptive Shoot-through VCC

 Power Good Monitor OSCILLATOR FS/EN

• Current Limit VID COMP

VCC Drive PHASE

PWM (Pulse-width LGATE

responsible for over- UGATE

voltage protection PWM HIP6601

GND BOOT Components

responsible for over-

VCC Drive PHASE

PCLK_RAID PDC 20378 20Mhz

30 AGPCLK AGP AGP Bus

Visual Inspection NG Change damaged CLK OK

Change CLK Generator Finished

Visual Inspection to check

Use Multi-Meter or Oscilloscope

Use Oscilloscope to measure

Use Oscilloscope to measure

If related RLC components

PSON Pull low circuit

+5 5VSB CPU SOCKET

GND GND (2) CPU

GND GND CPURST (6)

- 12V + 3V North Bridge

ASUS Confidential 58 RAID

1. Check if any burned components or traces

Pin Define Signal Description

Pin Define Signal Description

Next page describes the typical

1. The auxiliary device checks the 'clock' line. If the line is

Next page describes the typical

1. The system checks for an auxiliary device transmission in process. If a

Visual Inspection NG Change NG PS2 Connector, OK

NG Check PS2 Jumper is ok, Change NG PS2 Jumper,

Measure the bias value of Change NG RLC

Change Super I/O or SB

Visual Inspection check PS/2 connector

Check RLC components near PS/2

Use Multi-meter to check 5V_Dual for

Check K/B CLK, Data & Mouse

If the problem is still existing please

1. A8,K8 series (AMD 64bit) memory is

Integrated linear and

Modular Power Partition BOOT

Power Good Monitor OSCILLATOR FS/EN

Most of USB problems caused by USB 5V

1. Please make sure your LPT is enable to

1. Before test FDD function, confirm your