A 16-Bit ALU using Vedic Mathematics

A VLSITD LAB PROJECT REPORT

Submitted
in the partial fulfillment of the requirements for
the award of the degree of

BACHLEOR OF TECHNOLOGY
in
Electronics and Communication Engineering
by
BANKA SANDEEP REDDY (22315A0420)
S. SHIVA PRASAD REDDY (21311A04R9)

UNDER THE GUIDANCE OF

Dr .D. ASHADEVI,
Professor, Dept. of ECE

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

SREENIDHI INSTITUTE OF SCIENCE & TECHNOLOGY
Yamnampet, Ghatkesar, Hyderabad – 501 301
FEBRUARY 2020-2021
 SREENIDHI INSTITUTE OF SCIENCE & TECHNOLOGY

Yamnampet, Ghatkesar, Hyderabad – 501 301

CERTIFICATE

This is to certify that the Lab Project Work entitled “A 16-bit alu using Vedic

mathematics” being submitted by

BANKA SANDEEP REDDY (22315A0420)

S.SHIVA PRASAD REDDY (21311A04R9)

in partial fulfillment for the award of Bachelor of Technology in Electronics

and Communication Engineering [ECE], Sreenidhi Institute of Science and
Technology, an autonomous institute under Jawaharlal Nehru Technological
University, Telangana, is a record of bonafide work carried out by them under
our guidance and supervision.

Dr. D. ASHADEVI (Dr.S.P.V. Subba Rao)

Professor, Department of ECE. Professor & Head,ECE
 DECLARATION

We hereby declare that the work described in this report, entitled “A 16 bit alu
using Vedic mathematics” which is being submitted by us in partial fulfillment
for the award of Bachelor of Technology in Electronics and Communication
Engineering [ECE], Sreenidhi Institute Of Science & Technology affiliated
to Jawaharlal Nehru Technological University Hyderabad, Kukatpally,
Hyderabad (Telangana) -500 085 is the result of investigations carried out by
us/me under the Guidance of Dr.D.ASHADEVI, Professor, ECE Department,
Sreenidhi Institute Of Science And Technology, Hyderabad.

Place: Hyderabad
Date:

BANKA SANDEEP REDDY (22315A0420)

S. SHIVA PRASAD REDDY (21311A04R9)

 CONTENTS
Page No.
List of Figures i
Abstract ii
CHAPTER1 INTRODUCTION 1-4
1.1 Introduction 1-3
1.2 Strategy for building PWM signals in FPGA 3-4
using Verilog
1.3 implementation of Verilog codes in Xilinx
CHAPTER 2 EXPERIMENTAL WORK 4-6
2.1 Design Module 4-5
2.2 Testbench Module 5-6
2.3 Explanation of the Design Logic 6
CHAPTER 3 EXPERIMENTAL PROCEDURE 6-13
CHAPTER 4 RESULTS 14-18
4.1 RTL Schematic 14
4.2 Simulated Waveforms 14
4.3 XDC File 15
4.4 Implementation Schematic 16
4.5 Power Report 16
4.6 Utilization Report 17
4.7 Noise Report 17
4.8 Timing Report 18
CHAPTER 5 CONCLUSION 18
CHAPTER 6 REFERENCES 18
 LIST OF FIGURES

Fig. No. Figure Name PAGE NO.

4.1 RTL Schematic 14

4.2 Simulated Waveforms 14
4.3 XDC File 15
4.4 Implementation Schematic 16
4.5 Power Report 16
4.6 Utilization Report 17
4.7 Noise Report 17
4.8 Timing Report 18
LIST OF TABLES

Table no. table name page no.

1. conversion of firing angle to

time period 3
 ABSTRACT:

Background: An ALU is the most significant building block required in arithmetic and logical
functions. Multiplication unit is the key block of ALU and can be used to control many logical
implementations of the circuit. Although some multiplication based algorithms are in use, the
implementations of multipliers put up on Vedic mathematics have not got that much credit. The
structure minimizes the complexity. The technique is helpful in reducing the computational path
delay and by reutilization of resources the area overhead can be minimized to a certain extent.
Objective: In this paper a vedic Mathematics based multiplication unit is used to design an ALU.
The Vedic Mathematics based algorithm is adopted for multiplication in the projected advance in
addition to carry select adder bring into play in order to improve the timing complexity as well as
area overhead. Results: The proposed methodology is implemented using the Xilinx Spartan 6
FPGA and Verilog Hardware Description Language. In the proposed architecture the timing delay
is improved by a significant value of approx. 62% with the slight improvement in area.
Conclusion: The improvement in the timing delay allows the circuit to work faster in the digital
circuits. In the future the arithmetic operations unit must be further improved in terms of area
efficiency which increases its application in digital processing functions.

Keywords:
Vedic Multiplier, Arithmetic Logic Unit (ALU), DSP operations, ALU, CSA, Verilog

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 1. INTRODUCTION

The simultaneous deprecation of delay and power utilization has become the critical problems in
achievement of the top level presentation of processors. Arithmetic Logic Unit is a key portion of a
processor design. It accomplishes arithmetic, Logic operations on integers stored in accumulator,
register array, operand register and fetch value from external memory. In recent time a number of
designs have been represented for deprecated delay and energy optimisation. The fulfilment of basic
carry select adder by using half adders is playing a vital role, as the propagation of carry (CP) is
dependable for the delay in addition respectively. The arithmetic function units are made using different
approaches as adder unit using carry select adder, subtraction unit using same unit. Divider using
subtract and shift approach with the help of finite state machine, multiplier using Vedic mathematics
formula naming Urdhva Tiryakbhayam algorithm using CSA for partial product sum. Whereas the
logical operations are performed by using logic gates such as AND, OR, NOT, NAND, NOR, XAND,
XOR. The multiplier unit is responsible for causing a large quantity delay; as a result, the outputs of
multiplier affect the complete ALU unit. In addition to it, it encloses major area, as a result it is said
that optimisation of the area and delay of the multiplier unit in ALU is a critical design matter.

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 II. METHODOLOGY/LOGIC OF THE PROJECT

Performance of the ALU is prime focus for functions such as arithmetic calculations to be executed
properly. Hence to improve the performance of the ALU, a new Arithmetic unit is suggested which is
completely based on the principles of Vedic Mathematics.
In this Vedic ALU, all the arithmetic functions are performed using Vedic Maths sutras. Such
as, Addition – “Ekadhiken Purven” (One more than the Previous)
Subtraction – “Ekanyunen Purven” (One less than the previous)
Multiplication – “Urdhva Tiryagbhyam” (Vertically and crosswise)
Division – “Nikhilam Navatashcharamam Dashatah” (All from Nine and last from ten) and
“Ekanyunen Purven.
A. VEDIC MULTIPLICATION METHOD
While performing the multiplication using Vedic Maths sutras, the Sutra “Urdhva Tiryagbhyam” is
used. “Urdhva Tiryagbhyam” means „vertically and crosswise‟. As the name suggests, the given
method performs the multiplication first vertically between the two digits and then crosswise between
the digits of two numbers.
B. Working of “Urdhva Tiryagbhyam”
The method can be explained as follows: Ex: 426 x 115

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This gives the product as: 4 8 9 9 0
Similarly, multiplication can also be done in Binary system using Vedic Method Urdhva
Tiryagbhyam[2]:
Example: 110x111

This gives the product as: 1 0 1 0 10

In the above method, first the LSB of multiplicand is multiplied with LSB of Multiplier, which gives
the LSB of the product. This is „Vertical‟ multiplication. In next step, the LSB Of multiplicand is
multiplied with next higher bit of multiplier and the LSB of multiplier is multiplied with next higher
bit of multiplicand. This is the „crosswise‟ multiplication which gives the next bit of the product from
right to left. This method continues till the MSB of both the multiplicand and the multiplier multiply
each other to gives the MSB of the product, which is again a „vertical‟ multiplication. Following the
line diagram mentioned above, the algorithm for the Vedic multiplication can be given as:
Algorithm For Urdhva Tiyagbhyam Method for 4x4 Bit Multiplication:
A=A3A2A1A0
B=B3B2B1B0
Then, A3 A2 A1 A0
X B3 B2 B1 B0
P7 P6 P5 P4 P3 P2 P1 P0
Where,

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P0=A0.B0
P1=A1.B0+A0.B1
P2=A0.B2+A1.B1+A2.B0+C(P1)
P3=A0.B3+A3.B0+A2.B1+A1.B2+C(P2)
P4=A1.B3+A3.B1+A2.B2+C(P3)
P5=A3.B2+A2.B3+C(P4)
P6=A3.B3+C(P5)
P7=C(P6)
C(P) is the carry of the multiplication result
Similarly, the same algorithm can be implemented for 8x8 bit Multiplication as:
A= A7A6A5A4 A3A2A1A0
B= B7B6B5B4 B3B2B1B0
Let, A and B be split into upper and lower nibbles as
C1=A7A6A5A4
C0= A3A2A1A0
D1=B7B6B5B4
D0=B3B2B1B0
Then, C1 C0
X D1 D0
P3 P2 P1 P0
Where,
P0=A0*B0
P1=A1*B0+A0*B1+C(P0)
P2=A1*B1+C(P1)
P3=C(P2)
C(P) is the carry of multiplication result and the symbol “*‟follows the 4x4 bit multiplication.
Thus, we can use either 8x8 Bit Multiplication or 4x4 Bit Multiplication for 16x16 Bit multiplication.

C. Vedic Division Method

The Vedic method which is used for Division is “Nikhilam‟method. The sutra is called as “Nikhilam
Navatashcharamam Dashtah.” It means that „all from nine and last from ten. “while dividing a number
and the number being close to the base, the method suggests us to take the complement of the Divisor.

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D. Working of Nikhilam Method

In this method, there is no need for the division. It is simply done by the multiplication and addition.
Here, the complement of the divisor is obtained called Modified Divisor and the rest calculation is
done by the MD. The dividend is bifurcated into two parts so that the RHS of the dividend contains
equal number of digits to those of the Modified Divisor.
The method can be better explained with the example below.
Example:

III. PROPOSED METHOD OF VEDIC DIVISION

In the given Vedic Division method, i.e. Nikhilam method,the method requires frequent
multiplications. Also the multiplication with modified divisor becomes difficult when the MD is not
closer to the base but a greater number. The dividend is to be bifurcated into two parts, which requires
two registers to store the number. This leads to complicated multiplication as the dividend is split into
two parts.
On the other hand, Nikhilam method is most appropriate for the decimal number system. It
becomes complex during its execution on the binary number system.
Hence, a new method is derived from the Nikhilam method which is applicable for the binary
number system [3]. In this Method, only shifting and subtraction operations are needed to be
performed.

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The algorithm for the proposed method is given in the Fig Below:

Results: Quotient= 8+2+1+1=12(1100)

Remainder= 2(0010)

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 A. Working of Proposed Method

In this method, the divisor is shifted to the left by 1-Bit less to the MSB of the dividend. After that,
regular subtraction is performed. Result of the subtraction is now the New Dividend. Again, we shift
the divisor to left up to 1-bit less of the MSB of the New Dividend. This process is continued till we
get a number which is not divisible by the divisor. This number is the ultimate Remainder of the
Division. While shifting the Divisor to the left, we get the sub-quotients as 2n, where N=number of
shifts. The ultimate quotient is obtained by adding all the sub-quotients.

B. Advantages of derived method

** The derived method can be used for binary systems.
** We can divide any number of bits of dividend by any number of bits of divisor. There is no such
restriction on The divisor as such in Booth’s Algorithm.
**We are performing Shifting, Subtraction and addition. For which very few registers would be
required.
**No carry or borrow are generated during addition or Subtraction. Therefore, the flag register is not
affected much.

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 2.EXPERIMENTAL WORK:

2.1 DESIGNMODULE:

module PWM_Generator_Verilog(
input clk,
input increase_duty,
input decrease_duty,
output PWM_OUT
);
wire slow_clk_enable; // slow clock enable signal for debouncing FFs
reg[27:0] counter_debounce=0;// counter for creating slow clock enable signals
wire tmp1,tmp2,duty_inc;// temporary flip-flop signals for debouncing the increasing button
wire tmp3,tmp4,duty_dec;// temporary flip-flop signals for debouncing the decreasing button
reg[3:0] counter_PWM=0;// counter for creating 10Mhz PWM signal
reg[3:0] DUTY_CYCLE=5; // initial duty cycle is 50%
always @(posedge clk)
begin
counter_debounce<= counter_debounce + 1;
if(counter_debounce>=1)
counter_debounce<= 0;
end
assign slow_clk_enable = counter_debounce == 1 ?1:0;
DFF_PWM PWM_DFF1(clk,slow_clk_enable,increase_duty,tmp1);
DFF_PWM PWM_DFF2(clk,slow_clk_enable,tmp1, tmp2);
assign duty_inc= tmp1 & (~ tmp2) &slow_clk_enable;
DFF_PWM PWM_DFF3(clk,slow_clk_enable,decrease_duty, tmp3);
DFF_PWM PWM_DFF4(clk,slow_clk_enable,tmp3, tmp4);
assign duty_dec= tmp3 & (~ tmp4) &slow_clk_enable;
always @(posedge clk)
begin
if(duty_inc==1 && DUTY_CYCLE <= 9)
DUTY_CYCLE <= DUTY_CYCLE + 1;// increase duty cycle by 10%
else if(duty_dec==1 && DUTY_CYCLE>=1)
DUTY_CYCLE <= DUTY_CYCLE - 1;//decrease duty cycle by 10%
end
always @(posedge clk)
begin
counter_PWM<= counter_PWM + 1;
if(counter_PWM>=9)
counter_PWM<= 0;
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 end
assign PWM_OUT = counter_PWM< DUTY_CYCLE ? 1:0;
endmodule
module DFF_PWM(clk,en,D,Q);
input clk,en,D;
output reg Q;
always @(posedge clk)
begin
if(en==1) // slow clock enable signal
Q <= D;
end
endmodule

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 2.2 TESTBENCH MODULE:

module tb_PWM_Generator_Verilog;
reg clk;
reg increase_duty;
reg decrease_duty;
// Outputs
wire PWM_OUT;
// Instantiate the PWM Generator with variable duty cycle in Verilog
PWM_Generator_Veriloguut(
.clk(clk),
.increase_duty(increase_duty),
.decrease_duty(decrease_duty),
.PWM_OUT(PWM_OUT)
);
// Create 100Mhz clock
initial begin
clk = 0;
forever #5 clk = ~clk;
end
initial begin
increase_duty = 0;
decrease_duty = 0;
#100;
increase_duty = 1;
#100;// increase duty cycle by 10%
increase_duty = 0;
#100;
increase_duty = 1;
#100;// increase duty cycle by 10%
increase_duty = 0;
#100;
increase_duty = 1;
#100;// increase duty cycle by 10%
increase_duty = 0;
#100;
decrease_duty = 1;
#100;//decrease duty cycle by 10%
decrease_duty = 0;
#100;
decrease_duty = 1;
#100;//decrease duty cycle by 10%
decrease_duty = 0;
#100;
decrease_duty = 1;
#100;//decrease duty cycle by 10%
decrease_duty = 0;
end
endmodule
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 3.EXPERIMENTAL PROCEDURE:

Step-1: Open Vivado and Enter the “Project Name” at the desired location and Click “Next” as shown
be low

Step-2: Select RTL project and also click the checkbox “Do not specify sources at this time”

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Step-3: Select Family as “Artix-7”, Package as “csg324”, Speed as“-1” and then select the board
“xc7a100tcsg324-1” and then Click Next.

Click finish to create the project

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Step-4: Click on “Add Sources” in Flow Navigator, then click on “Add or Create design sources”.

Then create a file name as per the naming the variables in Verilog since it is used as the module name
then click “OK” and then click “Finish”.

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Step-5: Then click the “Port name” and the “Direction” as per the design of the black box of the circuit
and then click “OK” to create the design file. But in our project we directly clicked “OK” and gave the
input-output parameters directly in the code.

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Step-6: To create testbench module again click on “Add sources” and then click “Add or Create
simulation sources”.

Then create a file name as per the naming the variables in Verilog since it is used as the module name
then click “OK” and then click “Finish”.

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Step-7: to create test bench no need to specify input-output ports. So directly click “OK” in order to
create the required test bench file.

Step-8: After RTL synthesis create the xdc file by saving the constraints used by the device by selecting
I/O bus as “LVCMOS33”and keep the package pins as per the input-output pins of the FPGA board.

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Step9: Verify whether both the design file and the test bench file are present as top models in the Design
sources and Simulation sources.

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 4.RESULTS

The above mentioned algorithms for Vedic Multiplication and Vedic Division are implemented in
Xilinx ISE tool and the simulation results are checked using ISE simulator. The preferred language for
implementation is Verilog HDL. The design is implemented on Spartan 3E and the specifications of the
device are given as:
Family: Spartan 3E
Device: XC3S250E
Package: PQ208
Speed Grade: -5
Thus, the simulation results of both the algorithms can be shown as:

A. Simulation Results of Vedic Multiplier

The inputs fed to the Vedic Multiplier and the obtained outputs are as below:
Input A=16-Bit input data= 11111111 11111111 (b)
Input B=16-Bit input data= 11111111 11111111 (b)
Output R= 32-Bit Output Data= 1111 1111 1111 1110 0000 0000 0000 0001 (b)
Here, we can see that the multication result of two 16-Bit numbers is verified in the 32-Bit output.

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 B. Simulation Results of Vedic Division Method

The inputs given to the proposed Vedic Division algorithm and the obtained outputs are as
below:
Dividend= 16-Bit input data= 11111111 01010101 (b)
Divisor= 16-Bit Input Data= 00000000 01101010 (b)
Quotient= 16-Bit Output Data= 00000010 01101000 (b)
Remainder= 16-Bit Output Data= 00000000 01000101 (b)
Here, we can verify the division results as Quotient and remainder. Dividend and Divisor also
fed to the simulator. As per the proposed algorithm of Vedic Division method, the divisor is
shifted one bit less of the dividend and the same is continued till we obtain the shifted divisor
greater than the dividend. Thus, the shifted divisor is also observed in the simulation
waveforms.

C. Comparison Results

Comparing the Vedic Multiplier Using “UrdhvaTiyagbhyam” Method to the conventional

Multiplication method and proposed Vedic Division Method to the conventional Division
method, we get the comparison results as:

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Method Vedic multiplication method Conventional method of
binary multiplication
Number of 4 input LUTs 31 of 1536 678 of 4896
2% 13%
Number of occupied slices 23 of 768 375 of 2448
2% 15%
Number of bonded IOBs 65 of 124 65 of 158
52% 41%
Delay 6.216ns 15.966ns
Power 24mW 49mW

Comparison Results between Conventional and Vedic Multiplication Method

Method Proposed Vedic Division

Method Using “Nikhilam
Method “
Number of 4 input LUTs 678 of 4896 15%
Number of occupied slices 375 of 2448 13%
Number of bonded IOBs 65 of 158 41%
Delay 11.413ns
Power 49mW

Results of Proposed Vedic Division Method derived from Nikhilam Method

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 5. CONCLUSION AND FUTURE SCOPE

The proposed Vedic division method derived from “Nikhilam” method and the Vedic
Multiplication method using “Urdhva-Tiryagbhyam” method prove efficient over the
conventional methods of binary multiplication and division which are currently being
used in the processor hardware. Thus, assembling the Vedic Multiplier [4],[5] and Vedic
Divider, an efficient high speed Vedic ALU which performs the arithmetic operations
based on the Vedic Mathematics sutras is achieved.

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 6. REFERENCES

[1] Jagadguru Swami Sri Bharati Krishna Tirthaji Maharaj,” Vedic Mathematics”, Motilal
Banarsidas, Varanasi, India, 1986.
[2] Prof J M Rudagil, Vishwanath Amble, Vishwanath Munavalli, Ravindra Patil, Vinay Kumar
Sajjan, “Design and Implementation of Efficient Multiplier Using Vedic Mathematics”, Proc.
Of1nt. Con/, on Advances in Recent Technologies in Communication and Computing 2011
[3] Manish Karandikar, Neha Kawadkar, “Power Efficient High Speed Integer Division Method
for Binary System Based on Principles of Vedic Maths”, IRAJ International Conference
Hyderabad, 2015.
[4] M. Ramalatha, K. Deena Dayalan, P. Dharani, S. Deborah Priya, “High Speed Energy Efficient
ALU Design using Vedic Multiplication Techniques”, ACTEA 2009, July 15-17, 2009 Zouk
Mosbeh, Lebanon
[5] Anju & V.K. Agrawal, “FPGA Implementation of Low Power and High Speed Vedic Multiplier
using Vedic Mathematics”, IOSR Journal of VLSI and Signal Processing (IOSR-JVSP) Volume 2,
Issue 5 (May. –Jun.,2013), PP51-57

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