Chapter 1

Chapter 2 : Digital Components

Classification of ICs is based on

● number of gates and logic operations (SSI, MSI, LSI, VLSI, ULSI, GSI-Giga)
 ● circuit technology/ digital logic family (TTL, ECL, MOS, CMOS) : the basic circuit in
each technology uses NAND or NOR gate because
o NAND and NOR gates are created using 4 transistors whereas AND/OR require 6
transistors
o NAND and NOR can easily be turned into inverters.

SSI

LSI: Programmable modules : to implement combinational logic circuits

Eg. PAL- Programmable Array Logic

PLA – Programmable Logic Array

VLSI circuits are used everywhere, real applications include microprocessors in a personal
computer or workstation, chips in a graphic card, digital camera, chips in a cell phone or a
portable computing device, and embedded processors.

DL(Diode Logic) ->DTL (Diode-Transistor Logic)->RTL(Resistor-Transistor logic)-

>TTL(Transistor-transistor logic)

TTL (5400, 7400, 9000, 8000 series)– logic gates, flip-flops, counters

ECL (10000 series)–for systems requiring high speed operations: super computers and signal
processors( Analog to Digital and viceversa)

MOS- for systems that need high component density: micro-processors, memories)

CMOS (4000 series, 54C00, 74C00) -for systems requiring low power consumption. It is the
memory on motherboard that stores BIOS settings including system date and time. CMOS
battery provides constant power to chip.

TTL and CMOS logic family are most widely used IC technology.

TTL and ECL use bipolar transistors (both P and N carriers exist during normal operations)

Basic components on ICs: Decoder, encoder, multiplexer, register, counter, RAM, ROM)

Enable input : 2 uses: (a) An enable pin in an IC is used to literally enable it to work. It is a
switch to an IC. When the enable is active, it means that the IC could now function. (b) for
circuit expansion

Decoder: N x M decoder / N-to-M line decoder where M <=2N

Combinational Circuit with N input lines and M output lines.

4 bits are needed to generate 10 unique representations

4x10 decoder has N=4 input lines and M=10 output lines where M<2N

Decoder 3x8 has N=3 input lines and M=8 output lines where M=2N

2 x 4 AND gate decoder

NAND gate decoder : used when complemented outputs are needed.

D0=(E’A1’A0’)’

D1=(E’A1’A0)’

D2=(E’A1A0’)’

D3=(E’A1A0)’

E A1 A0 D0=(E’A1’A0’)’ D1=(E’A1’A0)’ D2=(E’A1A0’)’ D3=(E’A1A0)’

1 x x 1 1 1 1

0 0 0 0 1 1 1

0 0 1 1 0 1 1

0 1 0 1 1 0 1

0 1 1 1 1 1 0

In general, when block diagram is represented, it is assumed to be AND gate decoder.

22 21 20 Fig 2.3 (3x8 decoder using two 2x4 decoders)

A2 A1 A0 D0 D1 D2 D3 D4 D5 D6 D7
0 0 0 1 0 0 0 Decoder 2 is deactivated
0 0 1 0 1 0 0 resulting in values 0 for
0 1 0 0 0 1 0 D4,D5,D6,D7
0 1 1 0 0 0 1
1 0 0 Decoder 1 is deactivated 1 0 0 0
1 0 1 resulting in D0=D1=D3=D3=0 0 1 0 0
1 1 0 0 0 1 0
1 1 1 0 0 0 1

A2=0, 1st decoder is activated

A2=1, 2nd decoder is activated

Question

Construct a 5-to-32-line decoder with four 3-to-8-line decoders with enable and one 2-to-4 line
decoder. Use block diagrams similar to Fig. 2·3.
X4 X3 X2 X1 X0 output

0 0 0 0 0 D0=1

0 0 0 0 1 D1=1

0 0 0 1 0 D2=1

0 0 0 1 1 D3=1

0 0 1 0 0 D4=1

0 0 1 0 1 D5=1

0 0 1 1 0 D6=1

0 0 1 1 1 D7=1
In the same way,
when X4=0, X3=1 for all combinations from 000 to 111 for X2, X1, X0 one of the outputs
from D8 to D15 will be 1.
when X4=1, X3=0 for all combinations from 000 to 111 for X2, X1, X0 one of the outputs
from D16 to D23 will be 1.
when X4=1, X3=1 for all combinations from 000 to 111 for X2, X1, X0 one of the outputs
from D24 to D31 will be 1.

Encoder : inverse of decoder (<=2n input lines and n output lines)

Block diagram of 4x2 encoder

8x3 encoder (diagram 1)

8x3 encoder (diagram 2)

Multiplexer
4x1 multiplexer

Function table
 S1 S0 Y

0 0 I0

0 1 I1

1 0 I2

1 1 I3

(for 2nx1 multiplexer)

Function table shows single output as a function of n selection lines.

Fig.2.5
Construct a 16-to-1line multiplexer with two 8-to-1line multiplexers and one 2-to-1 line
multiplexer. Use block diagrams for the three multiplexers.
 S3 S2 S1 S0 Y

0 0 0 0 I0

0 0 0 1 I1

0 0 1 0 I2

0 0 1 1 I3

0 1 0 0 I4

0 1 0 1 I5

0 1 1 0 I6

0 1 1 1 I7

1 0 0 0 I8

1 0 0 1 I9

1 0 1 0 I10

1 0 1 1 I11

1 1 0 0 I12

1 1 0 1 I13

1 1 1 0 I14

1 1 1 1 I15

Applications of multiplexer
Data routing, parallel to serial conversion, logic function generation (n-variable logic
function can be generated using n-select inputs of a multiplexer.
Multiplexers are considered universal logic modules.

Registers

Register with parallel load: all bits of register are loaded simultaneously with a common
clock pulse transition.
Fig 2.8 Register with parallel load
Load input: it determines the actions to be taken with each clock pulse.
Load=1: data inputs I0, I1, I2, I3 are loaded in flip-flops.
Load=0: data inputs I0, I1, I2, I3 are inhibited (prevented) from loading and Q(t) values of
all flip-flops are fed to D inputs forming a feedback loop. This is required as D
flip-flop does not have a no change (Q(t)) condition.
Buffer gate in clock strengthens the signals and reduces power requirement from clock
generator.
Binary Counter

2 bit up counter: 00, 01, 10, 11, 00,……

2 bit down counter: 11, 10,01,00,11,…….

3 bit up counter: 000, 001, 010, 011, 100, 101, 110, 111, 000, 001, …….
3 bit down counter: 111, 110, 101, 100, 011, 010, 001, 000, 111, ………

General rule for UP counter: bit at 0th position is always complemented

bit at ith position is complemented iff all bits from 0th to (i-1)th
positions are 1 in the previous state.

General rule for DOWN counter: bit at 0th position is always complemented
bit at ith position is complemented iff all bits from 0th to
(i-1)th positions are 0 in the previous state.

Example 1 (UP counter):

Let A3(t)=0, A2(t)=1, A1(t)=1, A0(t)=1
Then
A0(t+1)=0 (since A0(t) is always complemented)
A1(t+1)=0 (complemented since A0(t)=1)
A2(t+1)=0 (complemented since A0(t)=A1(t)=1 resulting in A0(t).A1(t)=1)
A3(t+1)=1 (complemented since A0(t)=A1(t)=A2(t)=1 resulting in A0(t).A1(t).A2(t)=1)

So 0111 -> 1000

Example 2 (UP Counter):

Let A3(t)=1, A2(t)=0, A1(t)=0, A0(t)=0
Then
A0(t+1)=1 (since A0(t) is always complemented)
A1(t+1)=0 (unchanged since A0(t)=0)
A2(t+1)=0 (unchanged since A0(t)=A1(t)=0 resulting in A0(t).A1(t)=0)
A3(t+1)=1 (unchanged since A0(t)=A1(t)=A2(t)=0 resulting in A0(t).A1(t).A2(t)=0)

So 1000 -> 1001

 DOWN Counter
A3 A2 A1 A0
1 1 1 1
1 1 1 0
1 1 0 1
1 1 0 0
1 0 1 1

Fig. 2.10 4-bit synchronous UP counter

When count enable=0, All flip-flops have J=K=0. So Q(t+1) =Q(t) resulting in NO
CHANGE.

When count enable=1:

FF0: J=K=1 So A0(t+1) is always complemented
FF1: J=K=1.A0(t)=A0(t) A1(t+1) will be complemented if A0(t) =1
FF2: J=K=A0(t)A1(t) A2(t+1) will be complemented if A0(t)A1(t)=1
FF3: J=K=A0(t)A1(t)A2(t) A3(t+1) will be complemented if A0(t)A1(t)A2(t) =1

4-bit UP counter

Time t FF3(A3) FF2(A2) FF1 (A1) FF0 (A0)

0 0 0 0 0

1 0 0 0 1

2 0 0 1 0

3 0 0 1 1

4 0 1 0 0

5 0 1 0 1

6 0 1 1 0

7 0 1 1 1

8 1 0 0 0

9 1 0 0 1

10 1 0 1 0
 11 1 0 1 1

12 1 1 0 0

13 1 1 0 1

14 1 1 1 0

15 1 1 1 1

4-bit synchronous DOWN counter

When count enable=1:
FF0: J=K=1 So A0(t+1) is always complemented
FF1: J=K=1.A0’(t)=A0’(t) A1 (t+1) will be complemented if A0’(t) =1
FF2: J=K=A0’(t)A1’(t) A2 (t+1) will be complemented if A0’(t)A1’(t)=1
FF3: J=K=A0’(t)A1’(t)A2’(t) A3(t+1) will be complemented if A0’(t)A1’(t)A2’(t) =1
4-bit UP counter

Time t FF3(A3) FF2(A2) FF1 (A1) FF0 (A0)

0 1 1 1 1

1 1 1 1 0

2 1 1 0 1

3 1 1 0 0

4 1 0 1 1

5 1 0 1 0

6 1 0 0 1

7 1 0 0 0

8 0 1 1 1

9 0 1 1 0

10 0 1 0 1
11 0 1 0 0

12 0 0 1 1

13 0 0 1 0

14 0 0 0 1

15 0 0 0 0
 Clear Load Incremen Clear’ Load’ Y=Clear’Load’Increment Z=Clear’load
t

0 0 0 1 1 0 0

0 0 1 1 1 1 0

0 1 0 1 0 0 1

0 1 1 1 0 0 1

1 0 0 0 1 0 0

1 0 1 0 1 0 0

1 1 0 0 0 0 0

1 1 1 0 0 0 0

A0(t+1) : J0=Y+Z.I0 K0=clear+Y+Z.I0’

A1(t+1) : J1=Y.A0(t)+Z.I1 K1=clear+Y.A0(t)+Z.I1’
A2(t+1) : J2=Y.A0(t).A1(t)+Z.I2 K2=clear+Y.A0(t).A1(t)+Z.I2’
A3(t+1) : J3=Y.A0(t).A1(t).A2(t)+Z.I3 K3=clear+Y.A0(t).A1(t).A2(t)+Z.I3’

Clear Load Increment Y Z J0 K0 J1 K1 J2 K2 J3 K3

0 0 0 0 0 0 0 0 0 0 0 0 0

0 0 1 1 0 1 1 J1= K1= J2=K2= J3=K3=

A0(t) A0(t)A1(t) A0(t)A1(t)A2(t)

0 1 0 0 1 I0 I0’ I1 I1’ I2 I2’ I3 I3’

0 1 1 0 1 I0 I0’ I1 I1’ I2 I2’ I3 I3’

1 0 0 0 0 0 1 0 1 0 1 0 1

1 0 1 0 0 0 1 0 1 0 1 0 1

1 1 0 0 0 0 1 0 1 0 1 0 1

1 1 1 0 0 0 1 0 1 0 1 0 1

Function table
 Clock Clear Load Incrementer Operation

↑ (0→1) 0 0 0 No change

↑ 0 0 1 Increment count by 1

↑ 0 1 X Load inputs I0 to I3

↑ 1 X X Clear outputs to 0

Memory (RAM, ROM)

Circuit diagram of 4x3 RAM ( 4 words/memory locations with 3 bits per word): It consists
of one 2x4 decoder, one 4x2 encoder, 12 binary cells(BC) such that 3 binary cells denote one
word each stored in 4 memory locations, memory enable input, read/write input. The
circuit works when memory enable=1.
4 words =22 words=2 address lines.
3 bits per word=3 data input lines=3 data output lines.
Depending on address selection lines, one of the outputs D0 to D3 is 1 ( when 00 then D0=1,
01 implies D1=1, 10 implies D2=1, 11 implies D3=1).

Example: Read operation (Read=1)

If address lines are 10, then D2=1, bits stored in binary cells at memory location 2 will be
passed to OR gates of 3 data output lines.
Example : Write operation (Write=1)
If address lines are 10, then D2=1, data input bits will be stored in binary cells at memory
location 2.

ROM
Only read operation will take place.

Application of EEPROM devices : Storing current time and date in a machine.

Flash memory is a form of EEPROM. Applications are:

Storing messages in a mobile phone
Storing photographs in a digital camera.
 RAM (Random Access Memory)
RAM is volatile memory, which means that the stored information is lost when there is no
power. So RAM is used by the central processing unit (CPU) when a computer is running to
store information that needs to be used immediately, however, doesn’t store any information
permanently.

TYPES OF RAM-
RAM is of two types-

1. Static RAM (SRAM)

2. Dynamic RAM (DRAM)

1. Static RAM (SRAM)

Static indicates that the memory retains its contents as long as power is available. It is volatile in
nature and data is lost when the power goes off. Static RAM chip uses a matrix of 6-transistors
and no capacitors. Transistors do not require power to prevent leakage, so Static RAM needs to
be refreshed on a regular basis. Static RAM uses more chips than DRAM for the same amount of
storage space, thus making the manufacturing costs higher. Static RAM is used as cache memory
in system.

2. Dynamic RAM (DRAM)

Dynamic RAM must be continually refreshed in order for it to maintain the data. It can rewrites
the data several hundred times per second. Dynamic RAM is used because it is cheap and small.
All Dynamic RAMs are made up of memory cells. It very basic form, DRAM can be built of one
capacitor and one transistor.

ROM(Read Only Memory)

Read-only memory (ROM) is a type of storage that permanently stores data on personal
computers (PCs) and other devices.
It contains the programming needed to start a PC or laptop, which is required for boot-up. ROM
performs input/output tasks and holds programs and software instructions.
ROM is used to store the start-up instructions for a computer, also known as the firmware. Most
modern computers use flash-based ROM.
It is part of the BIOS chip, which is located on the motherboard.
Types of ROM –
▪ MROM (Masked ROM)
First ROMs were hard-wired devices that contained pre-programmed instructions. These were
known as masked ROMs. It was inexpensive ROM.

▪ PROM (Programmable Read only Memory)

PROM is a read-only memory and can be modified only once by a user. In a blank PROM, user
enters the desired contents using a PROM programmer. PROM chip contains small fuses which
are burnt open during programming. Once programmed, it is not erasable.

▪ EPROM (Erasable and Programmable Read Only Memory)

EPROM can be erased by ultra-violet light for a duration of up to 40 minutes. During
programming, an electrical charge is applied in an I/O gate. The charge is sustained for more
than ten years because the charge has no leakage path. For erasing the memory ultra-violet light
is used through a quartz crystal.

▪ EEPROM (Electrically Erasable and Programmable Read Only Memory)

EEPROM is programmed and erased electrically and reprogrammed many times. Both erasing
and programming to chip takes 4 to 10 milliseconds. EEPROM can be erased one byte at a time
instead of erasing the entire chip. Process of re-programming is slow.

RAM vs ROM –
1. RAM is volatile in nature as it is automatically erased when computer shuts down. ROM is
non-volatile since it is never erased when there is any shutdown or restart of computer.
2. RAM can be directly accessed by the processor. On the contrary, ROM cannot be directly
accessed by the processor, therefore it is transferred into RAM where it is executed by the
processor.
3. RAM is used to store the temporary information for limited time. ROM is used to store
permanent information that should not be deleted.
4. Writing data to a RAM chip is a faster process. Writing data to a ROM is a slow process.
5. A RAM chip can store multiple gigabytes (GB) of data, up to 16GB or more per chip. A
ROM can store only several megabytes (MB) of data, up to 4 MB or more per chip.
▪ Types of RAM are –Static and Dynamic RAM

▪ Types of ROM are PROM, EPROM and EEPROM