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Total No. of Questions : 8] SEAT No.

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PA-1191 [Total No. of Pages : 2

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S.E. (Electronics/E & T.C/Electronics & Computer)

1s
3:3
DIGITAL CIRCUITS

02 91
3:3
(2019 Pattern) (Semester-III) (204182)

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Time : 2½ Hours] 7/0 13 [Max. Marks : 70
0
Instructions to the candidates:
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1) Answer Q.1 or Q.2, Q.3 or Q.4, Q.5 or Q.6, Q.7 or Q.8.


2) Neat diagrams must be drawn wherever necessary.
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3) Figures to the right indicate full marks.
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Q1) a) Draw the logic diagram of full-adder and its truth table. [7]

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b) Implement a full-adder using Demultiplexer. [5]
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c) Implement the given logic function using a 4:1 multiplexer [5]
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3:3
30

f ( A, B, C ) =  m(0, 2, 4,6)
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01
02

OR
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Q2) a) Explain the working of a half-adder? Draw its logic diagram. [7]
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b) Implement the full subtractor using a 1:8 demultiplexer. [5]

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c) Implement the following function using multiplexer [5]


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f ( A, B, C ) =  m(0, 2, 4,6)
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3:3
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3:3

Q3) a) Design a sequence generator using T FFs. [8]


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b) Explain the types of shift register. [5]


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c) Explain with diagram the working of D type Flip-flop. Give its truth table.
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[5]
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OR
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Q4) a) Design a 3-Bit synchronous counter using JK FF. [8]


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b) With the neat diagram, explain the working operation of 4-bit SISO. [5]
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c) Explain S-R flip-flop using NOR gates. [5]


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P.T.O.
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8
Q5) a) Design the clocked sequential circuit for the state diagram using JK flip

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flop. [9]

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3:3
02 91
3:3
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b) Draw ASM chart for 2 bit binary counter having one enable line E such
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that: E=1, [8]

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c) Count Enable and E=0, Count Disable.
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OR
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3:3
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Q6) a) Design a sequence detector to detect a sequence 1101 using D FF [9]
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3:3
30

(Use Moore machine).


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b) Explain in short: [8]


02

i) State Assignment
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ii) ASM chart


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Q7) a) Explain the classification based on their physical characteristics. [8]

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b) Explain the concept of PLA with the help of a block diagram. [10]
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OR
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Q8) a) Explain the meaning of static and dynamic memories. State their
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3:3

applications. [8]
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b) Describe with neat diagram AND-OR structure of PLA and PAL. [10]
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
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