LA-H281PR10_MB_TR_0409C (1)

A B C D E
COMPAL
CONFIDENTIAL
MODEL NAME : EDA70 Vinafix.com
1 1
PCB NO : LA-H281P
BOM P/N : 451AG431L01
GPIO MAP: X10_CFLH_GPIO map Rev1.5_20181224
WHITEHAVEN MLK 17
Coffee Lake-R type (2 chip)
2 2
REV : 1.0(A00)
2019.4.10
Pop Component
EMI@, RF@, ESD@ : EMI/ESD/RF part POP
CONN@ : Connector Component
XDP@ : Total debug Component (pop them until ST)
3
NDS3@ : non Deep sleep support 3
eSPI@ : eSPI interface

RTD3@ : TBT RTD3 support
Layout Dell logo
@ : Nopop Component
@EMI@, @RF@, @ESD@ : EMI/ESD/RF part nopop
DS3@ : Deep sleep support
COPYRIGHT 2017
ALL RIGHT RESERVED
REV: X00
LPC@ : LPC interface
4
PWB: XXXXX
DATE: 1707-03 NRTD3@ : non TBT RTD3 support 4
PCB 26K LA-H281P REV0 MB AR 3

Part
Number Description
DELL CONFIDENTIAL/PROPRIETARY
DAB0004E000 PCB 26K LA-H281P REV0 MB AR 3
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
Cover
Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
1.0
Power CKT: LA-H281P
0108 Date: Tuesday, April 09, 2019 Sheet 1 of 103
A B C D E
A B C D E
I_eDP
eDP Panel SW1_eDP eDP MUX eDP
Conn PS8331 D_eDP A=C, N=D DDI1 (DDR4) Memory Bus DDR4 ECC-SO-DIMM X4
Intel BANK 0, 1, 2, 3, 4 ,5 ,6 ,7 P.23~26
P.38 P.29
Vinafix.com DDI2
CPU_DP2
1.2V DDR4 2400/2667MHz (Overclocking)
DDI3 CoffeeLake-H
1
CPU_DP1 PEG
6+2e BGA CPU 1
DP MUX1 1440 Pins

Type-C SW3_DP1 PS8461 PEG x8
Conn DP1.4 P.31 GPU_DP1 DP DEMUX (0~7) 42X28mm 45W
TBT
CPU_DP3
P.45 PS8338
Titan P.30
mDP
P.6~13
Type-C Ridge SW4_DP2 DP MUX2 PEG x8
DP SW2_DP2_2_1
Conn PS8461 (8~15) DMI x4 USB3 Port 1
P.45 P.42~45 HDMI
DP1.4 P.31 GPU_DP2 gen 3 USB 3.1 JUSB1
SW2_DP2_2_2
Right side
JDGFF1 JDGFF4 JDGFF2 JDGFF3 USB2 Port 1 USB Power Share
PD Cypress SLGC55544CVTRP.71 USB Charger
CCG5 P.71
CYPD5225 P.44
USB3 Port 3
P.28 JIO1 JDGFF1 P.27 JDGFF2 JDGFF3
USB2 Port4~ 5 USB 3.1 JUSB2
Right Side
HDMI2.0 DGFF CARD HDMI2.0 DGFF CARD USB2 Port 2 USB Power Share USB Charger
SLGC55544CVTRP.71
Conn UMA Conn A=E, N=C DSC Intel P.71
2 PS175 HDMI CannonLake-H 2
mDP 1.2 mDP

mDP 1.4 CM246
Conn PS8330 Conn A=D, N=E USB3.1
BGA
874 Pins
PCIE BUS 24X25mm
Port 6 Port 5 Port 1~4 Port 13~16 Port 21~24 Port 17~20 Port 9~12 Port8 Port 7 USB2.0
RTS5243 Intel Jacksonville M.2 Card M.2 Card M.2 Card M.2 Card M.2 Card M.2 Card
WGI219LM TBT DP slot_6 slot_5 slot_4 slot_3 slot_2 slot_1
SD5.1/MMC Titan Ridge SSD/ SSD/ SSD/ SSD/ WWAN/LTE WLAN/BT
P.51 NVME Optane Optane Optane /Cache /WiGig
P.70 HD
P.42~45 P.68 P.68 P.67 P.67 P.52 P.52 P.14~22
SATA Port0B SATA Port4 SATA Port1A USB2 Port8 USB2 Port 6
Audio USB2 Port 11 Digital Camera
RJ45 P.38
SDXC P.70 P.51 USB3 Port2
Micro SIM
SPI
Card P.52
SATA Winbon sop8 P.17
eSPI
Interposer board Golden Finger W25Q256FVFIQ
3 256Mb 4K sector 3
SATA redriver
PI3EQX6741ST
TDA8034HN
USB Port 10 LYNX(CV2)
TPM2.0 P.41
BRCM58102
NPCT750JABYXF Smart Card
GPIO Expander P.65
ITE IT8306 I2C BUS change model name SPI RFID/NFC
P.59
SMSC KBC SPI Fingerprint
MEC5106 CONN
On USH/B
P.58
change model name
I2C BUS
FAN CONN Universal Jack P.56

Free Fall Sensor Audio Codec
P.77 KB/TP
CONN LNG2DMTR ALC3281 Int. Speaker P.56
P.62 P.54 P.56
4 4
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT Block Diagram
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-H281P 1.0
Date: Tuesday, April 09, 2019 Sheet 2 of 103
A B C D E
5 4 3 2 1
POWER STATES
Signal SLP SLP SLP S4 ALWAYS RUN USB2 PORT# DESTINATION
S3# S4# S5# STATE# PLANE PLANE CLOCKS
State
1 JUSB1
S0 (Full ON) / M0 HIGH HIGH HIGH HIGH ON ON ON
Vinafix.com 2 JUSB2
D
S3 (Suspend to RAM) / M1 LOW HIGH HIGH HIGH ON OFF OFF D
3 JUSB3
S4 (Suspend to DISK) / M1 LOW LOW HIGH LOW ON OFF OFF
4 Cypress PD
S5 (SOFT OFF) / M1 LOW LOW LOW LOW ON OFF OFF
5 Cypress PD
S3 (Suspend to RAM) / M-OFF LOW HIGH HIGH HIGH ON OFF OFF
6 NA
S4 (Suspend to DISK) / M-OFF LOW LOW HIGH LOW ON OFF OFF PCH
7 NA
S5 (SOFT OFF) / M-OFF LOW LOW LOW LOW ON OFF OFF
8 M.2 Slot-2 (WWAN/LTE)
PM TABLE 9 17" NA/ 15" Touch screen
+PWR_SRC +3.3V_SUS +5V_RUN (M-OFF)
+5V_ALW +1.2V_MEM +3.3V_RUN +VCC_CORE 10 USH
C
+3.3V_ALW +2.5V_MEM +1.2V_RUN +VCC_GT C
power
plane +3.3V_ALW2 +1.0V_VCCST +3.3V_DGFF +VCC_IO 11 Camera
+3.3V_ALW_DSW +5V_DGFF +VCC_SA
+3.3V_ALW_PCH +DGFF_PWR_SRC +1.0V_VCCSTG 12 NA
+3.3V_RTC_LDO +0.675V_DDR_VTT +1.8V_RUN
+1.8V_ALW 13 NA
State
+1.0V_PRIM
+1.8V_PRIM 14 M.2 Slot-1 (BT)
S0 ON ON ON ON
0 BIO
S3 ON ON OFF OFF USH
1 NA
S5 S4/AC ON OFF OFF OFF
S5 S4/AC don't exist OFF OFF OFF OFF PCI EXPRESS DESTINATION
B PORT 1~4 TBT-Titan Ridge B
PORT 5 10/100/1G LOM

USB3.0 DESTINATION SATA DESTINATION
Port 1 JUSB1 SATA 0B SLOT6 SSD PORT 6 MMI(Card reader)
PORT 7 M.2 Slot-1 (WLAN/Wigig)

Port 2 M.2 Slot-2 (WWAN/LTE) SATA 1A SLOT3 SSD
PORT 8 M.2 Slot-2 (WWAN/LTE)
Port 3 JUSB2 SATA 2 NA
PORT9~12 SLOT3 SSD 2280/ Optane
Port 4 JUSB3 SATA 3 NA
PORT13~16 SLOT6 SSD 2280/NVME
Port 5 NA SATA 4 SLOT4 SSD/HDD
Port 6 NA SATA 5 NA PORT17~20 SLOT4 SSD 2280/ Optane

A PORT21~24 SLOT5 PCIE only 2280/ Optane A
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT Notes List
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Size Document Number Rev
LA-H281P 1.0

5 4 3 2 1
5 4 3 2 1
TYPE-C
+5V_ALW +TBTB_VBUS(5V~20V)
CYPD5225
+Vbus_1(5V~20V) (UT5) +TBTA_VBUS(5V~20V)
+Vbus_2(5V~20V)
Vinafix.com
D
EN_INVPWR DMP3050LVT D
(QV1) +BL_PWR_SRC
3.3V_RUN_GFX_ON
+3.3V_ALW +TBTA_VBUS
AO4435L RT9069
+DGFF_PWR_SRC (UT7) +3.3V_VDD_PIC
(QZ19)
+TBTB_VBUS
IMVP_VR_ON NCP81215MNTXG
+VCC_CORE +VCC_GT +VCC_SA
(PU1100) +DC_IN
+3.3V_TBT_SX
RUN_ON_EC RUN_ON SY8288RAC
SIO_SLP_S3# +1.0VS_VCCIO +PWR_SRC
ADAPTER (PU300)
SIO_SLP_S0# TPS22961
RUN_ON (UZ19) +1.0V_VCCSTG
+PWR_SRC
BATTERY
SIO_SLP_S4# TPS22961
+1.0V_PRIM +1.0V_VCCST
(UZ21)
PCH_PRIM_EN TPS51212
(PU800)
ALWON TPS51285B
RUN_ON EM5209VF
C (PU101) +5V_RUN +5V_RUN_AUDIO C
+5V_ALW (UZ40)
CHARGER
ALWON HDD_IFDET
ALWON RUN_ON
AOZ1336 +5V_HDD
(UZ23)
+5V_ALW2
SY8288BRAC TPS51285B USB_POWERSHARE_EN# SLGC55544CVTR
+3.3V_ALW2 +5V_USB_PWR1
(PU501) (PU100) (UI3)
3.3V_RUN_GFX_ON_EC
EM5209VF +5V_DGFF
SY8288CRAC +5V_ALW_R (UZ41)
+3.3V_ALW_R
SIO_SLP_S4#
USB_POWERSHARE_EN# SLGC55544CVTR
+3.3V_ALW (PU500) +5V_USB_PWR2
(UI1)
USB_POWERSHARE_EN# SLGC55544CVTR
+5V_USB_PWR3
(UI2)
SLOT6_SSD_PWR_EN
SLOT3_SSD_PWR_EN
SLOT5_SSD_PWR_EN
SLOT4_SSD_PWR_EN
LCD_VCC_TEST_EN
RT8207
3.3V_RUN_GFX_ON_EC
3.3V_WWAN_EN
SIO_SLP_WLAN#
AUX_EN_WOWL
SIO_SLP_LAN#
(PU200)
DGFF_ENVDD
PCH_ALW_ON
ENVDD_PCH
PCH_PRIM_EN
SIO_SLP_S4#
RUN_ON
B B
EM5209VF
EM5209VF AOZ1336 EM5209VF EM5209VF AOZ1336 AOZ1336 AOZ1336 G524B1T11U SY8003DFC SY8003DFC
(UZ44)
(UZ9) (UZ58) (UZ41) (UZ40) (UZ42) (UZ7) (UZ59) (UV24) (PU900) (PU400)
+0.6V_DDR_VTT +1.2V_MEM
+3.3V_LAN
+3.3V_RUN +LCDVDD +1.8V_PRIM +2.5V_MEM

+3.3V_DGFF
PCH_PRIM_EN
+3.3V_SSD4
+3.3V_WLAN
+3.3V_WWAN
+3.3V_ALW_PCH
+3.3V_SSD6
SIO_SLP_S4#
SIO_SLP_S4#
+3.3V_SSD3
+3.3V_SSD5
3.3V_CAM_EN#
RUN_ON
AOZ1336
+3.3V_RUN_AUDIO
AOZ1336 AOZ1336
(UZ45)
(UZ26) (UZ43) LP2301ALT1G
(QZ1)
+1.8V_RUN
+VCC_SFR_OC
+1.2V_RUN
A
+CAMERA_VDD A
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Power MAP
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
1.0
LA-H281P
5 4 3 2 1
5 4 3 2 1
Timing Diagram for S5 to S0 mode Power Button
CPU
1BAT 2AC
12
VCCST_PWRGD Vinafix.com +VCC_CORE
VCCST_PWRGD VCC ADAPTER
+PWR_SRC
D +1.0VS_VCCIO ALWON
+5V_ALW2 D
VCCIO
EC 5105 SYX198
H_PWRGD
+5V_ALW
15 PROCPWRGD +VCC_GT 1BAT
VCCGT +PWR_SRC
PCH_PLTRST#
+3.3V_RTC_LDO
+1.35V_MEM 2AC
17 PLTRST#
VDDQ BATTERY SYX198
+3.3V_ALW2
VDDQC +3.3V_ALW
0.6V_DDR_VTT_ON VCCPLL_OC +1.0V_PRIM
12 DDR_VTT_CNTL +1.0V_VCCST 11 SIO_SLP_S0#
VCCST TPS22961
VCCSTG
VCCPLL
+VCC_SA
RUN_ON
PCH_RSMRST# 5
VCCSA
7 SIO_SLP_SUS#
+3.3V_ALW
PCH_DPWROK
4 EM5209VF
@PCH_ALW_ON +3.3V_ALW_PCH 5
RESET_OUT#
+1.0V_PRIM 16
VCCPRIM_1P0
VCCPRIM_CORE
PCH PWRBTN#
SIO_PWRBTN# 8 Pop option
DCPDSW_1P0 +3.3V_SPI
VCCAPLL_1P0
RSMRST#
PCH_RSMRST#
7 5 SIO_SLP_SUS#
VCCCLK1~6
VCCMPHYGT_1P0 SLP_SUS#
SIO_SLP_SUS#
5 10 SIO_SLP_S4#
VCCSRAM_1P0 SIO_SLP_S5# SIO_SLP_S5#

C
VCCAMPHYPLL_1P0
VCCAPLLEBB
SLP_S5#
9 9 C
+3.3V_ALW +3.3V_ALW_DSW SIO_SLP_S4# SIO_SLP_LAN#

3 VCCDSW_3P3
SLP_S4# 10
+3.3V_SPI 5 +3.3V_ALW_PCH SLP_S3#
SIO_SLP_S3#
11 SIO_SLP_S3# +PWR_SRC
VCCHDA
VCCSPI SLP_A#
SIO_SLP_A# SIO_SLP_A# EN_INVPWR
AO6405 +BL_PWR_SRC 18
VCCPRIM_3P3
VCCPGPPA~E
VCCRTCPRIM
SLP_LAN#
SIO_SLP_LAN#
11 +PWR_SRC
6 +1.8V_PRIM SLP_WLAN#/GPD9
SIO_SLP_WLAN#
12 SIO_SLP_S4#
VCCPGPPA RESET_OUT#
+VCC_SA IMVP_VR_ON +PWR_SRC
+RTC_CELL
SYS_PWROK
16 13 +VCC_CORE ISL95857
PCH_PWROK +VCC_GT +1.2V_MEM
VCCRTC PCH_PWROK VDDQ
PCH_PLTRST#
14 RT8207MZ
+0.6V_DDR_VTT VTT
DDR
17 PLTRST# VCCST_PWRGD
VCCST_PWRGD
12 PCH_PWROK
12
PCH_DPWROK 0.6V_DDR_VTT_ON
4 DSW_PWROK H_PWRGD 14
PROCPWRGD
15
+3.3V_ALW
ENVDD_PCH
+LCDVDD AP2821K EDP_VDDEN
B
EC 5105 B
+3.3V_ALW 11 SIO_SLP_WLAN#
11
SIO_SLP_LAN# +5V_ALW
11 +3.3V_LAN EM5209VF SLP_LAN#
RUN_ON
+5V_RUN +5V_HDD
EM5209VF
+3.3V_RUN +3.3V_ALW
3.3V_CAM_EN#
+3.3V_CAM LP2301ALT1G GPD7 EM5209VF +3.3V_RUN +3.3V_HDD
+PWR_SRC
+3.3V_ALW @SIO_SLP_WLAN# TLV62130 +1.0VS_VCCIO

+PWR_SRC
+1.0V_PRIM SIO_SLP_SUS#
6 TLV62130 11 +3.3V_WLAN EM5209VF AUX_EN_WOWL
+3.3V_ALW
A
6 +1.8V_PRIM
TLV62130
A
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
Power Sequence
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. Size Document Number Rev
LA-H281P 1.0
5 4 3 2 1
5 4 3 2 1
Vinafix.com
D D
CFL-H
UC1C
PEG_CRX_GTX_P15 E25 B25 PEG_CTX_GRX_P15 CC34 1 2 0.22U_0402_16V7K PEG_CTX_C_GRX_P15
PEG_CRX_GTX_N15 D25 PEG_RXP_0 PEG_TXP_0 A25 PEG_CTX_GRX_N15 CC35 1 2 0.22U_0402_16V7K PEG_CTX_C_GRX_N15
PEG_RXN_0 PEG_TXN_0
PEG_CRX_GTX_N14 F24 PEG_RXP_1 PEG_TXP_1 C24 PEG_CTX_GRX_N14 CC37 1 2 0.22U_0402_16V7K PEG_CTX_C_GRX_N14
PEG_RXN_1 PEG_TXN_1
PEG_RXN_2 PEG_TXN_2
PEG_RXN_3 PEG_TXN_3
PEG_RXN_4 PEG_TXN_4
PEG_RXN_5 PEG_TXN_5
PEG_CRX_GTX_P[0..15] PEG_CRX_GTX_N9 D19 PEG_RXP_6 PEG_TXP_6 A19 PEG_CTX_GRX_N9 CC47 1 2 0.22U_0402_16V7K PEG_CTX_C_GRX_N9
PEG_CRX_GTX_P[0..15] <27> PEG_RXN_6 PEG_TXN_6
PEG_CRX_GTX_N[0..15] PEG_CRX_GTX_P8 E18 B18 PEG_CTX_GRX_P8 CC48 1 2 0.22U_0402_16V7K PEG_CTX_C_GRX_P8
PEG_CRX_GTX_N[0..15] <27> PEG_CRX_GTX_N8 PEG_RXP_7 PEG_TXP_7 PEG_CTX_GRX_N8 PEG_CTX_C_GRX_N8
F18 C18 CC49 1 2 0.22U_0402_16V7K
PEG_RXN_7 PEG_TXN_7
PEG_CTX_C_GRX_P[0..15] PEG_CRX_GTX_P7 D17 A17 PEG_CTX_GRX_P7 CC50 1 2 0.22U_0402_16V7K PEG_CTX_C_GRX_P7
PEG_CTX_C_GRX_P[0..15] <27> PEG_CRX_GTX_N7 E17 PEG_RXP_8 PEG_TXP_8 B17 PEG_CTX_GRX_N7 CC51 1 2 0.22U_0402_16V7K PEG_CTX_C_GRX_N7
C PEG_CTX_C_GRX_N[0..15] PEG_RXN_8 PEG_TXN_8 C
PEG_CTX_C_GRX_N[0..15] <27> PEG_CRX_GTX_P6 F16 C16 PEG_CTX_GRX_P6 CC52 1 2 0.22U_0402_16V7K PEG_CTX_C_GRX_P6
PEG_CRX_GTX_N6 E16 PEG_RXP_9 PEG_TXP_9 B16 PEG_CTX_GRX_N6 CC53 1 2 0.22U_0402_16V7K PEG_CTX_C_GRX_N6
PEG_RXN_9 PEG_TXN_9
PEG_CRX_GTX_P5 D15 A15 PEG_CTX_GRX_P5 CC54 1 2 0.22U_0402_16V7K PEG_CTX_C_GRX_P5
PEG_RXN_10 PEG_TXN_10
PEG_CRX_GTX_P4 F14 C14 PEG_CTX_GRX_P4 CC56 1 2 0.22U_0402_16V7K PEG_CTX_C_GRX_P4
+1.0VS_VCCIO PEG_RXN_15 PEG_TXN_15
1 2 PEG_COMP G2
RC2 24.9_0402_1% PEG_RCOMP
Trace width=5 mils

,Spacing=15mil DMI_CRX_PTX_P0 D8 B8 DMI_CTX_PRX_P0 DMI_CTX_PRX_P0 <15>
<15> DMI_CRX_PTX_P0 DMI_RXP_0 DMI_TXP_0
B Max length= 600 mils. <15> DMI_CRX_PTX_N0
DMI_CRX_PTX_N0 E8
DMI_RXN_0 DMI_TXN_0
A8 DMI_CTX_PRX_N0 DMI_CTX_PRX_N0 <15>
B
DMI_CRX_PTX_P1 E6 C6 DMI_CTX_PRX_P1 DMI_CTX_PRX_P1 <15>

<15> DMI_CRX_PTX_P1 DMI_CRX_PTX_N1 DMI_RXP_1 DMI_TXP_1 DMI_CTX_PRX_N1
F6 B6 DMI_CTX_PRX_N1 <15>
<15> DMI_CRX_PTX_N1 DMI_RXN_1 DMI_TXN_1
DMI_CRX_PTX_P2 D5 B5 DMI_CTX_PRX_P2 DMI_CTX_PRX_P2 <15>
<15> DMI_CRX_PTX_P2 DMI_CRX_PTX_N2 DMI_RXP_2 DMI_TXP_2 DMI_CTX_PRX_N2
E5 A5 DMI_CTX_PRX_N2 <15>
DMI_CRX_PTX_P3 J8 D4 DMI_CTX_PRX_P3 DMI_CTX_PRX_P3 <15>
<15> DMI_CRX_PTX_P3 DMI_CRX_PTX_N3 DMI_RXP_3 3 OF 13 DMI_TXP_3 DMI_CTX_PRX_N3
J9 B4 DMI_CTX_PRX_N3 <15>
CFL-H_BGA1440
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2017/01/01 Title
2016/01/01 Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CFL-H(1/8) DMI,PEG
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS A 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-H281P
5 4 3 2 1
5 4 3 2 1
+1.05V_PRIM +1.0V_PRIM_XDP
CFG11 CFG10
1
+3.3V_ALW_PCH @ RC216 1 2 0_0603_5% DMI_AC_coupled SAFE mode boot
CPU XDP @
RC441
@
RC440
XDP@ RC133
* HALF-SWING * enable
1.5K_0402_5%
1K_0402_5% 1 1K_0402_5% 1
1
+1.0V_PRIM_XDP
DC coupled
XDP@
2
+1.0V_PRIM_XDP XDP_PRSNT_PIN1 1 2 CFG3 FULL-SWING disable
RC121 1K_0402_5% +1.0V_PRIM_XDP
AC coupling 0 0
Vinafix.com
1 2
2
@ RC122 0_0402_5%
SYS_PWROK_R
0.1U_0402_25V6
0.1U_0402_25V6
JXDP1 CONN@
1 1 1 2 +1.0VS_VCCIO
3 1 2 4 CFG12 @ RC439
0.1U_0402_25V6
@ CC28
@ CC29
1 CPU_XDP_PREQ# CFG17
D CFG9 1 2 D
CPU_XDP_PRDY# 5 3 4 6
@ CC33
Place near JXDP1.47 CFG16 SVID NOT Present
1
7 5 6 8 1K_0402_5%
1
2 2 CFG0 9 7 8 10 CFG8 @
2 CFG1 11 9
13 11
10 12
12 14
CFG9 RC442
*
1K_0402_5% PMSYNC2.0 1
@ RC438
1K_0402_5%
* Present 1
CFG2 15 13 14 16 CFG10
2
17 15 16 18
2
CFG3 CFG11
19 17 18 20 LEGACY 0 Not presnet 0
Place near JXDP1 XDP_OBS0_R 21 19 20 22 CFG19
XDP_OBS1_R 23 21 22 24 CFG18
+3.3V_ALW_R 25 23 24 26
CFG4 27 25 26 28 CFG12
CFG5 29 27 28 30 CFG13 CFG8
31 29 30 32
1
1.5K_0402_5%
XDP@ RC241
1
CFG6 33 31 32 34 CFG14 CFG UNLOCK
CFG7 35 33 34 36 CFG15 @
<18,62> PCH_RSMRST#_AND 37 35 36 38 RC437
XDP@ RC124 1 2 1K_0402_5% H_VCCST_PWRGD_XDP 39 37 38 40 PCH_XDP_CLK_DP 1K_0402_5% * disable 1
PCH_XDP_CLK_DP <16>
2
SIO_PWRBTN# 41 39 40 42 PCH_XDP_CLK_DN
2
<18,58> SIO_PWRBTN# PCH_XDP_CLK_DN <16>
SIO_PWRBTN# FIVR_EN @ RC217 1 2 0_0402_5% 43 41 42 44
CFG0 XDP@ RC126 1 2 1K_0402_5% FIVR_EN_R 45 43 44 46 CPU_XDP_HOOK6 1 2 ITP_PMODE_CPU
ITP_PMODE_CPU <18>
enable 0
SYS_PWROK_R 47 45 46 48 XDP_DBRESET# @XDP@ RC144 0_0402_5%
0.1U_0402_25V6
XDP@ CC269
XDP@ RC128 1 2 1K_0402_5%

<17> PCH_SPI_D0
@ RC129 1 2 0_0402_5% 49 47 48 50
1 Place near JXDP1.41 <18,58> SYS_PWROK
51 49 50 52 CPU_XDP_TDO
XDP_DBRESET# <15>
<18,23,24,25,26,54> DDR_XDP_WAN_SMBDAT
53 51 52 54 CPU_XDP_TRST#
CPU_XDP_TRST# <20> CFG1
<18,23,24,25,26,54> DDR_XDP_WAN_SMBCLK
55 53 54 56 CPU_XDP_TDI
<18> PCH_JTAG_TCK
2 CPU_XDP_TCLK 57 55 56 58 CPU_XDP_TMS PCHLESS MODE (CRB)
1
59 57 58 60 CPU_XDP_PRS 1 2 PCH_SPI_D2_XDP Reserved CFG lane (EDS)
PCH_SPI_D2_XDP <17> @
61 59 60 XDP@ RC127 0_0402_5%
RC436
CPU_XDP_TDO H_VCCST_PWRGD_XDP CPU_XDP_TRST#
61
Change to 0 ohm 3/29 1K_0402_5% * NORMAL 1
0.1U_0402_25V6
@ESD@
62 63
2
GND GND
0.1U_0402_25V6
@ESD@
0.1U_0402_25V6
@ESD@
PCHLESS 0
1
+1.0V_PRIM_XDP
1
1
JXT_FP270H-061G1AM
C C
CPU_XDP_HOOK6 1 2
2
+1.0V_PRIM_XDP
CC306
XDP@ RC115 2.2K_0402_5%

2
2
CC307
CC308
+3.3V_ALW_PCH CFG0
CFG13
1 2 CPU_XDP_PREQ#
Stall reset sequence after PCU
1
XDP_DBRESET# 1 2
1
@ RC138 51_0402_5% SYNC & AYNC MODE PLL lock until de-asserted
RC137 3K_0402_5% @ @
RC321
+1.0VS_VCCIO PCH_JTAG_TMS PCH_XDP_PRDY# PCH_XDP_PREQ# +1.0V_VCCSTG RC443
*
1K_0402_5% ASYNCHRONOUS 1 1K_0402_5% * No Stall 1
CPU_XDP_TDO 1 2
0.1U_0402_25V6
@ESD@
0.1U_0402_25V6
@ESD@
0.1U_0402_25V6
@ESD@
2
2
1 2 FIVR_EN_R RC135 51_0402_5%
SYNCHRONOUS Stall 0
1
RC132 150_0402_5% CPU_XDP_TRST# 1 2 0

+1.0V_VCCSTG @ RC136 51_0402_5%
2
2
CC336
CC337
CC338
CPU_XDP_TCLK 1 2
RC139 51_0402_5% CFG2
1 2 PROCHOT#
RC83 1K_0402_5% XDP_DBRESET#
1
PEG LANE REVERSAL
+1.0V_VCCST
0.1U_0402_25V6
XDP@ CC32
Add ESD part 1 RC181
ESD request,Place near JXDP1 side. CFL-H
1 2 H_THERMTRIP# UC1E
1K_0402_5% NORMAL 1
2
RC80 1K_0402_5%
1 2 PCH_JTAGX 2 LANE
@ RC166 1K_0402_5% CPU_XDP_TMS 1 2 PCH_JTAG_TMS PCH_CPU_BCLK_R_D B31 BN25 CFG0 * REVERSED 0
PCH_JTAG_TMS <18> <16> PCH_CPU_BCLK_R_D BCLKP CFG_0
1 2 VCCST_PWRGD @RC228 0_0402_5% PCH_CPU_BCLK_R_D# A32 BN27 CFG1
RC71 1K_0402_5% CPU_XDP_TDI 1 2 <16> PCH_CPU_BCLK_R_D# BCLKN CFG_1
PCH_JTAG_TDI <18> BN26 CFG2
1 2 H_CATERR# @RC229 0_0402_5% PCH_CPU_PCIBCLK_R_D D35 CFG_2 BN28 CFG3
@ RC79 49.9_0402_1% CPU_XDP_TDO 1 2 <16> PCH_CPU_PCIBCLK_R_D PCH_CPU_PCIBCLK_R_D# C36 PCI_BCLKP CFG_3 BR20
PCH_JTAG_TDO <18> CFG4 CFG4
@RC230 0_0402_5% <16> PCH_CPU_PCIBCLK_R_D# PCI_BCLKN CFG_4 BM20 CFG5
+1.0V_VCCST CPU_XDP_TCLK 1 2 CFG_5 eDP enable
1
CPU_24MHZ_R_D E31 BT20 CFG6
PCH_JTAGX <18> <16> CPU_24MHZ_R_D CLK24P CFG_6
@RC143 0_0402_5% CPU_24MHZ_R_D# D31 BP20 CFG7
1 2 FIVR_EN CPU_XDP_PRDY# 1 2 PCH_XDP_PRDY# <16> CPU_24MHZ_R_D# CLK24N CFG_7 BR23 CFG8
@ RC218 150_0402_5% @RC314 0_0402_5%
PCH_XDP_PRDY# <20> CFG_8 BR22 CFG9
RC322 Disabled 1
CFG_9 1K_0402_5%
CPU_XDP_PREQ# 1 2 PCH_XDP_PREQ# BT23 CFG10
1 2 FIVR_EN PCH_XDP_PREQ# <20> CFG_10
2
B @RC315 0_0402_5% BT22 CFG11 B
@ RC219 10K_0402_5% CFG_11 BM19 CFG12 * Enabled 0
CFG_12 BR19 CFG13
CFG_13 BP19 CFG14
PCH_JTAGX CPU_VIDALERT# BH31 CFG_14 BT19 CFG15
1 2 VIDALERT# CFG_15
@ESD@ CC305 0.1U_0201_25V6K VR_SVID_CLK BH32
<90> VR_SVID_CLK VIDSCK
PCH_JTAG_TDI 1 2 VR_SVID_DATA BH29 BN23 CFG17 CFG5
PROCHOT# 1 2 H_PROCHOT#_R BR30 VIDSOUT CFG_17 BP23 CFG16
@ESD@ CC304 0.1U_0201_25V6K <27,58,83,85,90> PROCHOT# PROCHOT# CFG_16
1
PCH_JTAG_TDO 1 2 RC84 499_0402_1% BP22 CFG19 PCI Express* Bifurcation
+1.0V_VCCST DDR_VTT_CTRL BT13 CFG_19 BN22 CFG18
@ESD@ CC303 0.1U_0201_25V6K <23> DDR_VTT_CTRL DDR_VTT_CNTL CFG_18 @ [6:5]
RC323
ESD request,Place near JXDP1 side 1K_0402_5%
BR27 XDP_OBS0 @ RC239 1 2 0_0402_5% XDP_OBS0_R
BPM#_0 1x8, 2x4 00
2
1
BT27 XDP_OBS1 @ RC240 1 2 0_0402_5% XDP_OBS1_R

56.2_0402_1%
100_0402_5%
BPM#_1 BM31
RC152
RC157
VCCST_PWRGD 1 2 VCCST_PWRGD_CPU H13 BPM#_2 BT30

<59> VCCST_PWRGD
RC78 60.4_0402_1% VCCST_PWRGD BPM#_3 Reserved 01
CFG6
H_PWRGD BT31
<18> H_PWRGD PROCPWRGD
2
1
VR_SVID_DATA PLTRST_CPU# BP35 BT28 CPU_XDP_TDO 1
<90> VR_SVID_DATA <14> PLTRST_CPU# H_PM_SYNC BM34 RESET# PROC_TDO BL32 CPU_XDP_TDI 1 PAD~D @ T184 2x8 10
<14> H_PM_SYNC PM_SYNC PROC_TDI PAD~D @ T185 @
VR_SVID_ALERT# H_PM_DOWN 1 2 H_PM_DOWN_R BP31 BP28 CPU_XDP_TMS 1 RC324
<90> VR_SVID_ALERT# <14> H_PM_DOWN PM_DOWN PROC_TMS PAD~D @ T180
H_PECI CPU_XDP_TCLK
<14,58> H_PECI RC168 20_0402_5% BT34
PECI PROC_TCK
BR28 1
PAD~D @ T181 1K_0402_5%
* 1x16 11
1
H_THERMTRIP# 1 2 H_THERMTRIP#_R J31

220_0402_5%
<14,23,24,25,26,59> H_THERMTRIP# THERMTRIP#
2
@ RC169 0_0402_5% BP30 CPU_XDP_TRST# 1
RC153
@ RC319 1 PROC_TRST# PAD~D @ T179

2 0_0402_5% H_SKTOCC# BR33 BL30 CPU_XDP_PREQ#1
SKTOCC# PROC_PREQ# CPU_XDP_PRDY#1 PAD~D @ T190
BN1 BP27
1 2 SKL_CNL# PROC_SELECT# PROC_PRDY# PAD~D @ T189
VR_SVID_DATA
pop RC171 for CNL
2
@ RC171 0_0402_5% H_CATERR# BM30

depop RC171 for SKL & KBL (CFL CRB rev0.7) CATERR# BT25
CPU_VIDALERT# 1 AT13 CFG_RCOMP
PAD~D @ T26 ZVM# CFG7
1 AW13
PAD~D @ T25 MSM#
1
PEG Training
1 AU13 RC114 @
PAD~D @ T31 1 AY13 RSVD1 49.9_0402_1%
PAD~D @ T32 RSVD2 RC325 (default) PEG Train
A 5 OF 13
1K_0402_5%
* immediately following
RESET# de-assertion
1 A
2
CFL-H_BGA1440 PEG Wait for BIOS for
H_PWRGD VCCST_PWRGD H_THERMTRIP# PROCHOT#
training 0
RF Request
0.1U_0402_25V6
@ESD@
0.1U_0402_25V6
@ESD@
100P_0402_50V8J
ESD@
100P_0402_50V8J
ESD@
1
1
VR_SVID_CLK 1 2 DELL CONFIDENTIAL/PROPRIETARY

CC300
CC301
@RF@ CC325 33P_0402_50V8J Security Classification Compal Secret Data Compal Electronics, Inc.
2
2
2
CC323
CC324

CFL-H(2/8) XDP
Place close CPU side AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
ESD Request:place near CPU side B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5 4 3 2 1
5 4 3 2 1
Vinafix.com UC1B
CFL-H
DDR CHANNEL B
D <25,26> DDR_B_D[0..63] DDR4(IL)/LP3-DDR4(NIL) LP3/DDR4
D
CFL-H DDR_B_D0 BT11 AM9 DDR_B_CLK0
DDR_B_D1 DDR1_DQ_0/DDR0_DQ_16 DDR1_CKP_0/DDR1_CKP_0 DDR_B_CLK#0 DDR_B_CLK0 <26>
UC1A BR11 AN9
DDR_B_D2 BT9 DDR1_DQ_1/DDR0_DQ_17 DDR1_CKN_0/DDR1_CKN_0 AM7 DDR_B_CLK1 DDR_B_CLK#0 <26>
DDR CHANNEL A DDR_B_D3 DDR1_DQ_2/DDR0_DQ_18 DDR1_CKP_1/DDR1_CKP_1 DDR_B_CLK#1 DDR_B_CLK1 <26>
BR8 AM8
DDR4(IL)/LP3-DDR4(NIL) LP3/DDR4 DDR_B_D4 BP11 DDR1_DQ_3/DDR0_DQ_19 DDR1_CKN_1/DDR1_CKN_1 AM11 DDR_B_CLK2 DDR_B_CLK#1 <26>
<23,24> DDR_A_D[0..63] DDR_A_D0 BR6 AG1 DDR_A_CLK0 DDR_B_D5 BN11 DDR1_DQ_4/DDR0_DQ_20 NC/DDR1_CKP_2 AM10 DDR_B_CLK#2 DDR_B_CLK2 <25>
DDR_A_D1 BT6 DDR0_DQ_0/DDR0_DQ_0 DDR0_CKP_0/DDR0_CKP_0 AG2 DDR_A_CLK#0 DDR_A_CLK0 <24> DDR_B_D6 BP8 DDR1_DQ_5/DDR0_DQ_21 NC/DDR1_CKN_2 AJ10 DDR_B_CLK3 DDR_B_CLK#2 <25>
DDR_A_D2 BP3 DDR0_DQ_1/DDR0_DQ_1 DDR0_CKN_0/DDR0_CKN_0 AK2 DDR_A_CLK1 DDR_A_CLK#0 <24> DDR_B_D7 BN8 DDR1_DQ_6/DDR0_DQ_22 NC/DDR1_CKP_3 AJ11 DDR_B_CLK#3 DDR_B_CLK3 <25>
DDR_A_D3 DDR0_DQ_2/DDR0_DQ_2 DDR0_CKP_1/DDR0_CKP_1 DDR_A_CLK#1 DDR_A_CLK1 <24> DDR_B_D8 DDR1_DQ_7/DDR0_DQ_23 NC/DDR1_CKN_3 DDR_B_CLK#3 <25>
BR3 AK1 BL12
DDR_A_D4 BN5 DDR0_DQ_3/DDR0_DQ_3 DDR0_CKN_1/DDR0_CKN_1 AL3 DDR_A_CLK2 DDR_A_CLK#1 <24> DDR_B_D9 BL11 DDR1_DQ_8/DDR0_DQ_24 AT8 DDR_B_CKE0
DDR_A_D5 BP6 DDR0_DQ_4/DDR0_DQ_4 NC/DDR0_CKP_2 AK3 DDR_A_CLK#2 DDR_A_CLK2 <23> DDR_B_D10 BL8 DDR1_DQ_9/DDR0_DQ_25 DDR1_CKE_0/DDR1_CKE_0 AT10 DDR_B_CKE1 DDR_B_CKE0 <26>
DDR_A_D6 DDR0_DQ_5/DDR0_DQ_5 NC/DDR0_CKN_2 DDR_A_CLK3 DDR_A_CLK#2 <23> DDR_B_D11 DDR1_DQ_10/DDR0_DQ_26 DDR1_CKE_1/DDR1_CKE_1 DDR_B_CKE2 DDR_B_CKE1 <26>
BP2 AL2 BJ8 AT7
DDR_A_D7 DDR0_DQ_6/DDR0_DQ_6 NC/DDR0_CKP_3 DDR_A_CLK#3 DDR_A_CLK3 <23> DDR_B_D12 DDR1_DQ_11/DDR0_DQ_27 DDR1_CKE_2/DDR1_CKE_2 DDR_B_CKE3 DDR_B_CKE2 <25>
BN3 AL1 BJ11 AT11
DDR_A_D8 DDR0_DQ_7/DDR0_DQ_7 NC/DDR0_CKN_3 DDR_A_CLK#3 <23> DDR_B_D13 DDR1_DQ_12/DDR0_DQ_28 DDR1_CKE_3/DDR1_CKE_3 DDR_B_CKE3 <25>
BL4 BJ10
DDR_A_D9 BL5 DDR0_DQ_8/DDR0_DQ_8 AT1 DDR_A_CKE0 DDR_B_D14 BL7 DDR1_DQ_13/DDR0_DQ_29 AF11 DDR_B_CS#0
DDR_A_D10 BL2 DDR0_DQ_9/DDR0_DQ_9 DDR0_CKE_0/DDR0_CKE_0 AT2 DDR_A_CKE1 DDR_A_CKE0 <24> DDR_B_D15 BJ7 DDR1_DQ_14/DDR0_DQ_30 DDR1_CS#_0/DDR1_CS#_0 AE7 DDR_B_CS#1 DDR_B_CS#0 <26>
DDR_A_D11 DDR0_DQ_10/DDR0_DQ_10 DDR0_CKE_1/DDR0_CKE_1 DDR_A_CKE2 DDR_A_CKE1 <24> DDR_B_D16 DDR1_DQ_15/DDR0_DQ_31 DDR1_CS#_1/DDR1_CS#_1 DDR_B_CS#2 DDR_B_CS#1 <26>
BM1 AT3 BG11 AF10
DDR_A_D12 DDR0_DQ_11/DDR0_DQ_11 DDR0_CKE_2/DDR0_CKE_2 DDR_A_CKE3 DDR_A_CKE2 <23> DDR_B_D17 DDR1_DQ_16/DDR0_DQ_48 NC/DDR1_CS#_2 DDR_B_CS#3 DDR_B_CS#2 <25>
BK4 AT5 BG10 AE10
DDR_A_D13 DDR0_DQ_12/DDR0_DQ_12 DDR0_CKE_3/DDR0_CKE_3 DDR_A_CKE3 <23> DDR_B_D18 DDR1_DQ_17/DDR0_DQ_49 NC/DDR1_CS#_3 DDR_B_CS#3 <25>
BK5 BG8
DDR_A_D14 BK1 DDR0_DQ_13/DDR0_DQ_13 AD5 DDR_A_CS#0 DDR_B_D19 BF8 DDR1_DQ_18/DDR0_DQ_50 AF7 DDR_B_ODT0
DDR_A_D15 BK2 DDR0_DQ_14/DDR0_DQ_14 DDR0_CS#_0/DDR0_CS#_0 AE2 DDR_A_CS#1 DDR_A_CS#0 <24> DDR_B_D20 BF11 DDR1_DQ_19/DDR0_DQ_51 DDR1_ODT_0/DDR1_ODT_0 AE8 DDR_B_ODT1 DDR_B_ODT0 <26>
DDR_A_D16 DDR0_DQ_15/DDR0_DQ_15 DDR0_CS#_1/DDR0_CS#_1 DDR_A_CS#2 DDR_A_CS#1 <24> DDR_B_D21 DDR1_DQ_20/DDR0_DQ_52 NC/DDR1_ODT_1 DDR_B_ODT2 DDR_B_ODT1 <26>
BG4 AD2 BF10 AE9
DDR_A_D17 DDR0_DQ_16/DDR0_DQ_32 NC/DDR0_CS#_2 DDR_A_CS#3 DDR_A_CS#2 <23> DDR_B_D22 DDR1_DQ_21/DDR0_DQ_53 NC/DDR1_ODT_2 DDR_B_ODT3 DDR_B_ODT2 <25>
BG5 AE5 BG7 AE11
DDR_A_D18 DDR0_DQ_17/DDR0_DQ_33 NC/DDR0_CS#_3 DDR_A_CS#3 <23> DDR_B_D23 DDR1_DQ_22/DDR0_DQ_54 NC/DDR1_ODT_3 DDR_B_ODT3 <25>
BF4 BF7
DDR_A_D19 BF5 DDR0_DQ_18/DDR0_DQ_34 AD3 DDR_A_ODT0 DDR_B_D24 BB11 DDR1_DQ_23/DDR0_DQ_55 AH10 DDR_B_MA16
DDR_A_D20 DDR0_DQ_19/DDR0_DQ_35 DDR0_ODT_0/DDR0_ODT_0 DDR_A_ODT1 DDR_A_ODT0 <24> DDR_B_D25 DDR1_DQ_24/DDR0_DQ_56 DDR1_CAB_3/DDR1_MA_16 DDR_B_MA14 DDR_B_MA16 <25,26>
BG2 AE4 BC11 AH11
DDR_A_D21 DDR0_DQ_20/DDR0_DQ_36 NC/DDR0_ODT_1 DDR_A_ODT2 DDR_A_ODT1 <24> DDR_B_D26 DDR1_DQ_25/DDR0_DQ_57 DDR1_CAB_2/DDR1_MA_14 DDR_B_MA15 DDR_B_MA14 <25,26>
BG1 AE1 BB8 AF8
DDR_A_D22 DDR0_DQ_21/DDR0_DQ_37 NC/DDR0_ODT_2 DDR_A_ODT3 DDR_A_ODT2 <23> DDR_B_D27 DDR1_DQ_26/DDR0_DQ_58 DDR1_CAB_1/DDR1_MA_15 DDR_B_MA15 <25,26>
BF1 AD4 BC8
DDR_A_D23 DDR0_DQ_22/DDR0_DQ_38 NC/DDR0_ODT_3 DDR_A_ODT3 <23> DDR_B_D28 DDR1_DQ_27/DDR0_DQ_59 DDR_B_BA0
BF2 BC10 AH8
DDR_A_D24 DDR0_DQ_23/DDR0_DQ_39 DDR_A_BA0 DDR_B_D29 DDR1_DQ_28/DDR0_DQ_60 DDR1_CAB_4/DDR1_BA_0 DDR_B_BA1 DDR_B_BA0 <25,26>
BD2 AH5 BB10 AH9
DDR_A_D25 DDR0_DQ_24/DDR0_DQ_40 DDR0_CAB_4/DDR0_BA_0 DDR_A_BA1 DDR_A_BA0 <23,24> DDR_B_D30 DDR1_DQ_29/DDR0_DQ_61 DDR1_CAB_6/DDR1_BA_1 DDR_B_BG0 DDR_B_BA1 <25,26>
BD1 AH1 BC7 AR9
DDR_A_D26 DDR0_DQ_25/DDR0_DQ_41 DDR0_CAB_6/DDR0_BA_1 DDR_A_BG0 DDR_A_BA1 <23,24> DDR_B_D31 DDR1_DQ_30/DDR0_DQ_62 DDR1_CAA_5/DDR1_BG_0 DDR_B_BG0 <25,26>
BC4 AU1 BB7
DDR_A_D27 DDR0_DQ_26/DDR0_DQ_42 DDR0_CAA_5/DDR0_BG_0 DDR_A_BG0 <23,24> DDR_B_D32 DDR1_DQ_31/DDR0_DQ_63 DDR_B_MA0 DDR_B_MA[0..13] <25,26>
BC5 AA11 AJ9
DDR_A_D28 BD5 DDR0_DQ_27/DDR0_DQ_43 AH4 DDR_A_MA16 DDR_B_D33 AA10 DDR1_DQ_32/DDR1_DQ_16 DDR1_CAB_9/DDR1_MA_0 AK6 DDR_B_MA1
C DDR_A_D29 DDR0_DQ_28/DDR0_DQ_44 DDR0_CAB_3/DDR0_MA_16 DDR_A_MA14 DDR_A_MA16 <23,24> DDR_B_D34 DDR1_DQ_33/DDR1_DQ_17 DDR1_CAB_8/DDR1_MA_1 DDR_B_MA2 C
BD4 AG4 AC11 AK5
DDR_A_D30 DDR0_DQ_29/DDR0_DQ_45 DDR0_CAB_2/DDR0_MA_14 DDR_A_MA15 DDR_A_MA14 <23,24> DDR_B_D35 DDR1_DQ_34/DDR1_DQ_18 DDR1_CAB_5/DDR1_MA_2 DDR_B_MA3
BC1 AD1 AC10 AL5
DDR_A_D31 DDR0_DQ_30/DDR0_DQ_46 DDR0_CAB_1/DDR0_MA_15 DDR_A_MA15 <23,24> DDR_B_D36 DDR1_DQ_35/DDR1_DQ_19 NC/DDR1_MA_3 DDR_B_MA4
BC2 AA7 AL6
DDR_A_D32 DDR0_DQ_31/DDR0_DQ_47 DDR_A_MA0 DDR_A_MA[0..13] <23,24> DDR_B_D37 DDR1_DQ_36/DDR1_DQ_20 NC/DDR1_MA_4 DDR_B_MA5
AB1 AH3 AA8 AM6
DDR_A_D33 AB2 DDR0_DQ_32/DDR1_DQ_0 DDR0_CAB_9/DDR0_MA_0 AP4 DDR_A_MA1 DDR_B_D38 AC8 DDR1_DQ_37/DDR1_DQ_21 DDR1_CAA_0/DDR1_MA_5 AN7 DDR_B_MA6
DDR_A_D34 AA4 DDR0_DQ_33/DDR1_DQ_1 DDR0_CAB_8/DDR0_MA_1 AN4 DDR_A_MA2 DDR_B_D39 AC7 DDR1_DQ_38/DDR1_DQ_22 DDR1_CAA_2/DDR1_MA_6 AN10 DDR_B_MA7
DDR_A_D35 AA5 DDR0_DQ_34/DDR1_DQ_2 DDR0_CAB_5/DDR0_MA_2 AP5 DDR_A_MA3 DDR1_DQ_39/DDR1_DQ_23 DDR1_CAA_4/DDR1_MA_7
DDR_A_D36 AB5 DDR0_DQ_35/DDR1_DQ_3 NC/DDR0_MA_3 AP2 DDR_A_MA4 DDR_B_D40 W8 DDR4(IL)/LP3-DDR4(NIL) AN8 DDR_B_MA8
DDR_A_D37 AB4 DDR0_DQ_36/DDR1_DQ_4 NC/DDR0_MA_4 AP1 DDR_A_MA5 DDR_B_D41 W7 DDR1_DQ_40/DDR1_DQ_24 DDR1_CAA_3/DDR1_MA_8 AR11 DDR_B_MA9
DDR_A_D38 AA2 DDR0_DQ_37/DDR1_DQ_5 DDR0_CAA_0/DDR0_MA_5 AP3 DDR_A_MA6 DDR_B_D42 V10 DDR1_DQ_41/DDR1_DQ_25 DDR1_CAA_1/DDR1_MA_9 AH7 DDR_B_MA10
DDR_A_D39 AA1 DDR0_DQ_38/DDR1_DQ_6 DDR0_CAA_2/DDR0_MA_6 AN1 DDR_A_MA7 DDR_B_D43 V11 DDR1_DQ_42/DDR1_DQ_26 DDR1_CAB_7/DDR1_MA_10 AN11 DDR_B_MA11
DDR_A_D40 V5 DDR0_DQ_39/DDR1_DQ_7 DDR0_CAA_4/DDR0_MA_7 AN3 DDR_A_MA8 DDR_B_D44 W11 DDR1_DQ_43/DDR1_DQ_27 DDR1_CAA_7/DDR1_MA_11 AR10 DDR_B_MA12
DDR_A_D41 V2 DDR0_DQ_40/DDR1_DQ_8 DDR0_CAA_3/DDR0_MA_8 AT4 DDR_A_MA9 DDR_B_D45 W10 DDR1_DQ_44/DDR1_DQ_28 DDR1_CAA_6/DDR1_MA_12 AF9 DDR_B_MA13
DDR_A_D42 U1 DDR0_DQ_41/DDR1_DQ_9 DDR0_CAA_1/DDR0_MA_9 AH2 DDR_A_MA10 DDR_B_D46 V7 DDR1_DQ_45/DDR1_DQ_29 DDR1_CAB_0/DDR1_MA_13 AR7 DDR_B_BG1
DDR_A_D43 DDR0_DQ_42/DDR1_DQ_10 DDR0_CAB_7/DDR0_MA_10 DDR_A_MA11 DDR_B_D47 DDR1_DQ_46/DDR1_DQ_30 DDR1_CAA_9/DDR1_BG_1 DDR_B_ACT# DDR_B_BG1 <25,26>
U2 AN2 V8 AT9
DDR_A_D44 DDR0_DQ_43/DDR1_DQ_11 DDR0_CAA_7/DDR0_MA_11 DDR_A_MA12 DDR_B_D48 DDR1_DQ_47/DDR1_DQ_31 DDR1_CAA_8/DDR1_ACT# DDR_B_ACT# <25,26>
V1 AU4 R11
DDR_A_D45 V4 DDR0_DQ_44/DDR1_DQ_12 DDR0_CAA_6/DDR0_MA_12 AE3 DDR_A_MA13 DDR_B_D49 P11 DDR1_DQ_48/DDR1_DQ_48 AJ7 DDR_B_PARITY
DDR_A_D46 U5 DDR0_DQ_45/DDR1_DQ_13 DDR0_CAB_0/DDR0_MA_13 AU2 DDR_A_BG1 DDR_B_D50 P7 DDR1_DQ_49/DDR1_DQ_49 NC/DDR1_PAR AR8 DDR_B_ALERT# DDR_B_PARITY <25,26>
DDR_A_D47 DDR0_DQ_46/DDR1_DQ_14 DDR0_CAA_9/DDR0_BG_1 DDR_A_ACT# DDR_A_BG1 <23,24> DDR_B_D51 DDR1_DQ_50/DDR1_DQ_50 NC/DDR1_ALERT# DDR_B_ALERT# <25,26>
U4 AU3 R8
DDR_A_D48 DDR0_DQ_47/DDR1_DQ_15 DDR0_CAA_8/DDR0_ACT# DDR_A_ACT# <23,24> DDR_B_D52 DDR1_DQ_51/DDR1_DQ_51
R2 R10 DDR4(IL)/LP3-DDR4(NIL)
DDR_A_D49 DDR0_DQ_48/DDR1_DQ_32 DDR_A_PARITY DDR_B_D53 DDR1_DQ_52/DDR1_DQ_52 DDR_B_DQS#0 DDR_B_DQS#[0..7] <25,26>
P5 AG3 P10 BN9
DDR_A_D50 R4 DDR0_DQ_49/DDR1_DQ_33 NC/DDR0_PAR AU5 DDR_A_ALERT# DDR_A_PARITY <23,24> DDR_B_D54 R7 DDR1_DQ_53/DDR1_DQ_53DDR1_DQSN_0/DDR0_DQSN_2 BL9 DDR_B_DQS#1
DDR_A_D51 DDR0_DQ_50/DDR1_DQ_34 NC/DDR0_ALERT# DDR_A_ALERT# <23,24> DDR_B_D55 DDR1_DQ_54/DDR1_DQ_54DDR1_DQSN_1/DDR0_DQSN_3 DDR_B_DQS#2
P4 P8 BG9
DDR_A_D52 R5 DDR0_DQ_51/DDR1_DQ_35 DDR4(IL)/LP3-DDR4(NIL) DDR_B_D56 L11 DDR1_DQ_55/DDR1_DQ_55DDR1_DQSN_2/DDR0_DQSN_6 BC9 DDR_B_DQS#3
DDR_A_D53 DDR0_DQ_52/DDR1_DQ_36 DDR_A_DQS#0 DDR_A_DQS#[0..3] <23,24> DDR_B_D57 DDR1_DQ_56/DDR1_DQ_56DDR1_DQSN_3/DDR0_DQSN_7 DDR_B_DQS#4
P2 BR5 M11 AC9
DDR_A_D54 R1 DDR0_DQ_53/DDR1_DQ_37DDR0_DQSN_0/DDR0_DQSN_0 BL3 DDR_A_DQS#1 DDR_B_D58 L7 DDR1_DQ_57/DDR1_DQ_57DDR1_DQSN_4/DDR1_DQSN_2 W9 DDR_B_DQS#5
DDR_A_D55 P1 DDR0_DQ_54/DDR1_DQ_38DDR0_DQSN_1/DDR0_DQSN_1 BG3 DDR_A_DQS#2 DDR_B_D59 M8 DDR1_DQ_58/DDR1_DQ_58DDR1_DQSN_5/DDR1_DQSN_3 R9 DDR_B_DQS#6
DDR_A_D56 M4 DDR0_DQ_55/DDR1_DQ_39DDR0_DQSN_2/DDR0_DQSN_4 BD3 DDR_A_DQS#3 DDR_B_D60 L10 DDR1_DQ_59/DDR1_DQ_59DDR1_DQSN_6/DDR1_DQSN_6 M9 DDR_B_DQS#7
DDR_A_D57 DDR0_DQ_56/DDR1_DQ_40DDR0_DQSN_3/DDR0_DQSN_5 DDR_A_DQS#4 DDR_A_DQS#[4..7] <23,24> DDR_B_D61 DDR1_DQ_60/DDR1_DQ_60DDR1_DQSN_7/DDR1_DQSN_7
M1 AA3 M10
DDR_A_D58 DDR0_DQ_57/DDR1_DQ_41DDR0_DQSN_4/DDR1_DQSN_0 DDR_A_DQS#5 DDR_B_D62 DDR1_DQ_61/DDR1_DQ_61 DDR_B_DQS0 DDR_B_DQS[0..7] <25,26>
L4 U3 M7 BP9
DDR_A_D59 L2 DDR0_DQ_58/DDR1_DQ_42DDR0_DQSN_5/DDR1_DQSN_1 P3 DDR_A_DQS#6 DDR_B_D63 L8 DDR1_DQ_62/DDR1_DQ_62DDR1_DQSP_0/DDR0_DQSP_2 BJ9 DDR_B_DQS1
DDR_A_D60 M5 DDR0_DQ_59/DDR1_DQ_43DDR0_DQSN_6/DDR1_DQSN_4 L3 DDR_A_DQS#7 DDR1_DQ_63/DDR1_DQ_63DDR1_DQSP_1/DDR0_DQSP_3 BF9 DDR_B_DQS2
DDR_A_D61 DDR0_DQ_60/DDR1_DQ_44DDR0_DQSN_7/DDR1_DQSN_5 <25,26> DDR_B_CB[0..7] DDR_B_CB0 DDR1_DQSP_2/DDR0_DQSP_6 DDR_B_DQS3
M2 AW11 LP3/DDR4 BB9
DDR_A_D62 DDR0_DQ_61/DDR1_DQ_45 DDR_A_DQS0 DDR_A_DQS[0..3] <23,24> DDR_B_CB1 NC/DDR1_ECC_0 DDR1_DQSP_3/DDR0_DQSP_7 DDR_B_DQS4
L5 BP5 AY11 AA9
DDR_A_D63 L1 DDR0_DQ_62/DDR1_DQ_46DDR0_DQSP_0/DDR0_DQSP_0 BK3 DDR_A_DQS1 DDR_B_CB2 AY8 NC/DDR1_ECC_1 DDR1_DQSP_4/DDR1_DQSP_2 V9 DDR_B_DQS5
B DDR0_DQ_63/DDR1_DQ_47DDR0_DQSP_1/DDR0_DQSP_1 BF3 DDR_A_DQS2 DDR_B_CB3 AW8 NC/DDR1_ECC_2 DDR1_DQSP_5/DDR1_DQSP_3 P9 DDR_B_DQS6 B
LP3/DDR4 DDR0_DQSP_2/DDR0_DQSP_4 BC3 DDR_A_DQS3 DDR_B_CB4 AY10 NC/DDR1_ECC_3 DDR1_DQSP_6/DDR1_DQSP_6 L9 DDR_B_DQS7
<23,24> DDR_A_CB[0..7] DDR_A_CB0 DDR0_DQSP_3/DDR0_DQSP_5 DDR_A_DQS4 DDR_A_DQS[4..7] <23,24> DDR_B_CB5 NC/DDR1_ECC_4 DDR1_DQSP_7/DDR1_DQSP_7
BA2 AB3 AW10
DDR_A_CB1 BA1 NC/DDR0_ECC_0 DDR0_DQSP_4/DDR1_DQSP_0 V3 DDR_A_DQS5 DDR_B_CB6 AY7 NC/DDR1_ECC_5 AW9 DDR_B_DQS8
DDR_A_CB2 NC/DDR0_ECC_1 DDR0_DQSP_5/DDR1_DQSP_1 DDR_A_DQS6 DDR_B_CB7 NC/DDR1_ECC_6 DDR1_DQSP_8/DDR1_DQSP_8 DDR_B_DQS#8 DDR_B_DQS8 <25,26>
AY4 R3 AW7 AY9
DDR_A_CB3 AY5 NC/DDR0_ECC_2 DDR0_DQSP_6/DDR1_DQSP_4 M3 DDR_A_DQS7 NC/DDR1_ECC_7 DDR1_DQSN_8/DDR1_DQSN_8 DDR_B_DQS#8 <25,26>
DDR_A_CB4 BA5 NC/DDR0_ECC_3 DDR0_DQSP_7/DDR1_DQSP_5
DDR_A_CB5 BA4 NC/DDR0_ECC_4 AY3 DDR_A_DQS8
DDR_A_CB6 NC/DDR0_ECC_5 DDR0_DQSP_8/DDR0_DQSP_8 DDR_A_DQS#8 DDR_A_DQS8 <23,24>
AY1 BA3
DDR_A_CB7 NC/DDR0_ECC_6 DDR0_DQSN_8/DDR0_DQSN_8 DDR_A_DQS#8 <23,24>
AY2 1 OF 13
NC/DDR0_ECC_7 1 2 DDR_RCOMP0 G1 BN13
DDR_RCOMP_0 DDR_VREF_CA +DDR_VREF_CA
CFL-H_BGA1440 RC5 1 2 121_0402_1% DDR_RCOMP1 H1 BP13 1
DDR_RCOMP2 DDR_RCOMP_1 DDR0_VREF_DQ PAD~D @ T199
RC6 1 2 75_0402_1% J2 2 OF 13 BR13
DDR_RCOMP_2 DDR1_VREF_DQ +DDR_VREF_B_DQ
RC7 100_0402_1%
CFL-H_BGA1440
Trace width=12-15 mils

,Spacing=20mil
Max length= 500 mils.
A A
Security Classification Compal Secret Data
Title
Issued Date 2016/01/01 Deciphered Date 2017/01/01
CFL-H(3/8) DDR4
B 1.0
5 4 3 2 1
5 4 3 2 1
Vinafix.com
D D
CFL-H
UC1D
CPU_DP1_P0 K36 D29 EDP_TXP0

<31> CPU_DP1_P0 CPU_DP1_N0 K37 DDI1_TXP_0 EDP_TXP_0 E29 EDP_TXN0 EDP_TXP0 <29>
<31> CPU_DP1_N0 CPU_DP1_P1 J35 DDI1_TXN_0 EDP_TXN_0 F28 EDP_TXP1 EDP_TXN0 <29>
<31> CPU_DP1_P1 CPU_DP1_N1 J34 DDI1_TXP_1 EDP_TXP_1 E28 EDP_TXN1 EDP_TXP1 <29>
<31> CPU_DP1_N1 CPU_DP1_P2 H37 DDI1_TXN_1 EDP_TXN_1 A29 EDP_TXP2 EDP_TXN1 <29>
<31> CPU_DP1_P2 CPU_DP1_N2 H36 DDI1_TXP_2 EDP_TXP_2 B29 EDP_TXN2 EDP_TXP2 <29>
MUX PS8461 <31> CPU_DP1_N2 DDI1_TXN_2 EDP_TXN_2 EDP_TXN2 <29> MUX PS8331
CPU_DP1_P3 J37 C28 EDP_TXP3
<31> CPU_DP1_P3 CPU_DP1_N3 J38 DDI1_TXP_3 EDP_TXP_3 B28 EDP_TXN3 EDP_TXP3 <29>
<31> CPU_DP1_N3 DDI1_TXN_3 EDP_TXN_3 EDP_TXN3 <29>
CPU_DP1_AUXP D27 C26 EDP_AUXP
<31> CPU_DP1_AUXP CPU_DP1_AUXN DDI1_AUXP EDP_AUXP EDP_AUXN EDP_AUXP <29>
E27 B26
<31> CPU_DP1_AUXN DDI1_AUXN EDP_AUXN EDP_AUXN <29>
CPU_DP2_P0 H34
<30> CPU_DP2_P0 CPU_DP2_N0 H33 DDI2_TXP_0
<30> CPU_DP2_N0 CPU_DP2_P1 F37 DDI2_TXN_0 A33 1
<30> CPU_DP2_P1 CPU_DP2_N1 DDI2_TXP_1 EDP_DISP_UTIL PAD~D @ T194
G38
C <30> CPU_DP2_N1 CPU_DP2_P2 F34 DDI2_TXN_1 C
<30> CPU_DP2_P2 CPU_DP2_N2 F35 DDI2_TXP_2 D37 EDP_COMP +1.0VS_VCCIO
<30> CPU_DP2_N2 CPU_DP2_P3 E37 DDI2_TXN_2 DISP_RCOMP
DEMUX PS8338 <30> CPU_DP2_P3 DDI2_TXP_3
CPU_DP2_N3 E36
<30> CPU_DP2_N3 DDI2_TXN_3 EDP_COMP 1 2
RC1 24.9_0402_1%
CPU_DP2_AUXP F26
<30> CPU_DP2_AUXP CPU_DP2_AUXN E26 DDI2_AUXP
<30> CPU_DP2_AUXN DDI2_AUXN
CPU_DP3_P0 C34
<28> CPU_DP3_P0 CPU_DP3_N0 D34 DDI3_TXP_0 min Trace width=5 mils
<28> CPU_DP3_N0 CPU_DP3_P1 B36 DDI3_TXN_0 ,Spacing=20mil
<28> CPU_DP3_P1 CPU_DP3_N1 B34 DDI3_TXP_1 Max length= 600 mils.
<28> CPU_DP3_N1 CPU_DP3_P2 F33 DDI3_TXN_1
<28> CPU_DP3_P2 CPU_DP3_N2 E33 DDI3_TXP_2
UMA DGFF <28> CPU_DP3_N2 DDI3_TXN_2
CPU_DP3_P3 C33
<28> CPU_DP3_P3 CPU_DP3_N3 B33 DDI3_TXP_3
<28> CPU_DP3_N3 DDI3_TXN_3 G27 AUD_AZACPU_SCLK
CPU_DP3_AUXP PROC_AUDIO_CLK AUD_AZACPU_SDO AUD_AZACPU_SCLK <18>
A27 G25
<28> CPU_DP3_AUXP CPU_DP3_AUXN DDI3_AUXP PROC_AUDIO_SDI AUD_AZACPU_SDI AUD_AZACPU_SDO <18>
B27 G29
<28> CPU_DP3_AUXN DDI3_AUXN 4 ofPROC_AUDIO_SDO
13
CFL-H_BGA1440
AUD_AZACPU_SDI 1 2AUD_AZACPU_SDI_R
AUD_AZACPU_SDI_R <18>
RC66 20_0402_5%
B B
A A
CFL-H(4/8) DDI,eDP
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS A 1.0
5 4 3 2 1
5 4 3 2 1
PLACE CAP BACKSIDE

+1.2V_MEM +1.0V_VCCSTG +1.0V_VCCSFR_R +1.0V_VCCST +VCC_SFR_OC
CFL-H
UC1M
10U_0402_6.3V6M
22U_0603_6.3V6M
Vinafix.com
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
22U_0603_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
22U_0603_6.3V6M
1 2 2 2 1 2 1 2 2 1
@ CC195
CC333
@ CC569
@ CC568
PAD~D @ T4 1 E2
RSVD_TP5
CC185
CC186
CC192
CC191
CC210
CC209
PAD~D @ T3 1 IST_TRIG E3
1 E1 IST_TRIG
D PAD~D @ T2 D
1 D1 RSVD_TP4 2 1 1 1 2 1 2 1 1 2
PAD~D @ T1 RSVD_TP3
PAD~D @ T5 1 BR1 BK28 1
RSVD_TP1 RSVD11 T29 @ PAD~D FOLLOW PDG V1P8 P.616
PAD~D @ T6 1 BT2 BJ28 1
RSVD_TP2 RSVD10 T30 @ PAD~D downsize to SE00000UD00
1 BN35 11x 10uF 0402 follow Berlineeta add 22uF to solve PS4 idle hang
PAD~D @ T7 RSVD15 location:CC568 CC569 3/21
PAD~D @ T9 1 J24 close to UC1.Y12
1 H24 RSVD28
PAD~D @ T10 RSVD27
PAD~D @ T11 1 BN33 +1.0VS_VCCIO
1 BL34 RSVD14 +1.0V_VCCSFR LC562 +1.0V_VCCSFR_R
PAD~D @ T8 RSVD13 PLACE CAP BACKSIDE BLM18EG221TN1D_2P~D
PAD~D @ T14 1 N29 1 2
1 R14 RSVD30
PAD~D @ T13 RSVD31
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
PAD~D @ T15 1 AE29 Change LC422 from
@ CC272
RSVD2
22U_0603_6.3V6M
1 AA14 0_0603_5% to Beads 2
PAD~D @ T12 RSVD1
1
CC189
CC188
CC187
1 AP29
PAD~D @ T28 RSVD5
CC335
1 AP14
PAD~D @ T27 VSS_A36 RSVD4 PLACE CAP BACKSIDE or BOARD EDGE
A36
1
2
VSS_A36
VSS_A37 A37
VSS_A37
PCH_2_CPU_TRIGGER H23
<20> PCH_2_CPU_TRIGGER CPU_2_PCH_TRIGGER_R J23 PROC_TRIGIN
PROC_TRIGOUT
PAD~D @ T285 1TP_SKL_F30 F30
RSVD24
C
PAD~D @ T281 1TP_SKL_E30 E30 +1.0V_VCCST C
RSVD23
PAD~D @ T18 1 B30 BL31 1

RSVD7 RSVD12 T297@ PAD~D
PAD~D @ T19 1 C30 AJ8 1
G13 1
RSVD25 T299@ PAD~D
1U_0201_10V6M
1U_0201_10V6M
2 2
PAD~D @ T21 1 G3
RSVD26
CC193
CC194
PAD~D @ T20 1 J3 C38 1
C1 1
RSVD20 T301@ PAD~D 1 1
BR2 1
RSVD17 T302@ PAD~D
PAD~D @ T23 1 BR35 BP1 1
PAD~D @ T24 1 BR31 B38 1
PAD~D @ T22 1 BH30 B2 1
RSVD9 RSVD6 T305@ PAD~D downsize
13 OF 13
CFL-H_BGA1440
+1.2V_MEM
PLACE CAP BACKSIDE
+1.2V_MEM DECOUPLING
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
1 1 1 1 1 1 1 1 1 1
B B
CC161
CC170
CC164
CC168
CC163
CC166
CC171
CC165
CC172
CC167
2 2 2 2 2 2 2 2 2 2
CPU_2_PCH_TRIGGER 1 2 CPU_2_PCH_TRIGGER_R
<20> CPU_2_PCH_TRIGGER
RC177 30_0402_5%
VSS_A36 @ RC178 1 2 0_0402_5%

VSS_A37 @ RC179 1 2 0_0402_5%
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
1
1
CC81
CC82
CC83
CC84
2
2
A A
CFL-H(5/8) RSVD,Decoupling
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
5 4 3 2 1
5 4 3 2 1
+VCCPLL_OC source PDDG page19, if don`t support DS3, connect to VDDQ directly
+1.2V_MEM +VCC_SFR_OC
+VCC_GT +VCC_GT
Vinafix.com
1 2
CFL-H @ RZ119 0_0402_5%
UC1K +VCC_SA +1.2V_MEM
AT14 BD35 CFL-H Change CPN from SA00007XR00 to
AT31 VCCGT1 VCCGT80 BD36 UC1L SA00008R600 3/12
D VCCGT2 VCCGT81 D
AT32 BE31 12A UZ26
AT33 VCCGT3 VCCGT82 BE32 J30 AA6 1 2 1
AT34 VCCGT4 VCCGT83 BE33 K29 VCCSA1 VDDQ1 AE12 CZ102 1U_0201_10V6M 2 VIN1
AT35 VCCGT5 VCCGT84 BE34 K30 VCCSA2 VDDQ2 AF5 VIN2
AT36 VCCGT6 VCCGT85 BE35 K31 VCCSA3 VDDQ3 AF6 7 6 1 2
AT37 VCCGT7 VCCGT86 BE36 K32 VCCSA4 VDDQ4 AG5 VIN thermal VOUT CZ199 0.1U_0201_10V6K
AT38 VCCGT8 VCCGT87 BE37 K33 VCCSA5 VDDQ5 AG9 3
VCCGT9 VCCGT88 VCCSA6 VDDQ6 +5V_ALW_R VBIAS
AU14 BE38 K34 AJ12
AU29 VCCGT10 VCCGT89 BF13 K35 VCCSA7 VDDQ7 AL11 VCCSTG_EN @ RZ120 1 2 0_0402_5% 4 5
AU30 VCCGT11 VCCGT90 BF14 L31 VCCSA8 VDDQ8 AP6 ON GND
AU31 VCCGT12 VCCGT91 BF29 L32 VCCSA9 VDDQ9 AP7 +VCC_SFR_OC +3.3V_ALW_R
AU32 VCCGT13 VCCGT92 BF30 L35 VCCSA10 VDDQ10 AR12 EM5201V_DFN3X3-8-X
AU35 VCCGT14 VCCGT93 BF31 L36 VCCSA11 VDDQ11 AR6 @ CZ200
VCCGT15 VCCGT94 VCCSA12 VDDQ12
0.1U_0402_25V6
ESD@ CC334
AU36 BF32 L37 AT12 1 2
AU37 VCCGT16 VCCGT95 BF35 L38 VCCSA13 VDDQ13 AW6
1
AU38 BF36 M29 AY6 0.1U_0201_10V6K
5
AV29 BF37 M30 J5
AV30 VCCGT19 VCCGT98 BF38 M31 VCCSA16 VDDQ16 J6
VCC
2
AV31 VCCGT20 VCCGT99 BG29 M32 VCCSA17 VDDQ17 K12 1
VCCGT21 VCCGT100 VCCSA18 VDDQ18 <18,22,89> PCH_PRIM_EN IN1
AV32 BG30 M33 K6 4
AV33 VCCGT22 VCCGT101 BG31 M34 VCCSA19 VDDQ19 L12 2 OUT
GND
AV34 VCCGT23 VCCGT102 BG32 M35 VCCSA20 VDDQ20 L6 <11,18,19,88> SIO_SLP_S4# IN2
AV35 VCCGT24 VCCGT103 BG33 M36 VCCSA21 VDDQ21 R6
AV36 VCCGT25 VCCGT104 BG34 VCCSA22 VDDQ22 T6 @ UZ34
3
AW14 VCCGT26 VCCGT105 BG35 VDDQ23 W6 MC74VHC1G08DFT2G_SC70-5
AW31 VCCGT27 VCCGT106 BG36 VDDQ24 Y12
AW32 VCCGT28 VCCGT107 BH33 AG12 VDDQ25
VCCGT29 VCCGT108 +1.0VS_VCCIO VCCIO1
AW33 BH34 G15
AW34 VCCGT30 VCCGT109 BH35 G17 VCCIO2
AW35 VCCGT31 VCCGT110 BH36 G19 VCCIO3 BH13
VCCGT32 VCCGT111 VCCIO4 VCCPLL_OC1 +VCC_SFR_OC
AW36 BH37 G21 BJ13
AW37 VCCGT33 VCCGT112 BH38 H15 VCCIO5 VCCPLL_OC2 G11
AW38 VCCGT34 VCCGT113 BJ16 H16 VCCIO6 VCCPLL_OC3
VCCGT35 VCCGT114 VCCIO7
C
AY29
AY30
AY31
VCCGT36
VCCGT37
VCCGT115
VCCGT116
BJ17
BJ19
BJ20
H17
H19
H20
VCCIO8
VCCIO9
VCCST
H30
H29
+1.0V_VCCST
+1.0V_VCCSTG source +1.0V_VCCSTG +VCC_FUSEPRG
C
VCCGT38 VCCGT117 VCCIO10 VCCSTG2 +1.0V_VCCSTG
AY32 BJ21 H21 2 1
VCCGT39 VCCGT118 VCCIO11
1
AY35 BJ23 H26 G30 Change CPN from SA00007XR00 to 0_0402_5% @ RC326
VCCGT40 VCCGT119 VCCIO12 VCCSTG1 +VCC_FUSEPRG SA00008R600 3/12 JUMP@
AY36 BJ24 H27 +1.05V_PRIM
AY37 VCCGT41 VCCGT120 BJ26 J15 VCCIO13 H28 UZ19 PJP2
VCCGT42 VCCGT121 VCCIO14 VCCPLL1 +1.0V_VCCSFR_R CZ105
AY38 BJ27 J16 J28 1U_0201_10V6M 1 PAD-OPEN1x1m
BA13 VCCGT43 VCCGT122 BJ37 J17 VCCIO15 VCCPLL2 2 1 2 VIN1
BA14 VCCGT44 VCCGT123 BJ38 J19 VCCIO16 VIN2
2
BA29 VCCGT45 VCCGT124 BK16 J20 VCCIO17 M38 +5V_ALW_R 7 6 +1.0V_VCCSTG_C 1 2
VCCGT46 VCCGT125 VCCIO18 VCCSA_SENSE VCC_SA_SENSE <90> VIN thermal VOUT
BA30 BK17 J21 M37 VSS_SA_SENSE <90> CZ106
BA31 VCCGT47 VCCGT126 BK19 J26 VCCIO19 VSSSA_SENSE 3 0.1U_0201_10V6K
BA32 VCCGT48 VCCGT127 BK20 J27 VCCIO20 H14 VBIAS
VCCGT49 VCCGT128 VCCIO21 VCCIO_SENSE VCC_IO_SENSE <89> +1.8V_PRIM +3.3V_RUN
BA33 BK21 J14 4 5
VCCGT50 VCCGT129 VSSIO_SENSE VSS_IO_SENSE <89> ON GND
BA34 BK23 12 OF 13
BA35 VCCGT51 VCCGT130 BK24
BA36 VCCGT52 VCCGT131 BK26 CFL-H_BGA1440 EM5201V_DFN3X3-8-X
VCCGT53 VCCGT132
2
BB13 BK27 +1.8V_PRIM
BB14 VCCGT54 VCCGT133 BL15 RZ543 @
BB31 VCCGT55 VCCGT134 BL16 10K_0402_5% 0.1U_0201_25V6K CZ544
4.4mohm/6A
BB32 VCCGT56 VCCGT135 BL17 2 1 RZ542 TR=12.5us@Vin=1.05V
VCCGT57 VCCGT136
2
BB33 BL23 +3.3V_ALW_R
1
BB34 VCCGT58 VCCGT137 BL24
BB35 VCCGT59 VCCGT138 BL25 UZ61 10K_0402_5%
BB36 VCCGT60 VCCGT139 BL26 1 5
VCCGT61 VCCGT140 NC VCC
5
BB37 BL27
1
BB38 VCCGT62 VCCGT141 BL28 2
VCC
BC29 VCCGT63 VCCGT142 BL36 <14,89> CPU_C10_GATE# A 4 C10_PWR_GATE#
1
BC30 VCCGT64 VCCGT143 BL37 3 Y IN1 4 VCCSTG_EN
BC31 VCCGT65 VCCGT144 BM15 GND 2 OUT
GND
BC32 VCCGT66 VCCGT145 BM16 74AUP1G07GW_TSSOP5 IN2
BC35 VCCGT67 VCCGT146 BM17
BC36 VCCGT68 VCCGT147 BM36 @ RC562 1 2 UZ35
3
BC37 VCCGT69 VCCGT148 BM37 0_0201_5% MC74VHC1G08DFT2G_SC70-5
BC38 VCCGT70 VCCGT149 BN15
VCCGT71 VCCGT150 <22,58,59,67,70,89> RUN_ON
BD13 BN16
B BD14 VCCGT72 VCCGT151 BN17 B
BD29 VCCGT73 VCCGT152 BN36
BD32 VCCGT76 VCCGT155 BP15
Reserve for SIO_SLP_S0#
BP37 VCCGT79 VCCGT158 BR37
BP38 VCCGT159 VCCGT164 BT15
VCCGT160 VCCGT165 +VCC_SFR_OC
BR15 BT16
BR16
BR17
VCCGT161
VCCGT162
VCCGT163
VCCGT166
VCCGT167
VCCGT168
BT17
BT37
+1.05V_PRIM
+1.0V_VCCST source
Change CPN from SA00007XR00 to
1 SA00008R600 3/12
2.2P_0402_50V8C
AH37 UZ21 +1.0V_VCCST +1.0V_VCCSFR
11 OFVSSGT_SENSE VSS_GT_SENSE <90>
RF@ CC322
13 AH38 1 JUMP@
VCCGT_SENSE VCC_GT_SENSE <90>
2 2 VIN1 PJP1
CFL-H_BGA1440 +1.0V_VCCSTG +1.0V_VCCST +5V_ALW_R VIN2
7 6 +1.0V_VCCST_C 2 1 1 2
VIN thermal VOUT 0_0402_5%
@ RC304
1 2 1 3 PAD-OPEN1x1m
VBIAS
1U_0201_10V6M
@ RZ151 0_0402_5% 1
CZ100
0.1U_0201_10V6K
4 5
RF Request ON GND
CZ101
2
EM5201V_DFN3X3-8-X 2
4.4mohm/6A
TR=12.5us@Vin=1.05V
<11,18,19,88> SIO_SLP_S4#
A A
Title
CFL-H(6/8) PWR
B 1.0
5 4 3 2 1
5 4 3 2 1
+VCC_CORE +VCC_CORE
+VCC_CORE +VCC_CORE
Vinafix.com UC1J
CFL-H
UC1I
CFL-H
AA13 AH13
K14 W35 AA31 VCC1 VCC64 AH14
D D
L13 VCC1 VCC64 W36 AA32 VCC2 VCC65 AH29
L14 VCC2 VCC65 W37 AA33 VCC3 VCC66 AH30
N13 VCC3 VCC66 W38 AA34 VCC4 VCC67 AH31
N14 VCC4 VCC67 Y29 AA35 VCC5 VCC68 AH32
N30 VCC5 VCC68 Y30 AA36 VCC6 VCC69 AJ14
N35 VCC8 VCC71 Y33 AB29 VCC9 VCC72 AJ31
P13 VCC12 VCC75 AB35 VCC13 VCC76 AJ35
P14 VCC13 AB36 VCC14 VCC77 AJ36
P29 VCC14 AB37 VCC15 VCC78 AK31
P30 VCC15 AB38 VCC16 VCC79 AK32
P31 VCC16 AC13 VCC17 VCC80 AK33
R13 VCC22 AC33 VCC23 VCC86 AL13
R34 VCC26 AD13 VCC27 VCC90 AL32
C R37 VCC29 AD32 VCC30 VCC93 AL37 C
T29 VCC31 AD34 VCC32 VCC95 AM13
T36 VCC36 AE13 VCC37 VCC100 AM32
U29 VCC39 AE31 VCC40 VCC103 AM35
U30 VCC40 AE32 VCC41 VCC104 AM36
U31 VCC41 AE35 VCC42 VCC105 AN13
U35 VCC45 AF29 VCC46 VCC109 AN33
U36 VCC46 AF30 VCC47 VCC110 AN34
V13 VCC47 AF31 VCC48 VCC111 AN35
V33 VCC51 AF35 VCC52 VCC115 AP13
V37 VCC55 AG14 VCC56 VCC119 AP35
V38 VCC56 AG31 VCC57 VCC120 AP36
W13 VCC57 AG32 VCC58 VCC121 AP37
B W14 VCC58 AG33 VCC59 VCC122 AP38 B
W29 VCC59 AG34 VCC60 VCC123 K13
W30 VCC60 AG35 VCC61 VCC124
W31 VCC61 AG36 VCC62
W32 VCC62 10 OF 13 VCC63
VCC63
CFL-H_BGA1440
AG37 VCC_SENSE
VCC_SENSE VCC_SENSE <90>
9 OF 13 AG38 VSS_SENSE
VSS_SENSE VSS_SENSE <90>
CFL-H_BGA1440
CFL change form +VCCGT to +VCC_CORE
VSS_SENSE 1 2 VCC_SENSE
@ RC221 49.9_0402_1%
A A
CFL-H(7/8) +VCC_CORE
5 4 3 2 1
5 4 3 2 1
CFL-H CFL-H CFL-H

UC1F UC1G UC1H
A10 AK4 AW5 BJ15 BN4 F15
A12 VSS_1 VSS_82 AL10 AY12 VSS_163 VSS_244 BJ18 BN7 VSS_325 VSS_409 F17
A16 VSS_2 VSS_83 AL12 AY33 VSS_164 VSS_245 BJ22 BP12 VSS_326 VSS_410 F19
A18 VSS_3 VSS_84 AL14 AY34 VSS_165 VSS_246 BJ25 BP14 VSS_327 VSS_411 F2
A20 VSS_4 VSS_85 AL33 B9 VSS_166 VSS_247 BJ29 BP18 VSS_328 VSS_412 F21
A22
A24
VSS_5
VSS_6
VSS_7
VSS_86
VSS_87
VSS_88
AL34
AL4 Vinafix.com BA10
BA11
VSS_167
VSS_168
VSS_169
VSS_248
VSS_249
VSS_250
BJ30
BJ31
BP21
BP24
VSS_329
VSS_330
VSS_331
VSS_413
VSS_414
VSS_415
F23
F25
A26 AL7 BA12 BJ32 BP25 F27
A28 VSS_8 VSS_89 AL8 BA37 VSS_170 VSS_251 BJ33 BP26 VSS_332 VSS_416 F29
D D
A30 VSS_9 VSS_90 AL9 BA38 VSS_171 VSS_252 BJ34 BP29 VSS_333 VSS_417 F3
A6 VSS_10 VSS_91 AM1 BA6 VSS_172 VSS_253 BJ35 BP33 VSS_334 VSS_418 F31
A9 VSS_11 VSS_92 AM12 BA7 VSS_173 VSS_254 BJ36 BP34 VSS_335 VSS_419 F36
AA12 VSS_12 VSS_93 AM2 BA8 VSS_174 VSS_255 BK13 BP7 VSS_336 VSS_420 F4
AA29 VSS_13 VSS_94 AM3 BA9 VSS_175 VSS_256 BK14 BR12 VSS_337 VSS_421 F5
AA30 VSS_14 VSS_95 AM37 BB1 VSS_176 VSS_257 BK15 BR14 VSS_338 VSS_422 F8
AB33 VSS_15 VSS_96 AM38 BB12 VSS_177 VSS_258 BK18 BR18 VSS_339 VSS_423 F9
AB34 VSS_16 VSS_97 AM4 BB2 VSS_178 VSS_259 BK22 BR21 VSS_340 VSS_424 G10
AB6 VSS_17 VSS_98 AM5 BB29 VSS_179 VSS_260 BK25 BR24 VSS_341 VSS_425 G12
AC1 VSS_18 VSS_99 AN12 BB3 VSS_180 VSS_261 BK29 BR25 VSS_342 VSS_426 G14
AC12 VSS_19 VSS_100 AN29 BB30 VSS_181 VSS_262 BK6 BR26 VSS_343 VSS_427 G16
AC2 VSS_20 VSS_101 AN30 BB4 VSS_182 VSS_263 BL13 BR29 VSS_344 VSS_428 G18
AC38 VSS_23 VSS_104 AP10 BC12 VSS_185 VSS_266 BL19 BR7 VSS_347 VSS_431 G23
AC4 VSS_24 VSS_105 AP11 BC13 VSS_186 VSS_267 BL20 BT12 VSS_348 VSS_432 G24
AD10 VSS_27 VSS_108 AP34 BC34 VSS_189 VSS_270 BL29 BT21 VSS_351 VSS_435 G4
AD11 VSS_28 VSS_109 AP8 BC6 VSS_190 VSS_271 BL33 BT24 VSS_352 VSS_436 G5
AD12 VSS_29 VSS_110 AP9 BD10 VSS_191 VSS_272 BL35 BT26 VSS_353 VSS_437 G6
AD29 VSS_30 VSS_111 AR1 BD11 VSS_192 VSS_273 BL38 BT29 VSS_354 VSS_438 G8
AD30 VSS_31 VSS_112 AR13 BD12 VSS_193 VSS_274 BL6 BT32 VSS_355 VSS_439 G9
AD6 VSS_32 VSS_113 AR14 BD37 VSS_194 VSS_275 BM11 BT5 VSS_356 VSS_440 H11
AD8 VSS_33 VSS_114 AR2 BD6 VSS_195 VSS_276 BM12 C11 VSS_357 VSS_441 H12
AD9 VSS_34 VSS_115 AR29 BD7 VSS_196 VSS_277 BM13 C13 VSS_358 VSS_442 H18
AE33 VSS_35 VSS_116 AR3 BD8 VSS_197 VSS_278 BM14 C15 VSS_359 VSS_443 H22
AE34 VSS_36 VSS_117 AR30 BD9 VSS_198 VSS_279 BM18 C17 VSS_360 VSS_444 H25
C AE6 VSS_37 VSS_118 AR31 BE1 VSS_199 VSS_280 BM2 C19 VSS_361 VSS_445 H32 C
AF1 VSS_38 VSS_119 AR32 BE2 VSS_200 VSS_281 BM21 C21 VSS_362 VSS_446 H35
AF12 VSS_39 VSS_120 AR33 BE29 VSS_201 VSS_282 BM22 C23 VSS_363 VSS_447 J10
AG10 VSS_45 VSS_126 AR4 BF12 VSS_207 VSS_288 BM28 C5 VSS_369 VSS_453 J36
AG11 VSS_46 VSS_127 AR5 BF33 VSS_208 VSS_289 BM29 C8 VSS_370 VSS_454 J4
AG13 VSS_47 VSS_128 AT29 BF34 VSS_209 VSS_290 BM3 C9 VSS_371 VSS_455 J7
AG29 VSS_48 VSS_129 AT30 BF6 VSS_210 VSS_291 BM33 D10 VSS_372 VSS_456 K1
AG30 VSS_49 VSS_130 AT6 BG12 VSS_211 VSS_292 BM35 D12 VSS_373 VSS_457 K10
AG6 VSS_50 VSS_131 AU10 BG13 VSS_212 VSS_293 BM38 D14 VSS_374 VSS_458 K11
AH12 VSS_53 VSS_134 AU33 BG38 VSS_215 VSS_296 BM7 D20 VSS_377 VSS_461 K38
AH33 VSS_54 VSS_135 AU34 BG6 VSS_216 VSS_297 BM8 D22 VSS_378 VSS_462 K4
AH34 VSS_55 VSS_136 AU6 BH1 VSS_217 VSS_298 BM9 D24 VSS_379 VSS_463 K5
AH35 VSS_56 VSS_137 AU7 BH10 VSS_218 VSS_299 BN12 D26 VSS_380 VSS_464 K7
AJ1 VSS_59 VSS_140 AV37 BH14 VSS_221 VSS_302 BN19 D30 VSS_383 VSS_467 L29
AJ13 VSS_60 VSS_141 AV38 BH2 VSS_222 VSS_303 BN2 D33 VSS_384 VSS_468 L30
AJ2 VSS_61 VSS_142 AW1 BH3 VSS_223 VSS_304 BN20 D6 VSS_385 VSS_469 L33
AJ3 VSS_62 VSS_143 AW12 BH4 VSS_224 VSS_305 BN21 D9 VSS_386 VSS_470 L34
AJ37 VSS_63 VSS_144 AW2 BH5 VSS_225 VSS_306 BN24 E34 VSS_387 VSS_471 M12
AJ38 VSS_64 VSS_145 AW29 BH6 VSS_226 VSS_307 BN29 E35 VSS_388 VSS_472 M13
AJ4 VSS_65 VSS_146 AW3 BH7 VSS_227 VSS_308 BN30 E38 VSS_389 VSS_473 N10
B AJ5 VSS_66 VSS_147 AW30 BH8 VSS_228 VSS_309 BN31 E4 VSS_390 VSS_474 N11 B
AJ6 VSS_67 VSS_148 AW4 BH9 VSS_229 VSS_310 BN34 E9 VSS_391 VSS_475 N12
W4 VSS_68 VSS_149 U6 T2 VSS_230 VSS_311 P38 N3 VSS_392 VSS_476 N2
W5 VSS_69 VSS_150 V12 T3 VSS_231 VSS_312 P6 N33 VSS_393 VSS_477 BT8
Y10 VSS_70 VSS_151 V29 T33 VSS_232 VSS_313 R12 N34 VSS_394 VSS_478 BR9
Y11 VSS_71 VSS_152 V30 T34 VSS_233 VSS_314 R29 N4 VSS_395 VSS_479
Y13 VSS_72 VSS_153 A14 T4 VSS_234 VSS_315 AY14 N5 VSS_396 A3
Y14 VSS_73 VSS_154 AD7 T5 VSS_235 VSS_316 BD38 N6 VSS_397 VSS_A3 A34
Y37 VSS_74 VSS_155 V6 T7 VSS_236 VSS_317 R30 N7 VSS_398 VSS_A34 A4
Y38 VSS_75 VSS_156 W1 T8 VSS_237 VSS_318 T1 N8 VSS_399 VSS_A4 B3
Y7 VSS_76 VSS_157 W12 T9 VSS_238 VSS_319 T10 N9 VSS_400 VSS_B3 B37
Y8 VSS_77 VSS_158 W2 U37 VSS_239 VSS_320 T11 P12 VSS_401 VSS_B37 BR38
Y9 VSS_78 VSS_159 W3 U38 VSS_240 VSS_321 T12 P37 VSS_402 VSS_BR38 BT3
AK29 VSS_79 VSS_160 W33 BJ12 VSS_241 VSS_322 T13 M14 VSS_403 VSS_BT3 BT35
AK30 VSS_80
6 OF VSS_161
13 W34 BJ14 VSS_2427 OF VSS_323
13 T14 M6 VSS_404 VSS_BT35 BT36
VSS_81 VSS_162 VSS_243 VSS_324 N1 VSS_405 VSS_BT36 BT4
CFL-H_BGA1440 CFL-H_BGA1440 F11 VSS_406 VSS_BT4 C2
F13 VSS_4078 OF 13VSS_C2 D38
VSS_408 VSS_D38
CFL-H_BGA1440
A A
CFL-H(8/8) GND
5 4 3 2 1
5 4 3 2 1
+1.8V_PRIM +1.8V_PRIM
100K_0201_5%
1
4.7K_0201_5%
RH604
@
RH607
2
2
CNV_COEX1 CNV_BRI_PTX_DRX
100K_0201_5%
1
VCCSPI hard strap
10K_0201_5%
@
1
Xtal Frequency select
RH603
CNP-H
RH608
Vinafix.com UH1M HIGH 1.8V
* HIGH 24MHz
2
CAM_MIC_CBL_DET# AW13 BD4
2
<38> CAM_MIC_CBL_DET# GPP_G0/SD_CMD CNV_WR_CLKN CLK_CNV_PRX_DTX_N <52>
BE9 BE3
D
<27> GPU_EVENT#
<42> TBT_CIO_PLUG_EVENT#
BF8 GPP_G1/SD_DATA0
GPP_G2/SD_DATA1
CNV_WR_CLKP CLK_CNV_PRX_DTX_P <52> * LOW 3.3V 38.4/19.2MHz
(default) D
BF9 BB3
<27> GPU_GC6_FB_EN CONTACTLESS_DET# GPP_G3/SD_DATA2 CNV_WR_D0N CNV_PRX_DTX_N0 <52>
<65> CONTACTLESS_DET# BG8 BB4 CNP EDS rev0.7
HOST_SD_W P# GPP_G4/SD_DATA3 CNV_WR_D0P CNV_PRX_DTX_P0 <52>
BE8 BA3 An external pull-up is required on this strap
<70> HOST_SD_W P# GPP_G5/SD_CD# CNV_WR_D1N CNV_PRX_DTX_N1 <52>
BD8 BA2 since 38.4 MHz XTAL is not supported on the PCH.
GPP_G6/SD_CLK CNV_WR_D1P CNV_PRX_DTX_P1 <52>
AV13
<56> SMART_SPK_DET0# GPP_G7/SD_WP BC5
CNV_WT_CLKN CLK_CNV_PTX_DRX_N <52>
FOLLOW X10 H Dell GPIO map AP3 BB6 +1.8V_PRIM
GPP_I11/M2_SKT2_CFG0 CNV_WT_CLKP CLK_CNV_PTX_DRX_P <52>
AP2
AN4 GPP_I12/M2_SKT2_CFG1 BE6
GPP_I13/M2_SKT2_CFG2 CNV_WT_D0N CNV_PTX_DRX_N0 <52>
AM7 BD7
20K_0201_5%
2
GPP_I14/M2_SKT2_CFG3 CNV_WT_D0P CNV_PTX_DRX_P0 <52>
BG6
CNV_WT_D1N CNV_PTX_DRX_N1 <52>
<52> CNV_COEX3 AV6 BF6
GPP_J1 GPP_J0/CNV_PA_BLANKING CNV_WT_D1P CNV_W T_RCOMP CNV_PTX_DRX_P1 <52>
1 2 AY3 BA1 2 1
RH605
<11,89> CPU_C10_GATE# GPP_J1/CPU_C10_GATE# CNV_WT_RCOMP
@ RH616 0_0402_5% AR13 RH612 150_0402_1%
AV7 GPP_J11/A4WP_PRESENT B12 PCIECOMP# 2 1
1
RH446 @1 2 AW3 GPP_J10 PCIE_RCOMPN A13 PCIECOMP RH192 100_0402_1% CNV_RGI_PTX_DRX
<18,19,65> SIO_SLP_S0# GPP_J_2 PCIE_RCOMPP
0_0201_5% AT10 BE5 SD_RCOMP_1P8 2 1
+1.8V_PRIM CNV_BRI_PTX_DRX GPP_J_3 SD_1P8_RCOMP SD_RCOMP_3P3 RH611 2
AV4 BE4 1 200_0402_1%
1
<52> CNV_BRI_PTX_DRX CNV_BRI_PRX_DTX GPP_J4/CNV_BRI_DT/UART0B_RTS# SD_3P3_RCOMP
AY2 BD1 200_0402_1% M.2 CNV Mode Select
100K_0201_5%
<52> CNV_BRI_PRX_DTX RH610
1 2 CNV_BRI_PRX_DTX CNV_RGI_PTX_DRX BA4 GPP_J5/CNV_BRI_RSP/UART0B_RXDGPPJ_RCOMP_1P81 BE1 GPPJ_RCOMP 2 1 @
<52> CNV_RGI_PTX_DRX CNV_RGI_PRX_DTX GPP_J6/CNV_RGI_DT/UART0B_TXD GPPJ_RCOMP_1P82
@ RH614 20K_0402_5% AV3 BE2 RH609 200_0402_1%
RH606
CNV_RGI_PRX_DTX <52> CNV_RGI_PRX_DTX GPP_J7/CNV_RGI_RSP/UART0B_CTS#GPPJ_RCOMP_1P83 Integrated CNVi
1 2 AW2
@ RH613 20K_0402_5%
<52> CNV_COEX2
AU9 GPP_J8/CNV_MFUART2_RXD Y35 1 * HIGH disable
2
<52> CNV_COEX1 GPP_J9/CNV_MFUART2_TXD RSVD2 T34 @ PAD~D
CFL PDG rev0.5 Y36 1
To avoid floating input at the I/O pin it is recommended RSVD3 T33 @ PAD~D LOW Integrated CNVi
to add a weak pull up resistor to the SOC pin with a recommended value of 20K ohm. BC1 1 enable
13 OF 13 RSVD1 AL35 1 T36 @ PAD~D
TP T35 @ PAD~D
CNP-H_BGA874 Rev1.0
C C
CNP-H
UH1C
AR2 G36
<52> PCH_CL_CLK1 CL_CLK PCIE9_RXN PCIE_PRX_DTX_N9 <67>
AT5 F36
<52> PCH_CL_DATA1 CL_DATA PCIE9_RXP PCIE_PRX_DTX_P9 <67>
AU4 C34
<52> PCH_CL_RST1# CL_RST# PCIE9_TXN D34 PCIE_PTX_DRX_N9 <67>
P48 PCIE9_TXP PCIE_PTX_DRX_P9 <67>
GPP_K8 M.2 SSD
V47
V48 GPP_K9 K37 Slot#3
GPP_K10 PCIE10_RXN PCIE_PRX_DTX_N10 <67>
W47 J37
GPP_K11 PCIE10_RXP PCIE_PRX_DTX_P10 <67>
+3.3V_RUN C35
L47 PCIE10_TXN B35 PCIE_PTX_DRX_N10 <67>
L46 GPP_K0 PCIE10_TXP PCIE_PTX_DRX_P10 <67>
U48 GPP_K1 F44
CAM_MIC_CBL_DET# GPP_K2 PCIE15_RXN/SATA2_RXN PCIE_PRX_DTX_N15 <68>
1 2 U47 E45
GPP_K3 PCIE15_RXP/SATA2_RXP PCIE_PRX_DTX_P15 <68>
RH319 10K_0201_5% N48 B40
N47 GPP_K4 PCIE_15_SATA_2_TXN C40 PCIE_PTX_DRX_N15 <68>
GPP_K5 PCIE15_TXP/SATA2_TXP PCIE_PTX_DRX_P15 <68> M.2 SSD
P47
1 2 HOST_SD_W P# R46 GPP_K6 L41 Slot#6
GPP_K7 PCIE16_RXN/SATA3_RXN PCIE_PRX_DTX_N16 <68>
RH214 100K_0402_5% M40
HDD_DET# PCIE16_RXP/SATA3_RXP PCIE_PRX_DTX_P16 <68>
1 2 C36 B41
<67> PCIE_PTX_DRX_P11 B36 PCIE11_TXP/SATA0A_TXP PCIE16_TXN/SATA3_TXN C41 PCIE_PTX_DRX_N16 <68>
RH324 10K_0402_5%
BIOS_REC
M.2 SSD <67> PCIE_PTX_DRX_N11 PCIE11_TXN/SATA0A_TXN PCIE16_TXP/SATA3_TXP PCIE_PTX_DRX_P16 <68>
1 2 F39
RH76 10K_0402_5%
Slot#3 <67> PCIE_PRX_DTX_P11
G38 PCIE11_RXP/SATA0A_RXP K43
<67> PCIE_PRX_DTX_N11 PCIE11_RXN/SATA0A_RXN PCIE17_RXN/SATA4_RXN PCIE_PRX_DTX_N17 <67>
Reserve +3.3V_RUN for K44
PCH_TBT_PERST# 4/8 BIOS_REC PCIE17_RXP/SATA4_RXP PCIE_PRX_DTX_P17 <67>
AR42 A42
@RTD3@ 1 2 PCH_TBT_PERST# AR48 GPP_F10/SATA_SCLOCK PCIE17_TXN/SATA4_TXN B42 PCIE_PTX_DRX_N17 <67>
2 1 AU47 GPP_F11/SATA_SLOAD PCIE17_TXP/SATA4_TXP PCIE_PTX_DRX_P17 <67>
RT644 100K_0402_5% Tell EC don't read GFX Temp.in GC6 <59> GC6_THM_ON GPP_F13/SATA_SDATAOUT0 M.2 SSD
0_0402_5% @ RH6 AU46 P41
1 2 CONTACTLESS_DET# High: Read; Low: Don`t read GPP_F12/SATA_SDATAOUT1 PCIE18_RXN/SATA5_RXN R40
PCIE_PRX_DTX_N18 <67> Slot#4
PCIE18_RXP/SATA5_RXP PCIE_PRX_DTX_P18 <67>
RH90 10K_0402_5% C39 C42
<68> PCIE_PTX_DRX_N14 D39 PCIE14_TXN/SATA1B_TXN PCIE18_TXN/SATA5_TXN D42 PCIE_PTX_DRX_N18 <67>
1 2 SATALED# <68> PCIE_PTX_DRX_P14 D46 PCIE14_TXP/SATA1B_TXP PCIE18_TXP/SATA5_TXP PCIE_PTX_DRX_P18 <67>
<68> PCIE_PRX_DTX_N14 PCIE14_RXN/SATA1B_RXN
RH380 10K_0402_5% M.2 SSD <68> PCIE_PRX_DTX_P14
C47
PCIE14_RXP/SATA1B_RXP GPP_E8/SATA_LED#
AK48 SATALED#
SATALED# <67,68>
SPSGP0 1 M2_SLOT6_PEDET 0=SATA 1=PCIE
Slot#6 B38 AH41
<68> PCIE_PTX_DRX_N13 PCIE13_TXN/SATA0B_TXNGPP_E0/SATAXPCIE0/SATAGP0 M2_SLOT6_PEDET <68>
HDD <68> PCIE_PTX_DRX_P13
C38
PCIE13_TXP/SATA0B_TXPGPP_E1/SATAXPCIE1/SATAGP1
AJ43
M2_SLOT3_PEDET <67>
C45 AK47 HDD_DET#
<68> PCIE_PRX_DTX_N13 PCIE13_RXN/SATA0B_RXNGPP_E2/SATAXPCIE2/SATAGP2 HDD_DET# <67>
C46 AN47
<68> PCIE_PRX_DTX_P13 PCIE13_RXP/SATA0B_RXP
GPP_F0/SATAXPCIE3/SATAGP_3 M2_SLOT5_PEDET <68>
1 2 SATAGP5
GPP_F1/SATAXPCIE4/SATAGP4
AM46
M2_SLOT4_PEDET <67>
SPSGP2 1 HDD_DET# 0=SATA 1=PCIE
B @ RH325 10K_0201_5% M.2 SSD E37 AM43 SATAGP5 B
1 2 <67> PCIE_PTX_DRX_P12 D38 PCIE12_TXP/SATA1A_TXPGPP_F2/SATAXPCIE5/SATAGP5 AM47
SATAGP6
Slot#3 <67> PCIE_PTX_DRX_N12 PCIE12_TXN/SATA1A_TXNGPP_F3/SATAXPCIE6/SATAGP6
SATAGP6 Reserved
@ RH326 10K_0201_5%
<67> PCIE_PRX_DTX_P12
J41
PCIE12_RXP/SATA_1A_RXP
GPP_F4/SATAXPCIE7/SATAGP7
AM48 PCH_TBT_PERST#
PCH_TBT_PERST# <42>
H42
<67> PCIE_PRX_DTX_N12 PCIE12_RXN/SATA1A_RXN
FOLLOW X10 H Dell GPIO map AU48 FOLLOW X10 H Dell GPIO map
@ RT616 1 2 PCH_TBT_PERST# B44 GPP_F21/EDP_BKLTCTL AV46 BIA_PW M_PCH <38> SPSGP4 1 M2_SLOT4_PEDET 0=SATA 1=PCIE
100K_0402_5% <67> PCIE_PTX_DRX_P20 A44 PCIE20_TXP/SATA7_TXP GPP_F20/EDP_BKLTEN AV44 PANEL_BKEN_PCH <38>
<67> PCIE_PTX_DRX_N20 R37 PCIE20_TXN/SATA7_TXN GPP_F19/EDP_VDDEN ENVDD_PCH <38>
<67> PCIE_PRX_DTX_P20 PCIE20_RXP/SATA7_RXP PCH_THERMTRIP#
R35 AD3 1 2
<67> PCIE_PRX_DTX_N20 PCIE20_RXN/SATA7_RXN THRMTRIP# PCH_PECI H_THERMTRIP# <7,23,24,25,26,59>
M.2 SSD D43 AF2 RH75 1 2 620_0402_5% H_PECI
<67> PCIE_PTX_DRX_P19 PCIE19_TXP/SATA6_TXP PECI H_PM_SYNC_R H_PECI <7,58>
C44 AF3 RH73 1 2 13_0402_5% H_PM_SYNC
Slot#4 <67> PCIE_PTX_DRX_N19 N42 PCIE19_TXN/SATA6_TXN PM_SYNC AG5 RH156 30_0402_5% H_PM_SYNC <7>
+3.3V_ALW _PCH <67> PCIE_PRX_DTX_P19 PCIE19_RXP/SATA6_RXP 3 OF 13 PLTRST_CPU# PLTRST_CPU# <7>
M44 AE2
<67> PCIE_PRX_DTX_N19 PCIE19_RXN/SATA6_RXN PM_DOWN H_PM_DOW N <7>
CNP-H_BGA874 Rev1.0
FOLLOW X10 H Dell GPIO map
RTD3@ 1 2 PCH_TBT_PERST#
RT615 100K_0402_5%
PCH_PECI
1
@ RH74
10K_0402_5%
2
A A
Title
CNP-H(1/9) PCIE,CNV
C 1.0
5 4 3 2 1
5 4 3 2 1
Vinafix.com 0_0402_5% 2 1 @ RH66
D D
+3.3V_RUN
@ UC3 @ CH10
1 5 1 2
<7> XDP_DBRESET# IN B VCC
2 1 ME_RESET# 2 0.1U_0201_25V6K
@ RH70 8.2K_0402_5% IN A
CIS LINK OK 3 4 SYS_RESET#
GND OUT Y SYS_RESET# <18,19>
TC7SH09FU_SSOP5
CNP-H +3.3V_ALW_PCH
UH1B
K34 J3
<6> DMI_CTX_PRX_N0 DMI0_RXN USB2N_1 USB20_N1 <71> USB_OC1# RH710 1 2 10K_0402_5%
J35 J2
<6> DMI_CTX_PRX_P0 C33 DMI0_RXP USB2P_1 N13 USB20_P1 <71> ----->JUSB1 USB_OC2# RH711 1 2 10K_0402_5%
<6> DMI_CRX_PTX_N0 DMI0_TXN USB2N_2 USB20_N2 <71> USB_OC3# RH712 1 2 10K_0402_5%
B33 N15
<6> DMI_CRX_PTX_P0 G33 DMI0_TXP USB2P_2 K4 USB20_P2 <71> ----->JUSB2 USB_OC0# RH713 1 2 10K_0402_5%
<6> DMI_CTX_PRX_N1 F34 DMI1_RXN USB2N_3 K3 USB20_N3 <71>
C <6> DMI_CTX_PRX_P1 C32 DMI1_RXP USB2P_3 M10 USB20_P3 <71> ----->JUSB3 C
<6> DMI_CRX_PTX_N1 B32 DMI1_TXN USB2N_4 L9 USB20_N4 <44>
<6> DMI_CRX_PTX_P1 K32 DMI1_TXP USB2P_4 M1 USB20_P4 <44> ----->Cypress PD USB_OC4#
<6> DMI_CTX_PRX_N2 DMI2_RXN USB2N_5 USB20_N5 <44> RH714 1 2 10K_0402_5%
J32 L2
<6> DMI_CTX_PRX_P2 C31 DMI2_RXP USB2P_5 K7 USB20_N6 1 USB20_P5 <15,44> ----->Cypress PD USB_OC5#
USB_OC6#
RH715 1 2 10K_0402_5%
<6> DMI_CRX_PTX_N2 DMI2_TXN USB2N_6 T313 @ PAD~D RH716 1 2 10K_0402_5%
B31 K6 USB20_P6 1
<6> DMI_CRX_PTX_P2 G30 DMI2_TXP USB2P_6 L4 T314 @ PAD~D -----> M.2 2230 (BT) USB_OC7# RH717 1 2 10K_0402_5%
<6> DMI_CTX_PRX_N3 F30 DMI3_RXN USB2N_7 L3
<6> DMI_CTX_PRX_P3 C29 DMI3_RXP USB2P_7 G4
RP change to single Resister
<6> DMI_CRX_PTX_N3 B29 DMI3_TXN USB2N_8 G5 USB20_N8 <52>
<6> DMI_CRX_PTX_P3 A25 DMI3_TXP USB2P_8 M6 USB20_P8 <52>----->M.2 Slot-2 (WWAN/LTE/HCA)
B25 RSVD1 USB2N_9 N8
P24 RSVD2 USB2P_9 H3 ----->Touch Screen USB_OC3# 1 2
R24 RSVD3 USB2N_10 H2 USB20_N10 <65> USB_OC1# 1 2
@ RH718 15K_0402_5%
C26 RSVD4 USB2P_10 R10 USB20_P10 <65>----->USH USB_OC0# 1 2
@ RH719 15K_0402_5%
B26 RSVD5 USB2N_11 P9 USB20_N11 <38> USB_OC2# 1 2
@ RH720 15K_0402_5%
F26 RSVD6 USB2P_11 G1 USB20_P11 <38>----->Camera
@ RH721 15K_0402_5%
G26 RSVD7 USB2N_12 G2
B27 RSVD8 USB2P_12 N3 RP change to single Resistor
C27 RSVD9 USB2N_13 N2
L26 RSVD10 USB2P_13 E5
M26 RSVD11 USB2N_14 F6 USB20_N14 <52>
D29 RSVD12 USB2P_14 USB20_P14 <52> CNVi ----->M.2 2230 Slot-1 (WLAN/BT/WiGig)
E28 RSVD13 AH36 USB_OC0#
RSVD14 GPP_E9/USB2_OC0# Reserve
K29 AL40 USB_OC1#
M29 RSVD15 GPP_E10/USB2_OC1# AJ44 USB_OC2# USB_OC1# <71> ----->JUSB1
RSVD16 GPP_E11/USB2_OC2# AL41 USB_OC3# USB_OC2# <71> ----->JUSB2
G17 GPP_E12/USB2_OC3# AV47 USB_OC4# USB_OC3# <71> ----->JUSB3
<42> PCIE_PRX_TTX_N1 F16 PCIE1_RXN/USB31_7_RXNGPP_F15/USB2_OC4# AR35 USB_OC5# USB_OC4# <44> ----->TypeC PortA
<42> PCIE_PRX_TTX_P1 A17 PCIE1_RXP/USB31_7_RXP GPP_F16/USB2_OC5# AR37 USB_OC6# USB_OC5# <44> ----->TypeC PortB
<42> PCIE_PTX_TRX_N1 B17 PCIE1_TXN/USB31_7_TXN GPP_F17/USB2_OC6# AV43 USB_OC7# Reserve
<42> PCIE_PTX_TRX_P1 R21 PCIE1_TXP/USB31_7_TXP GPP_F18/USB2_OC7# Reserve
B <42> PCIE_PRX_TTX_N2 P21 PCIE2_RXN/USB31_8_RXN F4 USB2_COMP +3.3V_DSW B
RH193 1 2 113_0402_1%
<42> PCIE_PRX_TTX_P2 B18 PCIE2_RXP/USB31_8_RXP USB2_COMP F3 USB2_VBUSSENSE RH364 1 2 1K_0402_5%
<42> PCIE_PTX_TRX_N2 C18 PCIE2_TXN/USB31_8_TXN USB2_VBUSSENSE U13 1
TR TBT <42> PCIE_PTX_TRX_P2 PCIE2_TXP/USB31_8_TXP RSVD_1 USB2_ID T40 @ PAD~D @ RH3651
K18 G3 2 0_0402_5%
<42> PCIE_PRX_TTX_N3 J18 PCIE3_RXN/USB31_9_RXN USB2_ID
<42> PCIE_PRX_TTX_P3 B19 PCIE3_RXP/USB31_9_RXP BE41 TBT_RTD3_WAKE#_GPD7 1 2
<42> PCIE_PTX_TRX_N3 PCIE3_TXN/USB31_9_TXN GPD7 TBT_RTD3_WAKE# <18,42> TBT_RTD3_WAKE#_GPD7 1 2
C19 @ RH735 0_0402_5%
<42> PCIE_PTX_TRX_P3 N18 PCIE3_TXP/USB31_9_TXP G45 RH602 100K_0402_5%
<42> PCIE_PRX_TTX_N4 R18 PCIE4_RXN/USB31_10_RXN PCIE24_TXP G46 PCIE_PTX_DRX_P24 <68>
<42> PCIE_PRX_TTX_P4 D20 PCIE4_RXP/USB31_10_RXP PCIE24_TXN Y41 PCIE_PTX_DRX_N24 <68>
<42> PCIE_PTX_TRX_N4 C20 PCIE4_TXN/USB31_10_TXN PCIE24_RXP Y40 PCIE_PRX_DTX_P24 <68> Xtal input
<42> PCIE_PTX_TRX_P4 F20 PCIE4_TXP/USB31_10_TXP PCIE24_RXN G48 PCIE_PRX_DTX_N24 <68>
<51> PCIE_PRX_DTX_N5 G20 PCIE5_RXN PCIE23_TXP G49 PCIE_PTX_DRX_P23 <68> HIGH(DEFAULT) differential
LAN
<51> PCIE_PRX_DTX_P5 B21 PCIE5_RXP PCIE23_TXN W44 PCIE_PTX_DRX_N23 <68> LOW single-end
<51> PCIE_PTX_DRX_N5 A22 PCIE5_TXN PCIE23_RXP W43 PCIE_PRX_DTX_P23 <68>
<51> PCIE_PTX_DRX_P5 PCIE5_TXP PCIE23_RXN PCIE_PRX_DTX_N23 <68> M.2 SSD
K21 H48 CFL CRB rev0.5
<70> PCIE_PRX_DTX_N6 J21 PCIE6_RXN PCIE22_TXP H47 PCIE_PTX_DRX_P22 <68> Slot#5 Xtal input
<70> PCIE_PRX_DTX_P6 D21 PCIE6_RXP PCIE22_TXN U41 PCIE_PTX_DRX_N22 <68>
SD CARD <70> PCIE_PTX_DRX_N6 PCIE6_TXN PCIE22_RXP PCIE_PRX_DTX_P22 <68> High : differential
C21 U40 Low : single-end
<70> PCIE_PTX_DRX_P6 B23 PCIE6_TXP PCIE22_RXN F46 PCIE_PRX_DTX_N22 <68>
<52> PCIE_PTX_DRX_P7 C23 PCIE7_TXP PCIE21_TXP G47 PCIE_PTX_DRX_P21 <68> CNL- PCH EDS rev0.5
<52> PCIE_PTX_DRX_N7 J24 PCIE7_TXN PCIE21_TXN R44 PCIE_PTX_DRX_N21 <68> External pull-up is required. Recommend 100K if pulled
WLAN <52> PCIE_PRX_DTX_P7 PCIE7_RXP PCIE21_RXP PCIE_PRX_DTX_P21 <68> up to 3.3V
L24 T43
<52> PCIE_PRX_DTX_N7 F24 PCIE7_RXN PCIE21_RXN PCIE_PRX_DTX_N21 <68>
<52> PCIE_PRX_DTX_N8 G24 PCIE8_RXN
<52> PCIE_PRX_DTX_P8 B24 PCIE8_RXP
WWAN <52> PCIE_PTX_DRX_N8 PCIE8_TXN
C24 2 OF 13
<52> PCIE_PTX_DRX_P8 PCIE8_TXP
CNP-H_BGA874 Rev1.0
A A
Title
CannonLake PCH-H (2/9)
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
5 4 3 2 1
5 4 3 2 1
Vinafix.com
D D
CNP-H
UH1G
BE33
GPP_A16/CLKOUT_48
CPU_24MHZ_R_D @ RH169 1 2 0_0402_5% PCH_CPU_NSSC_CLK_D D7 Y3 PCH_XDP_CLK_DN_R @ RH154 1 2 0_0402_5% PCH_XDP_CLK_DN
<7> CPU_24MHZ_R_D CPU_24MHZ_R_D# PCH_CPU_NSSC_CLK_D# CLKOUT_CPUNSSC_P CLKOUT_ITPXDP# PCH_XDP_CLK_DP_R PCH_XDP_CLK_DN <7>
@ RH170 1 2 0_0402_5% C6 Y4 @ RH155 1 2 0_0402_5% PCH_XDP_CLK_DP
<7> CPU_24MHZ_R_D# CLKOUT_CPUNSSC# CLKOUT_ITPXDP_P PCH_XDP_CLK_DP <7>
PCH_CPU_BCLK_R_D @ RH161 1 2 0_0402_5% PCH_CPU_BCLK_D B8 B6 PCH_CPU_PCIBCLK_D# @ RH168 1 2 0_0402_5% PCH_CPU_PCIBCLK_R_D#
<7> PCH_CPU_BCLK_R_D PCH_CPU_BCLK_R_D#@ RH166 PCH_CPU_BCLK_D# CLKOUT_CPUBCLK_PCLKOUT_CPUPCIBCLK# PCH_CPU_PCIBCLK_D @ RH167 PCH_CPU_PCIBCLK_R_D# <7>
1 2 0_0402_5% C8 A6 1 2 0_0402_5% PCH_CPU_PCIBCLK_R_D
<7> PCH_CPU_BCLK_R_D# CLKOUT_CPUBCLK#CLKOUT_CPUPCIBCLK_P PCH_CPU_PCIBCLK_R_D <7>
XTAL24_OUT_R1 U9 AJ6
+1.0V_ALW_PCH pop RH171 for KBL-H XTAL24_IN_R1 U10 XTAL_OUT CLKOUT_PCIE_N0 AJ7 CLK_PEG_N0 <27>
pop RH435 for CFL-H , PDG 0.5 XTAL_IN CLKOUT_PCIE_P0 CLK_PEG_P0 <27> DGFF
@RH171 1 2 2.7K_0402_1% XCLK_RBIAS T3 AH9
XCLK_BIASREF CLKOUT_PCIE_N1 AH10 CLK_PCIE_N1 <70>
1 2 60.4_0402_1%
PCH_RTCX1 CLKOUT_PCIE_P1 CLK_PCIE_P1 <70> Card reader
RH435 BA49
PCH_RTCX2 BA48 RTCX1 AE14
2 1 10K_0201_5% RTCX2 CLKOUT_PCIE_N2 AE15 CLK_PCIE_N2 <52>
+3.3V_RUN RH123
CLKREQ_PEG#0 CLKOUT_PCIE_P2 CLK_PCIE_P2 <52> M.2 Slot2 WWAN
DGFF BF31
<27> CLKREQ_PEG#0 2 1 10K_0201_5% BE31 GPP_B5/SRCCLKREQ0# AE6
+3.3V_RUN RH124
CLKREQ_PCIE#1 AR32 GPP_B6/SRCCLKREQ1# CLKOUT_PCIE_N3 AE7 CLK_PCIE_N3 <51>
Card reader <70> CLKREQ_PCIE#1 GPP_B7/SRCCLKREQ2# CLKOUT_PCIE_P3 CLK_PCIE_P3 <51> LAN
RH126 2 1 10K_0201_5% BB30
+3.3V_RUN CLKREQ_PCIE#2 GPP_B8/SRCCLKREQ3#
M.2 Slot2 WWAN BA30 AC2
<52> CLKREQ_PCIE#2 2 1 10K_0201_5% AN29 GPP_B9/SRCCLKREQ4# CLKOUT_PCIE_N4 AC3 CLK_PCIE_N4 <42>
+3.3V_RUN RH127
CLKREQ_PCIE#3 GPP_B10/SRCCLKREQ5# CLKOUT_PCIE_P4 CLK_PCIE_P4 <42> TBT
LAN FOLLOW X10 H Dell GPIO map AE47
<51> CLKREQ_PCIE#3 2 1 10K_0201_5% AC48 GPP_H0/SRCCLKREQ6# AB2
+3.3V_RUN RH128
CLKREQ_PCIE#4 AE41 GPP_H1/SRCCLKREQ7# CLKOUT_PCIE_N5 AB3
TBT <42> CLKREQ_PCIE#4 GPP_H2/SRCCLKREQ8# CLKOUT_PCIE_P5
AF48
AC41 GPP_H3/SRCCLKREQ9# W4
2 1 10K_0201_5% AC39 GPP_H4/SRCCLKREQ10# CLKOUT_PCIE_N6 W3 CLK_PCIE_N6 <52>
+3.3V_RUN RH130
CLKREQ_PCIE#6 GPP_H5/SRCCLKREQ11# CLKOUT_PCIE_P6 CLK_PCIE_P6 <52> M.2 Slot1 WLAN
M.2 Slot1 WLAN AE39
C <52> CLKREQ_PCIE#6 2 1 10K_0201_5% AB48 GPP_H6/SRCCLKREQ12# W7 C
+3.3V_RUN RH131
CLKREQ_PCIE#7 AC44 GPP_H7/SRCCLKREQ13# CLKOUT_PCIE_N7 W6 CLK_PCIE_N7 <67>
M.2 Slot3 <67> CLKREQ_PCIE#7 GPP_H8/SRCCLKREQ14# CLKOUT_PCIE_P7 CLK_PCIE_P7 <67> M.2 Slot3
RH132 2 1 10K_0201_5% AC43
+3.3V_RUN CLKREQ_PCIE#8 GPP_H9/SRCCLKREQ15#
M.2 Slot4 AC14
<67> CLKREQ_PCIE#8 2 1 10K_0201_5% V2 CLKOUT_PCIE_N8 AC15 CLK_PCIE_N8 <67>
+3.3V_RUN RH133
CLKREQ_PCIE#9 CLKOUT_PCIE_N15 CLKOUT_PCIE_P8 CLK_PCIE_P8 <67> M.2 Slot4
M.2 Slot5 V3
<68> CLKREQ_PCIE#9 2 1 10K_0201_5% CLKOUT_PCIE_P15 U2
+3.3V_RUN RH134
CLKREQ_PCIE#10 T2 CLKOUT_PCIE_N9 U3 CLK_PCIE_N9 <68>
M.2 Slot6 <68> CLKREQ_PCIE#10 CLKOUT_PCIE_N14 CLKOUT_PCIE_P9 CLK_PCIE_P9 <68> M.2 Slot5
T1
CLKOUT_PCIE_P14 AC9
AA1 CLKOUT_PCIE_N10 AC11 CLK_PCIE_N10 <68>
CLKOUT_PCIE_N13 CLKOUT_PCIE_P10 CLK_PCIE_P10 <68> M.2 Slot6
Y2
CLKOUT_PCIE_P13 AE9
AC7 CLKOUT_PCIE_N11 AE11
AC6 CLKOUT_PCIE_N12 CLKOUT_PCIE_P11
CLKOUT_PCIE_P12 7 OF 13 R6
CLKIN_XTAL REFCLK_CNV <52>
CNP-H_BGA874 Rev1.0
2
RH110
10K_0402_5%
1
CH4
1 2 PCH_RTCX1_R 1 2 PCH_RTCX1 XTAL24_IN_R1 1 2 XTAL24_IN_R
@ RH43 0_0402_5% RH436 0_0201_5%
15P_0402_50V8J
1
1
B B
YH1 RH44 RH153
32.768KHZ_12.5PF_9H03200042 10M_0402_5% 1M_0402_1%
XTAL downsize
2
YH2
2
2
CH5 24MHZ_12PF_8Y24000034
1 2 PCH_RTCX2 XTAL24_OUT_R1 1 2 XTAL24_OUT 1 3
RH152 0_0201_5% 2 4
15P_0402_50V8J Remove RH437
1 CH13 change from 12P to 15P

CH14 1
CH13
15P_0402_50V8J
follow intel CFL-H PDG rev0.5, but CRB rev0.5 2 15P_0402_50V8J
2
A A
Title
CNP-H(3/9) CLK
5 4 3 2 1
5 4 3 2 1
+3.3V_ALW_PCH
+3.3V_ALW_PCH
Vinafix.com
5
1 2 SIO_EXT_SMI#
LPC@ RH310 10K_0402_5%
VCC
PCH_PLTRST# 1
D IN1 D
1 2 RTD3_CIO_PWR_EN 4 PCH_PLTRST#_AND @ RH619 1 2 0_0402_5%
LPC@ RH730 10K_0402_5% 2 OUT PCH_PLTRST#_R <42,52,67,68>
100K_0402_5%
GND
IN2
1
1 2 3.3V_CAM_EN#
@ RH65
ESD@ CH350
1
0.047U_0201_10V6K
RH736 100K_0402_5% @ RH622 1 2 0_0402_5% PLTRST_TPM#
3
UH7
MC74VHC1G08DFT2G_SC70-5
2
2
1 2 RTC_DET#
RH734 10K_0402_5%
for RTC_DET#
+3.3V_RUN CNP-H
UH1A
PAD~D @ T178 1 PME# BE36 AV29 PCH_PLTRST# @ RH623 2 1 0_0201_5%
GPP_A11/PME#/SD_VDD2_PWR_EN# GPP_B13/PLTRST# @ RH624 2 1 0_0201_5% PLTRST_TPM# <65>
@ RH625 2 1 0_0201_5% PLTRST_LAN# <51>
ESD@ CH349
1
0.047U_0201_10V6K
PAD~D @ T60 1 R15 Y47 @ RH626 1 2 0_0201_5% PLTRST_GPU# <27>
PAD~D @ T61 1 R13 RSVD2 GPP_K16/GSXCLK Y46 PLTRST_MMI# <70>
1 2 TOUCHPAD_INTR# RSVD1 GPP_K12/GSXDOUT Y48
RH402 10K_0402_5% GPP_K13/GSXSLOAD W46 2
PAD~D @ T63 1 AL37 GPP_K14/GSXDIN AA45
PAD~D @ T62 1 AN35 VSS GPP_K15/GSXSRESET#
TP
PCH_SPI_D0 AU41 AL47 SIO_EXT_SMI#
<7> PCH_SPI_D0 PCH_SPI_D1 SPI0_MOSI GPP_E3/CPU_GP0
BA45 AM45
PCH_SPI_CS#0 AY47 SPI0_MISO GPP_E7/CPU_GP1 BF32 TOUCHPAD_INTR#
PCH_SPI_CLK SPI0_CS0# GPP_B3/CPU_GP2 TOUCHPAD_INTR# <58,62>
AW47 BC33
+3.3V_SPI PCH_SPI_CS#1 AW48 SPI0_CLK GPP_B4/CPU_GP3
SPI0_CS1# AE44
Change to 1K 3/29 GPP_H18/SML4ALERT#
PCH_SPI_D2_XDP 1 2 PCH_SPI_D2 AY48 AJ46 FOLLOW X10 H Dell GPIO map
<7> PCH_SPI_D2_XDP
XDP@ RH180 PCH_SPI_D3
1K_0402_5% BA46 SPI0_IO2 GPP_H17/SML4DATA AE43 RTD3_CIO_PWR_EN RTD3_CIO_PWR_EN <42> +RTC_CELL_PCH
C AT40 SPI0_IO3 GPP_H16/SML4CLK AC47 GPP_H15 C
1 2 GPP_H12 <65> PCH_SPI_CS#2 Add WWAN_FULL_PWR_EN 3/6 SPI0_CS2# GPP_H15/SML3ALERT# AD48
GPP_H14/SML3DATA PCH Signal Glitch Free Implementation Requirements
1
@ RH615 2.2K_0402_5% Change net name 3/20 BE19 AF47
eSPI Flash sharing mode (GPP_H12) WWAN_FULL_PWR_EN BF19 GPP_D1/SPI1_CLK/SBK1_BK1 GPP_H13/SML3CLK AB47 GPP_H12 RH198 PCH_PLTRST# 1 2
<52> WWAN_FULL_PWR_EN
0 = Master Attached Flash Sharing (MAFS) enabled (Default) Change net location <84> RTC_DET#
RTC_DET# BF18 GPP_D0/SPI1_CS#/SBK0_BK0 GPP_H12/SML2ALERT# AD47 1M_0402_5% @RH641 100K_0201_5%
1 = Slave Attached Flash Sharing (SAFS) enabled.
from EC to PCH GPP_D3<38> 3.3V_CAM_EN# 3.3V_CAM_EN# BE18 GPP_D3/SPI1_MOSI/SBK3_BK3 GPP_H11/SML2DATA AE48 PCH_SPI_CLK 1 2
1 2 GPP_H15 Change net location BC17 GPP_D2/SPI1_MISO/SBK2_BK2 GPP_H10/SML2CLK
@RH640 100K_0201_5%
2
RH601 100K_0402_5% from BE41 to BE18 BD17 GPP_D22/SPI1_IO3 1 OF 13 BB44 PCH_INTRUDER_HDR#
1 2 PCH_SPI_D0 GPP_D21/SPI1_IO2 INTRUDER#
RH600 100K_0402_5% CNP-H_BGA874 Rev1.0
1 2 PCH_SPI_D2
RH30 20K_0402_5% CFL-H PDG rev0.7
1 2 PCH_SPI_D3 pop 20K for SPI0_IO2/3
RH335 20K_0402_5%
CNL- PCH EDS rev0.5 PCH_SPI_D1_R1 RH722 1 2 33_0402_5% PCH_SPI_D1_0_R
<65> PCH_SPI_D1_R1
1 2 PCH_SPI_D3 Reserved External pull-up is required. Recommend 100K if pulled PCH_SPI_D0_R1 RH723 1 2 33_0402_5% PCH_SPI_D0_0_R
up to 3.3V <65> PCH_SPI_D0_R1 PCH_SPI_CLK_R1 RH724 1 2 33_0402_5% PCH_SPI_CLK_0_R
@ RH334 1K_0402_5%
<65> PCH_SPI_CLK_R1 PCH_SPI_D3_R1 RH725 1 2 33_0402_5% PCH_SPI_D3_0_R
9/5 MOW
Option 1: Implement a 1 kOhm pull-down resistor on the signal and de-populate the
required 1 kOhm pull-up resistor. In this case, customers must ensure that the SPI PCH_SPI_D1_R1 @ RH726 1 2 33_0402_5% PCH_SPI_D1_1_R
flash device on the platform has HOLD functionality disabled by default. PCH_SPI_D0_R1 @ RH727 1 2 PCH_SPI_D0_1_R
33_0402_5%
PCH_SPI_CLK_R1 @ RH728 1 2 33_0402_5% PCH_SPI_CLK_1_R
Note that the pull down resistor on SPI0_IO3 is only needed for SKL U/Y platforms
with ES and SKL S/H platforms with pre-ES1/ES1 samples. PCH_SPI_D3_R1 @ RH729 1 2 33_0402_5% PCH_SPI_D3_1_R
RP change to single Resistor
256Mb Flash ROM +3.3V_SPI
CH9
1 2
B B
0.1U_0201_10V6K
UC5
PCH_SPI_CS#0_R1 @ RH37 1 2 0_0402_5% PCH_SPI_CS#0_R2 1 8
PCH_SPI_D1_0_R 2 CS# VCC 7 PCH_SPI_D3_0_R
PCH_SPI_D2_R1 RH351 1 2 33_0402_5% PCH_SPI_D2_0_R 3 DO IO3 6 PCH_SPI_CLK_0_R
ESPI LPC 4 IO2 CLK 5 PCH_SPI_D0_0_R
GND DI 9
ThemalPad JSPI1
RH351 33 ohm 15 ohm 2 1 PCH_SPI_CS#1_R1 1
W25Q256JVEIQ_WSON8_8X6 0_0201_5% @ RH177 PCH_SPI_CS#1 2 1
2 1 PCH_SPI_D0_R1 3 2 2
RPC1 33 ohm 15 ohm 4.99_0402_1% RH178 PCH_SPI_D0 4 3
2 1 PCH_SPI_D1_R1 5 4 4
4.99_0402_1% RH179 PCH_SPI_D1 6 5
RH178,RH179,RH181, 0 ohm 25 ohm +3.3V_SPI 2 1 PCH_SPI_CLK_R1 7 6 6
RH182,RH183,RH184 4.99_0402_1% RH181 PCH_SPI_CLK 8 7
@ CH270 2 1 PCH_SPI_CS#0_R1 9 8 8
1 2 0_0201_5% @ RH182 PCH_SPI_CS#0 10 9
reserve SO8 Flash ROM for colay 2 1 PCH_SPI_D2_R1 11 10
11
10
0.1U_0201_10V6K 4.99_0402_1% RH183 PCH_SPI_D2 12
@ UC6 PCH_SPI_D3_R1 12 12
2 1 13
PCH_SPI_CS#0_R1 @ RH352 1 2 0_0402_5% PCH_SPI_CS#0_R3 1 8 4.99_0402_1% RH184 PCH_SPI_D3 14 13
CS# VCC 14 14
15
PCH_SPI_D1_1_R 2 7 PCH_SPI_D3_1_R +3.3V_SPI 15
SO/SIO1 RESET#/SIO3 +3.3V_ALW_PCH
16
PCH_SPI_CLK_1_R PCH_SPI_CLK_0_R 17 16 16
PCH_SPI_D2_R1 @ RH353 1 2 33_0402_5% PCH_SPI_D2_1_R 3 6 PCH_SPI_CLK_1_R 18 17
WP#/SIO2 SCLK 18 18
19
33_0402_5%
33_0402_5%
19
1
4 5 PCH_SPI_D0_1_R 20
@EMI@
@EMI@
GND SI/SIO0 20 20
RH28
RH29
MX25L25645GM2I-10G_SO8
2 1 21
0_0402_5% RH185 G1 22
G2 23
2
G3 24
G4
33P_0402_50V8J
33P_0402_50V8J
ACES_50559-02001-001
@EMI@
@EMI@
A A
1
CONN@
CH321
CH322
2
Title
CNP-H(4/9) SPI,PLTRST
B 1.0
5 4 3 2 1
5 4 3 2 1
+3.3V_ALW_PCH +3.3V_1.8V_GPPA
1 2 MEM_SMBCLK ESPI_RESET# 1 2
RH56 1K_0402_5% @ RH95 10K_0402_5%
1 2 MEM_SMBDATA For DATA lines: microstrip routing, R1 = 15 Ohm. Otherwise, R1 = 0 Ohm ESPI_ALERT# 1 2
RH57 1K_0402_5% For Clock line: R1 = 33 Ohm RH340 8.2K_0402_1%
1 2 SML0_SMBCLK CNP-H 571391_CFL_H_PDG_Rev1p8 Table 26-2. 9/5 SUSACK#_R 1 2
RH67 499_0402_1% UH1F @ RH327 1K_0402_5%
1 2 SML0_SMBDATA F9 BB39 ESPI_IO0_R RC366 1 2 15_0402_5%
<71> USB3_PTX_DRX_N1 USB31_1_TXN GPP_A1/LAD0/ESPI_IO0 ESPI_IO1_R ESPI_IO0 <58,59>
RH77 499_0402_1% F7 AW37 RC367 1 2 15_0402_5%
1 2 SML1_SMBCLK <71> USB3_PTX_DRX_P1 D11 USB31_1_TXP GPP_A2/LAD1/ESPI_IO1 AV37 ESPI_IO2_R ESPI_IO1 <58,59>
JUSB1 RC368 1 2 15_0402_5% ESPI_IO2 <58,59>
<71> USB3_PRX_DTX_N1 USB31_1_RXN GPP_A3/LAD2/ESPI_IO2 ESPI_IO3_R SYS_RESET#
RH80 1K_0402_5% C11 BA38 RC369 1 2 15_0402_5%
<71> USB3_PRX_DTX_P1 USB31_1_RXP GPP_A4/LAD3/ESPI_IO3 ESPI_IO3 <58,59>
Vinafix.com
SML1_SMBDATA
@ESD@ CC302
1 2
0.1U_0201_25V6K
RH81 1K_0402_5% C3
1 2 TBT_RTD3_WAKE#_R <52> USB3_PTX_DRX_N2 D4 USB31_2_TXN BE38
USB31_2_TXP GPP_A5/LFRAME#/ESPI_CS0#
1
RH731 10K_0402_5% <52> USB3_PTX_DRX_P2 B9 AW35 ESPI_ALERT# ESPI_CS# <58,59>
WWAN <52> USB3_PRX_DTX_N2 USB31_2_RXN GPP_A6/SERIRQ/ESPI_CS1# ESPI_ALERT# <58>
C9 BA36
D
correct status is 10K 3/29 <52> USB3_PRX_DTX_P2 USB31_2_RXP GPP_A7/PIRQA#/ESPI_ALERT0# BE39 SIO_RCIN# D
2
C17 GPP_A0/RCIN#/ESPI_ALERT1# BF38 ESPI_RESET#
C16 USB31_6_TXN GPP_A14/SUS_STAT#/ESPI_RESET# ESPI_RESET# <58,59>
+3.3V_ALW_PCH G14 USB31_6_TXP BB36 ESPI_CLK 1 2
USB31_6_RXN GPP_A9/CLKOUT_LPC0/ESPI_CLK PCI_CLK_LPC1 EMI@ RH97 1 ESPI_CLK_5105 <58,59>
F14 BB34 2 33_0402_5%
C15 USB31_6_RXP GPP_A10/CLKOUT_LPC1 @ RH99 22_0402_5%
B15 USB31_5_TXN T48 CHECK,LPC_CLK FOR DEBUG CARD? ESD Request:place near PCH side
1 2 PCH_SMB_ALERT# J13 USB31_5_TXP GPP_K19/SMI# T47 TBT_RTD3_WAKE#_R 1 2
K13 USB31_5_RXN GPP_K18/NMI# TBT_RTD3_WAKE# <15,42>
RH61 4.7K_0402_5% @ RH732 0_0402_5% RF Request
TLS CONFIDENTIALITY USB31_5_RXP FOLLOW X10 H Dell GPIO map
HIGH ENABLE G12 AH40
LOW(DEFAULT) DISABLE <71> USB3_PTX_DRX_P3 F11 USB31_3_TXP GPP_E6/SATA_DEVSLP2 AH35
<71> USB3_PTX_DRX_N3 C10 USB31_3_TXN GPP_E5/SATA_DEVSLP1 AL48 SLOT3_DEVSLP <67>
JUSB2 <71> USB3_PRX_DTX_P3 USB31_3_RXP GPP_E4/SATA_DEVSLP0 SLOT6_DEVSLP <68>
B10 AP47
<71> USB3_PRX_DTX_N3 USB31_3_RXN GPP_F9/SATA_DEVSLP7
+3.3V_ALW_PCH AN37
C14 GPP_F8/SATA_DEVSLP6 AN46
<71> USB3_PTX_DRX_P4 B14 USB31_4_TXP GPP_F7/SATA_DEVSLP5 AR47 SML0_SMBCLK 1 2
1 2 GPP_C5 <71> USB3_PTX_DRX_N4 J15 USB31_4_TXN GPP_F6/SATA_DEVSLP4 AP48 SLOT4_DEVSLP <67> @RF@ CC318 33P_0402_50V8J
JUSB3 <71> USB3_PRX_DTX_P4 USB31_4_RXP
ESPI@ RH78 4.7K_0402_5% K16 6 OF 13GPP_F5/SATA_DEVSLP3
<71> USB3_PRX_DTX_N4 USB31_4_RXN SML1_SMBCLK
EC interface 1 2
HIGH ESPI CNP-H_BGA874 Rev1.0 @RF@ CC319 33P_0402_50V8J
LOW(DEFAULT) LPC
MEM_SMBCLK 1 2
@RF@ CC320 33P_0402_50V8J
+3.3V_ALW_PCH
Place close PCH side
RF@ 1 2 1 2 CNP-H
1 2 SPKR CH268 47P_0402_50V8J @RH637 100K_0201_5% UH1D
@ RH86 4.7K_0402_5% 1 2 HDA_BIT_CLK BD11 BF36
TOP SWAP STRAP <56> HDA_BIT_CLK_R EMI@ RH46 33_0402_5% HDA_SDIN0 BE11 HDA_BCLK/I2S0_SCLK GPP_A12/BM_BUSY#/ISH_GP6/SX_EXIT_HOLDOFF# AV32 CLKRUN#
<56> HDA_SDIN0 HDA_SDOUT HDA_SDI0/I2S0_RXD GPP_A8/CLKRUN#
HIGH ENABLE 1 2 BF12
LOW(DEFAULT) DISABLE <56> HDA_SDOUT_R ME_FWP_PCH RH45 1 2 33_0402_5% BG13 HDA_SDO/I2S0_TXD BF41
HDA_SYNC/I2S0_SFRM GPD11/LANPHYPC PM_LANPHY_ENABLE <51>
RH328 1 2 1K_0402_5% HDA_SYNC
<56> HDA_SYNC_R RH48 1 2 33_0402_5% HDA_RST# BE10 BD42
<56> HDA_RST#_R HDA_RST#/I2S1_SCLK GPD9/SLP_WLAN# SIO_SLP_WLAN# <54,58> +3.3V_ALW_PCH
RH50 33_0402_5% BF10
C +3.3V_ALW_PCH BE12 HDA_SDI1/I2S1_RXD BB46 C
1 2 I2S1_TXD/SNDW2_DATA DRAM_RESET# DDR4_DRAMRST#_PCH <23>
@RH636 100K_0201_5% BD12 BE32 VRALERT#
I2S1_SFRM/SNDW2_CLK GPP_B2/VRALERT# BF33
GPP_B1/GSPI1_CS1#/TIME_SYNC1 BE29 VRALERT# 1 2
1 2 KB_DET# AUD_AZACPU_SDO 1 2 AUD_AZACPU_SDO_R AM2 GPP_B0/GSPI0_CS1# R47 @ RH203 10K_0402_5%
<9> AUD_AZACPU_SDO AN3 HDACPU_SDO GPP_K17/ADR_COMPLETE AP29 SIO_SLP_LAN# 1 2
RC74 10K_0402_5% RH39 30_0402_5%
CNV_RF_RESET# <9> AUD_AZACPU_SDI_R AUD_AZACPU_SCLK AUD_AZACPU_SCLK_R HDACPU_SDI GPP_B11/I2S_MCLK SYS_PWROK MACO_EN <27>
2 1 1 2 AM3 AU3 @ RH204 10K_0402_5%
<9> AUD_AZACPU_SCLK HDACPU_SCLK SYS_PWROK SYS_PWROK <7,58>
75K_0402_5% RH617 RH38 30_0402_5%
2 1 CLKREQ_CNV AV18 BB47 PCH_PCIE_WAKE#
GPP_D8/I2S2_SCLK WAKE# PCH_PCIE_WAKE# <42,58,59>
75K_0402_5% RH733 AW18 BE40 SIO_SLP_A#
CLKREQ_CNV BA17 GPP_D7/I2S2_RXD GPD6/SLP_A# BF40 SIO_SLP_LAN# SIO_SLP_A# <19,58>
<52> CLKREQ_CNV CNV_RF_RESET# GPP_D6/I2S2_TXD/MODEM_CLKREQ SLP_LAN# SIO_SLP_LAN# <54,58> +3.3V_DSW
Add pull down 75K BE16 BC28
<52> CNV_RF_RESET# 1 TBT_PWR_EN BF15 GPP_D5/I2S2_SFRM/CNV_RF_RESET# GPP_B12/SLP_S0# BF42 SIO_SLP_S0# <14,19,65>
T269 @ PAD~D IR_CAM_DET# GPP_D20/DMIC_DATA0/SNDW4_DATA GPD4/SLP_S3# SIO_SLP_S3# <19,42,59> PCH_PCIE_WAKE#
BD16 BE42 1 2
+3.3V_ALW_PCH <38> IR_CAM_DET# GPP_D19/DMIC_CLK0/SNDW4_CLK GPD5/SLP_S4# SIO_SLP_S4# <11,19,88>
AV16 BC42 RH92 1K_0201_5%
<27,58> DGPU_PWROK KB_DET# GPP_D18/DMIC_DATA1/SNDW3_DATA GPD10/SLP_S5# SIO_SLP_S5# <19> LAN_WAKE#
AW15 1 2
<62> KB_DET# GPP_D17/DMIC_CLK1/SNDW3_CLK BE45
+RTC_CELL_PCH SUSCLK RH93 10K_0201_5%
2
GPD8/SUSCLK BF44 PCH_BATLOW# SUSCLK <52,67,68> PCH_BATLOW# 1 2

RH329 GPD0/BATLOW# BE35 SUSACK#_R @ RH4431 2 0_0402_5% RH94 8.2K_0402_5%
150K_0402_5% GPP_A15/SUSACK# SUSACK# <58>
1 2 PCH_RTCRST# BE47 BC37 ME_SUS_PWR_ACK_R 1 AC_PRESENT 1 2
RTCRST# GPP_A13/SUSWARN#/SUSPWRDNACK PAD~D @ T319
RH200 1 220K_0402_5% SRTCRST# BD46 RH243 10K_0402_5%
RH201 20K_0402_5% SRTCRST#
1
GPP_B23 PCH_PWROK AY42 BG44 LAN_WAKE# +3.3V_RUN

<90> PCH_PWROK PCH_RSMRST#_AND PCH_PWROK GPD2/LAN_WAKE# AC_PRESENT LAN_WAKE# <51,58>
BA47 BG42
<7,62> PCH_RSMRST#_AND RSMRST# GPD1/ACPRESENT AC_PRESENT <58> SIO_RCIN#
WEAK INTERNAL PD ~20K BD39 1
SLP_SUS# SIO_SLP_SUS# <58> PAD~D @ T317
BE46 SIO_PWRBTN# <7,58>
PCH_DPWROK AW41 GPD3/PWRBTN# AU2 SYS_RESET# CLKRUN# 1
Intel DCI-OOB <58> PCH_DPWROK PCH_SMB_ALERT# BE25 DSW_PWROK SYS_RESET# AW29 SPKR
SYS_RESET# <15,19> PAD~D @ T318
GPP_C2/SMBALERT# GPP_B14/SPKR SPKR <56>
HIGH ENABLED MEM_SMBCLK BE26
GPP_C0/SMBCLK CPUPWRGD
AE3
H_PWRGD <7>
SYS_PWROK 1 2
MEM_SMBDATA BF26 RH199 100K_0402_5%
LOW(DEFAULT) DIABLED GPP_C5 BF24 GPP_C1/SMBDATA AL3
SML0_SMBCLK GPP_C5/SML0ALERT# ITP_PMODE PCH_JTAGX ITP_PMODE_CPU <7>
BF25 AH4
<42,51> SML0_SMBCLK SML0_SMBDATA GPP_C3/SML0CLK PCH_JTAGX PCH_JTAG_TMS PCH_JTAGX <7> IR_CAM_DET#
If USB 3.0 Port 1 is used for 4-wire DCI.OOB (BSSB), and alternate functionality is also used on the pin, BE24 AJ4 1 2
<42,51> SML0_SMBDATA GPP_B23 GPP_C4/SML0DATA PCH_JTAG_TMS PCH_JTAG_TDO PCH_JTAG_TMS <7>
pull up to V3.3S with >100K resistor to avoid noise. BD33 AH3 RH373 100K_0402_5%
SML1_SMBCLK GPP_B23/SML1ALERT#/PCHHOT# PCH_JTAG_TDO PCH_JTAG_TDI PCH_JTAG_TDO <7> PCH_JTAG_TCK
BF27 AH2 1 2
If USB 3.0 Port 1 is used for DCI.OOB (BSSB) 4-wire BSSB, and NO alternate functionalityis used, <58> SML1_SMBCLK SML1_SMBDATA BE27 GPP_C6/SML1CLK PCH_JTAG_TDI AJ3 PCH_JTAG_TCK PCH_JTAG_TDI <7>
B 4 OF 13 @ RH313 51_0402_5% B
leave float. <58> SML1_SMBDATA GPP_C7/SML1DATA PCH_JTAG_TCK PCH_JTAG_TCK <7> PCH_PWROK 1 2
CNP-H_BGA874 Rev1.0 @ RH424 10K_0402_5%
If DCI.OOB (BSSB) 2+2 functionality is used, pull up to V3.3S with a 4.7K resistor.
SUSCLK 1 2
@ RH83 1K_0402_5%
1 2 SRTCRST#
CH41 1U_0201_6.3V6M +1.0V_VCCSTG
PCH_RTCRST# HDA_SDIN0 HDA_SYNC HDA_SDOUT
1 2
CH40 1U_0201_6.3V6M SIO_SLP_SUS# RH441 1 2 0_0402_5% PCH_JTAG_TMS 1 2
PCH_PRIM_EN <11,22,89>
2P_0402_50V8C
@
2P_0402_50V8C
@
2P_0402_50V8C
@
<20> VCCDSW_EN_GPIO DS3@ RH312 51_0402_5%

1
<19,58> PCH_RTCRST# NDS3@ DH1 PCH_JTAG_TDI 1 2

RH314 51_0402_5%
1 2 1 2 2 1 VCCDSW_EN_Q RH442 1 2 0_0402_5% PCH_JTAG_TDO 1 2
CA73
CA74
CA76
2
1 2 <58> VCCDSW_EN
@ RH445 0_0402_5% @NDS3@ RH315 51_0402_5%
RB751S-40_SOD523-2 +3.3V_RUN
@ CMOS1 SHORT PADS~D
NDS3@ DH2 DDR_XDP_WAN_SMBDAT 1 2
place close to UH1 place close to UH1 place close to UH1 <43,62,86> ALW_PWRGD_3V_5V
1 2 RH374 2.2K_0402_5%
DDR_XDP_WAN_SMBCLK 1 2
Service Mode Switch: RB751S-40_SOD523-2 RH333 2.2K_0402_5%
Add a switch to ME_FWP signal to unlock the ME region and For DS3: PCH Signal Glitch Free Implementation Requirements
allow the entire region of the SPI flash to be updated using FPT. Pop RE349, RE536, RH439, RH441, RH443 SIO_SLP_S3# 1 2 SIO_SLP_S3# 1 2
RH215 Depop DH1, RH215, RH440, RH442
pop for MP 3/6 +3.3V_RUN @CH341 0.033U_0402_16V7 @RH634 100K_0201_5%
+3.3V_ALW_PCH ME_FWP SIO_SLP_S4# 1 2 SIO_SLP_S4# 1 2
1 2 ME_FWP_PCH For NDS3 :
POP NO Support Deep sleep @ RH100 0_0402_5% Pop DH1, RH215, RH440, RH442 @CH342 0.033U_0402_16V7 @RH635 100K_0201_5%
DE-POP Support Deep sleep Depop RE349, RE536, RH439, RH441, RH443 SIO_SLP_A# 1 2 SIO_SLP_A# 1 2
PT,ST pop RH101 and SW1; MP pop RH100 @CH343 0.033U_0402_16V7 @RH638 100K_0201_5%
SIO_SLP_WLAN# 1 2 SIO_SLP_WLAN# 1 2
1
PCH_DPWROK 1 2 PCH_RSMRST#_AND de-pop for MP

RH215 0_0402_5% @ RH101 @CH344 0.033U_0402_16V7 @RH629 100K_0201_5%
SIO_SLP_SUS# 1 2 SIO_SLP_SUS# 1 2
@NDS3@ 1K_0402_5% @CH345 0.033U_0402_16V7 @RH639 100K_0201_5%
1
0.01U_0402_16V7K
100K_0402_5%
MEM_SMBCLK 6 1
1 DDR_XDP_WAN_SMBCLK <7,23,24,25,26,54> SIO_SLP_LAN# 1 2 SIO_SLP_LAN# 1 2
1
10K_0402_5%
@
A A
2
@CH346 0.033U_0402_16V7 @RH631 100K_0201_5%

CH266
RH308
RC75
@ SW1 SIO_SLP_S5# 1 2
SIO_SLP_S5# 1 2
5
1 QH4A
2 <58> ME_FWP A @CH347 0.033U_0402_16V7 @RH632 100K_0201_5%
2 L2N7002DW1T1G_SC88-6 ESPI_RESET# 1 2
2
ME_FWP_PCH 3 B ESPI_RESET# 1 2
@RH633 75K_0201_5%
2
4 C MEM_SMBDATA 3 4 @CH348 0.033U_0402_16V7

G1 DDR_XDP_WAN_SMBDAT <7,23,24,25,26,54>
5
G2
SS3-CMFTQR9_3P QH4B
L2N7002DW1T1G_SC88-6
ME_FWP PCH has internal 20K PD.
(suspend power rail)
Title
FLASH DESCRIPTOR SECURITY OVERRIDE CNP-H(5/9) USB,HDA,SMB
LOW = ENABLE (DEFAULT) -->Pin1 & Pin3 short AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
B 1.0
HIGH = DISABLE (ME can update) -->Pin2 & Pin3 short DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5 4 3 2 1
5 4 3 2 1
+3.3V_RUN
1 2 FFS_INT2
RH378 10K_0402_5%
+3.3V_RUN
CNP-H
UH1K
1 2 UART2_TXD BBS_BIT6 BA26 BA20 MEM_INTERLEAVED LCD_CBL_DET# RC370 1 2 10K_0201_5%

GPP_B22/GSPI1_MOSI GPP_D9/ISH_SPI_CS#/GSPI2_CS0#
Vinafix.com
@ RH360 49.9K_0402_1% BD30 BB20 DGPU_HOLD_RST#
1 2 UART2_RXD 2 1 SIO_EXT_SCI# AU26 GPP_B21/GSPI1_MISO GPP_D10/ISH_SPI_CLK/GSPI2_CLK BB16 AR_DET# DGPU_HOLD_RST# <27> PCH_DPB_CTRL_CLK RH628 1 2 2.2K_0402_5%
@ RH361 49.9K_0402_1% RC561 @ 0_0402_5%<54> HDD_FALL_INT AW26 GPP_B20/GSPI1_CLK GPP_D11/ISH_SPI_MISO/GP_BSSB_CLK/GSPI2_MISO AN18 GPP_D12 PCH_DPB_CTRL_DATA RH221 1 2 2.2K_0402_5%
HDD_FALL_INT HDD_FALL_INT GPP_B19/GSPI1_CS0# GPP_D12/ISH_SPI_MOSI/GP_BSSB_DI/GSPI2_MOSI PCH_DPC_CTRL_CLK
1 2 RH222 1 2 2.2K_0402_5%
RH355 10K_0402_1% NRB_BIT BE30 BF14 PCH_DPC_CTRL_DATA RH223 1 2 2.2K_0402_5%
D
1 2 SIO_EXT_SCI# 2 1 TPM_PIRQ#_R BD29 GPP_B18/GSPI0_MOSI GPP_D16/ISH_UART0_CTS#/CNV_WCEN AR18 ISH_UART0_CTS# <52> PCH_DPD_CTRL_CLK D
<65> TPM_PIRQ# RH224 1 2 2.2K_0402_5%
TBT_ID BF29 GPP_B17/GSPI0_MISO GPP_D15/ISH_UART0_RTS#/GSPI2_CS1#/CNV_WFEN BF17 ISH_UART0_RTS# <52>WLAN PCH_DPD_CTRL_DATA
RH339 10K_0402_5% RC560 0_0402_5% RH225 1 2 2.2K_0402_5%
NRB_BIT GPP_B16/GSPI0_CLK GPP_D14/ISH_UART0_TXD/I2C2_SCL ISH_UART0_TXD <52>
1 2 BB26 BE17 Change to pop 4/1
<70> MEDIACARD_IRQ# GPP_B15/GSPI0_CS0# GPP_D13/ISH_UART0_RXD/I2C2_SDA ISH_UART0_RXD <52>
@ RH331 4.7K_0402_5%
PCH STRAPS IF SAMPLED HIGH[ NO REBOOT ] BB24
<59> SBIOS_TX BE23 GPP_C9/UART0A_TXD
TYPEC_CON_SEL2 AP24 GPP_C8/UART0A_RXD
+3.3V_ALW_PCH TYPEC_CON_SEL1 BA24 GPP_C11/UART0A_CTS#
Align BH 1/221 GPP_C10/UART0A_RTS# AG45 DGPU_HOLD_RST# @ RH350 1 2 100K_0402_5%
BD21 GPP_H20/ISH_I2C0_SCL AH46
LCD_CBL_DET# AW24 GPP_C15/UART1_CTS#/ISH_UART1_CTS# GPP_H19/ISH_I2C0_SDA
1 2 SIO_EXT_WAKE# <38> LCD_CBL_DET# AP21 GPP_C14/UART1_RTS#/ISH_UART1_RTS# AH47
RH309 10K_0402_5% SIO_EXT_WAKE# AU24 GPP_C13/UART1_TXD/ISH_UART1_TXD GPP_H22/ISH_I2C1_SCL AH48
<58> SIO_EXT_WAKE# GPP_C12/UART1_RXD/ISH_UART1_RXD GPP_H21/ISH_I2C1_SDA
8/20
1 2 UART2_TXD AV21
RH330 49.9K_0402_1% AW21 GPP_C23/UART2_CTS#
UART2_TXD BE20 GPP_C22/UART2_RTS# AV34 LID_CL#_PCH 1 GPP_D12 @ RH349 1 2 100K_0402_5%
UART2_RXD <44> UART2_TXD UART2_RXD GPP_C21/UART2_TXD GPP_A23/ISH_GP5 TPM_TYPE PAD~D @ T268
1 2 BD20 AW32
<44> UART2_RXD GPP_C20/UART2_RXD GPP_A22/ISH_GP4
RH376 49.9K_0402_1% BA33
BE21 GPP_A21/ISH_GP3 BE34
<62> I2C1_SCK_TP BF21 GPP_C19/I2C1_SCL GPP_A20/ISH_GP2 BD34
<62> I2C1_SDA_TP GPP_C18/I2C1_SDA GPP_A19/ISH_GP1
1 2 CPU_EDP_HPD 1 BC22 BF35 CLKDET# 1 TPM_TYPE 1 2
T307 @ PAD~D GPP_C17/I2C0_SCL GPP_A18/ISH_GP0 PAD~D @ T258
RH1 100K_0402_5% 1 BF23 BD38 Reserved @ RH379 100_0402_1%
T306 @ PAD~D GPP_C16/I2C0_SDA GPP_A17/SD_VDD1_PWR_EN#/ISH_GP7
BE15
<42> TBT_FORCE_PWR FFS_INT2 GPP_D4/ISH_I2C2_SDA/I2C3_SDA/SBK4_BK4
BE14 11 OF 13
<54> FFS_INT2 GPP_D23/ISH_I2C2_SCL/I2C3_SCL
CNP-H_BGA874 Rev1.0
C C
+3.3V_ALW_PCH
1
@ RH311
8.2K_0402_5% +3.3V_ALW_PCH +3.3V_ALW_PCH
CNP-H
UH1E
2
2
AL13 PCH_DPB_CTRL_CLK
BBS_BIT6 GPP_I5/DDPB_CTRLCLK AR8 PCH_DPB_CTRL_DATA @ RH555 @ RH553
AT6 GPP_I6/DDPB_CTRLDATA AN13 PCH_DPC_CTRL_CLK
<31> PCH_DPB_HPD GPP_I0/DDPB_HPD0/DISP_MISC0 GPP_I7/DDPC_CTRLCLK PCH_DPC_CTRL_CLK <30> 10K_0402_5% 10K_0402_5%
AN10 AL10 PCH_DPC_CTRL_DATA
<30> PCH_DPC_HPD GPP_I1/DDPC_HPD1/DISP_MISC1 GPP_I8/DDPC_CTRLDATA PCH_DPD_CTRL_CLK PCH_DPC_CTRL_DATA <30>
BOOT BIOS Destination(Bit 6) AP9 AL9
<28> PCH_DPD_HPD
1
AL15 GPP_I2/DDPD_HPD2/DISP_MISC2 GPP_I9/DDPD_CTRLCLK AR3 PCH_DPD_CTRL_DATA +3.3V_RUN
GPP_I3/DDPF_HPD3/DISP_MISC3 GPP_I10/DDPD_CTRLDATA AN40 TYPEC_CON_SEL1 TYPEC_CON_SEL2
HIGH LPC @ RH6301 2 100K_0402_5% GPP_F23/DDPF_CTRLDATA AT49 GPP_F22 @ RC444 1 2 10K_0402_5%
LOW(DEFAULT) SPI GPP_F22/DDPF_CTRLCLK
1
AP41 CRB RV0.7
CPU_EDP_HPD AN6 GPP_F14/PS_ON# @ RH556
<29> CPU_EDP_HPD GPP_I4/EDP_HPD/DISP_MISC4 10K_0402_5% @ RH554
M45 10K_0402_5%
2
GPP_K23/IMGCLKOUT1 L48
2
GPP_K22/IMGCLKOUT0 T45
GPP_K21 T46
5 OF 13 GPP_K20 AJ47
GPP_H23/TIME_SYNC0 Align BH 1/221
CNP-H_BGA874 Rev1.0
Vendor JAE FOXCON TBD TBD
TYPEC_CON_SEL1 LOW LOW HIGH HIGH
B TYPEC_CON_SEL2 LOW HIGH LOW HIGH B
+3.3V_ALW_PCH +3.3V_ALW_PCH Check ME about wire to board PN

JAPS1
+3.3V_RUN 1
+3.3V_ALW_PCH 1
2
<18,42,59> SIO_SLP_S3# 2
10K_0402_5%
+3.3V_ALW
3
3
2
@ RH267
4
<18> SIO_SLP_S5# 4
2
2
5
<11,18,88> SIO_SLP_S4# 5
RH371 @ RH400 6
<18,58> SIO_SLP_A# 7 6
10K_0402_5% 10K_0402_5% +3.3V_ALW 7
8
1
9 8
<18,58> PCH_RTCRST#
1
TBT_ID 10 9
11 10
<59,77> POWER_SW#_MB 11
1
MEM_INTERLEAVED AR_DET#
10K_0402_5%
12
13 12
<15,18> SYS_RESET# 13
RH268
14
15 14
<14,18,65> SIO_SLP_S0# 15
16
2
16
1
17
@ 18 17
RH372 RH401 18
19
10K_0402_5% 10K_0402_5% 20 GND1
GND2
2
TBT_ID DIMM TYPE AR_DET# CONN@

ACES_50506-01841-P01
Intel Management Engine Test Suite
HIGH Alpine Redge HIGH Interleave HIGH NON TBT
LOW Titan Redge
A A
LOW Non-Interleave LOW TBT
Title
CNP-H(6/9) GPIO,HPD,DDC
Custom 1.0
5 4 3 2 1
5 4 3 2 1
CNP-H
UH1H
+1.05V_PRIM +1.0V_ALW_PCH +3.3V_ALW_PCH +3.3V_ALW_PCHRES +1.8V_PRIM +1.8V_ALW_PCHRES +RTC_CELL_PCH +3.3V_PRTC +1.05V_PRIM AA22 AW9 +3.3V_PHVC
AA23 VCCPRIM_1P051 VCCPRIM_3P32
8.21A VCCPRIM_1P052
AB20 BF47
VCCPRIM_1P053 DCPRTC1
0.1U_0201_10V6K
1 2 1 2 1 2 1 2 0.000416A 571182-cnl-pch-h-eds-rev2p2 AB22 BG47 +VCCRTCEXT
@ RH254 0_1206_5% @ RH279 0_1206_5% @ RH247 0_0603_5% @RH297 0_0402_5% P65 Table 10-6. AB23 VCCPRIM_1P054 DCPRTC2
VCCPRIM_1P055 1
CH68
AB27 V23 +3.3V_PUSB2
AB28 VCCPRIM_1P056 VCCPRIM_3P35
AB30 VCCPRIM_1P057 AN44 +3.3V_1.8V_SPI
+3.3V_ALW_PCHRES VCCPRIM_1P058 VCCSPI
+1.0V_ALW_PCH AD20 2
+1.8V_PRIM +1.8V_PRIM_PCH AD23 VCCPRIM_1P059 BC49
VCCPRIM_1P0510 VCCRTC1
Vinafix.com
eSPI Power AD27 BD49 +3.3V_PRTC
+1.0V_DSW +3.3V_1.8V_GPPA 1 2 AD28 VCCPRIM_1P0511 VCCRTC2
+1.8V_ALW_PCHRES @ RH242 0_0603_5% AD30 VCCPRIM_1P0512 AN21 +3.3V_PGPPG
1 2 0.0454A 1 2 0.101A 1 2 AF23 VCCPRIM_1P0513 VCCPGPPG_3P3 AY8
@ RH255 0_0402_5% RH291 0_0402_5% @ESPI@ RH294 0_0402_5% AF27 VCCPRIM_1P0516 VCCPRIM_3P33 BB7 +3.3V_PHVLDO
D VCCPRIM_1P0517 VCCPRIM_3P34 D
LPC@ +1.8V_PHVLDO AF30
+1.0V_PRIM_FUSE +3.3V_PGPPBC VCCPRIM_1P0518 AC35
0.882A1 2 +1.0V_MPHY U26 VCCPGPPHK1 AC36 +3.3V_PGPPHK
1 2 0.0012A 1 2 0.343A @ RH239 0_0603_5% U29 VCCPRIM_1P0523 VCCPGPPHK2 AE35
@RH256 0_0402_5% @RH304 0_0402_5% V25 VCCPRIM_1P0524 VCCPGPPEF1 AE36 +3.3V_PGPPEF
V27 VCCPRIM_1P0525 VCCPGPPEF2
+1.0V_PRIM_CNV_HVLO +3.3V_1.8V_GPPD V28 VCCPRIM_1P0526 AN24 +3.3V_1.8V_GPPD
+1.8V_ALW_PCHRES V30 VCCPRIM_1P0527 VCCPGPPD AN26
1 2 0.2A 1 2 0.14A 2 1 V31 VCCPRIM_1P0528 VCCPGPPBC1 AP26 +3.3V_PGPPBC
@RH257 0_0402_5% @RH293 0_0402_5% @ RH296 0_0402_5% VCCPRIM_1P0529 VCCPGPPBC2
+1.24V_DPHY +1.24V_LDOSRAM +1.0V_PRIM_FUSE AD31 AN32 +3.3V_1.8V_GPPA
+1.0V_SRC +3.3V_PGPPEF VCCPRIM_1P0514 VCCPGPPA
+1.0V_PRIM_CNV_HVLO AE17 AT44 +3.3V_FUSE
1 2 0.169A 1 2 0.174A 1 2 VCCPRIM_1P0515 VCCPRIM_3P31 BE48
@RH258 0_0402_5% @RH303 0_0402_5% @RH237 0_0402_5% W22 VCCDSW_3P31 BE49 +3.3V_DSW
+1.0V_DUSB W23 VCCDUSB_1P051 VCCDSW_3P32
+1.0V_BCLKPLL2 +3.3V_PGPPG VCCDUSB_1P052 BB14 +3.3V_1.8V_AZIO_R 2 1
+1.0V_DSW VCCHDA +3.3V_1.8V_AZIO
BG45 AG19 BLM15GA750SN1D_2P
VCCDSW_1P051 VCCPRIM_1P83
0.1U_0201_10V6K
1 2 0.021A 1 2 0.145A BG46 AG20 LC1
VCCDSW_1P052 VCCPRIM_1P84 1
0.1U_0201_10V6K
@RH259 0_0402_5% @RH305 0_0402_5% +1.0V_CLPLLEBB W31 AN15
CC310
VCCPRIM_MPHY_1P05 VCCPRIM_1P85 1
AR15 +1.8V_PRIM_PCH
CC329
+1.0V_DUSB +3.3V_PGPPHK D1 VCCPRIM_1P86 BB11 0.766A
+1.0V_AZPLL E1 VCCPRIM_1P0521 VCCPRIM_1P87 2
1 2 0.42A 1 2 0.262A +1.0V_OCPLL1_R C49 VCCPRIM_1P0522 AF19 +1.8V_PHVLDO 2
VCCAMPHYPLL_1P051 VCCPRIM_1P81 @
@RH286 0_0402_5% @RH306 0_0402_5% D49 AF20
1 2 E49 VCCAMPHYPLL_1P052 VCCPRIM_1P82
+1.0V_OCPLL1 +1.0V_AMPHYPLL
+2.8V_FHV0 BLM15GA750SN1D_2P VCCAMPHYPLL_1P053 AG31 +2.8V_FHV1
+3.3V_1.8V_SPI LC3 P2 VCCPRIM_1P0520 AF31 +2.8V_FHV0
+1.8V_ALW_PCHRES VCCA_XTAL_1P051 VCCPRIM_1P0519
1 2 0.0859A +1.0V_XTAL P3 AK22
1 2 0.05A 1 2 W19 VCCA_XTAL_1P052 VCCPRIM_1P241 AK23 1
0.1U_0201_10V6K
0.1U_0201_10V6K
@RH287 0_0402_5% +1.24V_LDOSRAM
1 1 +1.0V_SRC VCCA_SRC_1P051 VCCPRIM_1P242 PAD~D @ T287
@RH246 0_0402_5% @ RH250 0_0402_5% W20
VCCA_SRC_1P052
CC332
CC331
+2.8V_FHV1 AJ22
+1.0V_OCPLL1_R C1 VCCDPHY_1P241 AJ23 +1.24V_DPHY
1 2 0.193A +3.3V_1.8V_AZIO C2 VCCAPLL_1P054 VCCDPHY_1P242 BG5 +1.24V_DPHY_MAR 1
+1.8V_ALW_PCHRES 2@ 2 VCCAPLL_1P055 VCCDPHY_1P243 PAD~D @ T75
@RH288 0_0402_5% +1.0V_OC V19
C 1 2 0.00767A 2 1 VCCA_BCLK_1P05 K47 C
VCCMPHY_SENSE VCCMPHY_SENSE <89>
JUMP@ +1.0V_MPHY @RH292 0_0402_5% @ RH295 0_0402_5% B1 K46
+1.0V_BCLKPLL2_R VCCAPLL_1P051 VSSMPHY_SENSE VSSMPHY_SENSE <89>
PJP3 B2
2 1 6.66A 1 2 B3 VCCAPLL_1P052 8 OF 13
2 1 +3.3V_FUSE +1.0V_BCLKPLL2 VCCAPLL_1P053
BLM15GA750SN1D_2P 1
Rev1.0 1 PAD~D @ T76
JUMP_43X79 LC2 CNP-H_BGA874
PAD~D @ T77
+1.0V_CLPLLEBB 1 2 0.106A
@RH300 0_0402_5%
0.1U_0201_10V6K
0.1U_0201_10V6K
1 2 0.109A
1 1
@RH290 0_0402_5% +3.3V_PHVC
CC330
CC311
+1.0V_OC
1 2 0.182A
1 2 0.0085A @RH299 0_0402_5% 2@ 2
@RH260 0_0402_5%
+3.3V_PHVLDO
+1.0V_OCPLL1
1 2 0.97A
1 2 0.0198A @ RH298 0_0603_5%
@RH240 0_0402_5%
+3.3V_PUSB2
1 2 0.536A
@RH302 0_0402_5%
571182-cnl-pch-h-eds-rev2p2
P65 Table 10-6. +3.3V_DSW
+3.3V_ALW_PCH
0.113A
1 2
@NDS3@ RH440 0_0402_5% +3.3V_ALW
CNP-H
UH1J
Y14 1 @
RSVD7 PAD~D T288
Material shortage SB00000QP00 Y15 1 @
change to SB00000T900 1/15 RSVD8 PAD~D T289
U37 1 @ T290
RSVD6 U35 1 PAD~D
B DS3@ QH7 @ T291
B
RSVD5 PAD~D
PJ2301_SOT23-3
DS3@ N32
1 2 +3.3V_ALW_DSW_R
1 3 RSVD3 R32
S
D
RSVD4
499K_0402_1%
DS3@ RH432
RH439 0_0402_5%
1
AH15 1
RSVD2 PAD~D @ T294
AH14 1
PAD~D @ T295
G
2
RSVD1
2
AL2 PCH_XDP_PREQ#
PREQ# PCH_XDP_PRDY# PCH_XDP_PREQ# <7>
AM5
PRDY# CPU_XDP_TRST# PCH_XDP_PRDY# <7>
AM4
100K_0402_5%
CPU_TRST# CPU_XDP_TRST# <7>

2
PCH_2_CPU_TRIGGER_R
0.1U_0201_25V6K
49.9K_0402_1%
DS3@ RH433
RF Request AK3
TRIGGER_OUT
1
@ AK2 CPU_2_PCH_TRIGGER
RH431
TRIGGER_IN CPU_2_PCH_TRIGGER <10>

CH340
+3.3V_1.8V_AZIO_R +1.0V_CLPLLEBB 10 OF 13
2
CNP-H_BGA874 Rev1.0
1
2
L2N7002WT1G_SC-70-3
1 1
2.2P_0402_50V8C
2.2P_0402_50V8C
DS3@ QH6
RF@ CC327
RF@ CC328
D PCH_2_CPU_TRIGGER_R 1 2 PCH_2_CPU_TRIGGER
2 2 PCH_2_CPU_TRIGGER <10>
2 RH42 30_0402_5%
VCCDSW_EN_GPIO <18>
G
S
3
Change to DS3 4/1
A A
Title
CNP-H(7/9) PWR,RSVD
Custom 1.0
5 4 3 2 1
5 4 3 2 1
CNP-H CNP-H
UH1I UH1L
A2 AL12
PDG V1P8 Table 50-8 +1.0V_AMPHYPLL PDG V1P8 Table 50-8. +1.0V_AZPLL PDG V1P8 Table 50-9. +1.0V_XTAL A28 VSS1 VSS73 AL17 BG3 M24
+1.0V_ALW_PCH
1x 1uF 0402, close PCH 3mm
+1.0V_AMPHYPLL +1.0V_ALW_PCH Vinafix.com 1x 4.7uF, 0402, close PCH 5mm
+1.0V_AZPLL +1.0V_ALW_PCH
1x 22uF 0603 depop
+1.0V_XTAL
A3
A33
A37
VSS2
VSS3
VSS4
VSS74
VSS75
VSS76
AL21
AL24
AL26
BG33
BG37
BG4
VSS145
VSS146
VSS147
VSS196
VSS197
VSS198
M32
M34
M49
A4 VSS5 VSS77 AL29 BG48 VSS148 VSS199 M5
D LQM18PN2R2NC0L_2P~D LQM18PN2R2NC0L_2P~D A45 VSS6 VSS78 AL33 C12 VSS149 VSS200 N12 D
LH423 0.0015A LH421 1 0.00428A VSS7 VSS79 VSS150 VSS201
1 2 0.213A 1 2 2 A46 AL38 C25 N16
VSS8 VSS80 VSS151 VSS202
1U_0201_6.3V6M
RH241 0_0603_5% A47 AM1 C30 N34
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
4.7U_0402_6.3V6M
47U_0603_6.3V6M
Align Northbay pop LH423,CH560,CH324 Intel recommend to follow 2% spec A48 AM18 C4 N35
22U_0603_6.3V6M
22U_0603_6.3V6M
1 VSS10 VSS82 VSS153 VSS204
@ CH29
RH289 change to LH423 A5 AM32 C48 N37
CH324 change to pop 1 1 1 1 1 1 VSS11 VSS83 VSS154 VSS205
CH267
CH555
A8 AM49 C5 N38
CH560
CH324
@CH46
Add CH560 2 VSS12 VSS84 VSS155 VSS206
CH32
CH45
AA19 AN12 D12 P26
11/28 2 AA20 VSS13 VSS85 AN16 D16 VSS156 VSS207 P29
2 2 2 2 2 2 AA25 VSS14 VSS86 AN34 D17 VSS157 VSS208 P4
1 AA27 VSS15 VSS87 AN38 D30 VSS158 VSS209 P46
AA28 VSS16 VSS88 AP4 D33 VSS159 VSS210 R12
AA30 VSS17 VSS89 AP46 D8 VSS160 VSS211 R16
8/17 downsize to AA31 VSS18 VSS90 AR12 E10 VSS161 VSS212 R26
8/17 downsize to SE00000UC00 AA49 VSS19 VSS91 AR16 E13 VSS162 VSS213 R29
SE00000UC01, and add 1 uF AA5 VSS20 VSS92 AR34 E15 VSS163 VSS214 R3
AB19 VSS21 VSS93 AR38 E17 VSS164 VSS215 R34
AB25 VSS22 VSS94 AT1 E19 VSS165 VSS216 R38
AB31 VSS23 VSS95 AT16 E22 VSS166 VSS217 R4
AC12 VSS24 VSS96 AT18 E24 VSS167 VSS218 T17
PDG V1P8 Table 50-8 +VCCPRIM_1P8 PDG V1P8 Table 50-8 +VCCPRIM_1P05 AC38 VSS27 VSS99 AT26 E33 VSS170 VSS221 T4
PDG V1P8 Table 50-8 +1.05V_PRIM 1x 4.7uF 0603, close PCH 3mm PDG V1P8 Table 50-8 VCCAPLL_1P05 1x 1uF 0402, 3mm, close PCH 5mm AC4 VSS28 VSS100 AT29 E35 VSS171 VSS222 T49
1x 1uF, 0402, close PCH 3mm 1x 1uF 0402, close PCH 3mm 1x 1uF, 0402, close PCH 5mm 1x 22uF 0805, 5mm, close PCH 5mm AC46 VSS29 VSS101 AT32 E40 VSS172 VSS223 T5
AD1 VSS30 VSS102 AT34 E42 VSS173 VSS224 T7
+1.05V_PRIM +1.8V_PRIM_PCH +1.0V_OCPLL1_R +1.0V_BCLKPLL2_R +1.0V_MPHY VSS31 VSS103 VSS174 VSS225
AD19 AT45 E8 U12
AD2 VSS32 VSS104 AV11 F41 VSS175 VSS226 U15
AD22 VSS33 VSS105 AV39 F43 VSS176 VSS227 U17
AD25 VSS34 VSS106 AW10 F47 VSS177 VSS228 U21
4.7U_0402_6.3V6M
AD49 AW4 G44 U24

1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
22U_0603_6.3V6M
AE12 AW40 G6 U33
1U_0201_6.3V6M
1 1 1 1 1 1 1 VSS37 VSS109 VSS180 VSS231

AE33 AW46 H8 U38
CH36
CH22
CH20
CH31
CH34
CH47
C AE38 B47 J10 V20 C
CH21
AE4 VSS39 VSS111 B48 J26 VSS182 VSS233 V22

2 2 2 2 2 2 2 AE46 VSS40 VSS112 B49 J29 VSS183 VSS234 V4
AF22 VSS41 VSS113 BA12 J4 VSS184 VSS235 V46
AF25 VSS42 VSS114 BA14 J40 VSS185 VSS236 W25
AF28 VSS43 VSS115 BA44 J46 VSS186 VSS237 W27
AG1 VSS44 VSS116 BA5 J47 VSS187 VSS238 W28
AG22 VSS45 VSS117 BA6 J48 VSS188 VSS239 W30
8/17 downsize to 8/17 downsize to 8/17 downsize to AG23 VSS46 VSS118 BB41 J9 VSS189 VSS240 Y10
8/17 downsize to 8/17 downsize to SE00000UC00 SE00000UC00 SE00000UC00 AG25 VSS47 VSS119 BB43 K11 VSS190 VSS241 Y12
SE00000UC00 SE00000UC00 AG27 VSS48 VSS120 BB9 K39 VSS191 VSS242 Y17
AG28 VSS49 VSS121 BC10 M16 VSS192 VSS243 Y33
AG30 VSS50 VSS122 BC13 M18 VSS193 VSS244 Y38
AG49 VSS51 VSS123 BC15 M21 VSS194 VSS245
12 OF 13 Y9
AH12 VSS52 VSS124 BC19 VSS195 VSS246
AH17 VSS53 VSS125 BC24 CNP-H_BGA874 Rev1.0
PDG V1P8 Table 50-8 +VCCRTC PDG V1P8 Table 50-8 +VCCDPHY_1P24 PDG V1P8 Table 50-8 +VCCPRIM_3P3 AH33 VSS54 VSS126 BC26
1x 0.1uF 0402, close PCH 3mm 1x 4.7uF 0402, close PCH 5mm 1x 1uF, 0603, close PCH 3mm AH38 VSS55 VSS127 BC31
1x 1uF 0402, close PCH 5mm VSS56 VSS128
Place close to AY8, BB7 pins. AJ19
VSS57 VSS129
BC35
AJ20 BC40
+3.3V_PRTC +1.24V_DPHY_MAR +3.3V_PHVLDO AJ25 VSS58 VSS130 BC45
AJ27 VSS59 VSS131 BC8
AJ28 VSS60 VSS132 BD43
AJ30 VSS61 VSS133 BE44
VSS62 VSS134
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
AJ31 BF1
4.7U_0402_6.3V6M
VSS63 VSS135
1U_0201_6.3V6M
0.1U_0201_10V6K
1U_0201_6.3V6M
0.1U_0201_10V6K
1 1 1 1 1 1 AK19 BF2
1 VSS64 VSS136
@ CH323
AK20 BF3
VSS65 VSS137
CH33
CH65
CH559
CH37
CH67
AK25 BF48
CH30
AK27 VSS66 VSS138 BF49

2 2 2 2 2 2 2 AK28 VSS67 VSS139 BG17
AK30 VSS68 VSS140 BG2
AK31 VSS69 VSS141 BG22
B AK4 VSS70 VSS142 BG25 B
AK46 VSS71 9 OF VSS143
13 BG28
VSS72 VSS144
CNP-H_BGA874 Rev1.0
8/17 downsize 8/17 downsize to 8/17 Add CH559 8/17 downsize to 8/17 downsize to
to SE00000UC00 SE00000SV00 SE00000UC00 SE00000SV00
CFL-H PDG rev0.5 4.7uF x1
CRB-H rev0.7 0.1uF x1, 1uF x1
PDG V1P8 Table 50-8 depop, but reserved

+3.3V_PGPPEF +1.0V_OC +3.3V_PGPPHK +3.3V_DSW
+1.0V_DSW +1.0V_DUSB +1.0V_CLPLLEBB
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
@ CH62
@ CH64
0.1U_0201_10V6K
1 1 1 1
@ CH44
@ CH63
1U_0201_6.3V6M
0.1U_0201_10V6K
0.1U_0201_10V6K
1 1 1
CH35
CH38
CH66
2 2 2 2
2 2 2
8/17 downsize to
SE00000SV00
8/17 downsize to 8/17 downsize to 8/17 downsize to
SE00000UC00 SE00000SV00 SE00000SV00
A A
Title
CNP-H(8/9) PWR,CAP
5 4 3 2 1
5 4 3 2 1
+3.3V_ALW to +3.3V_DGFF
+1.2V_RUN Source +5V_ALW to +5V_DGFF +5V_DGFF
+5V_DGFF_PWR JUMP@
UZ41 PJP65
+1.2V_RUN_PWR +1.2V_RUN 1 14 +5V_DGFF_PWR 2 1
+5V_ALW_R VIN1_1 VOUT1_1 2 1
0.1U_0201_10V6K
82P_0402_50V8J
UZ43 JUMP@ 2 13
VIN1_2 VOUT1_2
RF@ CZ529
PJP66 1 2 1 1 JUMP_43X79
<11,22,58,59,67,70,89> RUN_ON
CZ513
+1.2V_MEM 1 7 2 1 @RZ549 0_0402_5% 3 12
VIN1 VOUT1 2 1 ON1 CT1
Vinafix.com
2 8 1 2
VIN2 VOUT2 <58> 3.3V_RUN_GFX_ON
0.1U_0201_10V6K
JUMP_43X79 @ RZ548 0_0402_5% 4 11
RUN_ON 3 6 VBIAS GND 2 2 +3.3V_DGFF_PWR +3.3V_DGFF
ON CT 1 +5V_ALW_R
CZ514
5 10 JUMP@
ON2 CT2 PJP43
D D
+3.3V_DGFF_PWR
470P_0402_50V7K
+5V_ALW
4 2 +3.3V_ALW_R
6 9 2 1
VBIAS 5 2 7 VIN2_1 VOUT2_1 8 2 1
GND1 VIN2_2 VOUT2_2
CZ515
0.1U_0201_10V6K
9 JUMP_43X79
GND2
470P_0402_50V7K
470P_0402_50V7K
82P_0402_50V8J
RF@ CZ528
15 2 2 1 1
1 GPAD
CZ518
CZ516
CZ517
AOZ1336DI_DFN8_2X2 EM5209VF_DFN14_3X2
1 1 2 2
+3.3V_ALW_PCH Source
+3.3V_ALW
+5V_RUN_PWR +5V_RUN
+3.3V_ALW_PCH_PWR +3.3V_ALW_PCH +3.3V_RUN /+5V_RUN Source JUMP@
UZ40 PJP40
UZ42 JUMP@ 1 14 +5V_RUN_PWR 2 1
+5V_ALW_R VIN1_1 VOUT1_1
PJP38 2 13
VIN1_2 VOUT1_2
0.1U_0201_10V6K
1 2 1 7 2 1 PAD-OPEN 4x4m
<11,18,89> PCH_PRIM_EN 2 VIN1 VOUT1 8 2 1 1 2 RUN_ON_R 3 12
@RZ509 0_0402_5% 1
VIN2 VOUT2 <11,22,58,59,67,70,89> RUN_ON ON1 CT1
0.1U_0201_10V6K
CZ519
@RZ510 0_0402_5%
3 6 JUMP_43X79 4 11
ON CT 1 +5V_ALW_R VBIAS GND
CZ520
+3.3V_RUN_PWR +3.3V_RUN
5 10 2 JUMP@
ON2 CT2
470P_0402_50V7K
+5V_ALW 4 PJP39
VBIAS 5 2 6 9 +3.3V_RUN_PWR 2 1
GND1 2 +3.3V_ALW_R VIN2_1 VOUT2_1 2 1
9 7 8
CZ521
GND2 VIN2_2 VOUT2_2 JUMP_43X79
1000P_0402_50V7K
470P_0402_50V7K
0.1U_0201_10V6K
15 2 2 1
GPAD
CZ522
1
CZ524
AOZ1336DI_DFN8_2X2
CZ523
EM5209VF_DFN14_3X2
1 1 2
C C
follow naming rule
+19.5VB_DGFF +19.5VB_DGFF
DGFF_PWR_SRC Source
100K_0402_5%
QZ19
1
JUMP@
AOSP21357L_SO8
RZ512
0.47U_0402_25V6K
+DGFF_PWR PJP67 +DGFF_PWR_SRC

1
1 8 JUMP_43X118
2 7 1
1 2
2 +1.8V_RUN Source
CZ526
3 6
2
5 +1.8V_RUN_PWR +1.8V_RUN
0.1U_0201_25V6K
100K_0402_5%
UZ45 JUMP@
1
82P_0402_50V8J
RF@
1 PJP42
4
+1.8V_RUN_PWR
CZ525
RZ513
PWR change AO4455 to AOSP21357L 1 7 2 1
+1.8V_PRIM VIN1 VOUT1 2 1
2 8
+DGFF_SRC_EN# VIN2 VOUT2
CZ545
0.1U_0201_10V6K
2
2 RUN_ON 3 6 JUMP_43X79
1
2
ON CT
1
20K_0402_5%
CZ120
RZ514
470P_0402_50V7K
1
CZ121
+5V_ALW_R
4
Material shortage SB00000J500 VBIAS 5 2
change to SB00001OO00 1/15 GND1 9
1 2
GND2 2
QZ20 D
3.3V_RUN_GFX_ON 2 AOZ1336DI_DFN8_2X2
100K_0402_5%
G DMN3150LW-7_SOT323-3
1
S
3
RZ547
B
VGS max =1.4V Special for EC VTR3 rail 1.8V. B
2
Discharg Circuit
+5V_RUN
1
RZ518
20_0603_5%
2
+5V_RUN_CHG
1
D
2 QZ21
<58> RUN_ON#
G L2N7002WT1G_SC-70-3
S
3
change SB00000UO00 to SB000009Q80/

SB00000ST00 as main source,
SB00000UO00 as 3rd source
A A
Title
CNP-H(9/9) Power Control
Custom 1.0
5 4 3 2 1
5 4 3 2 1
All VREF traces should

JDIMM1 REV Type H=5.2
+1.2V_MEM +1.2V_MEM
have 10 mil trace width JDIMM1
CH-B CH-A
1 2
DDR_A_D4 3 VSS1
DQ5
VSS2
DQ4
4 DDR_A_D1 REV STD
5 6
DDR_A_D0 7 VSS3 VSS4 8 DDR_A_D5 JDIMM4 -->CKE0,1 JDIMM2 -->CKE0,1
9 DQ1 DQ0 10
DDR_A_DQS#0 11 VSS5 VSS6 12 CPU D B Top Side
Vinafix.com
<8,24> DDR_A_CB[0..7] DDR_A_DQS0 DQS0_c DM0_n/DBI0_n
13 14 B A
15 DQS0_t VSS7 16 DDR_A_D6
<8,24> DDR_A_DQS#[0..3] DDR_A_D7 VSS8 DQ6
17 18
19 DQ7 VSS9 20 DDR_A_D2 C A Bottom Side
<8,24> DDR_A_DQS[0..3] DDR_A_D3 VSS10 DQ2
21 22
D 23 DQ3 VSS11 24 DDR_A_D9 JDIMM3 -->CKE2,3 JDIMM1 -->CKE2,3 D
<8,24> DDR_A_DQS#[4..7] DDR_A_D13 VSS12 DQ12
25 26
<8,24> DDR_A_DQS[4..7] DDR_A_D12
27 DQ13
VSS14
VSS13
DQ8
28 DDR_A_D8 STD REV
29 30
31 DQ9 VSS15 32 DDR_A_DQS#1
<8,24> DDR_A_D[0..63] VSS16 DQS1_c DDR_A_DQS1
33 34
35 DM1_n/DBI_n DQS1_t 36
<8,24> DDR_A_MA[0..13] DDR_A_D15 VSS17 VSS18 DDR_A_D10
37 38
39 DQ15 DQ14 40
+2.5V_MEM DDR_A_D14 41 VSS19 VSS20 42 DDR_A_D11
43 DQ10 DQ11 44 +1.2V_MEM
DDR_A_D21 45 VSS21 VSS22 46 DDR_A_D16
47 DQ21 DQ20 48
VSS23 VSS24
1U_0201_10V6M
1U_0201_10V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
DDR_A_D20 49 50 DDR_A_D17
DQ17 DQ16
1
1 1 1 1 51 52
DDR_A_DQS#2 53 VSS25 VSS26 54 RD4
DDR_A_DQS2 DQS2_c DM2_n/DBI2_n
CD1
CD2
CD3
CD4
55 56 470_0402_1%
2 2 2 2 DDR_A_D22 59 VSS28 DQ22 60
2
61 DQ23 VSS29 62 DDR_A_D23
DDR_A_D18 63 VSS30 DQ18 64 @ RD76 1 2 0_0402_5% DDR_A_DRAMRST#
DQ19 VSS31 DDR_A_D24 <18> DDR4_DRAMRST#_PCH DDR_B_DRAMRST# DDR_A_DRAMRST# <24>
downsize 65 66 @ RD77 1 2 0_0402_5%
DDR_A_D29 VSS32 DQ28 DDR_B_DRAMRST# <25,26>
change package to 0603 67 68
DQ29 VSS33
0.1U_0402_10V6K
69 70 DDR_A_D25
DDR_A_D28 71 VSS34 DQ24 72
DQ25 VSS35 1
+1.2V_MEM
@ CD5
73 74 DDR_A_DQS#3
75 VSS36 DQS3_c 76 DDR_A_DQS3
CD14 change to SGA20331E10 77 DM3_n/DBI3_n DQS3_t 78
DDR_A_D27 79 VSS37 VSS38 80 DDR_A_D26 2
81 DQ30 DQ31 82
VSS39 VSS40
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
DQ26 DQ27
330U_D2_2V_Y
1 85 86
DDR_A_CB0 87 VSS41 VSS42 88 DDR_A_CB1
1 1 1 1 1 1 1 1 <8,24> DDR_A_CB0 CB5/NC CB4/NC DDR_A_CB1 <8,24>
CD6
CD7
CD8
CD9
CD10
CD11
CD12
CD13
CD14
+ 89 90
<8,24> DDR_A_CB5 CB1/NC CB0/NC DDR_A_CB4 <8,24> JDIMM1_EVENT# H_THERMTRIP#
93 94 1 2
2 2 2 2 2 2 2 2 2 DDR_A_DQS#8 VSS45 VSS46 H_THERMTRIP# <7,14,24,25,26,59>
95 96 @ RD7 1K_0402_5%
<8,24> DDR_A_DQS#8 DDR_A_DQS8 DQS8_c DM8_n/DBI_n/NC
97 98
<8,24> DDR_A_DQS8 DQS8_t VSS47 DDR_A_CB7
99 100
DDR_A_CB3 VSS48 CB6/NC DDR_A_CB7 <8,24>
101 102
<8,24> DDR_A_CB3 CB2/NC VSS49 DDR_A_CB6
103 104
105 106
C <8,24> DDR_A_CB2 CB3/NC VSS51 DDR_A_DRAMRST# C
107 108 1 2
DDR_A_CKE2 109 VSS52 RESET_n 110 DDR_A_CKE3 @ CD15 0.1U_0201_10V6K
<8> DDR_A_CKE2 CKE0 CKE1 DDR_A_CKE3 <8>
111 112
DDR_A_BG1 113 VDD1 VDD2 114 DDR_A_ACT# +1.2V_MEM
<8,24> DDR_A_BG1 DDR_A_BG0 BG1 ACT_n DDR_A_ALERT# DDR_A_ACT# <8,24>
115 116
<8,24> DDR_A_BG0 BG0 ALERT_n DDR_A_ALERT# <8,24>
1U_0201_10V6M
1U_0201_10V6M
1U_0201_10V6M
1U_0201_10V6M
1U_0201_10V6M
1U_0201_10V6M
1U_0201_10V6M
1U_0201_10V6M
117 118
VDD3 VDD4
0.1U_0402_10V6K
DDR_A_MA12 119 120 DDR_A_MA11
1 1 1 1 1 1 1 1 A12 A11
1
+DDR_VREF_CA +V_DDR_REFCA_B
1K_0402_5%
@ CD16
A9 A7 1
CD17
CD18
CD19
CD20
CD21
CD22
CD23
CD24
RD8
123 124
DDR_A_MA8 125 VDD5 VDD6 126 DDR_A_MA5 1 2 +V_DDR_REFCA_B
2 2 2 2 2 2 2 2 DDR_A_MA6 127 A8 A5 128 DDR_A_MA4 @ RD9 2_0402_1%
129 A6 A4 130 2
2
DDR_A_MA3 131 VDD7 VDD8 132 DDR_A_MA2 1 2 +V_DDR_REFCA_A
downsize DDR_A_MA1 133 A3 A2 134 JDIMM1_EVENT# RD10 2_0402_1%
A1 EVENT_n/NF
0.022U_0402_16V7K
0.1U_0402_10V6K
135 136
VDD9 VDD10
1
@ CD26
1K_0402_5%
DDR_A_CLK2 137 138 DDR_A_CLK3
<8> DDR_A_CLK2 CK0_t CK1_t/NF DDR_A_CLK3 <8> 1 1
RD11
DDR_A_CLK#2 139 140 DDR_A_CLK#3
<8> DDR_A_CLK#2 CK0_c CK1_c/NF DDR_A_CLK#3 <8>
CD25
141 142
Layout Note: <8,24> DDR_A_PARITY
DDR_A_PARITY 143 VDD11 VDD12 144 DDR_A_MA0
PARITY A0 2 2
Place near JDIMM1.258
2
DDR_A_BA1 145 146 DDR_A_MA10
<8,24> DDR_A_BA1 BA1 A10/AP
147 148
DDR_A_CS#2 149 VDD13 VDD14 150 DDR_A_BA0
<8> DDR_A_CS#2 DDR_A_BA0 <8,24>
1
DDR_A_MA14 CS0_n BA0 DDR_A_MA16
24.9_0402_1%
151 152
<8,24> DDR_A_MA14 WE_n/A14 RAS_n/A16 DDR_A_MA16 <8,24>
RD12
+V_DDR_REFCA_A 153 154
DDR_A_ODT2 155 VDD15 VDD16 156 DDR_A_MA15
<8> DDR_A_ODT2 DDR_A_CS#3 ODT0 CAS_n/A15 DDR_A_MA13 DDR_A_MA15 <8,24>
+0.6V_DDR_VTT 157 158
<8> DDR_A_CS#3 CS1_n A13 +V_DDR_REFCA_A
159 160
2
DDR_A_ODT3 VDD17 VDD18
0.1U_0402_10V6K
161 162 1 T46 @ PAD~D

<8> DDR_A_ODT3 ODT1 C0/CS2_n/NC
2.2U_0402_6.3V6M
163 164 +V_DDR_REFCA_A

1 1 VDD19 VREFCA
10U_0603_6.3V6M
1U_0201_10V6M
1U_0201_10V6M
@ CD29
PAD~D @ T47 1 165 166 DIMM1_SA2

C1, CS3_n,NC SA2
CD28
1 1 1 167 168
VSS53 VSS54
CD27
DDR_A_D33 169 170 DDR_A_D36

2 2 DQ37 DQ36
CD30
CD31
171 172
2 2 2 175 DQ33 DQ32 176
DDR_A_DQS#4 177 VSS57 VSS58 178
DDR_A_DQS4 179 DQS4_c DM4_n/DBI4_n 180
downsize 181 DQS4_t VSS59 182 DDR_A_D35
DDR_A_D38 183 VSS60 DQ39 184
185 DQ38 VSS61 186 DDR_A_D34
B B
DDR_A_D39 187 VSS62 DQ35 188
189 DQ34 VSS63 190 DDR_A_D40
DDR_A_D44 191 VSS64 DQ45 192
193 DQ44 VSS65 194 DDR_A_D45
DIMM Select +3.3V_RUN +3.3V_RUN +3.3V_RUN
+3.3V_RUN
DDR_A_D41 195
197
199
VSS66
DQ40
VSS68
DQ41
VSS67
DQS5_c
196
198
200
DDR_A_DQS#5
DDR_A_DQS5
2
201 DM5_n/DBI5_n DQS5_t 202

@ RD78 @ RD14 @ RD15 DDR_A_D43 203 VSS69 VSS70 204 DDR_A_D47
DQ46 DQ47
2
0_0402_5% 0_0402_5% 0_0402_5% 205 206

@ RD16 DDR_A_D46 207 VSS71 VSS72 208 DDR_A_D42
0_0603_5% 209 DQ42 DQ43 210
1

DIMM1_SA0 213 DQ52 DQ53 214
1
DIMM1_SA1 +3.3V_RUN_DIMM1 DDR_A_D52 215 VSS75 VSS76 216 DDR_A_D49

DQ49 DQ48
0.1U_0402_10V6K
DIMM1_SA2 217 218

SA0 SA1 SA2 VSS77 VSS78
2.2U_0603_10V7K
DDR_A_DQS#6 219 220

1 1
1
DDR_A_DQS6 221 DQS6_c DM6_n/DBI6_n 222 +3.3V_RUN

DIMM2 0 0 0 DQS6_t VSS79
CD32
CD33
@ RD18 @ RD79 @ RD80 223 224 DDR_A_D53

0_0402_5% 0_0402_5% 0_0402_5% DDR_A_D54 225 VSS80 DQ54 226
DIMM4 0 1 0 2 2 227 DQ55 VSS81 228 DDR_A_D55
VSS82 DQ50
1
330K_0402_5%
DDR_A_D51 229 230
* DIMM1 1 0 0
2
DQ51 VSS83 DDR_A_D56
RD17
231 232
DDR_A_D57 233 VSS84 DQ60 234
DIMM3 1 1 0 235 DQ61 VSS85 236 DDR_A_D60
DDR_A_D61 237 VSS86 DQ57 238 +1.2V_MEM
2
241 VSS88 DQS7_c 242 DDR_A_DQS7 UD1
243 DM7_n/DBI7_n DQS7_t 244 1 5 1 2
DDR_A_D62 245 VSS89 VSS90 246 DDR_A_D59 NC VCC @ CD34 0.1U_0402_25V6
247 DQ62 DQ63 248 2
DDR_A_D58 VSS91 VSS92 DDR_A_D63 <7> DDR_VTT_CTRL A 0.6V_DDR_VTT_ON
249 250 4
DQ58 DQ59 Y 0.6V_DDR_VTT_ON <88>
251 252 3
253 VSS93 VSS94 254 GND
<7,18,24,25,26,54> DDR_XDP_W AN_SMBCLK +3.3V_RUN_DIMM1 SCL SDA DIMM1_SA0 DDR_XDP_W AN_SMBDAT <7,18,24,25,26,54>
255 256 74AUP1G07GW _TSSOP5
257 VDDSPD SA0 258
+2.5V_MEM VPP1 VTT DIMM1_SA1 +0.6V_DDR_VTT
259 260
261 VPP2 SA1 262
GND1 GND2
263 264
A NPTH1 NPTH2 A
ADDR0208-P001A02
CONN@
SP07001JH0L
Title
Issued Date 2016/01/01 Deciphered Date 2017/01/01 DDR4_DIMM1
Custom 1.0
5 4 3 2 1
5 4 3 2 1
JDIMM2 STD Type H=4

+1.2V_MEM +1.2V_MEM CH-B CH-A
JDIMM2
REV STD
1 2
<8,23> DDR_A_CB[0..7] DDR_A_D1 3 VSS1 VSS2 4 DDR_A_D4 JDIMM4 -->CKE0,1 JDIMM2 -->CKE0,1
5 DQ5 DQ4 6
<8,23> DDR_A_DQS#[0..3] DDR_A_D5 7 VSS3
DQ1
VSS4
DQ0
8 DDR_A_D0 CPU D B Top Side
9 10 B A
<8,23> DDR_A_DQS[0..3] DDR_A_DQS#0 VSS5 VSS6
11 12
Vinafix.com DDR_A_DQS0 13 DQS0_c DM0_n/DBI0_n 14

<8,23> DDR_A_DQS#[4..7]
15 DQS0_t VSS7 16 DDR_A_D7 C A Bottom Side
DDR_A_D6 17 VSS8 DQ6 18
<8,23> DDR_A_DQS[4..7]
19 DQ7 VSS9 20 DDR_A_D3 JDIMM3 -->CKE2,3 JDIMM1 -->CKE2,3
D <8,23> DDR_A_D[0..63]
DDR_A_D9
23 DQ3
VSS12
VSS11
DQ12
24 DDR_A_D13 STD REV D
25 26
<8,23> DDR_A_MA[0..13] DQ13 VSS13 DDR_A_D12
27 28
+2.5V_MEM DDR_A_D10 37 VSS17 VSS18 38 DDR_A_D15
39 DQ15 DQ14 40
43 DQ10 DQ11 44
DDR_A_D16 VSS21 VSS22 DDR_A_D21 DDR_A_DRAMRST#
1U_0201_10V6M
1U_0201_10V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
45 46
DQ21 DQ20 DDR_A_DRAMRST# <23>
1 1 1 1 47 48
DQ17 DQ16
CD36
CD37
CD38
CD35
51 52
2 2 2 2 DDR_A_DQS2 55 DQS2_c DM2_n/DBI2_n 56
DDR_A_D19 59 VSS28 DQ22 60 JDIMM2_EVENT# 1 2 H_THERMTRIP#
DQ23 VSS29 DDR_A_D18 H_THERMTRIP# <7,14,23,25,26,59>
downsize 61 62 @ RD21 1K_0402_5%
DDR_A_D23 63 VSS30 DQ18 64
65 DQ19 VSS31 66 DDR_A_D29
DDR_A_D24 67 VSS32 DQ28 68
+1.2V_MEM 69 DQ29 VSS33 70 DDR_A_D28
DDR_A_D25 71 VSS34 DQ24 72
CD25 change to SGA20331E10 73 DQ25 VSS35 74 DDR_A_DQS#3
VSS37 VSS38
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
DQ30 DQ31
330U_D2_2V_Y
1 81 82
VSS39 VSS40
@ CD47
1 1 1 1 1 1 1 1 DQ26 DQ27
CD39
CD40
CD41
CD42
CD43
CD44
CD45
CD46
+ 85 86
<8,23> DDR_A_CB0 CB5/NC CB4/NC DDR_A_CB1 <8,23>
89 90
2 2 2 2 2 2 2 2 2 DDR_A_CB5 91 VSS43 VSS44 92 DDR_A_CB4
<8,23> DDR_A_CB5 CB1/NC CB0/NC DDR_A_CB4 <8,23>
93 94
<8,23> DDR_A_DQS#8 DDR_A_DQS8 DQS8_c DM8_n/DBI_n/NC
97 98
<8,23> DDR_A_DQS8 DQS8_t VSS47 DDR_A_CB7
99 100
101 102
<8,23> DDR_A_CB3 CB2/NC VSS49 DDR_A_CB6
103 104
105 106
C <8,23> DDR_A_CB2 CB3/NC VSS51 DDR_A_DRAMRST# C
107 108 1 2
DDR_A_CKE0 109 VSS52 RESET_n 110 DDR_A_CKE1 @ CD48 0.1U_0201_10V6K
<8> DDR_A_CKE0 CKE0 CKE1 DDR_A_CKE1 <8>
111 112
VDD1 VDD2
1U_0201_10V6M
1U_0201_10V6M
1U_0201_10V6M
1U_0201_10V6M
1U_0201_10V6M
1U_0201_10V6M
1U_0201_10V6M
1U_0201_10V6M DDR_A_BG1 113 114 DDR_A_ACT#

<8,23> DDR_A_BG1 DDR_A_BG0 BG1 ACT_n DDR_A_ALERT# DDR_A_ACT# <8,23>
1 1 1 1 1 1 1 1 115 116
<8,23> DDR_A_BG0 BG0 ALERT_n DDR_A_ALERT# <8,23>
117 118
VDD3 VDD4
CD49
CD50
CD51
CD52
CD53
CD54
CD55
CD56

DDR_A_MA9 121 A12 A11 122 DDR_A_MA7
2 2 2 2 2 2 2 2 123 A9 A7 124
DDR_A_MA8 125 VDD5 VDD6 126 DDR_A_MA5
DDR_A_MA6 127 A8 A5 128 DDR_A_MA4
downsize 129 A6 A4 130
DDR_A_MA3 131 VDD7 VDD8 132 DDR_A_MA2
DDR_A_MA1 133 A3 A2 134 JDIMM2_EVENT#
135 A1 EVENT_n/NF 136
DDR_A_CLK0 137 VDD9 VDD10 138 DDR_A_CLK1
Layout Note: <8> DDR_A_CLK0 DDR_A_CLK#0 139 CK0_t CK1_t/NF 140 DDR_A_CLK#1 DDR_A_CLK1 <8>
<8> DDR_A_CLK#0 CK0_c CK1_c/NF DDR_A_CLK#1 <8>
Place near JDIMM2.258 DDR_A_PARITY
141
143 VDD11 VDD12
142
144 DDR_A_MA0
<8,23> DDR_A_PARITY PARITY A0
DDR_A_BA1 145 146 DDR_A_MA10

<8,23> DDR_A_BA1 BA1 A10/AP
147 148
DDR_A_CS#0 149 VDD13 VDD14 150 DDR_A_BA0
+V_DDR_REFCA_A <8> DDR_A_CS#0 DDR_A_MA14 CS0_n BA0 DDR_A_MA16 DDR_A_BA0 <8,23>
151 152
<8,23> DDR_A_MA14 WE_n/A14 RAS_n/A16 DDR_A_MA16 <8,23>
+0.6V_DDR_VTT 153 154
DDR_A_ODT0 155 VDD15 VDD16 156 DDR_A_MA15
<8> DDR_A_ODT0 DDR_A_CS#1 ODT0 CAS_n/A15 DDR_A_MA13 DDR_A_MA15 <8,23>
157 158
<8> DDR_A_CS#1 CS1_n A13 +V_DDR_REFCA_A
0.1U_0402_10V6K
159 160
DDR_A_ODT1 VDD17 VDD18
10U_0603_6.3V6M
1U_0201_10V6M
1U_0201_10V6M
2.2U_0402_6.3V6M
1 1 161 162 1 T48 @ PAD~D

<8> DDR_A_ODT1 ODT1 C0/CS2_n/NC
@ CD61
163 164 +V_DDR_REFCA_A

1 1 1 VDD19 VREFCA
CD57
CD60
PAD~D @ T49 1 165 166 DIMM2_SA2

C1, CS3_n,NC SA2
CD58
CD59
167 168
2 2 DDR_A_D36 169 VSS53 VSS54 170 DDR_A_D33
2 2 2 171 DQ37 DQ36 172
175 DQ33 DQ32 176
downsize DDR_A_DQS#4 177 VSS57 VSS58 178
DDR_A_DQS4 179 DQS4_c DM4_n/DBI4_n 180
DDR_A_D35 183 VSS60 DQ39 184
185 DQ38 VSS61 186 DDR_A_D39
B B
DDR_A_D34 187 VSS62 DQ35 188
189 DQ34 VSS63 190 DDR_A_D44
+3.3V_RUN
DDR_A_D40
DDR_A_D45
191
193
195
VSS64
DQ44
VSS66
DQ45
VSS65
DQ41
192
194
196
DDR_A_D41
DQ40 VSS67
1
197 198 DDR_A_DQS#5

@ RD22 @ RD23 @ RD24 199 VSS68 DQS5_c 200 DDR_A_DQS5
2
0_0402_5% 0_0402_5% 0_0402_5% 201 DM5_n/DBI5_n DQS5_t 202

@ RD92 DDR_A_D47 203 VSS69 VSS70 204 DDR_A_D43
0_0603_5% 205 DQ46 DQ47 206
2

DIMM2_SA0 209 DQ42 DQ43 210
1
DIMM2_SA1 +3.3V_RUN_DIMM2 DDR_A_D48 211 VSS73 VSS74 212 DDR_A_D50

DQ52 DQ53
0.1U_0402_10V6K
DIMM2_SA2 213 214

SA0 SA1 SA2 VSS75 VSS76
2.2U_0603_10V7K
DDR_A_D49 215 216 DDR_A_D52

1 1 DQ49 DQ48
2
DIMM2 0 0 0 217 218

* VSS77 VSS78
CD62
CD63
@ RD81 @ RD82 @ RD83 DDR_A_DQS#6 219 220

0_0402_5% 0_0402_5% 0_0402_5% DDR_A_DQS6 221 DQS6_c DM6_n/DBI6_n 222
DIMM4 0 1 0 2 2 223 DQS6_t VSS79 224 DDR_A_D54
DDR_A_D53 225 VSS80 DQ54 226
DIMM1 1 0 0
1
227 DQ55 VSS81 228 DDR_A_D51

DDR_A_D55 229 VSS82 DQ50 230
DIMM3 1 1 0 231 DQ51 VSS83 232 DDR_A_D57
DDR_A_D56 233 VSS84 DQ60 234
235 DQ61 VSS85 236 DDR_A_D61
DDR_A_D60 237 VSS86 DQ57 238
247 DQ62 DQ63 248
251 DQ58 DQ59 252
253 VSS93 VSS94 254
255 256
257 VDDSPD SA0 258
259 260
261 VPP2 SA1 262
GND1 GND2
263 264
A NPTH1 NPTH2 A
BELLW _80888-2021
CONN@
SP07001GA0L
Title
DDR4_DIMM2
Custom 1.0
5 4 3 2 1
5 4 3 2 1
JDIMM3 STD Type H=5.2

+1.2V_MEM +1.2V_MEM CH-B CH-A
JDIMM3
REV STD
1 2
DDR_B_D4 3 VSS1 VSS2 4 DDR_B_D5 JDIMM4 -->CKE0,1 JDIMM2 -->CKE0,1
5 DQ5 DQ4 6
DDR_B_D1 7 VSS3
DQ1
VSS4
DQ0
8 DDR_B_D0 CPU D B Top Side
9 10 B A
Vinafix.com DDR_B_DQS#0 11 VSS5 VSS6 12

<8,26> DDR_B_CB[0..7] DDR_B_DQS0 DQS0_c DM0_n/DBI0_n
13 14
15 DQS0_t VSS7 16 DDR_B_D2 C A Bottom Side
<8,26> DDR_B_DQS#[0..7] DDR_B_D6 VSS8 DQ6
17 18
19 DQ7 VSS9 20 DDR_B_D7 JDIMM3 -->CKE2,3 JDIMM1 -->CKE2,3
D <8,26> DDR_B_DQS[0..7] DDR_B_D3 VSS10 DQ2 D
21 22
<8,26> DDR_B_D[0..63] DDR_B_D10
23 DQ3
VSS12
VSS11
DQ12
24 DDR_B_D8 STD REV
25 26
27 DQ13 VSS13 28 DDR_B_D14
<8,26> DDR_B_MA[0..13] DDR_B_D9 VSS14 DQ8
29 30
31 DQ9 VSS15 32 DDR_B_DQS#1
33 VSS16 DQS1_c 34 DDR_B_DQS1
DDR_B_D12 37 VSS17 VSS18 38 DDR_B_D11
39 DQ15 DQ14 40
+2.5V_MEM DDR_B_D13 41 VSS19 VSS20 42 DDR_B_D15
43 DQ10 DQ11 44
47 DQ21 DQ20 48
VSS23 VSS24
1U_0201_10V6M
1U_0201_10V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
DDR_B_D22 49 50 DDR_B_D16
51 DQ17 DQ16 52
1 1 1 1 VSS25 VSS26
DDR_B_DQS#2 53 54
DQS2_c DM2_n/DBI2_n
CD64
CD65
CD66
CD67
DDR_B_DQS2 55 56
57 DQS2_t VSS27 58 DDR_B_D23
2 2 2 2 DDR_B_D19 59 VSS28 DQ22 60
61 DQ23 VSS29 62 DDR_B_D21
DDR_B_D20 63 VSS30 DQ18 64 DDR_B_DRAMRST#
DQ19 VSS31 DDR_B_D28 DDR_B_DRAMRST# <23,26>
downsize 65 66
DDR_B_D25 67 VSS32 DQ28 68
69 DQ29 VSS33 70 DDR_B_D27
DDR_B_D30 71 VSS34 DQ24 72
+1.2V_MEM 73 DQ25 VSS35 74 DDR_B_DQS#3
75 VSS36 DQS3_c 76 DDR_B_DQS3 JDIMM3_EVENT# 1 2 H_THERMTRIP#
DM3_n/DBI3_n DQS3_t H_THERMTRIP# <7,14,23,24,26,59>
77 78 @ RD29 1K_0402_5%
81 DQ30 DQ31 82
DDR_B_D31 VSS39 VSS40 DDR_B_D24
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
83 84
DQ26 DQ27
330U_D2_2V_Y
1 85 86
DDR_B_CB4 87 VSS41 VSS42 88 DDR_B_CB1
1 1 1 1 1 1 1 1 <8,26> DDR_B_CB4 CB5/NC CB4/NC DDR_B_CB1 <8,26>
CD68
CD69
CD70
CD71
CD72
CD73
CD74
CD75
CD76
+ 89 90
DDR_B_CB2 91 VSS43 VSS44 92 DDR_B_CB3 +1.2V_MEM
<8,26> DDR_B_CB2 CB1/NC CB0/NC DDR_B_CB3 <8,26>
93 94
2 2 2 2 2 2 2 2 2 DDR_B_DQS#8 95 VSS45 VSS46 96
<8,26> DDR_B_DQS#8 DQS8_c DM8_n/DBI_n/NC
0.1U_0402_10V6K
DDR_B_DQS8 97 98
<8,26> DDR_B_DQS8 DQS8_t VSS47
1
1K_0402_5%
@ CD77
99 100 DDR_B_CB6
VSS48 CB6/NC DDR_B_CB6 <8,26> 1
RD30
DDR_B_CB7 101 102
<8,26> DDR_B_CB7 CB2/NC VSS49 DDR_B_CB0 +DDR_VREF_B_DQ
103 104
C DDR_B_CB5 VSS50 CB7/NC DDR_B_CB0 <8,26> C
105 106
<8,26> DDR_B_CB5 CB3/NC VSS51 DDR_B_DRAMRST# 2
107 108 1 2
2
DDR_B_CKE2 109 VSS52 RESET_n 110 DDR_B_CKE3 @ CD78 0.1U_0201_10V6K
<8> DDR_B_CKE2 CKE0 CKE1 DDR_B_CKE3 <8>
111 112
DDR_B_BG1 113 VDD1 VDD2 114 DDR_B_ACT# 1 2 +DIMM_DQ_R_VREF_B
<8,26> DDR_B_BG1 DDR_B_BG0 BG1 ACT_n DDR_B_ALERT# DDR_B_ACT# <8,26>
115 116 RD31 2_0402_1%
<8,26> DDR_B_BG0 BG0 ALERT_n DDR_B_ALERT# <8,26>
1U_0201_10V6M
1U_0201_10V6M
1U_0201_10V6M
1U_0201_10V6M
1U_0201_10V6M
1U_0201_10V6M
1U_0201_10V6M
1U_0201_10V6M
0.022U_0402_16V7K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
117 118
VDD3 VDD4
1
@ CD88
@ CD89
1K_0402_5%
@ CD90
DDR_B_MA12 119 120 DDR_B_MA11
1 1 1 1 1 1 1 1 A12 A11 1 1 1 1
RD32
A9 A7
CD79
CD80
CD81
CD82
CD83
CD84
CD85
CD86
CD87
123 124
DDR_B_MA8 125 VDD5 VDD6 126 DDR_B_MA5
2 2 2 2 2 2 2 2 DDR_B_MA6 127 A8 A5 128 DDR_B_MA4 2 2 2 2
2
129 A6 A4 130
downsize DDR_B_MA1 133 A3 A2 134 JDIMM3_EVENT#
VDD9 VDD10
1
24.9_0402_1%
DDR_B_CLK2 137 138 DDR_B_CLK3
<8> DDR_B_CLK2 CK0_t CK1_t/NF DDR_B_CLK3 <8>
RD33
DDR_B_CLK#2 139 140 DDR_B_CLK#3
<8> DDR_B_CLK#2 CK0_c CK1_c/NF DDR_B_CLK#3 <8>
141 142
Layout Note: <8,26> DDR_B_PARITY
DDR_B_PARITY 143 VDD11 VDD12 144 DDR_B_MA0
PARITY A0
Place near JDIMM3.258
2
DDR_B_BA1 145 146 DDR_B_MA10
<8,26> DDR_B_BA1 BA1 A10/AP
147 148
DDR_B_CS#2 149 VDD13 VDD14 150 DDR_B_BA0
<8> DDR_B_CS#2 DDR_B_MA14 CS0_n BA0 DDR_B_MA16 DDR_B_BA0 <8,26>
151 152
<8,26> DDR_B_MA14 WE_n/A14 RAS_n/A16 DDR_B_MA16 <8,26>
153 154
+V_DDR_REFCA_B DDR_B_ODT2 155 VDD15 VDD16 156 DDR_B_MA15 +1.2V_MEM
<8> DDR_B_ODT2 DDR_B_CS#3 ODT0 CAS_n/A15 DDR_B_MA13 DDR_B_MA15 <8,26>
+0.6V_DDR_VTT 157 158
<8> DDR_B_CS#3 CS1_n A13 +V_DDR_REFCA_B
159 160
VDD17 VDD18
0.1U_0402_10V6K
DDR_B_ODT3 161 162 1 T50 @ PAD~D
<8> DDR_B_ODT3 ODT1 C0/CS2_n/NC
1
0.1U_0402_10V6K
1K_0402_5%
163 164 +V_DDR_REFCA_B @ @
VDD19 VREFCA 1
10U_0603_6.3V6M
1U_0201_10V6M
1U_0201_10V6M
2.2U_0402_6.3V6M
RD34
CD96
PAD~D @ T51 1 165 166 DIMM3_SA2
1 1 C1, CS3_n,NC SA2
@ CD95
1 1 1 167 168
CD91
CD94
169 170
DQ37 DQ36 2
CD92
CD93
171 172
2
2 2 DDR_B_D34 173 VSS55 VSS56 174 DDR_B_D39
2 2 2 175 DQ33 DQ32 176 @ RD84
DDR_B_DQS#4 177 VSS57 VSS58 178 +DIMM_DQ_R_VREF_B 2 1 +V_DDR_REFCA_B 1 2
DDR_B_DQS4 179 DQS4_c DM4_n/DBI4_n 180 @ RD36 0_0402_5%
downsize 181 DQS4_t VSS59 182 DDR_B_D36 0_0402_5%
VSS60 DQ39
1
0.1U_0402_10V6K
1K_0402_5%
B
DDR_B_D33 183 184 @ B
DQ38 VSS61
@ CD97
RD37
185 186 DDR_B_D37
VSS62 DQ35 1
DDR_B_D32 187 188
189 DQ34 VSS63 190 DDR_B_D44
DDR_B_D40 191 VSS64 DQ45 192
2
193 DQ44 VSS65 194 DDR_B_D45 2
+3.3V_RUN
DDR_B_D41 195
197
199
VSS66
DQ40
VSS68
DQ41
VSS67
DQS5_c
196
198
200
DDR_B_DQS#5
DDR_B_DQS5
DM5_n/DBI5_n DQS5_t
2
201 202
@ RD85 @ RD86 @ RD40 DDR_B_D42 203 VSS69 VSS70 204 DDR_B_D47
DQ46 DQ47
2
0_0402_5% 0_0402_5% 0_0402_5% 205 206

@ RD93 DDR_B_D46 207 VSS71 VSS72 208 DDR_B_D43
0_0603_5% 209 DQ42 DQ43 210
1

DIMM3_SA0 213 DQ52 DQ53 214
1
DIMM3_SA1 +3.3V_RUN_DIMM3 DDR_B_D52 215 VSS75 VSS76 216 DDR_B_D54

DQ49 DQ48
0.1U_0402_10V6K
DIMM3_SA2 217 218

SA0 SA1 SA2 DDR_B_DQS#6 VSS77 VSS78
2.2U_0603_10V7K
1 1 219 220
DQS6_c DM6_n/DBI6_n
1
DDR_B_DQS6 221 222

DIMM2 0 0 0 DQS6_t VSS79
CD98
CD99
@ RD42 @ RD43 @ RD87 223 224 DDR_B_D53

0_0402_5% 0_0402_5% 0_0402_5% DDR_B_D50 225 VSS80 DQ54 226
DIMM4 0 1 0 2 2 227 DQ55 VSS81 228 DDR_B_D49
DDR_B_D55 229 VSS82 DQ50 230
DIMM1 1 0 0
2
231 DQ51 VSS83 232 DDR_B_D59

DDR_B_D57 233 VSS84 DQ60 234
* DIMM3 1 1 0 235 DQ61 VSS85 236 DDR_B_D62
DDR_B_D61 237 VSS86 DQ57 238
247 DQ62 DQ63 248
251 DQ58 DQ59 252
253 VSS93 VSS94 254
255 256
257 VDDSPD SA0 258
259 260
261 VPP2 SA1 262
GND1 GND2
A 263 264 A
NPTH1 NPTH2
BELLW _80888-2021
CONN@
SP07001GT0L
Title
DDR4_DIMM3
Custom 1.0
5 4 3 2 1
5 4 3 2 1
JDIMM4 REV Type H=4

+1.2V_MEM +1.2V_MEM
JDIMM4
1
VSS1 VSS2
2
CH-B CH-A
DDR_B_D5 3 4 DDR_B_D4
DDR_B_D0
5 DQ5
VSS3
DQ4
VSS4
6
DDR_B_D1
REV STD
7 8
9 DQ1 DQ0 10 JDIMM4 -->CKE0,1 JDIMM2 -->CKE0,1
DDR_B_DQS#0 11 VSS5 VSS6 12
<8,25> DDR_B_CB[0..7] DDR_B_DQS0 13 DQS0_c DM0_n/DBI0_n 14 CPU D B Top Side
Vinafix.com 15 DQS0_t VSS7 16 DDR_B_D6
<8,25> DDR_B_DQS#[0..7] VSS8 DQ6 B A
DDR_B_D2 17 18
19 DQ7 VSS9 20 DDR_B_D3
<8,25> DDR_B_DQS[0..7] DDR_B_D7 21 VSS10 DQ2 22
C A Bottom Side
D <8,25> DDR_B_D[0..63] DDR_B_D8 25 VSS12 DQ12 26
JDIMM3 -->CKE2,3 JDIMM1 -->CKE2,3 D
<8,25> DDR_B_MA[0..13] DDR_B_D14 29 VSS14
DQ9
DQ8
VSS15
30
DDR_B_DQS#1
STD REV
31 32
39 DQ15 DQ14 40
43 DQ10 DQ11 44
+2.5V_MEM 47 DQ21 DQ20 48
51 DQ17 DQ16 52
DDR_B_DQS#2 53 VSS25 VSS26 54
DQS2_c DM2_n/DBI2_n
1U_0201_10V6M
1U_0201_10V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
DDR_B_DQS2 55 56
57 DQS2_t VSS27 58 DDR_B_D19
1 1 1 1 VSS28 DQ22
DDR_B_D23 59 60
DQ23 VSS29
CD100
CD101
CD102
CD103
61 62 DDR_B_D20
DDR_B_D21 63 VSS30 DQ18 64 DDR_B_DRAMRST#
2 2 2 2 DQ19 VSS31 DDR_B_D25 DDR_B_DRAMRST# <23,25>
65 66
DDR_B_D28 67 VSS32 DQ28 68
69 DQ29 VSS33 70 DDR_B_D30
downsize DDR_B_D27 71 VSS34 DQ24 72
75 VSS36 DQS3_c 76 DDR_B_DQS3 JDIMM4_EVENT# 1 2 H_THERMTRIP#
DM3_n/DBI3_n DQS3_t H_THERMTRIP# <7,14,23,24,25,59>
77 78 @ RD45 1K_0402_5%
+1.2V_MEM DDR_B_D26 79 VSS37 VSS38 80 DDR_B_D29
81 DQ30 DQ31 82
85 DQ26 DQ27 86
DDR_B_CB4 87 VSS41 VSS42 88 DDR_B_CB1
<8,25> DDR_B_CB4 CB5/NC CB4/NC DDR_B_CB1 <8,25>
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
89 90
VSS43 VSS44
330U_D2_2V_Y
DDR_B_CB2 91 92 DDR_B_CB3
1 <8,25> DDR_B_CB2 CB1/NC CB0/NC DDR_B_CB3 <8,25>
@ CD112
1 1 1 1 1 1 1 1 93 94
VSS45 VSS46
CD104
CD105
CD106
CD107
CD108
CD109
CD110
CD111
+ DDR_B_DQS#8 95 96
<8,25> DDR_B_DQS#8 DDR_B_DQS8 DQS8_c DM8_n/DBI_n/NC
97 98
<8,25> DDR_B_DQS8 DQS8_t VSS47 DDR_B_CB6
99 100
2 2 2 2 2 2 2 2 2 DDR_B_CB7 VSS48 CB6/NC DDR_B_CB6 <8,25>
101 102
<8,25> DDR_B_CB7 CB2/NC VSS49 DDR_B_CB0
103 104
DDR_B_CB5 VSS50 CB7/NC DDR_B_CB0 <8,25>
105 106
<8,25> DDR_B_CB5 CB3/NC VSS51 DDR_B_DRAMRST#
107 108 1 2
C DDR_B_CKE0 VSS52 RESET_n DDR_B_CKE1 C
109 110 @ CD113 0.1U_0201_10V6K
<8> DDR_B_CKE0 CKE0 CKE1 DDR_B_CKE1 <8>
111 112
DDR_B_BG1 113 VDD1 VDD2 114 DDR_B_ACT#
<8,25> DDR_B_BG1 DDR_B_BG0 BG1 ACT_n DDR_B_ALERT# DDR_B_ACT# <8,25>
115 116
<8,25> DDR_B_BG0 BG0 ALERT_n DDR_B_ALERT# <8,25>
117 118
DDR_B_MA9 121 A12 A11 122 DDR_B_MA7
A9 A7
1U_0201_10V6M
1U_0201_10V6M
1U_0201_10V6M
1U_0201_10V6M
1U_0201_10V6M
1U_0201_10V6M
1U_0201_10V6M
1U_0201_10V6M
123 124
1 1 1 1 1 1 1 1 A8 A5
A6 A4
CD114
CD115
CD116
CD117
CD118
CD119
CD120
CD121
129 130
2 2 2 2 2 2 2 2 DDR_B_MA1 133 A3 A2 134 JDIMM4_EVENT#
DDR_B_CLK0 137 VDD9 VDD10 138 DDR_B_CLK1
<8> DDR_B_CLK0 DDR_B_CLK#0 CK0_t CK1_t/NF DDR_B_CLK#1 DDR_B_CLK1 <8>
downsize 139 140
<8> DDR_B_CLK#0 CK0_c CK1_c/NF DDR_B_CLK#1 <8>
141 142
DDR_B_PARITY 143 VDD11 VDD12 144 DDR_B_MA0
<8,25> DDR_B_PARITY PARITY A0
Layout Note: <8,25> DDR_B_BA1

DDR_B_BA1 145 146 DDR_B_MA10
BA1 A10/AP
Place near JDIMM4.258 DDR_B_CS#0
147
149 VDD13 VDD14
148
150 DDR_B_BA0
<8> DDR_B_CS#0 DDR_B_MA14 CS0_n BA0 DDR_B_MA16 DDR_B_BA0 <8,25>
151 152
<8,25> DDR_B_MA14 WE_n/A14 RAS_n/A16 DDR_B_MA16 <8,25>
153 154
DDR_B_ODT0 155 VDD15 VDD16 156 DDR_B_MA15
<8> DDR_B_ODT0 DDR_B_CS#1 ODT0 CAS_n/A15 DDR_B_MA13 DDR_B_MA15 <8,25>
157 158
<8> DDR_B_CS#1 CS1_n A13 +V_DDR_REFCA_B
159 160
+V_DDR_REFCA_B DDR_B_ODT1 161 VDD17 VDD18 162 1 T52 @ PAD~D
<8> DDR_B_ODT1 ODT1 C0/CS2_n/NC +V_DDR_REFCA_B
+0.6V_DDR_VTT 163 164
PAD~D @ T53 1 165 VDD19 VREFCA 166 DIMM4_SA2
167 C1, CS3_n,NC SA2 168
VSS53 VSS54
0.1U_0402_10V6K
DDR_B_D38 169 170 DDR_B_D35

DQ37 DQ36
10U_0603_6.3V6M
1U_0201_10V6M
1U_0201_10V6M
2.2U_0402_6.3V6M
1 1 171 172
@ CD126
1 1 1 173 174
DQ33 DQ32
CD122
CD125
175 176
VSS57 VSS58
CD123
CD124
DDR_B_DQS#4 177 178

2 2 DDR_B_DQS4 179 DQS4_c DM4_n/DBI4_n 180
2 2 2 181 DQS4_t VSS59 182 DDR_B_D33
DDR_B_D36 183 VSS60 DQ39 184
185 DQ38 VSS61 186 DDR_B_D32
downsize DDR_B_D37 187 VSS62 DQ35 188
B B
189 DQ34 VSS63 190 DDR_B_D40
DDR_B_D44 191 VSS64 DQ45 192
193 DQ44 VSS65 194 DDR_B_D41
DDR_B_D45 195 VSS66 DQ41 196
+3.3V_RUN
DDR_B_D47
201
203
205
DM5_n/DBI5_n
VSS69
DQ46
DQS5_t
VSS70
DQ47
202
204
206
DDR_B_D42
VSS71 VSS72
1
DDR_B_D43 207 208 DDR_B_D46

@ RD46 @ RD88 @ RD48 209 DQ42 DQ43 210
VSS73 VSS74
2
0_0402_5% 0_0402_5% 0_0402_5% DDR_B_D51 211 212 DDR_B_D48

@ RD94 213 DQ52 DQ53 214
0_0603_5% DDR_B_D54 215 VSS75 VSS76 216 DDR_B_D52
2
217 DQ49 DQ48 218

DIMM4_SA0 DDR_B_DQS#6 219 VSS77 VSS78 220
1
DIMM4_SA1 +3.3V_RUN_DIMM4 DDR_B_DQS6 221 DQS6_c DM6_n/DBI6_n 222

DIMM4_SA2 DQS6_t VSS79 DDR_B_D50
0.1U_0402_10V6K
223 224
SA0 SA1 SA2 VSS80 DQ54
2.2U_0603_10V7K
DDR_B_D53 225 226

1 1 DQ55 VSS81
2
227 228 DDR_B_D55

DIMM2 0 0 0 VSS82 DQ50
CD127
CD128
@ RD89 @ RD51 @ RD90 DDR_B_D49 229 230

0_0402_5% 0_0402_5% 0_0402_5% 231 DQ51 VSS83 232 DDR_B_D57
* DIMM4 0 1 0 2 2 DDR_B_D59 233 VSS84 DQ60 234
235 DQ61 VSS85 236 DDR_B_D61
DIMM1 1 0 0
1
DDR_B_D62 237 VSS86 DQ57 238

DIMM3 1 1 0 241 VSS88 DQS7_c 242 DDR_B_DQS7
247 DQ62 DQ63 248
251 DQ58 DQ59 252
253 VSS93 VSS94 254
255 256
257 VDDSPD SA0 258
259 260
261 VPP2 SA1 262
GND1 GND2
263 264
NPTH1 NPTH2
A ADDR0206-P001A02 A
CONN@
SP07001CY0L
Title
DDR4_DIMM4
Custom 1.0
5 4 3 2 1
5 4 3 2 1
40mil(1A)
+5V_DGFF +3.3V_DGFF +3.3V_DGFF +3.3V_RUN
+DGFF_PW R_SRC +3.3V_DGFF
DGPU_PEX_RST#
CONN@
JDG1 +3.3V_DGFF
DGPU_PWROK
0.1U_0201_16V6K
10U_0402_6.3V6M
10U_0402_6.3V6M
0.1U_0201_10V6K
1
1 +3.3V_DGFF
82P_0402_50V8J
RF@ CV957
82P_0402_50V8J
RF@ CV956
10K_0402_5%
1 1 1 1 1 1 2
2
CV806
100K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
3
3
1
CV805
CV902
CV903
4
4
RV803
RV904
@
5
Vinafix.com
5
2
2 2 2 2 2 2
RV804
RV805
6
G
GND1 7 Cancel double pull high
GND2
2
G
8 1 2 DGPU_PW ROK
G
2
2
GND3 9 @ RV806 10K_0402_5%
GND4 1 2 DGFF_CLK_REQ# DGFF_ALERT# 3 1 GPU_SMBDAT_R 1 6 CLKREQ_PEG#0 1 3 DGFF_CLK_REQ#
S
D
DGPU_ALERT# <59> GPU_SMDAT <58> <16> CLKREQ_PEG#0 D
D
BELLW _80252-0521 @ RV807 10K_0402_5%
S
100mil(2.5A, 5VIA) QV30A
Update symbol Ver. 0725
5
QV41 2N7002KDW _SOT363-6 QV42
G
L2N7002W T1G_SC-70-3 L2N7002W T1G_SC-70-3
change SB00000UO00 to SB000009Q80/ change SB00000UO00 to SB000009Q80/
SB00000ST00 as main source, SB00000ST00 as main source,
SB00000UO00 as 3rd source GPU_SMBCLK_R 4 3 SB00000UO00 as 3rd source
S
GPU_SMCLK <58>
D
2 DP channels from GPU QV30B
2N7002KDW _SOT363-6
( A & B & EDP)

PCIe x8 Lanes 0-7 JDGFF2
PCIe x8 Lanes 8-15
JDGFF1 JDGFF3
PEG_CRX_C_GTX_P7 A1 H1 PEG_CTX_C_GRX_P3
GPU_DP1_P1 A1 H1 GPU_DP2_P1 PEG_CRX_C_GTX_N7 A2 A1 P P H1 H2 PEG_CTX_C_GRX_N3 PEG_CTX_C_GRX_P13 A1 H1 PEG_CRX_C_GTX_P10
<31> GPU_DP1_P1 A1 P P H1 GPU_DP2_P1 <31> A2 N N H2 A1 P P H1
GPU_DP1_N1 A2 H2 GPU_DP2_N1 A3 H3 PEG_CTX_C_GRX_N13 A2 H2 PEG_CRX_C_GTX_N10
<31> GPU_DP1_N1 A2 N N H2 GPU_DP2_N1 <31> A3 G G H3 A2 N N H2
A3 H3 PEG_CRX_C_GTX_P6 A4 H4 PEG_CTX_C_GRX_P1 A3 H3
GPU_DP2_AUXP A3 G G H3 GPU_DP2_P2 PEG_CRX_C_GTX_N6 A4 P P H4 PEG_CTX_C_GRX_N1 PEG_CTX_C_GRX_P15 A4 A3 G G H3 PEG_CRX_C_GTX_P9
<31> GPU_DP2_AUXP A4 H4 GPU_DP2_P2 <31> A5 H5 H4
GPU_DP2_AUXN A5 A4 P P H4 H5 GPU_DP2_N2 A6 A5 N N H5 H6 PEG_CTX_C_GRX_N15 A5 A4 P P H4 H5 PEG_CRX_C_GTX_N9
<31> GPU_DP2_AUXN A5 N N H5 GPU_DP2_N2 <31> A6 G G H6 A5 N N H5
A6 H6 PEG_CRX_C_GTX_P5 A7 H7 PEG_CTX_C_GRX_P0 A6 H6
GPU_DP2_P0 A7 A6 G G H6 H7 PEG_CRX_C_GTX_N5 A8 A7 P P H7 H8 PEG_CTX_C_GRX_N0 PEG_CTX_C_GRX_P14 A7 A6 G G H6 H7 PEG_CRX_C_GTX_P8
<31> GPU_DP2_P0 A7 P P H7 CLK_PEG_P0 <16> A8 N N H8 A7 P P H7
GPU_DP2_N0 A8 H8 A9 H9 PEG_CTX_C_GRX_N14 A8 H8 PEG_CRX_C_GTX_N8
<31> GPU_DP2_N0 A8 N N H8 CLK_PEG_N0 <16> A9 G G H9 A8 N N H8
A9 H9 A10 H10 DGFF_PW R_LEVEL A9 H9
DGFF_ALERT# A10 A9 G G H9 H10 GPU_DP2_HPD_GATE A10 H10 A10 A9 G G H9 H10
A10 H10 B1 G1 A10 H10
B1 G1 PEG_CRX_C_GTX_P4 B2 B1 G G G1
G2 PEG_CTX_C_GRX_P5 B1 G1
GPU_EDP_P1 B2 B1 G G G1
G2 GPU_DP1_P2 PEG_CRX_C_GTX_N4 B3 B2 P P G2
G3 PEG_CTX_C_GRX_N5 PEG_CTX_C_GRX_P10 B2 B1 G G G1
G2 PEG_CRX_C_GTX_P12
<29> GPU_EDP_P1 B2 P P G2 GPU_DP1_P2 <31> B3 N N G3 B2 P P G2
GPU_EDP_N1 B3 G3 GPU_DP1_N2 B4 G4 PEG_CTX_C_GRX_N10 B3 G3 PEG_CRX_C_GTX_N12
<29> GPU_EDP_N1 B3 N N G3 GPU_DP1_N2 <31> B4 G G G4 B3 N N G3
B4 G4 PEG_CRX_C_GTX_P3 B5 G5 PEG_CTX_C_GRX_P2 B4 G4
GPU_DP2_P3 B4 G G G4 GPU_DP1_P3 PEG_CRX_C_GTX_N3 B5 P P G5 PEG_CTX_C_GRX_N2 PEG_CTX_C_GRX_P11 B5 B4 G G G4 PEG_CRX_C_GTX_P11
B5 G5 GPU_DP1_P3 <31> B6 G6 G5
<31> GPU_DP2_P3 GPU_DP2_N3 B5 P P G5 GPU_DP1_N3 B6 N N G6 PEG_CTX_C_GRX_N11 B6 B5 P P G5 PEG_CRX_C_GTX_N11
B6 G6 GPU_DP1_N3 <31> B7 G7 G6
<31> GPU_DP2_N3 B6 N N G6 PEG_CRX_C_GTX_P1 B8 B7 G G G7 PEG_CTX_C_GRX_P4 B6 N N G6
B7 G G7
G7 P G8
G8 B7 G G7
G7
GPU_EDP_AUXP B8 B7 G G8 GPU_EDP_P0 PEG_CRX_C_GTX_N1 B9 B8 P G9 PEG_CTX_C_GRX_N4 PEG_CTX_C_GRX_P12 B8 B7 G G8 PEG_CRX_C_GTX_P13
<29> GPU_EDP_AUXP B8 P P G8 GPU_EDP_P0 <29> B9 N N G9 B8 P P G8
GPU_EDP_AUXN B9 G9 GPU_EDP_N0 B10 G10 PEG_CTX_C_GRX_N12 B9 G9 PEG_CRX_C_GTX_N13
C <29> GPU_EDP_AUXN B9 N N G9 GPU_EDP_N0 <29> B10 G G G10 B9 N N G9 C
B10 G10 B10 G10
B10 G G G10 GPU_SMBCLK_R B10 G G G10
C1 F1 VGA_IDENTIFY <28,58>
DGFF_OVERT# C1 F1 GPU_SMBDAT_R C2 C1 P P F1 F2 C1 F1
C1 P P F1 C2 N N F2 DGPU_PW R_EN_R <59> C1 P P F1
DGFF_IFP_HPD C2 F2 DGPU_PEX_RST# C3 F3 C2 F2
C3 C2 N N F2 F3 PEG_CRX_C_GTX_P2 C4 C3 G G F3 F4 PEG_CTX_C_GRX_P6 C3 C2 N N F2 F3
GPU_EDP_P3 C3 G G F3 GPU_DP1_AUXP PEG_CRX_C_GTX_N2 C4 P P F4 PEG_CTX_C_GRX_N6 PEG_CTX_C_GRX_P9 C3 G G F3 PEG_CRX_C_GTX_P14
<29> GPU_EDP_P3
C4 F4 GPU_DP1_AUXP <31> C5 F5 C4 F4
GPU_EDP_N3 C5 C4 P P F4 F5 GPU_DP1_AUXN C6 C5 N N F5 F6 PEG_CTX_C_GRX_N9 C5 C4 P P F4 F5 PEG_CRX_C_GTX_N14
<29> GPU_EDP_N3 C5 N N F5 GPU_DP1_AUXN <31> C6 G G F6 C5 N N F5
C6 F6 PEG_CRX_C_GTX_P0 C7 F7 PEG_CTX_C_GRX_P7 C6 F6
GPU_EDP_P2 C7 C6 G G F6 F7 GPU_DP1_P0 PEG_CRX_C_GTX_N0 C8 C7 P P F7 F8 PEG_CTX_C_GRX_N7 PEG_CTX_C_GRX_P8 C7 C6 G G F6 F7 PEG_CRX_C_GTX_P15
<29> GPU_EDP_P2 C7 P P F7 GPU_DP1_P0 <31> C8 N N F8 C7 P P F7
GPU_EDP_N2 C8 F8 GPU_DP1_N0 DGFF_CLK_REQ# C9 F9 MACO_EN PEG_CTX_C_GRX_N8 C8 F8 PEG_CRX_C_GTX_N15
<29> GPU_EDP_N2 C8 N N F8 GPU_DP1_N0 <31> C9 F9 MACO_EN <18> C8 N N F8
GPU_DP1_HPD_GATE C9 F9 C10 F10 GPU_GC6_FB_EN_R 1 2 C9 F9
C9 F9 DGPU_PW ROK <18,58> C10 F10 GPU_GC6_FB_EN <14> C9 F9
C10 F10 @ RV485 0_0402_5% FOR NV GC6_FB_EN C10 F10
C10 F10 D1 E1 C10 F10
GPU_EDP_HPD <38> DGFF_ENVDD D1 E1 DGFF_BIA_PW M <38>
D1 E1 GPU_EDP_HPD <29> D2 E2 RB751VM-40TE-17_SOD323-2
2 1 D1 E1
<59> DGFF_VGA_DIS# D1 E1 <38> DGFF_PANEL_BKEN D2 E2 GPU_EVENT# <14> D1 E1
D2 E2 PCIE_W AKE# <42,52,59,67,68> D9 E9 DV44 D2 E2
<38> DGPU_TYPE# D2 E2 D9 E9 D2 E2
D9 E9 +5V_DGFF
D10 E10 +3.3V_DGFF
D9 E9
D10 D9 E9 E10 D10 E10 D10 D9 E9 E10
HDR monitor for AMD/NV/UMA +5V_DGFF D10 E10 +3.3V_DGFF D10 E10
1 3
edp output detect 1/29 1 3 2 NPTH1 NPTH3 4 1 3
2 NPTH1 NPTH3 4 NPTH2 NPTH4 2 NPTH1 NPTH3 4
NPTH2 NPTH4 UNIMI_FBGCAX011 NPTH2 NPTH4
UNIMI_FBGCAX011 UNIMI_FBGCAX011
X-Beam I/per pin=0.5A CONN@
CONN@ CONN@
I/per connector=0.75A
TBT/DP MUX1 PortA DV43

DGFF_IFP_HPD 2 1
TBT/DP MUX2 PortB <6> PEG_CRX_GTX_P[0..15]

PEG_CRX_GTX_P[0..15] RB751VM-40TE-17_SOD323-2
PEG_CRX_GTX_N[0..15] DV32
<6> PEG_CRX_GTX_N[0..15] GPU_DP1_HPD 2 1
eDP MUX PortC <6> PEG_CTX_C_GRX_P[0..15]
PEG_CTX_C_GRX_P[0..15] RB751VM-40TE-17_SOD323-2
DGFF_DP_HDMI_HPD <58>
1
PEG_CTX_C_GRX_N[0..15]
100K_0402_5%
DV33
<6> PEG_CTX_C_GRX_N[0..15] GPU_DP2_HPD 2 1
RV905
B RB751VM-40TE-17_SOD323-2 B
2
PEG_CRX_GTX_P0 CV427 2 1 0.22U_0201_6.3V6K PEG_CRX_C_GTX_P0 +3.3V_ALW _R
PEG_CRX_GTX_N0 CV428 2 1 0.22U_0201_6.3V6K PEG_CRX_C_GTX_N0
+3.3V_DGFF
PEG_CRX_GTX_P1 CV429 2 1 0.22U_0201_6.3V6K PEG_CRX_C_GTX_P1 @ CV810 +3.3V_DGFF
PEG_CRX_GTX_N1 CV430 2 1 0.22U_0201_6.3V6K PEG_CRX_C_GTX_N1 1 2 @ CV809
1 2
PEG_CRX_GTX_P2 CV431 2 1 0.22U_0201_6.3V6K PEG_CRX_C_GTX_P2 0.1U_0201_10V6K
PEG_CRX_GTX_N2 CV432 2 1 0.22U_0201_6.3V6K PEG_CRX_C_GTX_N2 0.1U_0201_10V6K
5
5
PEG_CRX_GTX_P3 CV433 2 1 0.22U_0201_6.3V6K PEG_CRX_C_GTX_P3 1 DGPU_PEX_RST#_D 1 DGPU_PEX_RST#_D
P
PEG_CRX_GTX_N3 CV434 2 1 0.22U_0201_6.3V6K PEG_CRX_C_GTX_N3 1 GPU_DP2_HPD_GATE 4 IN1 GPU_DP1_HPD_GATE 4 IN1
P
DGPU_PEX_RST# IN1 DGPU_HOLD_RST# <19> O O

4 2 2
O IN2 GPU_DP2_HPD <31> IN2 GPU_DP1_HPD <31>
G
PEG_CRX_GTX_P4 CV435 2 1 0.22U_0201_6.3V6K PEG_CRX_C_GTX_P4 2
IN2 PLTRST_GPU# <17>
G
100K_0402_5%
PEG_CRX_GTX_N4 CV436 2 1 0.22U_0201_6.3V6K PEG_CRX_C_GTX_N4 UV61 UV62
3
1
1
100K_0402_5%
UV63 SN74AHC1G08DCKR_SC70-5 SN74AHC1G08DCKR_SC70-5

3
RV813
PEG_CRX_GTX_P5 CV437 2 1 0.22U_0201_6.3V6K PEG_CRX_C_GTX_P5 SN74AHC1G08DCKR_SC70-5

RV812
PEG_CRX_GTX_P6 CV439 2 1 0.22U_0201_6.3V6K PEG_CRX_C_GTX_P6

2

PEG_CRX_GTX_N7 CV442 2 1 0.22U_0201_6.3V6K PEG_CRX_C_GTX_N7 +3.3V_DGFF +3.3V_DGFF +3.3V_ALW _R
DGPU_PEX_RST#
1
10K_0402_5%
+3.3V_ALW _R +3.3V_ALW_R +1.0V_VCCST
@ RV815
10K_0402_5%
1
10K_0402_5%
1
RV816
RV817
2
PEG_CRX_GTX_N10 CV448 2 1 0.22U_0201_6.3V6K PEG_CRX_C_GTX_N10 @ DV34
+3.3V_DGFF <58,62,85> ACAV_IN DGPU_PEX_RST# DGPU_PEX_RST#_D DGPU_PW ROK
1 2 @ RV800 1 2
2
1
2
10K_0402_5%
1000P_0402_50V7K
G
PEG_CRX_GTX_P11 CV449 2 1 0.22U_0201_6.3V6K PEG_CRX_C_GTX_P11 0_0402_5%
2
PEG_CRX_GTX_N11 PEG_CRX_C_GTX_N11
10K_0402_5%
RV821
RV820
100K_0402_5%
CV450 2 1 0.22U_0201_6.3V6K @ CV811 UV68 RB751VM-40TE-17_SOD323-2
4.7K_0402_5%
1
1
1 2 5 1 DGFF_OVERT# 3 1
Vcc OE 1 THERMTRIP1# <58>
@ CV812
PEG_CRX_GTX_P12 2 1 0.22U_0201_6.3V6K PEG_CRX_C_GTX_P12
RV819
CV451
D
RV818
PEG_CRX_GTX_N12 CV452 2 1 0.22U_0201_6.3V6K PEG_CRX_C_GTX_N12 0.1U_0201_10V6K UV69
2
A 2 5 1 A
PEG_CRX_GTX_P13 CV453 2 1 0.22U_0201_6.3V6K PEG_CRX_C_GTX_P13 IN A VCC NC 2 QV40
2
2
5
PEG_CRX_GTX_N13 CV454 2 1 0.22U_0201_6.3V6K PEG_CRX_C_GTX_N13 2 L2N7002W T1G_SC-70-3

A PROCHOT# <7,58,83,85,90>
1 4 3 4 change SB00000UO00 to SB000009Q80/
G VCC
PEG_CRX_GTX_P14 CV455 2 1 0.22U_0201_6.3V6K PEG_CRX_C_GTX_P14 DGFF_PW R_LEVEL 4 B OUT YGND Y 3 SB00000ST00 as main source,
PEG_CRX_GTX_N14 CV456 2 1 0.22U_0201_6.3V6K PEG_CRX_C_GTX_N14 Y 2 GND SB00000UO00 as 3rd source
A GPU_PW R_LEVEL <58>
74AUP1G07GW _TSSOP5
PEG_CRX_GTX_P15 CV457 2 1 0.22U_0201_6.3V6K PEG_CRX_C_GTX_P15 M74VHC1GT125DF2G_SC70-5
change net name
3
PEG_CRX_GTX_N15 CV458 2 1 0.22U_0201_6.3V6K PEG_CRX_C_GTX_N15 UV60

MC74VHC1G09DFT2G_SC70-5
Title
DGFF CONN.
Custom 1.0
5 4 3 2 1
5 4 3 2 1
Vinafix.com
D
UMA DGFF CON.
JDGFF4
D
CPU_DP3_P0 A1 H1
<9> CPU_DP3_P0 CPU_DP3_N0 A1 P P H1
A2 H2
<9> CPU_DP3_N0 A2 N N H2
A3 G H3
CPU_DP3_P1 A4 A3 G H3 H4
<9> CPU_DP3_P1 CPU_DP3_N1 A4 P P H4
A5 H5
CPU <9>
<9>
CPU_DP3_N1
CPU_DP3_P2
CPU_DP3_P2
A6
A7
A5 N
A6 G
A7 P
N
G
P
H5
H6
H7
H6
H7
CPU_DP3_N2 A8 H8
HDMI2.0 <9> CPU_DP3_N2
A9 A8 N N H8 H9
A10 A9 G G H9 H10
<19> PCH_DPD_HPD A10 H10
B1 G1
CPU_DP3_P3 B2 B1 G G G1
G2
<9> CPU_DP3_P3 B2 P P G2
CPU_DP3_N3 B3 G3
<9> CPU_DP3_N3 B3 N N G3
B4 G G4 G4
B5 B4 G G5
<9> CPU_DP3_AUXP B5 P P G5
B6 N G6 G6
<9> CPU_DP3_AUXN B6 N
B7 G G7 G7
B8 B7 G G8
<30> SW2_DP2_2_P0 B8 P P G8
B9 N G9 G9
<30> SW2_DP2_2_N0 B10 B9 N G10
B10 G G G10
C1 F1
C2 C1 P P F1 F2 MDP_CA_DET VGA_IDENTIFY <27,58>
<30> SW2_DP2_2_HPD C2 N N F2 MDP_CA_DET <30>
C3 F3
C3 G G F3
C4 F4
C <30> SW2_DP2_2_P1 C5 C4 P P F4 F5
SW2_DP2_2_AUXP <30> C
PS8338 mDP
<30> SW2_DP2_2_N1
<30> SW2_DP2_2_P2
C6
C7
C5 N
C6 G
C7 P
N
G
P
F5
F6
F7
F6
F7
SW2_DP2_2_AUXN
SW2_DP2_2_P3
<30>
<30>
C8 F8
<30> SW2_DP2_2_N2 C9 C8 N N F8 F9 SW2_DP2_2_N3 <30>
C10 C9 F9 F10
+3.3V_RUN C10 F10 +3.3V_RUN
D1 E1
D2 D1 E1 E2
D2 E2 +3.3V_RUN
D9 E9
D10 D9 E9 E10
+3.3V_RUN D10 E10 +5V_RUN
1 3
2 NPTH1 NPTH3 4
NPTH2 NPTH4
UNIMI_FBGCAX011
CONN@
B B
A A
DGFF CONN.
5 4 3 2 1
5 4 3 2 1
+3.3V_RUN
+3.3V_RUN
4.7U_0402_6.3V6M
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
EDP_SW1_PC0 @ RV822 1
82P_0402_50V8J
RF@ CV955
1 1 1 1 1 1 2 4.7K_0402_5%
EDP_SW1_PC1 @ RV823 1
CV813
CV814
CV815
CV816
CV817
2 4.7K_0402_5%
Vinafix.com
2 2 2 2 2 2 EDP_IN1_AEQ# @ RV824 1 2 4.7K_0402_5%
UV64 EDP_IN2_AEQ# @ RV825 1 2 4.7K_0402_5%

D 21 D
26 VDD33_1 EDP_IN1_PEQ @ RV826 1 2 4.7K_0402_5%
35 VDD33_2
49 VDD33_3 32 SW1_EDP_AUXP EDP_IN2_PEQ @ RV827 1 2 4.7K_0402_5%
60 VDD33_4 OUT_AUXp_SCL 31 SW1_EDP_AUXN SW1_EDP_AUXP <38>
VDD33_5 OUT_AUXn_SDA SW1_EDP_AUXN <38> EDP_SW1_PI0 @ RV828 1 2 4.7K_0402_5%
EDP_IN2_PEQ 51
EDP_IN1_PEQ 52 IN2_PEQ/SCL_CTL 53
EDP_IN1_AEQ# 59 IN1_PEQ/SDA_CTL I2C_CTL_EN SW1_CET CV818 2 1 2.2U_0402_6.3V6M
EDP_IN2_AEQ# 58 IN1_AEQ#
IN2_AEQ# 56 EDP_SW1_PI0 EDP_SW1_PI0 @ RV829 1 2 4.7K_0402_5%
PI0 38 EDP_SW1_PC0
EDP_TXP0 CV829 1 2 0.1U_0201_10V6K EDP_TXP0_C 1 PC0 55 EDP_SW1_PC1 EDP_SW1_PC0 @ RV830 1 2 4.7K_0402_5%
<9> EDP_TXP0 EDP_TXN0 1 2 EDP_TXN0_C 2 IN1_D0p PC1
CV830 0.1U_0201_10V6K
<9> EDP_TXN0 EDP_TXP1 1 2 EDP_TXP1_C 4 IN1_D0n EDP_SW1_PC1 @ RV831 1 2 4.7K_0402_5%
CV831 0.1U_0201_10V6K
<9> EDP_TXP1 EDP_TXN1 1 2 EDP_TXN1_C 5 IN1_D1p
CV832 0.1U_0201_10V6K
<9> EDP_TXN1 EDP_TXP2 1 2 EDP_TXP2_C 6 IN1_D1n 48 1 2 EDP_IN1_PEQ @ RV833 1 2 4.7K_0402_5%
CV833 0.1U_0201_10V6K
CPU <9>
<9>
<9>
EDP_TXP2
EDP_TXN2
EDP_TXP3
EDP_TXN2
EDP_TXP3
CV834
CV835
1
1
2
2
0.1U_0201_10V6K
0.1U_0201_10V6K
EDP_TXN2_C
EDP_TXP3_C
7
9
IN1_D2p
IN1_D2n
IN1_D3p
CA_DET RV832 1M_0402_5%
EDP_IN2_PEQ @ RV834 1 2 4.7K_0402_5%
EDP_TXN3 CV836 1 2 0.1U_0201_10V6K EDP_TXN3_C 10 46 SW1_EDP_P0
<9> EDP_TXN3 IN1_D3n OUT_D0p 45 SW1_EDP_N0 SW1_EDP_P0 <38>
EDP_AUXP CV837 1 2 0.1U_0201_10V6K EDP_AUXP_C 28 OUT_D0n 43 SW1_EDP_P1 SW1_EDP_N0 <38>
<9> EDP_AUXP EDP_AUXN 1 2 0.1U_0201_10V6K EDP_AUXN_C 27 IN1_AUXp OUT_D1p 42 SW1_EDP_N1 SW1_EDP_P1 <38>
CV838
<9> EDP_AUXN 23
22
IN1_AUXn
IN1_SCL
IN1_SDA
OUT_D1n
OUT2_D2p
OUT2_D2n
40
39
SW1_EDP_P2
SW1_EDP_N2
SW1_EDP_N1
SW1_EDP_P2
SW1_EDP_N2
<38>
<38>
<38>
eDP
GPU_EDP_P0 1 2 GPU_EDP_P0_C 11
OUT_D3p
OUT_D3n
37
36
SW1_EDP_P3
SW1_EDP_N3 SW1_EDP_P3
SW1_EDP_N3
<38>
<38>
Conn
CV819 0.1U_0201_10V6K
<27> GPU_EDP_P0 GPU_EDP_N0 1 2 GPU_EDP_N0_C 12 IN2_D0p
CV820 0.1U_0201_10V6K
<27> GPU_EDP_N0 GPU_EDP_P1 1 2 GPU_EDP_P1_C 14 IN2_D0n 54 +3.3V_RUN
CV821 0.1U_0201_10V6K
<27> GPU_EDP_P1 GPU_EDP_N1 1 2 GPU_EDP_N1_C 15 IN2_D1p SW
CV822 0.1U_0201_10V6K
<27> GPU_EDP_N1 GPU_EDP_P2 1 2 GPU_EDP_P2_C 16 IN2_D1n 44 SW1_EDP_HPD
CV823 0.1U_0201_10V6K
DSC DGFF <27> GPU_EDP_P2 IN2_D2p OUT_HPD SW1_EDP_HPD <38>
1
10K_0402_5%
C GPU_EDP_N2 CV824 1 2 0.1U_0201_10V6K GPU_EDP_N2_C 17 C
<27> GPU_EDP_N2 GPU_EDP_P3 1 2 GPU_EDP_P3_C 19 IN2_D2n
CV825 0.1U_0201_10V6K
<27> GPU_EDP_P3 GPU_EDP_N3 GPU_EDP_N3_C IN2_D3p
RV900
CV826 1 2 0.1U_0201_10V6K 20
<27> GPU_EDP_N3 IN2_D3n 34 SW1_REXT +3.3V_RUN
GPU_EDP_AUXP CV827 1 2 0.1U_0201_10V6K GPU_EDP_AUXP_C 30 REXT 47 SW1_CET
<27> GPU_EDP_AUXP
2
IN2_AUXp CEXT
2
GPU_EDP_AUXN CV828 1 2 0.1U_0201_10V6K GPU_EDP_AUXN_C 29
<27> GPU_EDP_AUXN IN2_AUXn
1
8.2K_0402_5%
25 RV835
IN2_SCL
RV901
24 8 4.99K_0402_1%
IN2_SDA GND1 18
GND2 33
1
CPU_EDP_HPD 3 GND3 41
2
<19> CPU_EDP_HPD GPU_EDP_HPD 13 IN1_HPD GND4 57
<27> GPU_EDP_HPD IN2_HPD GND5
1
61 D From EC
Epad 50 2
PD SW Input QV43
DGPU_SELECT# <38,59>
L2N7002WT1G_SC-70-3 G
PS8331BQFN60GTR-A0_QFN60_5X9 H IN2 S DGPU_SELECT#: 0=DGFF ; 1=i-GPU
3
PN change to SA000060U10 L (Default) IN1 change SB00000UO00 to SB000009Q80/
INy_PEQ = Programmable input equalization levels

L: default, LEQ, compensate channel loss up to 11.5dB @ HBR2
H: HEQ, compensate channel loss up to 14.5dB @ HBR2
M: LLEQ, compensate channel loss up to 8.5dB @ HBR2
B B
INy_AEQ# = Automatic EQ disable

L: Automatic EQ enable (default)
H: Automatic EQ disable
PI0 = Auto test enable

L: Auto test disable & input offset cancellation enable (default)
H: Auto test enable & input offset cancellation enable
M: Auto test disable & input offset cancellation disable
PC0 = AUX interception disable

L: AUX interception enable, driver configuration is set by link training (default)
H: AUX interception disable, driver output with fixed 800mV and 0dB
M: AUX interception disable, driver output with fixed 400mV and 0dB
PC1 = Output swing adjustment

L: default
H: +20%
M: -16.7%
A A
Title
eDP MUX (PS8331)
5 4 3 2 1
5 4 3 2 1
+3.3V_RUN
CV62 CV90 close to pin30 &57 +3.3V_RUN
CV66,CV69,CV70 close to pin5,21,51
1 2 DP1_SW2_CFG0
Vinafix.com
0.01U_0402_16V7K
0.01U_0402_16V7K
0.1U_0201_25V6K
0.1U_0201_25V6K
0.1U_0201_25V6K
RV125 4.7K_0402_5%
1 2 DP1_SW2_SW
UV8
1
@ RV126 4.7K_0402_5%
DP1_SW2_PI0
CV60
CV61
CV62
CV63
CV64
D 1 2 D
RV127 4.7K_0402_5% 5
2
21 VDD33_1 50 SW2_DP2_1_P0
30 VDD33_2 OUT1_D0p 49 SW2_DP2_1_N0 SW2_DP2_1_P0 <31>
51 VDD33_3 OUT1_D0n SW2_DP2_1_N0 <31>
57 VDD33_4 47 SW2_DP2_1_P1
1 2 OUT1_CA_DET VDD33_5 OUT1_D1p 46 SW2_DP2_1_N1 SW2_DP2_1_P1 <31>
RV130
1 2
1M_0402_5%
MDP_CA_DET
<9> CPU_DP2_P0
CPU_DP2_P0 CV65 1 2 0.1U_0201_10V6K CPU_DP2_P0_C 6
IN_D0p
OUT1_D1n
OUT1_D2p
45 SW2_DP2_1_P2
SW2_DP2_1_N1
SW2_DP2_1_P2
<31>
<31>
TBT/MUX2
RV131 1M_0402_5% CPU_DP2_N0 CV66 1 2 0.1U_0201_10V6K CPU_DP2_N0_C 7 44 SW2_DP2_1_N2
<9> CPU_DP2_N0 IN_D0n OUT1_D2n SW2_DP2_1_N2 <31>
CPU_DP2_P1 CV67 1 2 0.1U_0201_10V6K CPU_DP2_P1_C 9 42 SW2_DP2_1_P3
<9> CPU_DP2_P1 CPU_DP2_N1 CV68 1 2 0.1U_0201_10V6K CPU_DP2_N1_C 10 IN_D1p OUT1_D3p 41 SW2_DP2_1_N3 SW2_DP2_1_P3 <31>
<9> CPU_DP2_N1 IN_D1n OUT1_D3n SW2_DP2_1_N3 <31>
CPU <9>
<9>
CPU_DP2_P2
CPU_DP2_N2
CPU_DP2_P2
CPU_DP2_N2
CV69
CV70
1
1
2 0.1U_0201_10V6K
2 0.1U_0201_10V6K
CPU_DP2_P2_C
CPU_DP2_N2_C
12
13 IN_D2p
IN_D2n OUT2_D0p
40
SW2_DP2_2_P0 <28>
39
CPU_DP2_P3 CV71 1 2 0.1U_0201_10V6K CPU_DP2_P3_C 15 OUT2_D0n SW2_DP2_2_N0 <28>
<9> CPU_DP2_P3 CPU_DP2_N3 CV72 1 2 0.1U_0201_10V6K CPU_DP2_N3_C 16 IN_D3p 37
<9> CPU_DP2_N3 IN_D3n OUT2_D1p 36 SW2_DP2_2_P1 <28>
+3.3V_RUN OUT2_D1n SW2_DP2_2_N1 <28>
4
IN_CA_DET
OUT2_D2p
OUT2_D2n
35
34 SW2_DP2_2_P2
SW2_DP2_2_N2
<28>
<28>
UMA DGFF
3
<19> PCH_DPC_HPD 2 IN_HPD 32
DP1_SW2_PI1 I2C_CTL_EN OUT2_D3p SW2_DP2_2_P3 <28>
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
1 31
Pl1/SCL_CTL OUT2_D3n SW2_DP2_2_N3 <28>
1
DP1_SW2_PI0 60
Pl0/SDA_CTL
RV55
@ RV57
RV59
@ RV61
@ RV63
@ RV65
26 SW2_DP2_1_AUXP
PCH_DPC_CTRL_CLK 22 OUT1_AUXp_SCL 27 SW2_DP2_1_AUXN SW2_DP2_1_AUXP <31>
<19> PCH_DPC_CTRL_CLK PCH_DPC_CTRL_DATA 23 IN_DDC_SCL OUT1_AUXn_SDA SW2_DP2_1_AUXN <31>
<19> PCH_DPC_CTRL_DATA
2
DP1_SW2_PI1 CPU_DP2_AUXP CV73 1 2 0.1U_0201_10V6K CPU_DP2_AUXP_C 24 IN_DDC_SDA 28

C <9> CPU_DP2_AUXP CPU_DP2_AUXN 1 2 0.1U_0201_10V6K CPU_DP2_AUXN_C 25 IN_AUXp OUT2_AUXp_SCL 29 SW2_DP2_2_AUXP <28> C
CV74
DP1_SW2_PC10 <9> CPU_DP2_AUXN IN_AUXn OUT2_AUXn_SDA SW2_DP2_2_AUXN <28>
DP1_SW2_CFG0 59 43 OUT1_CA_DET
DP1_SW2_PC11 58 CFG0 OUT1_CA_DET 48 SW2_DP2_1_HPD
DP1_SW2_PC10 56 CFG1 OUT1_HPD SW2_DP2_1_HPD <31>
DP1_SW2_PC20 DP1_SW2_PC11 55 PC10 33 MDP_CA_DET
DP1_SW2_PC20 54 PC11 OUT2_CA_DET 38 MDP_CA_DET <28>
DP1_SW2_PC21 DP1_SW2_PC21 53 PC20 OUT2_HPD SW2_DP2_2_HPD <28>
PC21 18 DP1_SW2_SW
DP1_SW2_PEQ 11 SW 8 DP1_SW2_PEQ
GND1 PEQ
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
19 14
GND2 PD
1
52 17
GND3 CEXT
RV56
@ RV58
@ RV60
@ RV62
@ RV64
@ RV66
61 20
PAD(GND) REXT
2.2U_0402_6.3V6M
1
4.99K_0402_1%
PS8338BQFN60GTR-A1_QFN60_5X9
1
RV50
2
CV75
2
2
Port switching control or priority configuration. Internal pull down ~150KΩ, 3.3V I/O
For Control Switching Mode (CFG0 = L):
SW = L: Port1 is selected (default) H L
SW = H: Port2 is selected
For Automatic Switching Mode (CFG0 = H): (By OUT1_HPD and OUT2_HPD)
CFG0 V
SW = L: Port1 has higher priority when both ports are plugged (default)
SW = H: Port2 has higher priority when both ports are plugged SW V
B B
A A
Title
DP DeMUX (PS8338)
5 4 3 2 1
5 4 3 2 1
+3.3V_RUN VDDA12_A VDDRX12_A +3.3V_RUN +1.2V_RUN
0.1U_0201_10V6K
1U_0201_10V6M
VDD12_A VDDTX12_A +3.3V_RUN
1 1
VDD33_A
CV940
LV4 1 2 BLM18KG331SN1D_2P
CV939
I2C_ADDR_MUX1 @ RV849 1 2 4.7K_0402_5% VDD12_A LV5 1 2
4.7U_0402_6.3V6M
0.1U_0201_10V6K
0.1U_0201_10V6K
0.01U_0402_16V7K
0.01U_0402_16V7K
BLM18KG331SN1D_2P
2 2
4.7U_0402_6.3V6M
0.1U_0201_10V6K
0.1U_0201_10V6K
0.01U_0402_16V7K
0.01U_0402_16V7K
MUX1_IN1_EQ1 @ RV850 1 2 4.7K_0402_5%
1 1 1
1
29
32
56
43
24
42
55
1 1 1
1
MUX1_IN2_EQ1
CV854
CV855
CV856
CV857
CV858
UV66 @ RV851 1 2 4.7K_0402_5%
CV950
CV951
CV948
CV947
CV901
VDD33_1
VDD33_2
VDD12_1
VDD12_2
VDDA12
VDDRX12_1
VDDRX12_2
VDDTX12_1
VDDTX12_2
VDD_DDC
2
GPU_DP1_P0 CV860 2 1 0.22U_0201_6.3V6K GPU_DP1_P0_C 4 54 2 2 2 MUX1_IN1_EQ0 RV852 1 2 4.7K_0402_5%
<27> GPU_DP1_P0
2
GPU_DP1_N0 CV861 2 1 0.22U_0201_6.3V6K GPU_DP1_N0_C 5 IN1_D0p OUT_D0p 53 SW3_DP1_P0 <42> 2 2 2
<27> GPU_DP1_N0
Vinafix.com
IN1_D0n OUT_D0n SW3_DP1_N0 <42> MUX1_IN2_EQ0 @ RV853 1 2 4.7K_0402_5% +1.2V_RUN
GPU_DP1_P1 CV862 2 1 0.22U_0201_6.3V6K GPU_DP1_P1_C 7
<27> GPU_DP1_P1 IN1_D1p
GPU_DP1_N1 CV863 2 1 0.22U_0201_6.3V6K GPU_DP1_N1_C 8
<27> GPU_DP1_N1 IN1_D1n 51
GPU_DP1_P2 CV864 2 1 0.22U_0201_6.3V6K GPU_DP1_P2_C 10 OUT_D1p 50 SW3_DP1_P1 <42> SW 3_DP1_AUXN RV855 1 2 100K_0402_5% VDDRX12_A LV6 1 2
<27> GPU_DP1_P2
D
DSC DGFF <27> GPU_DP1_N2
GPU_DP1_N2 CV865 2 1 0.22U_0201_6.3V6K GPU_DP1_N2_C 11 IN1_D2p
IN1_D2n
OUT_D1n SW3_DP1_N1 <42>
MUX1_CFG0
BLM18KG331SN1D_2P D
4.7U_0402_6.3V6M
0.1U_0201_10V6K
0.1U_0201_10V6K
0.01U_0402_16V7K
0.01U_0402_16V7K
RV879 1 2 4.7K_0402_5%
<27> GPU_DP1_P3 1 1 1
IN1_D3p
TBT/DP
1
GPU_DP1_N3 CV867 2 1 0.22U_0201_6.3V6K GPU_DP1_N3_C 13 MUX1_CFG1 RV878 1 2 4.7K_0402_5%
<27> GPU_DP1_N3 IN1_D3n
CV910
CV908
CV909
CV952
CV949
MUX1_CFG2 @ RV877 1 2 4.7K_0402_5%
2
CPU_DP1_P0 CV868 2 1 0.22U_0201_6.3V6K CPU_DP1_P0_C 14 48 2 2 2
<9> CPU_DP1_P0 CPU_DP1_N0 CV869 2 1 0.22U_0201_6.3V6K CPU_DP1_N0_C 15 IN2_D0p OUT_D2p 47 SW3_DP1_P2 <42> MUX1_CFG3 @ RV848 1 2 4.7K_0402_5% +1.2V_RUN
<9> CPU_DP1_N0 IN2_D0n OUT_D2n SW3_DP1_N2 <42>
CPU_DP1_P1 CV870 2 1 0.22U_0201_6.3V6K CPU_DP1_P1_C 17 MUX1_CFG4 RV891 1 2 4.7K_0402_5%
<9> CPU_DP1_P1 CPU_DP1_N1 CV871 2 1 0.22U_0201_6.3V6K CPU_DP1_N1_C 18 IN2_D1p
CPU <9>
<9>
CPU_DP1_N1
CPU_DP1_P2
CPU_DP1_P2 CV872 2 1 0.22U_0201_6.3V6K CPU_DP1_P2_C 20
IN2_D1n
IN2_D2p
OUT_D3p
OUT_D3n
45
44 SW3_DP1_P3
SW3_DP1_N3
<42>
<42>
VDDTX12_A LV7 1
BLM18KG331SN1D_2P
2
4.7U_0402_6.3V6M
0.1U_0201_10V6K
0.1U_0201_10V6K
0.01U_0402_16V7K
0.01U_0402_16V7K
CPU_DP1_N2 CV873 2 1 0.22U_0201_6.3V6K CPU_DP1_N2_C 21 MUX1_CFG0 RV876 1 2 4.7K_0402_5%
<9> CPU_DP1_N2 IN2_D2n
1 1 1
1
CPU_DP1_P3 CV874 2 1 0.22U_0201_6.3V6K CPU_DP1_P3_C 22 MUX1_CFG1 @ RV856 1 2 4.7K_0402_5%
<9> CPU_DP1_P3 CPU_DP1_N3 CV875 CPU_DP1_N3_C IN2_D3p
CV914
CV913
CV915
CV911
CV912
2 1 0.22U_0201_6.3V6K 23
MUX1
<9> CPU_DP1_N3 IN2_D3n MUX1_CFG2 @ RV857 1 2 4.7K_0402_5%
2
2 2 2
DP1_SW 1_REXT 31 28 MUX1_CFG0 MUX1_CFG3 @ RV858 1 2 4.7K_0402_5% +1.2V_RUN
REXT CFG0 27 MUX1_CFG1
2
34 CFG1 26 MUX1_CFG2 MUX1_CFG4 RV892 1 2 4.7K_0402_5%
RV861 33 CSCL CFG2 25 MUX1_CFG3
I2C_ADDR_MUX1 6 CSDA CFG3 46 MUX1_CFG4 MUX1_IN1_EQ1 @ RV882 1 2 4.7K_0402_5% VDDA12_A LV8 1 2
4.99K_0402_1%
I2C_ADDR CFG4 BLM18KG331SN1D_2P
4.7U_0402_6.3V6M
0.1U_0201_10V6K
1U_0201_10V6M
0.01U_0402_16V7K
MUX1_IN2_EQ1 @ RV880 1 2 4.7K_0402_5%
1
1 1 1
1
CV917
66 58 SW 3_DP1_AUXP MUX1_IN1_EQ0 @ RV881 1 2 4.7K_0402_5%
IN1_SCL OUT_AUXp_SCL SW 3_DP1_AUXP <42>
CV919
CV918
CV916
65 57 SW 3_DP1_AUXN
IN1_SDA OUT_AUXn_SDA SW 3_DP1_AUXN <42> MUX1_IN2_EQ0 @ RV883 1 2 4.7K_0402_5%
2
CV945 1 2 0.1U_0201_10V6K GPU_DP1_C_AUXP 62 2 2 2
<27> GPU_DP1_AUXP IN1_AUXp
CV946 1 2 0.1U_0201_10V6K GPU_DP1_C_AUXN 61 52 MID1_CA_DET MID1_CA_DET RV895 1 2 1M_0402_5%
<27> GPU_DP1_AUXN IN1_AUXn DP_CADET
SW 3_DP1_AUXP RV890 1 2 100K_0402_5%
64
63 IN2_SCL GPU_DP1_HPD @ RV898 1 2 100K_0402_5%
IN2_SDA
CPU_DP1_AUXP CV876 1 2 0.1U_0201_10V6K CPU_DP1_AUXP_C 60 PCH_DPB_HPD @ RV902 1 2 100K_0402_5%
<9> CPU_DP1_AUXP CPU_DP1_AUXN CV877 1 2 0.1U_0201_10V6K CPU_DP1_AUXN_C 59 IN2_AUXp
<9> CPU_DP1_AUXN IN2_AUXn
C GPU_DP1_HPD C
16 49
<27> GPU_DP1_HPD IN1_HPD OUT_HPD SW 3_DP1_HPD <42>
PCH_DPB_HPD 19
<19> PCH_DPB_HPD IN2_HPD
MUX1_IN1_EQ0 40 37 1
MUX1_IN1_EQ1 IN1_EQ0 RSV0 PAD~D @ T315
41 36 +1.2V_RUN
MUX1_IN2_EQ0 38 IN1_EQ1 RSV1 35 +3.3V_RUN
MUX1_IN2_EQ1 39 IN2_EQ0 RSV2 +3.3V_RUN
IN2_EQ1 VDD33_B 1 2 BLM18KG331SN1D_2P
SW DP1_GPU_SEL# LV9
VDD12_B LV10 1 2
0.1U_0201_10V6K
1U_0201_10V6M
4.7U_0402_6.3V6M
0.1U_0201_10V6K
0.1U_0201_10V6K
0.01U_0402_16V7K
0.01U_0402_16V7K
DP1_GPU_SEL# 9 BLM18KG331SN1D_2P
<59> DP1_GPU_SEL# SW
4.7U_0402_6.3V6M
0.1U_0201_10V6K
0.1U_0201_10V6K
0.01U_0402_16V7K
0.01U_0402_16V7K
0 DGFF VDDA12_B VDDRX12_B
1 1 1 1 1
1
CV942
30 67 VDD12_B VDDTX12_B
1 1 1
1
PD# EPAD(GND)
CV941
CV878
CV879
CV880
CV881
CV882
CV924
CV922
CV923
CV920
CV921
1 (Default) CPU
2
PS8461QFN66GTR-A0_QFN66_5X10 2 2 2 2 2
2
PS8461QFN66GTR-A0 change to A4 2 2 2
+1.2V_RUN
29
32
56
43
24
42
55
1
3
UV67
VDDRX12_B LV11 1 2
VDD33_1
VDD33_2
VDD12_1
VDD12_2
VDDA12
VDDRX12_1
VDDRX12_2
VDDTX12_1
VDDTX12_2
VDD_DDC
GPU_DP2_P0 CV883 2 1 0.22U_0201_6.3V6K GPU_DP2_P0_C 4 54 BLM18KG331SN1D_2P
<27> GPU_DP2_P0 GPU_DP2_N0 GPU_DP2_N0_C IN1_D0p OUT_D0p SW4_DP2_P0 <42>
4.7U_0402_6.3V6M
0.1U_0201_10V6K
0.1U_0201_10V6K
0.01U_0402_16V7K
0.01U_0402_16V7K
CV884 2 1 0.22U_0201_6.3V6K 5 53
<27> GPU_DP2_N0 IN1_D0n OUT_D0n SW4_DP2_N0 <42>
1 1 1
1
<27> GPU_DP2_P1 IN1_D1p
CV928
CV927
CV929
CV925
CV926
GPU_DP2_N1 CV886 2 1 0.22U_0201_6.3V6K GPU_DP2_N1_C 8
<27> GPU_DP2_N1 IN1_D1n 51
DSC DGFF
2
GPU_DP2_P2 CV887 2 1 0.22U_0201_6.3V6K GPU_DP2_P2_C 10 OUT_D1p 50 SW4_DP2_P1 <42> 2 2 2
<27> GPU_DP2_P2 GPU_DP2_N2 GPU_DP2_N2_C IN1_D2p OUT_D1n SW4_DP2_N1 <42>
CV888 2 1 0.22U_0201_6.3V6K 11 +1.2V_RUN
<27> GPU_DP2_N2 IN1_D2n
<27> GPU_DP2_P3 GPU_DP2_N3 GPU_DP2_N3_C IN1_D3p
<27> GPU_DP2_N3 CV890 2 1 0.22U_0201_6.3V6K 13
IN1_D3n VDDTX12_B LV12 1 2
BLM18KG331SN1D_2P
TBT/DP
4.7U_0402_6.3V6M
0.1U_0201_10V6K
0.1U_0201_10V6K
0.01U_0402_16V7K
0.01U_0402_16V7K
SW 2_DP2_1_P0 CV891 2 1 0.22U_0201_6.3V6K SW 2_DP2_1_P0_C 14 48
<30> SW 2_DP2_1_P0 SW 2_DP2_1_N0 CV892 2 1 0.22U_0201_6.3V6K SW 2_DP2_1_N0_C 15 IN2_D0p OUT_D2p 47 SW4_DP2_P2 <42>
<30> SW 2_DP2_1_N0 IN2_D0n OUT_D2n SW4_DP2_N2 <42> 1 1 1
1
SW 2_DP2_1_P1 CV893 SW 2_DP2_1_P1_C
CV933
CV932
CV934
CV930
CV931
2 1 0.22U_0201_6.3V6K 17
<30> SW 2_DP2_1_P1 SW 2_DP2_1_N1 CV894 2 1 0.22U_0201_6.3V6K SW 2_DP2_1_N1_C 18 IN2_D1p
DEMUX
2
+3.3V_RUN <30> SW 2_DP2_1_N1 IN2_D1n 45 2 2 2
B SW4_DP2_P3 <42> B
SW 2_DP2_1_P2 CV895 2 1 0.22U_0201_6.3V6K SW 2_DP2_1_P2_C 20 OUT_D3p 44 +1.2V_RUN
4.7K_0402_5% 2 1RV862 @ I2C_ADDR_MUX2 <30> SW 2_DP2_1_P2 SW 2_DP2_1_N2 CV896 2 1 0.22U_0201_6.3V6K SW 2_DP2_1_N2_C 21 IN2_D2p OUT_D3n SW4_DP2_N3 <42>
<30> SW 2_DP2_1_N2 IN2_D2n
SW 2_DP2_1_P3 CV897 2 1 0.22U_0201_6.3V6K SW 2_DP2_1_P3_C 22
MUX2
<30> SW 2_DP2_1_P3 SW 2_DP2_1_N3 CV898 2 1 0.22U_0201_6.3V6K SW 2_DP2_1_N3_C 23 IN2_D3p VDDA12_B LV13 1 2
4.7K_0402_5% 2 1RV864 MUX2_IN1_EQ0 <30> SW 2_DP2_1_N3 IN2_D3n BLM18KG331SN1D_2P
4.7U_0402_6.3V6M
0.1U_0201_10V6K
1U_0201_10V6M
0.01U_0402_16V7K
4.7K_0402_5% 2 1RV865 @ MUX2_IN1_EQ1 DP2_SW 1_REXT 31 28 MUX2_CFG0
REXT CFG0 1 1 1
1
CV938
27 MUX2_CFG1
CFG1
2
CV936
CV937
CV935
4.7K_0402_5% 2 1RV866 @ MUX2_IN2_EQ0 34 26 MUX2_CFG2
RV870 33 CSCL CFG2 25 MUX2_CFG3
2
4.7K_0402_5% 2 1RV867 @ MUX2_IN2_EQ1 4.99K_0402_1% I2C_ADDR_MUX2 6 CSDA CFG3 46 MUX2_CFG4 2 2 2
I2C_ADDR CFG4
100K_0402_5% 2 1RV869 SW 4_DP2_AUXN
1
66 58 SW 4_DP2_AUXP
MUX2_CFG0 IN1_SCL OUT_AUXp_SCL SW 4_DP2_AUXN SW 4_DP2_AUXP <42>
4.7K_0402_5% 2 1RV887 65 57
IN1_SDA OUT_AUXn_SDA SW 4_DP2_AUXN <42>
4.7K_0402_5% 2 1RV888 MUX2_CFG1 CV944 1 2 0.1U_0201_10V6K GPU_DP2_C_AUXP 62
<27> GPU_DP2_AUXP IN1_AUXp
CV943 1 2 0.1U_0201_10V6K GPU_DP2_C_AUXN 61 52 MID2_CA_DET
<27> GPU_DP2_AUXN IN1_AUXn DP_CADET
4.7K_0402_5% 2 1RV886 @ MUX2_CFG2
4.7K_0402_5% 2 1RV885 @ MUX2_CFG3 64

63 IN2_SCL
4.7K_0402_5% 2 1RV893 MUX2_CFG4 IN2_SDA
SW 2_DP2_1_AUXP 1 2 SW 2_DP2_1_AUXP_C 60
<30> SW 2_DP2_1_AUXP SW 2_DP2_1_AUXN@ RV808 1 SW 2_DP2_1_AUXN_C IN2_AUXp
2 0_0402_5% 59
<30> SW 2_DP2_1_AUXN IN2_AUXn
@ RV809 0_0402_5%
4.7K_0402_5% 2 1RV871 MUX2_CFG0
4.7K_0402_5% 2 1RV872 @ MUX2_CFG1 GPU_DP2_HPD 16 49

<27> GPU_DP2_HPD IN1_HPD OUT_HPD SW 4_DP2_HPD <42>
4.7K_0402_5% 2 1RV873 @ MUX2_CFG2 SW 2_DP2_1_HPD 19
<30> SW 2_DP2_1_HPD IN2_HPD
4.7K_0402_5% 2 1RV874 @ MUX2_CFG3
MUX2_IN1_EQ0 40 37 1
MUX2_CFG4 MUX2_IN1_EQ1 IN1_EQ0 RSV0 PAD~D @ T316
4.7K_0402_5% 2 1RV894 41 36
MUX2_IN2_EQ0 38 IN1_EQ1 RSV1 35
4.7K_0402_5% 2 1RV875 @ MUX2_IN1_EQ0 MUX2_IN2_EQ1 39 IN2_EQ0 RSV2
IN2_EQ1
4.7K_0402_5% 2 1RV868 @ MUX2_IN1_EQ1
A DP2_GPU_SEL# 9 A
MUX2_IN2_EQ0 <59> DP2_GPU_SEL# SW
4.7K_0402_5% 2 1RV863 @
30 67
4.7K_0402_5% 2 1RV884 @ MUX2_IN2_EQ1 PD# EPAD(GND)
1M_0402_5% 1 2 RV896 MID2_CA_DET PS8461QFN66GTR-A0_QFN66_5X10

PS8461QFN66GTR-A0 change to A4
100K_0402_5% 2 1RV889 SW 4_DP2_AUXP
100K_0402_5% 2 1RV897 @ GPU_DP2_HPD
100K_0402_5% 2 1RV903 @ SW 2_DP2_1_HPD DELL CONFIDENTIAL/PROPRIETARY

Title
MUX PS8461
Custom 1.0
5 4 3 2 1
5 4 3 2 1
Vinafix.com
D D
Reserve
C C
B B
A A
DGPU
5 4 3 2 1
5 4 3 2 1
Vinafix.com
D D
Reserve
C C
B B
A A
DGPU
5 4 3 2 1
5 4 3 2 1
Vinafix.com
D D
C C
Reserve
B B
A A
DGPU
5 4 3 2 1
5 4 3 2 1
Vinafix.com
D D
C C
Reserve
B B
A A
DGPU
5 4 3 2 1
5 4 3 2 1
Vinafix.com
D D
C C
Reserve
B B
A A
DGPU
5 4 3 2 1
2 1
Vinafix.com
B B
Reserve
A A
DGPU
2 1
A B C D E
+3.3V_RUN
1 2
same 111H40-100100-G4-R PANEL_BKEN_PCH <14>
1
CONN@ @ RV739 +3.3V_RUN DV35
JEDP1 10K_0402_5% RB751VM-40TE-17_SOD323-2
1 +BL_PWR_SRC
1
1
2 DV36
2
2 3 DID2_GPIO1_HDR RV740 DISP_ON 1 2
3 DGFF_PANEL_BKEN <27>
4 10K_0402_5%
4
6
Vinafix.com
5 RB751VM-40TE-17_SOD323-2
4.7K_0402_5%
5
1
6 +LCDVDD
2
6 7 DV37
RV836
7 8 2 DID2_GPIO1_R 1 2
8 +CAMERA_VDD PANEL_BKEN_EC <58>
1
9 1
9 10 RB751VM-40TE-17_SOD323-2
+3.3V_RUN_R
2
10
3
11 DMIC_CLK QV44A
DMIC_CLK <56>
1
11 12
12 L2N7002DW1T1G_SC88-6
13 DMIC0
13 DMIC0 <56> DMIC_CLK
14 5 1 2 1 2
14 15 USB20_N11_R DID2_GPIO1 <59>
RV741 1K_0402_5% @EMI@ CV842 100P_0402_50V8J
15 16 USB20_P11_R DMIC0 1 2
16 17 QV44B @EMI@ CV843 100P_0402_50V8J
CAM_MIC_CBL_DET# <14>
4
17 18 EMI@ LV1 1 2 BIA_PWM L2N7002DW1T1G_SC88-6
18 19 DISP_ON BLM15PX221SN1D_2P
19 20 DV38
20 21 LCD_CBL_DET# <19> 1 2 1 2
21 DGPU_TYPE# <27> BIA_PWM_PCH <14>
22 RV742 0_0201_5%
22 23 1 2 DID2_GPIO1_HDR RB751VM-40TE-17_SOD323-2
23 24 RV737 0_0201_5%
24 25 LCD_TST <58>
25 SW1_EDP_HPD <29>
26 DID2_GPIO1_MUX 1 2 DID2_GPIO1 +3.3V_RUN
26 27 @ RV738 0_0201_5%
27 28 DID2_GPIO2 0.1U_0201_10V6K
SW1_EDP_AUXP_C <59> 2 1 CV1
28 SW1_EDP_AUXN_C SW1_EDP_AUXP <29> HDR monitor for AMD/NV/UMA CV844 UV65
29 0.1U_0201_10V6K 2 1 CV2 2 1 5 1
29 30 SW1_EDP_AUXN <29> edp output detect 1/29 Vcc OE DGPU_SELECT# <29,59>
30 31 0.1U_0201_10V6K
31 32 SW1_EDP_N3_C 0.1U_0201_10V6K 2 1 CV3 2
32 SW1_EDP_P3_C SW1_EDP_N3 <29> IN A DGFF_BIA_PWM <27>
33 0.1U_0201_10V6K 2 1 CV4
33 SW1_EDP_N2_C SW1_EDP_P3 <29>
34 0.1U_0201_10V6K 2 1 CV5 DV39
34 SW1_EDP_P2_C SW1_EDP_N2 <29> BIA_PWM
35 0.1U_0201_10V6K 2 1 CV6 1 2 4 3
35 SW1_EDP_N1_C SW1_EDP_P2 <29> OUT Y GND
41 36 0.1U_0201_10V6K 2 1 CV845
G1 36 SW1_EDP_P1_C SW1_EDP_N1 <29>
42 37 0.1U_0201_10V6K 2 1 CV846 RB751VM-40TE-17_SOD323-2
G2 37 SW1_EDP_N0_C SW1_EDP_P1 <29>
43 38 0.1U_0201_10V6K 2 1 CV847
4.7K_0402_5%
G3 38 SW1_EDP_N0 <29>
1
44 39 SW1_EDP_P0_C 0.1U_0201_10V6K 2 1 CV848 M74VHC1GT125DF2G_SC70-5
G4 39 SW1_EDP_P0 <29>
45 40
RV839
G5 40 PN change to SA00000RY00
ACES_50398-04041-001
DV40
2
Update symbol Ver. 0725 1 2
2 BIA_PWM_EC <58> 2
EMI@ LV2 RB751VM-40TE-17_SOD323-2
1 2 USB20_N11_R
+BL_PWR_SRC +LCDVDD <15> USB20_N11
4 3 USB20_P11_R
<15> USB20_P11
0.1U_0402_50V7K
0.1U_0201_25V6K
MCM1012B900F06BP_4P
2 1 EMC request change main source
For BL_PWR_SRC & LCDVDD monitor
3
2
CV20
to SM070003Z00
CV849
ESD@ DV41
PESD5V0U2BT_SOT23-3 +BL_PWR_SRC +3.3V_ALW +LCDVDD
1 2
1
1
RV907 RV909 RV910

4.3M_0402_1% 100K_0402_5% 100K_0402_5%
Close to
2
JEDP1 Close to PANEL_MONITOR <58>
JEDP1
1
+3.3V_RUN
3
RV911
1
1M_0402_1%
SW1_EDP_AUXN 2 1 Keep PANEL_MONITOR
100K_0402_5% RV840 2 5 voltage on 3V,Change
Close to JEDP1
2
RV908 to 1M 3/29
SW1_EDP_AUXP 2 1 3M_0402_1%
2
100K_0402_5% RV842 QV23A QV23B
4
ESD@ RV907 change to 4.3M 1/21 L2N7002DW1T1G_SC88-6 L2N7002DW1T1G_SC88-6
DV4 RV908 change to 3M 4/8
DMIC0 2
1
DMIC_CLK 3 +LCDVDD
3 3
AZ5125-02S.R7G_SOT23-3 SW1_EDP_HPD 4.7K_0402_5% 2 1 @ RV7

PS8331 HPD input internal PD 150K
Webcam PWR CTRL
LCD Power
+BL_PWR_SRC
Align NB reserve fuse FZ3, FZ4 location and netname 3/29 Change fuse to 0603 package
+3.3V_RUN_R +CAMERA_VDD T0603FF1500TM 1/18 +LCDVDD JUMP@ +EDP_VDD
CV16 +3.3V_ALW
PJP12
1 2 1 2 FV1 10U_0402_6.3V6M UV24
RZ551 0_0603_5% +3.3V_RUN_R_F RZ550 0_0603_5% Material shortage SB000010C00 2 1 1 2 1
60mil change to SB000008S80 1/15
1.5A_65V_T0603FF1500TM
RF require
VOUT
VIN
5
+3.3V_RUN QZ1 follow naming rule PAD-OPEN1x1m
PJ2301_SOT23-3 +19.5VB 2
FZ1
QV1
RF require +LCDVDD GND 4
1 2 3 +CAMERA_VDD_F EN
S
1 AO6405_TSOP6 Add net name

D
6 +BL_PWR_SRC_F +BL_PWR_SRC 1 2 3
D
5 @ RV843 100K_0402_5% /OC

60mil
S
1A_65V_T0603FF1000TM 4
10U_0402_6.3V6M
0.1U_0201_25V6K
RF@
10P_0402_50V8J
2.2P_0402_50V8C
RF@ CV853
2 G524B1T11U_SOT23-5
G
2
10P_0402_50V8J
1U_0603_50V6K
100K_0402_5%
82P_0402_50V8J
RF@ CV852
Reserve for Material shortage
1 1 1 1
1
2
SB00000QP00 change
@ CZ510
RF@CZ512
CV13
0.1U_0402_50V7K
82P_0402_50V8J
22P_0402_50V8J
RF@ CV841
FUSE locatiom DV42
CV839 RF@
G
to SB00000T900 1/15 1 1
2
CZ511
RV4
CV15
82P_0402_50V8J
RF@ CV840
CV851
RB751VM-40TE-17_SOD323-2
3
1 2 1 1
2 1
<14> ENVDD_PCH
1
2
2 2 2
0.1U_0201_25V6K
0.1U_0201_25V6K
@ CV954
1 1
1
2 2
CZ509
@ RZ545
2
0_0201_5% 2 1 2 2
BL_PWR_SRC_ON
100K_0402_5%
1
2 2 Close to JEDP1 2
<58> LCD_VCC_TEST_EN
1
RV3
1
3.3V_CAM_EN# <17> QV2
0.01U_0402_50V7K
1
L2N7002WT1G_SC-70-3 3
<27> DGFF_ENVDD
CV14
2
1 2 1 3
D
4
2 RV5 47K_0402_5% DV3 4
JIR1 BAT54CW_SOT323-3
1 change SB00000UO00 to SB000009Q80/
G
IR_CAM_DET# <18>
2
1 2 SB00000ST00 as main source,

2 <58> EN_INVPWR SB00000UO00 as 3rd source
3 Reserve for FUSE locatiom
3 4
4 5 FZ2 Panel backlight power control by EC
5 6 +IR_F 1 2
6
7 Add net name 1A_65V_T0603FF1000TM
+19.5VB
follow naming rule
GND1
GND2
8 Security Classification Compal Secret Data Compal Electronics, Inc.
Title
ACES_50228-0067N-001
CONN@
eDP / CAM / TS
Custom 1.0
A B C D E
5 4 3 2 1
Vinafix.com
D D
C C
Reserve
B B
A A
DP
5 4 3 2 1
5 4 3 2 1
Vinafix.com
D D
C C
Reserve
B B
A A
HDMI2.0
5 4 3 2 1
5 4 3 2 1
Vinafix.com
D D
C C
Reserve
B B
A A
CRT
5 4 3 2 1
5 4 3 2 1
+3.3V_TBT_FLASH_R +3.3V_TBT_FLASH_R
+3.3V_TBT_LC +3.3V_TBT_FLASH_R +3.3V_TBT_LC
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
0.1U_0201_10V6K
2
2
3.3K_0402_5%
2.2K_0402_5%
2.2K_0402_5%
3.3K_0402_5%
@ RT9 1 2 0_0402_5%
1
CT1
RT5
RT6
RT7
RT8
RT1
RT2
RT3
RT4
Vinafix.com
2
+3.3V_VDD_PIC
1
TBT_JTAG_TDI
UT2 TBT_JTAG_TMS
8 1 TBT_ROM_CS# TBT_JTAG_TCK
TBT_ROM_HOLD# 7 VCC CS# 2 TBT_ROM_DO TBT_JTAG_TDO RT578 1 2 0_0402_5%
D TBT_ROM_CLK 6 HOLD#(IO3) DO(IO1) 3 TBT_ROM_W P# D
TBT_ROM_DI 5 CLK WP#(IO2) 4 Rework Debug Pin1 +3.3V_TBT_LC, Pin6 GND
DI(IO0) GND
W 25Q80DVSSIG_SO8
UT1A
PCIE_PTX_TRX_P1 0.22U_0201_6.3V6K 2 1 CT2 PCIE_PTX_C_TRX_P1 Y23 V23 PCIE_PRX_C_TTX_P1 0.22U_0201_6.3V6K 2 1 CT6 PCIE_PRX_TTX_P1
<15> PCIE_PTX_TRX_P1 PCIE_PTX_TRX_N1 PCIE_PTX_C_TRX_N1 PCIE_RX0_P PCIE_TX0_P PCIE_PRX_C_TTX_N1 PCIE_PRX_TTX_P1 <15>
0.22U_0201_6.3V6K 2 1 CT3 Y22 V22 0.22U_0201_6.3V6K 2 1 CT7 PCIE_PRX_TTX_N1
<15> PCIE_PTX_TRX_N1 PCIE_RX0_N PCIE_TX0_N PCIE_PRX_TTX_N1 <15>
PCIE_PTX_TRX_P2 0.22U_0201_6.3V6K 2 1 CT4 PCIE_PTX_C_TRX_P2 T23 P23 PCIE_PRX_C_TTX_P2 0.22U_0201_6.3V6K 2 1 CT8 PCIE_PRX_TTX_P2
0.22U_0201_6.3V6K 2 1 CT5 T22 P22 0.22U_0201_6.3V6K 2 1 CT9 PCIE_PRX_TTX_N2
<15> PCIE_PTX_TRX_N2 PCIE_RX1_N PCIE_TX1_N PCIE_PRX_TTX_N2 <15> +3.3V_RUN
PCIe GEN3
PCIE_PTX_TRX_P3 0.22U_0201_6.3V6K 2 1 CT123 PCIE_PTX_C_TRX_P3 M23 K23 PCIE_PRX_C_TTX_P3 0.22U_0201_6.3V6K 2 1 CT127PCIE_PRX_TTX_P3
0.22U_0201_6.3V6K 2 1 CT124 M22 K22 0.22U_0201_6.3V6K 2 1 CT128PCIE_PRX_TTX_N3
<15> PCIE_PTX_TRX_N3 PCIE_RX2_N PCIE_TX2_N PCIE_PRX_TTX_N3 <15> RTD3_CIO_PW R_EN_R @ RT643 1 2 10K_0201_5%
PCIE_PTX_TRX_P4 0.22U_0201_6.3V6K 2 1 CT125 PCIE_PTX_C_TRX_P4 H23 F23 PCIE_PRX_C_TTX_P4 0.22U_0201_6.3V6K 2 1 CT129PCIE_PRX_TTX_P4 Reserve +3.3V_TBT_S0 for
0.22U_0201_6.3V6K 2 1 CT126 H22 F22 0.22U_0201_6.3V6K 2 1 CT130PCIE_PRX_TTX_N4 RTD3_CIO_PWR_EN_R 4/9
<15> PCIE_PTX_TRX_N4 PCIE_RX3_N PCIE_TX3_N PCIE_PRX_TTX_N4 <15>
T4 TBT_PERST#
V19 PERST# +3.3V_ALW _PCH
<16> CLK_PCIE_P4 REFCLK_100_IN_P
TBT support RTD3,Follow NB
T19 N16
<16> CLK_PCIE_N4 REFCLK_100_IN_N PCIE_RBIAS
Y6 Y2
<16> CLKREQ_PCIE#4 PCIE_CLKREQ# PEWAKE# TBT_PCIE_RBIAS 1 RT34 2 3.01K_0402_1%
0.22U_0201_6.3V6K 2 1 CT11 SW 3_DP1_N0_C AB7 AB21
<31> SW 3_DP1_N0 DPSNK1_ML0_N DPSRC_ML0_P
0.22U_0201_6.3V6K 2 1 CT10 SW 3_DP1_P0_C AC7 AC21 PCIE_W AKE#_AR TBT_CIO_PLUG_EVENT# RT391 1 2 10K_0402_5%
<31> SW 3_DP1_P0 DPSNK1_ML0_P DPSRC_ML0_N
TBT support RTD3,Follow NB For backdrive
<31> SW 3_DP1_P1
0.22U_0201_6.3V6K
0.22U_0201_6.3V6K
2
2
1 CT12 SW 3_DP1_P1_C
1 CT13 SW 3_DP1_N1_C
AB9
AC9 DPSNK1_ML1_P DPSRC_ML1_P
AC19
AB19
issue
<31> SW 3_DP1_N1 DPSNK1_ML1_N DPSRC_ML1_N
SOURCE PORT 0
SINK PORT 1
0.22U_0201_6.3V6K 2 1 CT14 SW 3_DP1_P2_C AC11 AB17 +3.3V_TBT_SX
MUX1 PS8461 <31> SW 3_DP1_P2
0.22U_0201_6.3V6K 2 1 CT15 SW 3_DP1_N2_C AB11 DPSNK1_ML2_P DPSRC_ML2_P AC17
<31> SW 3_DP1_N2 DPSNK1_ML2_N DPSRC_ML2_N PCIE_W AKE#_AR RTD3@ RT613 1 2 10K_0201_5%
0.22U_0201_6.3V6K 2 1 CT16 SW 3_DP1_P3_C AB13 AC15
<31> SW 3_DP1_P3 DPSNK1_ML3_P DPSRC_ML3_P
0.22U_0201_6.3V6K 2 1 CT17 SW 3_DP1_N3_C AC13 AB15
<31> SW 3_DP1_N3 DPSNK1_ML3_N DPSRC_ML3_N TBTA_I2C_INT# @ RT16 1 2 10K_0201_5%
0.22U_0201_6.3V6K 2 1 CT18 SW 3_DP1_AUXP_C N1 N4 TBTB_I2C_INT# @ RT17 1 2 10K_0201_5%
<31> SW 3_DP1_AUXP SW 3_DP1_AUXN_C DPSNK1_AUX_P DPSRC_AUX_P TBT_RESET_N_EC
0.22U_0201_6.3V6K 2 1 CT19 N2 N5 correct status is down @ RT11 1 2 10K_0402_5%
<31> SW 3_DP1_AUXN DPSNK1_AUX_N DPSRC_AUX_N RTD3_USB_PW R_EN
change to @ 3/29 @ RT591 1 2 10K_0201_5%
C SW 3_DP1_HPD TBT_FORCE_PW R C
AA2 @ RT592 1 2 10K_0201_5%
<31> SW 3_DP1_HPD DPSNK1_HPD R5 DPSRC_HPD SIO_SLP_S3# @ RT593 1 2 10K_0402_5%
DPSRC_HPD CLKREQ_PCIE#4 @ RT502 1 2 10K_0402_5%
0.22U_0201_6.3V6K 2 1 CT186 SW 4_DP2_P0_C A5 TDOCK_BATLOW # RT20 1 2 10K_0402_5%
<31> SW 4_DP2_P0 SW 4_DP2_N0_C DPSNK2_ML0_P RTD3_CIO_PW R_EN_R
0.22U_0201_6.3V6K 2 1 CT187 B5 @ RT372 1 2 10K_0402_5%
<31> SW 4_DP2_N0 DPSNK2_ML0_N DG_GPIO8 RT503 1 2 2.2K_0402_5%
0.22U_0201_6.3V6K 2 1 CT183 SW 4_DP2_P1_C B3 W1 GPIO_0 Change to depop
<31> SW 4_DP2_P1 DPSNK2_ML1_P GPIO_0
LC GPIO
0.22U_0201_6.3V6K 2 1 CT180 SW 4_DP2_N1_C A3 W2 GPIO_1 Change BOM Structure to @
<31> SW 4_DP2_N1 DPSNK2_ML1_N GPIO_1
SINK PORT 2
Y1 GPIO_3
0.22U_0201_6.3V6K 2 1 CT185 SW 4_DP2_P2_C C2 TMU_CLKOUT AA1 TBT_CIO_PLUG_EVENT#
MUX2 PS8461 <31> SW 4_DP2_P2
0.22U_0201_6.3V6K 2 1 CT179 SW 4_DP2_N2_C C1 DPSNK2_ML2_P CIO_PLUG_EVENT# W6 DG_GPIO8 TBT_CIO_PLUG_EVENT# <14>
<31> SW 4_DP2_N2 DPSNK2_ML2_N TMU_CLKIN
0.22U_0201_6.3V6K 2 1 CT182 SW 4_DP2_P3_C E2 Change BOM Structure
<31> SW 4_DP2_P3 SW 4_DP2_N3_C DPSNK2_ML3_P RTD3_CIO_PW R_EN_R
0.22U_0201_6.3V6K 2 1 CT181 E1 V1 RT614 1 2 100K_0402_5%
<31> SW 4_DP2_N3 DPSNK2_ML3_N I2C_SDA TBT_I2C_SDA <44> DPSRC_HPD
V2 RT184 1 2 100K_0402_5%
I2C_SCL TBT_I2C_SCL <44>
POC GPIO
0.22U_0201_6.3V6K 2 1 CT178 SW 4_DP2_AUXP_C P1 V5 RTD3_USB_PW R_EN TBTA_HPD RT23 1 2 100K_0402_5%
<31> SW 4_DP2_AUXP SW 4_DP2_AUXN_C DPSNK2_AUX_P USB_FORCE_PWR TBT_FORCE_PW R TBTB_HPD
0.22U_0201_6.3V6K 2 1 CT184 P2 V4 RT33 1 2 100K_0402_5%
<31> SW 4_DP2_AUXN DPSNK2_AUX_N FORCE_PWR TDOCK_BATLOW # TBT_FORCE_PW R <19>
U2
SW 4_DP2_HPD Y4 BATLOW# U1 SIO_SLP_S3#
<31> SW 4_DP2_HPD DPSNK2_HPD SLP_S3# RTD3_CIO_PW R_EN_R 1 SIO_SLP_S3# <18,19,59> RTD3_USB_PW R_EN
T5 2 RT26 1 2 100K_0402_5%
RTD3_PWR_EN @ RT392 0_0201_5% RTD3_CIO_PW R_EN <17> TBT_FORCE_PW R RT27 1 2 100K_0402_5%
AC3 E5 TBT_RESET_N_EC 1 2
U0_SSRXp1 RESET# CCG5_AR_RST# <44>
AB3 @ RT37 0_0402_5%
U0_SSRXn1 Misc XTAL_25_IN TBT_RESET_N_EC <58> GPIO_0
D22 1 2 RT505 1 2 100K_0402_5%
USB
AB5 XTAL_25_IN D23 XTAL_25_OUT 1 2 XTAL_25_OUT_R RT394 0_0402_5% GPIO_1 RT506 1 2 100K_0402_5%
AC5 U0_SSTXn1 XTAL_25_OUT RT40 0_0402_5% GPIO_3 RT507 1 2 100K_0402_5%
U0_SSTXp1 YT1 DG_GPIO8 @ RT553 1 2 10K_0402_5%
TBT_JTAG_TDI W20 3 1
TBT_JTAG_TMS Y20 TDI Y18 TBT_ROM_DI OUT IN
TBT_JTAG_TCK W19 TMS EE_DI W16 TBT_ROM_DO 4 2 DG_PA_USB2_MXCTL RT508 1 2 100K_0402_5%
TCK EE_DO GND2 GND1
1
TBT_JTAG_TDO Y19 MISC W18 TBT_ROM_CS# DG_PB_USB2_MXCTL RT509 1 2 100K_0402_5%
TDO EE_CS# Y16 TBT_ROM_CLK CT20 25MHZ_20PF_FL2500123Z CT21
TBT_RBIAS J6 EE_CLK W4 TBT_ROM_W P# 20P_0402_50V8 20P_0402_50V8
2
1 2 TBT_RSENSE J5 RBIAS EE_WP#
RSENSE
4.75K_0402_0.5% RT39 support vpro on docking side reserve
@ RT595 1 2 0_0201_5% TBT_A_TRX_DTX_P1_R B21 A13 TBT_B_TRX_DTX_P1_R 1@ RT599 2 0_0201_5%
<45> TBT_A_TRX_DTX_P1 TBT_A_TRX_DTX_N1_R ASSRXp1 BSSRXp1 TBT_B_TRX_DTX_P1 <45>
@ RT594 1 2 0_0201_5% A21 B13 TBT_B_TRX_DTX_N1_R 1 2 0_0201_5%
<45> TBT_A_TRX_DTX_N1 ASSRXn1 BSSRXn1 TBT_B_TRX_DTX_N1 <45> TBTA_HPD_R 0_0201_5%
@ RT598 2 1 @ RT623
SML0_SMBCLK <18,51>
A19 A11
<45> TBT_A_TTX_DRX_P1 B19 ASSTXp1 BSSTXp1 B11 TBT_B_TTX_DRX_P1 <45> TBTB_HPD_R 0_0201_5% 2 1 @ RT624
B
TypeC CONN1 <45> TBT_A_TTX_DRX_N1 ASSTXn1 BSSTXn1 TBT_B_TTX_DRX_N1 <45> SML0_SMBDATA <18,51>
B
@ RT597 1 2 0_0201_5% TBT_A_TRX_DTX_P2_R A15 B7 TBT_B_TRX_DTX_P2_R 1@ RT601 2 0_0201_5%
<45> TBT_A_TRX_DTX_P2
@ RT596 1 2 0_0201_5% TBT_A_TRX_DTX_N2_R B15 ASSRXp2 BSSRXp2 A7 TBT_B_TRX_DTX_N2_R 1 2 0_0201_5%
TBT_B_TRX_DTX_P2 <45> TypeC CONN2
<45> TBT_A_TRX_DTX_N2 ASSRXn2 BSSRXn2 TBT_B_TRX_DTX_N2 <45>
@ RT600
TBT PORTS
A17 A9
<45> TBT_A_TTX_DRX_P2 ASSTXp2 BSSTXp2 TBT_B_TTX_DRX_P2 <45>
Port A
PORT B
B17 B9
<45> TBT_A_TTX_DRX_N2 ASSTXn2 BSSTXn2 TBT_B_TTX_DRX_N2 <45>
H4 L4
<44>
<44>
TBT_A_SBU1
TBT_A_SBU2
J4 ASBU1
ASBU2
BSBU1
BSBU2
L5
TBT_B_SBU1
TBT_B_SBU2
<44>
<44>
TBT support RTD3,Follow NB
To PD <44> USB20_PA
E20 E19
USB20_PB <44>
TBT RTD3 Support 1 2
D20 PA_USB2_D_P PB_USB2_D_P D19 NRTD3@ RT612 0_0201_5%
<44> USB20_NA PA_USB2_D_N PB_USB2_D_N USB20_NB <44>
TBTA_HPD @ RT619 1 2 0_0201_5% TBTA_HPD_R T2 T1 TBTB_HPD_R @ RT620 1 2 0_0201_5% TBTB_HPD +3.3V_ALW RTD3@ CT389
<44> TBTA_HPD
M4 PA_HPD PB_HPD M5
TBTB_HPD <44> To PD 0.1U_0201_10V6K
<44> TBTA_I2C_INT# DG_PA_USB2_MXCTL PA_I2C_INT PB_I2C_INT DG_PB_USB2_MXCTL TBTB_I2C_INT# <44>
R2 R1 1 2
PA_USB2_MXCTL PB_USB2_MXCTL
5
1 2 TBTA_USB2_RBIAS H19 F19 TBTB_USB2_RBIAS 2 1
RT41 200_0402_1% PA_USB2_RBIAS PB_USB2_RBIAS 200_0402_1% RT42
VCC
@RTD3@ RT499 1 2 0_0201_5% 1
TEST_PW RGD <17,52,67,68> PCH_PLTRST#_R IN1 TBT_PERST#_R TBT_PERST#
V8 W5 1 2 4 1 2
THERMDA TEST_PWR_GOOD R4 RT36 100_0402_5% @RTD3@ RT500 1 2 0_0201_5% 2 OUT @RTD3@ RT501 0_0201_5%
100K_0201_5%
GND
TEST_EN <14> PCH_TBT_PERST# IN2
2
D4 B23
RTD3@ RT611
L8 TEST_EDM USB2_ATEST AB23
FUSE_VQPS_64 PCIE_ATEST J9
DEBUG
3
A23 ATEST_P J11 RTD3@ UT34
A1 PA_MONDC ATEST_N H5 MC74VHC1G08DFT2G_SC70-5
1
AC23 PB_MONDC VGA_RES
AC1 PC_MONDC
D5 USB_MONDC Reserve RT621,RT622 0 1 2
MONDC_SVR
ohm(align Northbay) @ RT621
1
0_0201_5%
2
11/28 @ RT622 0_0201_5%
THUNDERBOLT_BGA337 RTD3@
+3.3V_ALW CT237
Titan Redge 0.1U_0201_10V6K
TBT_RTD3_W AKE#
DP <15,18> TBT_RTD3_W AKE# @RTD3@ RT456
1 2
0_0201_5% RTD3@UT32
1 2
PCH_PCIE_W AKE# 1 2 1 5
IN NC NO
<18,58,59> PCH_PCIE_W AKE# @ RT445 0_0201_5% NO V+
PCIE_W AKE# 1 2 3 4 PCIE_W AKE#_AR_R 1 2 PCIE_W AKE#_AR
<27,52,59,67,68> PCIE_W AKE# @RTD3@ RT448 0_0201_5% NC COM @RTD3@ RT441 0_0201_5%
L COM X
6 2
<59> RTD3_SELECT IN GND
2
A
H X COM A
2
RTD3@ TS5A3159ADCKR_SC70-6 @ RT440
RT447 1M_0201_5%
10K_0201_5%
1
1
Title
TBT-TR(1/2) DP, PCIE
Custom 1.0
5 4 3 2 1
5 4 3 2 1
+3.3V_TBT_S0 +3.3V_TBT
+3.3V_RUN +3.3V_TBT 1 2
LT2 1UH_LQM18PN1R0MFHD_20% UT1B
JUMP@ +3.3V_TBT_SX +3.3V_ALW +0.9V_TBT_SVR +3.3V_TBT_S0
1U_0201_10V6M
47U_0603_6.3V6M
47U_0603_6.3V6M
CT67
PJP5 1 1 JUMP@
1
2 1 H9 G1
CT68
CT69
2 1 PJP6 VCC0P9_SVR_PAB_ANA1 VCC3P3_SVR1 input
Output H11 G2
JUMP_43X79 1 2 H12 VCC0P9_SVR_PAB_ANA2 VCC3P3_SVR2 H2
2
2 2 H13 VCC0P9_SVR_PAB_ANA3 VCC3P3_SVR3 E6
PAD-OPEN1x1m H15 VCC0P9_SVR_PAB_ANA4 VCC3P3A
VCC0P9_SVR_PAB_ANA5
Vinafix.com
H16 L6
VCC0P9_SVR_PAB_ANA6 VCC3P3_S0
DT62 @ RT542 T12 F18 +3.3V_TBT_SX
RB520SM-30T2R_EMD2-2 UT7 0_0805_5% T13 VCC0P9_SVR_PC_ANA1 VCC3P3_SX1 R6 input
2 1 LDO_IN 1 5 1 2 T15 VCC0P9_SVR_PC_ANA2 VCC3P3_SX2 +0.9V_TBT_SVR
D +20V_TBTA_VBUS VCC VOUT +3.3V_VDD_PICP VCC0P9_SVR_PC_ANA3 J13
D
2 change footprint from 0402 to 0805 T9 VCC0P9_SVR1 L11

Use RB520SM Vf=0.51V@200mA, for 5V input GND T11 VCC0P9_SVR_USB_ANA1 VCC0P9_SVR2 L13 Output
1U_0201_10V6M
CT374 1 VCC0P9_SVR_USB_ANA2 VCC0P9_SVR3
DT60 3 4 M8
NC EN +0.9V_TBT_PCIE N6 VCC0P9_SVR4 M11
CT372
RB520SM-30T2R_EMD2-2 1000P_0402_50V7K
2 1 1 2 VCC0P9_SVR_DPAUX_ANA VCC0P9_SVR5 M13
+20V_TBTB_VBUS RT9069-33GB_SOT23-5 2 J18 VCC0P9_SVR6 N8
change to 1000pF for solving L19 VCC0P9_PCIE VCC0P9_SVR7 N11
high pulse when AC plug in to M19 VCC0P9_ANA_PCIE_1_1 VCC0P9_SVR8 N13
DT63 system 4/3 RT543 L18 VCC0P9_ANA_PCIE_1_2 VCC0P9_SVR9 R8
RB520SM-30T2R_EMD2-2 300K_0402_5% M16 VCC0P9_ANA_PCIE_2_1 VCC0P9_SVR10 R11
2 1 1 2 M18 VCC0P9_ANA_PCIE_2_2 VCC0P9_SVR11 R13
+19.5V_DC_IN +0.9V_TBT_LC VCC0P9_ANA_PCIE_2_3 VCC0P9_SVR12 R16
DT63,DT64 for keeping +3.3V_VDD_PIC stable VCC0P9_SVR13 T8
VCC0P9_SVR14
1
QT10 DT64 under abnormal haywire circumstance between J8 T16 +TBT_SVR_IND
1U_0201_10V6M
1 VCC0P9_LC VCC0P9_SVR15
300K_0402_5%
RB520SM-30T2R_EMD2-2 +TBTA_VBUS and 19V power source. +0.9V_TBT_LVR_OUT E8
RT544
VCC0P9_SVR_BRD_SENSE
1
3 1 (LPS_OFF must keep low when haywire happened) D
S
1 2 H8
CT373
VCC
+19.5VB 2 H6 VCC0P9_LVR K1
follow naming rule EMB80P03JS_SOT-23-3 2 G ALW_PWRGD_3V_5V <18,43,62,86> VCC0P9_LVR_SENSE SVR_IND1 K2
2
L2N7002WT1G_SC-70-3 SVR_IND2 L1
G
S
2
3
Change CPN from @ QT1 H18 SVR_IND3 L2
SB000016O00 to L16 VCC3P3_ANA_USB2 SVR_IND4
SB00001GQ00 3/12 change SB00000UO00 to SB000009Q80/ E16 VCC3P3_ANA_PCIE H1
SB00000ST00 as main source, +3.3V_TBT_ANA VCC3P3_ANA SVR_VSS1 J1
<85> LPS_OFF_BATT_R SB00000UO00 as 3rd source +3.3V_TBT_ANA_PCIE +3.3V_TBT_LC V6 SVR_VSS2 J2
Normal S5 on DC mode , LPS_OFF_BATT_R = +PWR_SRC, and PMOS open,so without +3.3V_VDD_PIC +3.3V_TBT_ANA_USB2 VCC3P3_LC SVR_VSS3
Output
single fault S5 on DC mode , LPS_OFF_BATT=0, LPS_OFF_BATT_R = +PWR_SRC/2 ,PMOS close ,so +3.3V_VDD_PIC can latch
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
QT2
10K_0402_5%
+3.3V_VDD_PICP S TR AO7401 1P SC70-3
2
1 1 1 1 A6 AB18
Pin H18
Pin L16
Pin E16
1 3 A8 VSS_ANA1 VSS_ANA67 AB20
CT300
CT301
RT554
CT302
CT303
D
Pin V6
A10 VSS_ANA2 VSS_ANA68 AB22
RT545 A12 VSS_ANA3 VSS_ANA69 AC6
1M_0402_1% 2 2 2 2 A14 VSS_ANA4 VSS_ANA70 AC8
G
2
1
1 2 A16 VSS_ANA5 VSS_ANA71 AC10
A18 VSS_ANA6 VSS_ANA72 AC12
10K_0402_1%
VSS_ANA7 VSS_ANA73
1
C A20 AC14 C
CT375
0.01U_0402_16V7K A22 VSS_ANA8 VSS_ANA74 AC16
RT546
1 2 B6 VSS_ANA9 VSS_ANA75 AC18

B8 VSS_ANA10 VSS_ANA76 AC20
B10 VSS_ANA11 VSS_ANA77 AC22
QT3
2
@ RT547 B12 VSS_ANA12 VSS_ANA78 E4

S TR AO7401 1P SC70-3 VSS_ANA13 VSS_ANA79
0_0805_5% B14 F5
+3.3V_ALW 1 3 1 2 +3.3V_VDD_PIC B16 VSS_ANA14 VSS_ANA80 J12
D
B18 VSS_ANA15 VSS_ANA81 F6

change footprint from 0402 to 0805 B20 VSS_ANA16 VSS_ANA82 J15
RT548 B22 VSS_ANA17 VSS_ANA83 B2
G
2
VSS_ANA18 VSS_ANA84
6
D 100K_0402_1% D8 B1
QT4A 2 1 2 D9 VSS_ANA19 VSS_ANA85 D1
G D11 VSS_ANA20 VSS_ANA86 A2
2N7002KDW_SOT363-6 VSS_ANA21 VSS_ANA87
D12 J16
VSS_ANA22 VSS_ANA88
1
S D13 V13
1
@ RT549 D15 VSS_ANA23 VSS_ANA89 V12

D16 VSS_ANA24 VSS_ANA90 V11
0_0402_5% VSS_ANA25 VSS_ANA91
D18 M6
GND
E9 VSS_ANA26 VSS_ANA92 U23
3 2
E11 VSS_ANA27 VSS_ANA93 U22

D QT4B E15 VSS_ANA28 VSS_ANA94 T20
<18,43,62,86> ALW_PWRGD_3V_5V 1 2 5 2N7002KDW_SOT363-6 H20 VSS_ANA29 VSS_ANA95 R23
G E22 VSS_ANA30 VSS_ANA96 R22
@ RT550 E23 VSS_ANA31 VSS_ANA97 R20
0.1U_0201_25V6K
0_0402_5% S F9 VSS_ANA32 VSS_ANA98 R19

4
VSS_ANA33 VSS_ANA99
1
F16 R18
CT376
F20 VSS_ANA34 VSS_ANA100 W11

G22 VSS_ANA35 VSS_ANA101 Y11
2
G23 VSS_ANA36 VSS_ANA102 C23

L20 VSS_ANA37 VSS_ANA103 F15
L22 VSS_ANA38 VSS_ANA104 V9
+0.9V_TBT_SVR +0.9V_TBT_LVR_OUT L23 VSS_ANA39 VSS_ANA105 V15
J19 VSS_ANA40 VSS_ANA106 V20
SVR_VSS:Minimum of 4 vias must be used. VSS_ANA41 VSS_ANA107
J20 W8
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
B J22 VSS_ANA42 VSS_ANA108 W9 B
1U_0201_6.3V6M
J23 VSS_ANA43 VSS_ANA109 W22
1 1 1 1 1 1 1 1 1 1 1
Pin E8
Pin H6
Pin H8
Pin H11
Pin H13
Pin H16
Pin J13
Pin L11
Pin M11
M20 VSS_ANA44 VSS_ANA110 W23

CT305
CT306
CT307
CT308
CT309
CT310
CT311
CT329
CT330
CT331
CT332
N20 VSS_ANA45 VSS_ANA111 Y9
N22 VSS_ANA46 VSS_ANA112 Y13
2 2 2 2 2 2 2 2 2 2 2 N23 VSS_ANA47 VSS_ANA113 AA22
C22 VSS_ANA48 VSS_ANA114 AA23
E18 VSS_ANA49 VSS_ANA115 AB6
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
W13 VSS_ANA50 VSS_ANA116 AB8

AB2 VSS_ANA51 VSS_ANA117 AB10
1 1 1 1 1 1 1
Pin N6
Pin R8
Pin T8
Pin N11
Pin R16
Pin T13
Pin T16
A4 VSS_ANA52 VSS_ANA118 AB12

CT316
CT317
CT318
CT319
CT320
CT321
CT322
B4 VSS_ANA53 VSS_ANA119 AB14

+0.9V_TBT_SVR Y8 VSS_ANA54 VSS_ANA120 AB16
2 2 2 2 2 2 2 F2 VSS_ANA55 VSS_ANA121 N19
D2 VSS_ANA56 VSS_ANA122 N18
F1 VSS_ANA57 VSS_ANA123 F8
AC4 VSS_ANA58 VSS_ANA124 F13
AB4 VSS_ANA59 VSS_ANA125 F12
+0.9V_TBT_PCIE Y5 VSS_ANA60 VSS_ANA126 F11
+3.3V_TBT_S0 Y12 VSS_ANA61 VSS_ANA127 E13
W12 VSS_ANA62 VSS_ANA128 E12
D6 VSS_ANA63 VSS_ANA129 W15
10U_0402_6.3V6M
AB1 VSS_ANA64 VSS_ANA130 Y15

1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
AC2 VSS_ANA65 VSS_ANA131

CT323
CT324
CT325
CT326
1 1 1 1 1 1 1 VSS_ANA66
CT327
CT328
CT337
1 1 1 1
Pin E6
Pin L6
Pin L19
Pin M19
Pin L18
Pin M16
CT338
CT339
CT340
CT341
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
2 2 2 2 2 2 2
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
2 2 2 2
Share same GND plane
M15
V16
L12
R15
R9
R12
L9
M9
F4
V18
L15
N15
M1
M2
N12
T6
T18
N9
M12
A A
+TBT_SVR_IND THUNDERBOLT_BGA337
+0.9V_TBT_SVR
VCC0P9_SVR:0.9V @ 1.8A max +0.9V_TBT_LC +3.3V_TBT_SX
Minimum of 4vias must be used
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
LT101 2
1 1 1
47U_0603_6.3V6M
47U_0603_6.3V6M
47U_0603_6.3V6M
Pin J8
CT334
CT335
CT336
CT333
CT314
CT315
0.6UH_MND-04ABIR60M-XGL_20% 1 1 1
Pin R6
Pin F18
2 2 2
Title
2 2 2 Issued Date 2016/01/01 Deciphered Date 2017/01/01
TBT-TR(2/2) PWR,VSS
Custom 1.0
5 4 3 2 1
5 4 3 2 1
follow naming rule
+20V_TBTA_VBUS +20V_TBTB_VBUS
1
100_0603_5%
100_0603_5%
+5V_ALW +VDD_SUPPLY
RT565
RT566
follow naming rule
1U_0201_6.3V6M
1U_0201_6.3V6M
1 2
1 2
+VDD_SUPPLY UT5 +20V_TBTA_VBUS +20V_TBTB_VBUS
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
D D
1 1 1 1 1
CCG5_VBUS_DISCHARGE_P1 2 CCG5_VBUS_DISCHARGE_P2 2 D10 D1
CT342
CT343
CT344
CT345
CT346
QT6 QT7 input
L2N7002W T1G_SC-70-3 L2N7002W T1G_SC-70-3 VDDD VBUS_P1
G G 3.3V Output
S S C10 L3
Vinafix.com
3
3
2 2 2 2 2 VDD_IO VBUS_P2
100K_0201_5%
100K_0201_5%
1
1
CT348 1U_0201_10V6M +3.3V_ALW
+5V_ALW +5V_ALW 1 2 B10 input
RT567 VCCD A5 +Vsys 1 2
RT568
J2 VSYS @ RT512 0_0603_5%
D V5V_P1 D
input
2
2
L9 1 2 +Vsys
V5V_P2 +3.3V_VDD_PIC
J1 RT569 0_0603_5%
CSP_P1
1U_0201_6.3V6M
+3.3V_ALW CCG5_XRES1 H6 L2
0.1U_0201_10V6K
<42> CCG5_AR_RST# XRES CSP_P2
1 1
CT347
CT349
CCG5_SW D_IO1 B2 B3
SWD_IO/AR_RST# /GPIO_B2 CSN_P1
2
2.2K_0402_5%
2.2K_0402_5%
2.2K_0402_5%
2.2K_0402_5%
2 2
RT510
RT514
RT511
RT515
CCG5_SW D_CLK1 C2 K8
SWD_CLK/I2C_CFG_EC/GPIO_C2 CSN_P2
I2C_SLAVE TO COMMUNICATE
WITH TR
1
3/3: follow Cypress suggest <42> TBT_I2C_SDA
D2 H4
I2C_SDA_SCB2_AR/GPIO_D2 NC1 H5
E2 NC2 H8 +3.3V_ALW
+VDD_SUPPLY <42> TBT_I2C_SCL I2C_SCL_SCB2_AR/GPIO_E2 NC3 G8
F2 NC4
<42> TBTA_I2C_INT# I2C_INT_AR_P1/GPIO_F2
G2 L4 MOD_ID2
<42> TBTB_I2C_INT# I2C_INT_AR_P2/GPIO_G2 VSEL_1_P2 / GPIO_L4 H10 CCG5_VBUS_DISCHARGE_P2 TBTA_DPSRC_AUX_N_C @ RT516 1 2 100K_0201_5%
RT517 1 2 10K_0201_5% CCG5_VBUS_5V_ON1# VSEL_2_P2 / GPIO_H10 B6
UV_OCP_TRIP_P1 / GPIO_B6
Pull up at EC side
CCG5_I2C_INT1# L5 B7 TBTB_DPSRC_AUX_N_C @ RT518 1 2 100K_0201_5%
CCG5_VBUS_5V_ON2# <58> CCG5_I2C_INT1# I2C_INT_EC/GPIO_L5 UV_OCP_TRIP_P2 / GPIO_B7
RT519 1 2 10K_0201_5% B8 @ RT589 1 2 0_0201_5% CCG5_ILIM1#
CCG5_SMBDAT K6 VCON_OCP_TRIP_P1 / GPIO_B8 B9 @ RT590 1 2 0_0201_5% CCG5_ILIM2#
VBUS_C_CTRL_P1# <58> CCG5_SMBDAT I2C_SDA_SCB1_EC/GPIO_K6 VCON_OCP_TRIP_P2 / GPIO_B9
RT521 1 2 10K_0201_5% G10
CCG5_SMBCLK L6 SDA_4/GPIO_G10 F10
RT522 1 2 10K_0201_5% VBUS_C_CTRL_P2# <58> CCG5_SMBCLK I2C_SCL_SCB1_EC/GPIO_L6 SCL_4/GPIO_F10 L7 FRS_ON_P1
GPIO_L7 TBTA_DPSRC_AUX_P_C @ RT523 1 2 100K_0201_5%
I2C_SLAVE TO COMMUNICATE
WITH EMBEDDED CONTROLLER TBTB_DPSRC_AUX_P_C @ RT524 1 2 100K_0201_5%
FRS_ON_P2 L8 K5
OVP_TRIP_P2 / GPIO_L8 OVP_TRIP_P1 / GPIO_K5 FRS_ON_P1 RT617 1 2 100K_0201_5%
RT525 1 2 4.7K_0402_5% CCG5_XRES1 MOD_ID1 L10 J10 CCG5_VBUS_DISCHARGE_P1
+VDD_SUPPLY SCL_3 / VSEL_1_P1 /GPIO_L10 SDA_3 / VSEL_2_P1 / GPIO_J10 FRS_ON_P2 RT618 1 2 100K_0201_5%
CT350 1 2 0.1U_0201_10V6K FRS_ON_P1 and FRS_ON_P2 have a spike to

turn on 5V VBUS when CCG5 get power.
RT617,RT618 change to pop
CCG5_VBUS_5V_ON2# B4 K3 CCG5_VBUS_5V_ON1#
<84> CCG5_VBUS_5V_ON2# VBUS_P_CTRL_P2/ P4_2 VBUS_P_CTRL_P1 CCG5_VBUS_5V_ON1# <84>
C VBUS_C_CTRL_P2# VBUS_C_CTRL_P1# C
B5 K4
<82,83> VBUS_C_CTRL_P2# VBUS_C_CTRL_P2/ P4_1 VBUS_C_CTRL_P1 VBUS_C_CTRL_P1# <82,83>
(0 - VBUS Path on, Z- VBUS (0 - VBUS Path on, Z- VBUS
Path off) Path off)
To configure CCG5 I2C address
<45> TBTB_CC1
K9 K2 TBTA_CC1 <45>
1 2 CC1_P2 CC1_P1 1 2
RT526 2 @ 1 1K_0402_5% CCG5_SW D_CLK1 CT351 390P_0402_50V7K CT352 390P_0402_50V7K
+VDD_SUPPLY
<45> TBTB_CC2 K10 H2 TBTA_CC2 <45>
1 2 CC2_P2 CC2_P1 1 2
RT527 2 1 1K_0402_5% CT353 390P_0402_50V7K CT354 390P_0402_50V7K
+3.3V_ALW RT528 1 @ 2 10K_0201_5% @ RT529 2 1 10K_0402_5% +3.3V_ALW
To configure CCG5 I2C address E10 K7
Don't mount RT526 and RT527 for the I2C <42> TBTB_HPD HPD_P2/GPIO_E10 HPD_P1/GPIO_K7 TBTA_HPD <42>
address 0x08. This is the default one. change C to R 1/15 change C to R 1/15
Mount RT527 for the I2C address 0x40. @ RT608 1 2 0_0201_5% K11 A10 @ RT606 1 2 0_0201_5%
Mount RT526 for the I2C address 0x42. LSTX_P2/GPIO_K11 LSTX_P1/GPIO_A10
@ RT609 1 2 0_0201_5% L11 A11 @ RT607 1 2 0_0201_5%
@ RT385 1 2 0_0201_5% TBTB_DPSRC_AUX_P_C LSRX_P2/GPIO_L11 LSRX_P1/GPIO_A11 TBTA_DPSRC_AUX_P_C @ RT387 1 2 0_0201_5%
<42> TBT_B_SBU1 TBT_A_SBU1 <42>
D11 B11
@ RT386 1 2 0_0201_5% TBTB_DPSRC_AUX_N_C E11 AUX_P_P2/GPIO_D11 AUX_P_P1/GPIO_B11 C11 TBTA_DPSRC_AUX_N_C @ RT388 1 2 0_0201_5%
<42> TBT_B_SBU2 AUX_N_P2/GPIO_E11 AUX_N_P1/GPIO_C11 TBT_A_SBU2 <42>
TBTB_SBU1 E1 A3 TBTA_SBU1
<45> TBTB_SBU1 TBTB_SBU2 SBU1_P2 SBU1_P1 TBTA_SBU2 TBTA_SBU1 <45>
F1 A4
TBT PORT B
<45> TBTB_SBU2 SBU2_P2 SBU2_P1 TBTA_SBU2 <45>

CCG5 debug CCG5_SMBCLK @ RT582 1 2 0_0201_5% @ RT580 1 2 0_0201_5% CCG5_SMBCLK
TBT PORT A
AMI still suggest us to reserve it for source level debug. CCG5_SMBDAT @ RT581 1 2 0_0201_5% H11 A8 @ RT579 1 2 0_0201_5% CCG5_SMBDAT
@ RT555 1 2 0_0201_5% J11 UART_TX_P2/GPIO_H11 UART_TX_P1/GPIO_A8 A9 @ RT559 1 2 0_0201_5%
<15> USB20_P5 UART_RX_P2/GPIO_J11 UART_RX_P1/GPIO_A9 USB20_P4 <15>
JCCG1 <15> USB20_N5 @ RT556 1 2 0_0201_5% @ RT560 1 2 0_0201_5% USB20_N4 <15>
1 @ RT557 1 2 0_0201_5% TBT_B_USB20P F11 A6 TBT_A_USB20P @ RT561 1 2 0_0201_5%
1 CCG5_XRES1 +VDD_SUPPLY <42> USB20_PB TBT_B_USB20N D+_SYS_P2 D+_SYS_P1 TBT_A_USB20N USB20_PA <42>
2 @ RT558 1 2 0_0201_5% G11 A7 @ RT562 1 2 0_0201_5%
2 CCG5_SW D_CLK1 <42> USB20_NB D-_SYS_P2 D-_SYS_P1 USB20_NA <42>
3
3 4 CCG5_SW D_IO1 K1 B1
4 CCG5_SMBDAT <45> SW _TBT_B_USB20_P2 D+_B_P2 D+_B_P1 SW _TBT_A_USB20_P2 <45>
5 L1 C1
5 CCG5_SMBCLK <45> SW _TBT_B_USB20_N2 D-_B_P2 D-_B_P1 SW _TBT_A_USB20_N2 <45>
6 G1 A1
6 <45> SW _TBT_B_USB20_P1 D+_T_P2 D+_T_P1 SW _TBT_A_USB20_P1 <45>
7 H1 A2
7 +5V_ALW <45> SW _TBT_B_USB20_N1 D-_T_P2 D-_T_P1 SW _TBT_A_USB20_N1 <45>
8 UART2TXD @ RT551 1 2 0_0201_5%
8 UART2_TXD <19>
9 UART2RXD @ RT552 1 2 0_0201_5%
9 UART2_RXD <19>
10 D5 H7
10 D6 GND1 GND19 G7
D7 GND2 GND18 G6
11 D8 GND3 GND17 G5
GND1 12 E4 GND4 CSP_GND_P2 G4
B B
GND2 E5 GND5 CSP_GND_P1 F8
E6 GND6 GND14 F7
E7 GND7 GND13 F6
ACES_50521-01041-P01 E8 GND8 GND12 F5
GND9 GND11 F4
CONN@ GND10
Type-C port1 USB2 Power Share

+5V_ALW
+3.3V_VDD_PIC CT370 @ CYPD5225-96BZXI_BGA96_6X6
2 1
+5V_VBUS1 UT9
13 1 0.1U_0201_10V6K
OUT IN
5
UT10 RILIM ILIM(A)

1 USB_POW ERSHARE_VBUS_EN# +5V_ALW CCG5_ILIM1#
ILIM(A)=100/RILIM
G Vcc
51K_0201_1% 1 2 RT571 12 2 4 B (Kohm)

VLIM EN Y 2 CCG5_VBUS_5V_ON1#
Min Typ Max CCG5_ILIM2#
USB_ILIM1 11 3 FRS_ON1_R A
ILIM FRS 74AUP1G02GW _TSSOP5 56 1.785 LOW MOD_ID1=L7,MOD_ID2=L4, the Dedicated ID for Whitehaven DVT TR+CCG5.
10U_0603_10V6M
1U_0201_10V6M
1 1
3
2
1000P_0201_25V7K 1 2 CT378 10 6 3.326 HIGH

DV/DT DISC1 7 +3.3V_VDD_PIC 30.06
CT356
@ RT570
100K_0201_5% 1 2 RT573 9 DISC2 +VDD_SUPPLY +VDD_SUPPLY
CT355
0_0402_5%
IMON 5 2 2 USB_ILIM2 USB_ILIM1
VREG 1
1
@ RT564
100K_0402_5%
8
<15> USB_OC4#
1
FAULTB CT377 FRS_ON_P1
1
14 4
64.9K_0402_1%
64.9K_0402_1%
SRC GND
1
1 2 2
0.1U_0201_10V6K RT535
RT586
RT588
CT383 0.1U_0201_10V6K DPS1113FIA-13_QFN18_4X4 RT534 13.3K_0402_1%
2
1.3K_0402_1%
L7 =2.887V L4 =1.650V
56K_0402_1%
2
USB_POW ERSHARE_VBUS_EN# MOD_ID1 MOD_ID2
RT587
Type-C port2 USB2 Power Share
2
2
1
CCG5_ILIM2# CCG5_ILIM1#
56K_0402_1%
1
+3.3V_VDD_PIC
RT585
CT371 @
+5V_ALW 2 1 RT536 RT537
100K_0201_5%
100K_0201_5%
2
1
2
+5V_VBUS2 UT11 D QT8 D QT9 13.3K_0402_1%
RT583
RT584
9.1K_0402_1%
1
13 1 0.1U_0201_10V6K D From EC 2 2
2
OUT IN +5V_ALW 2 G G
USB_POW ERSHARE_VBUS_EN <58,71>
2
5
UT12 G S S
3
3
1 USB_POW ERSHARE_VBUS_EN# S L2N7002W T1G_SC-70-3 L2N7002W T1G_SC-70-3
G Vcc
1
51K_0201_1% 1 2 RT575 12 2 4 B @ QT5 L2N7002W T1G_SC-70-3
VLIM EN Y 2 CCG5_VBUS_5V_ON2#
10U_0603_10V6M
1U_0201_10V6M
A 1 1
A USB_ILIM2 11 3 FRS_ON2_R change SB00000UO00 to SB000009Q80/ Resistor values for MOD_ID settings A
ILIM FRS SB00000ST00 as main source, are decides based on the table shown
CT358
74AUP1G02GW _TSSOP5
3
2
1000P_0201_25V7K 1 2 CT38010 6 SB00000UO00 as 3rd source

CT357
DV/DT DISC1
2
7 @ RT574 2 2
100K_0201_5% 1 2 RT577 9 DISC2 0_0402_5% RT610
IMON 5 1 10K_0201_5%
8 VREG
<15> USB_OC5#
1
FAULTB CT379 FRS_ON_P2

1
14 4
1 2 SRC GND 2
0.1U_0201_10V6K
CT384 0.1U_0201_10V6K DPS1113FIA-13_QFN18_4X4
Issued Date 2017/04/07 Deciphered Date 2018/12/31 Title
P044 - TYPE-C_Port1 (1/2) PD
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-H281P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5 4 3 2 1
5 4 3 2 1
follow naming rule
+20V_TBTA_VBUS +20V_TBTA_VBUS
ESD@ DT5 AZ5B75-01B.R7G_CSP0603P2Y2 ESD@ DT13 AZ5B75-01B.R7G_CSP0603P2Y2
Change part number / foorprint TBT_A_TTX_C_DRX_P1 1 2 TBT_A_TRX_DTX_P1 1 2

JUSBC1A
11 3
5 NPTH1 GND9 2 ESD@ DT6 AZ5B75-01B.R7G_CSP0603P2Y2 ESD@ DT14 AZ5B75-01B.R7G_CSP0603P2Y2
4 GND7 GND8 1
GND5 GND6 TBT_A_TTX_C_DRX_N1 1 2 TBT_A_TRX_DTX_N1 1 2
B1 A12
Bottom
1 2 TBT_A_TTX_C_DRX_P1 B2 GND3 GND4 A11 TBT_A_TRX_DTX_P1
Vinafix.com
<42> TBT_A_TTX_DRX_P1 TBT_A_TTX_C_DRX_N1 SSTXp2 SSRXp2 TBT_A_TRX_DTX_N1 TBT_A_TRX_DTX_P1 <42>
CT95 1 2 0.22U_0201_6.3V6K B3 A10
<42> TBT_A_TTX_DRX_N1 SSTXn2 SSRXn2 TBT_A_TRX_DTX_N1 <42>
TOP
CT96 0.22U_0201_6.3V6K B4 A9 ESD@ DT9 AZ5B75-01B.R7G_CSP0603P2Y2 ESD@ DT17 AZ5B75-01B.R7G_CSP0603P2Y2
2 1 B5 VBUS3 VBUS4 A8 1 2
CT91 0.47U_0201_25V6M B6 CC2 SBU1 A7 CT101 0.47U_0201_25V6M TBT_A_TRX_DTX_N2 1 2 TBT_A_TTX_C_DRX_P2 1 2
TBTA_CC1 B7 Dp2 Dn1 A6 TBTA_SBU2
D <44> TBTA_CC1 Dn2 Dp1 TBTA_SBU2 <44> D
B8 A5 @EMI@RT122
@EMI@RT120 1 2 0_0402_5% SW _TBT_A_USB20_P1_R B9 SBU2 CC1 A4 SW _TBT_A_USB20_N2_R 1 2 0_0402_5%
<44> SW _TBT_A_USB20_P1 VBUS1 VBUS2 SW _TBT_A_USB20_N2 <44>
<44> SW _TBT_A_USB20_N1
@EMI@RT121 1 2 0_0402_5% SW _TBT_A_USB20_N1_R B10 A3 SW _TBT_A_USB20_P2_R 1 2 0_0402_5% SW _TBT_A_USB20_P2 <44> ESD@ DT10 AZ5B75-01B.R7G_CSP0603P2Y2 ESD@ DT18 AZ5B75-01B.R7G_CSP0603P2Y2
B11 SSRXn1 SSTXn1 A2 @EMI@RT123
TBTA_SBU1 B12 SSRXp1 SSTXp1 A1 TBTA_CC2 TBT_A_TRX_DTX_P2 1 2 TBT_A_TTX_C_DRX_N2 1 2
<44> TBTA_SBU1 GND1 GND2 TBTA_CC2 <44>
2 1
CT109 0.47U_0201_25V6M 1 2
TBT_A_TRX_DTX_N2 FOX_UT12113-1160D-7H~D CT102 0.47U_0201_25V6M
<42> TBT_A_TRX_DTX_N2 TBT_A_TRX_DTX_P2 CONN@ TBT_A_TTX_C_DRX_N2 2 1
<42> TBT_A_TRX_DTX_P2 TBT_A_TTX_C_DRX_P2 TBT_A_TTX_DRX_N2 <42>
0.22U_0201_6.3V6K 2 1 CT98
TBT_A_TTX_DRX_P2 <42>
0.22U_0201_6.3V6K CT97
ESD@ DT7 ESD@ DT8

TBTA_CC1 9 10 1 TBTA_CC1 TBTA_SBU2 9 10 1 TBTA_SBU2
RF Request
follow naming rule
1 1
SW _TBT_A_USB20_P1_R 8 9 2 2 SW _TBT_A_USB20_P1_R SW _TBT_A_USB20_N2_R 8 9 2 2 SW _TBT_A_USB20_N2_R
+20V_TBTA_VBUS +20V_TBTA_VBUS
SW _TBT_A_USB20_N1_R 7 7 4 4 SW _TBT_A_USB20_N1_R SW _TBT_A_USB20_P2_R 7 7 4 4 SW _TBT_A_USB20_P2_R
TBTA_SBU1 6 6 5 5 TBTA_SBU1 TBTA_CC2 6 6 5 5 TBTA_CC2
3 3 3 3
8 8
AZ4024_02S_R7G_SOT23-3
3
2
12P_0402_50V8J
RF@ CT189
82P_0402_50V8J
RF@ CT190
1 1
ESD@ DT4
AZ1045-04F_DFN2510P10E-10-9 AZ1045-04F_DFN2510P10E-10-9
2 2
1
C C
follow naming rule ESD@ DT43 AZ5B75-01B.R7G_CSP0603P2Y2 ESD@ DT44 AZ5B75-01B.R7G_CSP0603P2Y2
+20V_TBTB_VBUS +20V_TBTB_VBUS TBT_B_TTX_C_DRX_P1 1 2 TBT_B_TRX_DTX_P1 1 2
ESD@ DT48 AZ5B75-01B.R7G_CSP0603P2Y2 ESD@ DT45 AZ5B75-01B.R7G_CSP0603P2Y2
Change part number / foorprint TBT_B_TTX_C_DRX_N1 1 2 TBT_B_TRX_DTX_N1 1 2

JUSBC1B
12 8
10 NPTH1 GND9 7 ESD@ DT51 AZ5B75-01B.R7G_CSP0603P2Y2 ESD@ DT52 AZ5B75-01B.R7G_CSP0603P2Y2
9 GND7 GND8 6
GND5 GND6 TBT_B_TRX_DTX_N2 1 2 TBT_B_TTX_C_DRX_P2 1 2
1B1 1A12
Bottom
1 2 TBT_B_TTX_C_DRX_P1 1B2 GND3 GND4 1A11 TBT_B_TRX_DTX_P1

<42> TBT_B_TTX_DRX_P1 TBT_B_TTX_C_DRX_N1 SSTXp2 SSRXp2 TBT_B_TRX_DTX_N1 TBT_B_TRX_DTX_P1 <42>
CT359 1 2 0.22U_0201_6.3V6K 1B3 1A10
<42> TBT_B_TTX_DRX_N1 SSTXn2 SSRXn2 TBT_B_TRX_DTX_N1 <42>
TOP
CT360 0.22U_0201_6.3V6K 1B4 1A9 ESD@ DT53 AZ5B75-01B.R7G_CSP0603P2Y2 ESD@ DT54 AZ5B75-01B.R7G_CSP0603P2Y2
2 1 1B5 VBUS3 VBUS4 1A8 1 2
CT361 0.47U_0201_25V6M 1B6 CC2 SBU1 1A7 CT362 0.47U_0201_25V6M TBT_B_TRX_DTX_P2 1 2 TBT_B_TTX_C_DRX_N2 1 2
TBTB_CC1 1B7 Dp2 Dn1 1A6 TBTB_SBU2
<44> TBTB_CC1 Dn2 Dp1 TBTB_SBU2 <44>
1B8 1A5 @EMI@
@EMI@RT538 1 2 0_0402_5% SW _TBT_B_USB20_P1_R 1B9 SBU2 CC1 1A4 SW _TBT_B_USB20_N2_R RT539 1 2 0_0402_5%
<44> SW _TBT_B_USB20_P1 VBUS1 VBUS2 SW _TBT_B_USB20_N2 <44>
@EMI@RT540 1 2 0_0402_5% SW _TBT_B_USB20_N1_R 1B10 1A3 SW _TBT_B_USB20_P2_R RT541 1 2 0_0402_5%
<44> SW _TBT_B_USB20_N1 SSRXn1 SSTXn1 SW _TBT_B_USB20_P2 <44>
1B11 1A2 @EMI@
TBTB_SBU1 1B12 SSRXp1 SSTXp1 1A1 TBTB_CC2
<44> TBTB_SBU1 GND1 GND2 TBTB_CC2 <44>
2 1 1 2
0.47U_0201_25V6M CT363 FOX_UT12113-1160D-7H~D CT364 0.47U_0201_25V6M
CONN@ TBT_B_TTX_C_DRX_N2 2 1
TBT_B_TRX_DTX_N2 TBT_B_TTX_C_DRX_P2 TBT_B_TTX_DRX_N2 <42>
0.22U_0201_6.3V6K 2 1 CT365
<42> TBT_B_TRX_DTX_N2 TBT_B_TRX_DTX_P2 TBT_B_TTX_DRX_P2 <42>
0.22U_0201_6.3V6K CT366
<42> TBT_B_TRX_DTX_P2
ESD@ DT11 ESD@ DT12

TBTB_CC1 9 10 1 1 TBTB_CC1 TBTB_SBU2 9 10 1 1 TBTB_SBU2
SW _TBT_B_USB20_P1_R 8 9 2 2 SW _TBT_B_USB20_P1_R SW _TBT_B_USB20_N2_R 8 9 2 2 SW _TBT_B_USB20_N2_R
B
SW _TBT_B_USB20_N1_R 7 7 4 4 SW _TBT_B_USB20_N1_R SW _TBT_B_USB20_P2_R 7 7 4 4 SW _TBT_B_USB20_P2_R B
TBTB_SBU1 6 6 5 5 TBTB_SBU1 TBTB_CC2 6 6 5 5 TBTB_CC2

RF Request
follow naming rule 3 3
3 3
+20V_TBTB_VBUS +20V_TBTB_VBUS 8 8
AZ1045-04F_DFN2510P10E-10-9 AZ1045-04F_DFN2510P10E-10-9
AZ4024_02S_R7G_SOT23-3
3
2
DT59
12P_0402_50V8J
RF@ CT367
82P_0402_50V8J
RF@ CT368
1 1 Add symbol for EE 1/24

ESD@
DT1 DT2 DT3 DT16

1
2 2
SW _TBT_A_USB20_P1 2 SW _TBT_A_USB20_P2 2 SW _TBT_B_USB20_P1 2 SW _TBT_B_USB20_P2 2
N1 N1 N1 N1
P 1 P 1 P 1 P 1
SW _TBT_A_USB20_N1 3 N2 SW _TBT_A_USB20_N2 3 N2 SW _TBT_B_USB20_N1 3 N2 SW _TBT_B_USB20_N2 3 N2
SDMP0340LAT-7-F_SOT-523-3 SDMP0340LAT-7-F_SOT-523-3 SDMP0340LAT-7-F_SOT-523-3 SDMP0340LAT-7-F_SOT-523-3
Material shortage change to SCS0000F800 1/15
DT2001 DT2003 DT2005 DT2007

TBTA_CC1 1 2 TBTA_CC2 1 2 TBTB_CC1 1 2 TBTB_CC2 1 2
SBR1A20T5-7_SOD523-2-2 SBR1A20T5-7_SOD523-2-2 SBR1A20T5-7_SOD523-2-2 SBR1A20T5-7_SOD523-2-2
DT2002 DT2004 DT2006 DT2008

TBTA_SBU1 1 2 TBTA_SBU2 1 2 TBTB_SBU1 1 2 TBTB_SBU2 1 2
A SBR1A20T5-7_SOD523-2-2 SBR1A20T5-7_SOD523-2-2 SBR1A20T5-7_SOD523-2-2 SBR1A20T5-7_SOD523-2-2 A
Title
TYPE-C_Port1 (2/2) CONN
Custom 1.0
5 4 3 2 1
5 4 3 2 1
Vinafix.com
D D
C C
Reserve
B B
A A
TYPE-C_Port2-1
5 4 3 2 1
5 4 3 2 1
Vinafix.com
D D
C C
Reserve
B B
A A
TYPE-C_Port2-2
5 4 3 2 1
5 4 3 2 1
Vinafix.com
D D
Reserve C
B B
A A
TYPE-C_Port3-1
5 4 3 2 1
5 4 3 2 1
Vinafix.com
D D
C C
Reserve
B B
A A
TYPE-C_Port3-2
5 4 3 2 1
5 4 3 2 1
Vinafix.com
D D
C C
Reserve
B B
A A
TYPE-C_PWR Path
5 4 3 2 1
5 4 3 2 1
+3.3V_LAN UL1 QL1A

change 15 to 0 ohm 1/15 2N7002KDW _SOT363-6
1 2 TP_LAN_JTAG_TMS 48 13 LAN_MDIP0 @ RL71 1 2 0_0402_5% LAN_ACTLED_YEL# 1 6 LAN_ACTLED_YEL#_Q
D
<16> CLKREQ_PCIE#3 CLK_REQ_N MDI_PLUS0 LAN_MDIP0_L <51>
S
@ RL1 10K_0402_5% 36 14 LAN_MDIN0 @ RL72 1 2 0_0402_5%
TP_LAN_JTAG_TCK <17> PLTRST_LAN# PE_RST_N MDI_MINUS0 LAN_MDIN0_L <51>
1 2
@ RL2 10K_0402_5% CLK_PCIE_P3 44 17 LAN_MDIP1 @ RL73 1 2 0_0402_5%
Vinafix.com
<16> CLK_PCIE_P3 CLK_PCIE_N3 PE_CLKP MDI_PLUS1 LAN_MDIN1 LAN_MDIP1_L <51>
45 18 @ RL74 1 2 0_0402_5%
<16> CLK_PCIE_N3 PE_CLKN MDI_MINUS1 LAN_MDIN1_L <51>
1 PCIE_PRX_C_DTX_P5 +3.3V_LAN
G
2
PCIE
MDI
2
CL1 0.1U_0201_10V6K 38 20 LAN_MDIP2 @ RL75 1 2 0_0402_5%
2 1 PCIE_PRX_C_DTX_N5 39 PETp MDI_PLUS2 21 LAN_MDIN2 @ RL76 1 2 0_0402_5% LAN_MDIP2_L <51> LED_MASK#
<15> PCIE_PRX_DTX_N5 PETn MDI_MINUS2 LAN_MDIN2_L <51> LED_MASK# <58,62>
1
CL2 0.1U_0201_10V6K
D 1 2 PCIE_PTX_C_DRX_P5 41 23 LAN_MDIP3 @ RL77 1 2 0_0402_5% RL29 D
+3.3V_LAN <15> PCIE_PTX_DRX_P5 PERp MDI_PLUS3 LAN_MDIN3 LAN_MDIP3_L <51>
CL5 0.1U_0201_10V6K 42 24 @ RL78 1 2 0_0402_5% 1M_0402_5%
PERn MDI_MINUS3 LAN_MDIN3_L <51>
1 2 PCIE_PTX_C_DRX_N5
<15> PCIE_PTX_DRX_N5 QL1B
CL6 0.1U_0201_10V6K @ RL3 1 2 0_0402_5%
2
2N7002KDW _SOT363-6
10K_0402_5%
28 6 VCT_LAN_R1 @ RL50 2 1 4.7K_0402_5%
<18,42> SML0_SMBCLK SMB_CLK SVR_EN_N +3.3V_LAN
1
31 LED_100_ORG# 4 3 LED_100_ORG#_Q
SMBUS
@
D
<18,42> SML0_SMBDATA SMB_DATA
S
+RSVD_VCC3P3_2
RL5
SMBus Device Address 0xC8 1 RL6 2 1 4.7K_0402_5%
RSVD1_VCC3P3
@ RL10 1 2 0_0402_5% 2 5
<18,58> LAN_W AKE# LAN_DISABLE#_R 3 LANWAKE_N VDD3P3_IN
2
LAN_DISABLE_N
G
4 +3.3V_LAN_OUT @ RL8 1 2 0_0603_5% +3.3V_LAN
5
VDD3P3_4
1U_0201_10V6M
@ RL7 1 2 0_0402_5% LAN_DISABLE#_R 15 LED_MASK#
<18> PM_LANPHY_ENABLE VDD3P3_15 1
LAN_ACTLED_YEL# 26 19
LED0 VDD3P3_19
CL7
LED_100_ORG# 27 29
LED1 VDD3P3_29
10K_0402_5%
LED_10_GRN# 25
LED
1
LED2 2
@ RL9
47
VDD0P9_47 +0.9V_LAN
46
1 TP_LAN_JTAG_TDI 32 VDD0P9_46 37 +3.3V_LAN
@ T73 PAD~D 1 TP_LAN_JTAG_TDO 34 JTAG_TDI VDD0P9_37 @ CL15
2
@ T74 PAD~D TP_LAN_JTAG_TMS 33 JTAG_TDO 43 1 2
JTAG
TP_LAN_JTAG_TCK 35 JTAG_TMS VDD0P9_43
JTAG_TCK 11 0.1U_0201_10V6K
VDD0P9_11
XTALO 9 40 UL2
5
XTALI 10 XTAL_OUT VDD0P9_40 22 SN74AHC1G08DCKR_SC70-5
XTAL_IN VDD0P9_22 16 LED_100_ORG# 1
P
VDD0P9_16 8 IN1 4
LAN_TEST_EN 30 VDD0P9_8 LED_10_GRN# 2 O LOM_CABLE_DETECT# <58>
TEST_EN IN2
G
XTALO_R RL34 1 2 0_0402_5% XTALO
RES_BIAS 12 7 +REGCTL_PNP10
3
RBIAS CTRL0P9
1K_0402_1%
3.01K_0402_1%
XTALI 49
VSS_EPAD
1
+3.3V_LAN
RL12
RL13
W GI219LM-SLKJ2-A0_QFN48_6X6~D
PN change to SA000081G1L
1
Y1
25MHZ_18PF_7V25000015 RL30
2
3 1 1M_0402_5% change SB00000UO00 to SB000009Q80/
OUT IN QL7 SB00000ST00 as main source,
L2N7002W T1G_SC-70-3 SB00000UO00 as 3rd source
27P_0402_50V8J
27P_0402_50V8J
4 2
2
C GND2GND1 +0.9V_LAN C
1 1
+0.9V_LAN +3.3V_LAN
CL13
CL14
LED_10_GRN# 3 1 LED_10_GRN#_Q
D
LL1
+REGCTL_PNP10 1 2
2 2 4.7UH_MPB201210T-4R7M-NA2_20%
G
2
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
22U_0603_6.3V6M
22U_0603_6.3V6M
10U_0402_6.3V6M
0.1U_0201_10V6K
Idc
0.1U_0201_10V6K
1 1 1 1 1 min=500mA 1 1
CL8
CL3
CL4
LED_MASK#
1 1
DCR=100m
CL12
CL9
CL10
CL11
CL28
CL280
2 2 2 2 2
ohm 2 2
2 2
Note: +1.0V_LAN will work at 0.95V to

1.15V Place C462, C463 and L29 close to
U31
+3.3V_LAN/+3.3V_LAN_LOM:20mils
+3.3V_LAN
B B
CONN@
JLOM1
TL1 LAN_ACTLED_YEL#_Q 1 2 A2
LAN_MDIP0_L 1 24 RJ45_MDIP0 RL14 150_0402_5% AMBER_LED-
<51> LAN_MDIP0_L TD1+ TX1+ A1
LAN_MDIN0_L 2 23 RJ45_MDIN0 AMBER_LED+
<51> LAN_MDIN0_L TD1- TX1- RJ45_MDIN3 8
+TRM_CT1 3 22 Z2805 PR4-
TDCT1 TXCT1 RJ45_MDIP3 7
+TRM_CT2 4 21 Z2807 PR4+
TDCT2 TXCT2
0.47U_0201_25V6M
0.47U_0201_25V6M
RJ45_MDIN1 6
LAN_MDIP1_L 5 20 RJ45_MDIP1 PR2-
<51> LAN_MDIP1_L TD2+ TX2+ RJ45_MDIN2
1 1 5
PR3-
CL16
CL17
LAN_MDIN1_L 6 19 RJ45_MDIN1
<51> LAN_MDIN1_L TD2- TX2- RJ45_MDIP2 4
LAN_MDIP2_L 7 18 RJ45_MDIP2 PR3+
2 2 <51> LAN_MDIP2_L TD3+ TX3+ RJ45_MDIP1 3
75_0402_1%
75_0402_1%
75_0402_1%
75_0402_1%
LAN_MDIN2_L 8 17 RJ45_MDIN2 PR2+

<51> LAN_MDIN2_L TD3- TX3- RJ45_MDIN0 2 10
+TRM_CT3 9 16 Z2806 PR1- GND1
TDCT3 TXCT3 RJ45_MDIP0 1 9
+TRM_CT4 10 15 Z2808 PR1+ GND2
TDCT4 TXCT4 LED_10_GRN#_Q
0.47U_0201_25V6M
1 2 B1
GREEN_LED-
0.47U_0201_25V6M
LAN_MDIP3_L 11 14 RJ45_MDIP3 RL19 150_0402_5%

<51> LAN_MDIP3_L TD4+ TX4+
1
1 1 B3
LAN_MDIN3_L 12 13 RJ45_MDIN3 ORANGE_LED-
<51> LAN_MDIN3_L TD4- TX4-
CL20
CL21
LED_100_ORG#_Q 1 2 B2
RL20 150_0402_5% YELLOW_LED+
2 2 SANTA_130456-911
2
MHPC_NS692417
RL15
RL17
RL16
RL18
+3.3V_LAN
9/5
1 2 GND_CHASSIS
1U_0201_10V6M
0.1U_0201_10V6K
470P_0402_50V7K
EMI@ CL22
10P_1808_3KV8J 1 1 1
CL199
CL19
CL18
GND CHASSIS
2 2 2
A A
Close to JLOM1
Title
LAN / LAN SW
Custom 1.0
5 4 3 2 1
5 4 3 2 1
Reserve for CNVI

+1.8V_PRIM_PCH
@ RZ378
RF Request
WLAN/BT
100K_0402_5%
1 2
1
@RF@ RI49 0_0402_5%
+3.3V_ALW
NGFF slot_1 Key A L1
100K_0402_5%
@ RZ377
1 2 USB20_N14_R
2
<15> USB20_N14
1
CNV_RF_RESET#_R
+3.3V_WLAN
Vinafix.com
3
4 3 USB20_P14_R
JNGFF1 <15> USB20_P14
1 2 MCM1012B900F06BP_4P
2
USB20_P14_R 3 1 2 4 5
USB20_N14_R 5 3 4 6
D 7 5 6 1 2 @ QZ17B D
7 Reserve for CNVI @RF@ RI50 0_0402_5% Remove CNV_RF_RESET L2N7002DW 1T1G_SC88-6
4
6
@ RZ531 1 2 22_0402_5% CNV_RF_RESET#_R
Reserve for CNVI @ RZ532 1 2 22_0402_5% CLKREQ_CNV_R
8 @ RZ533 1 2 22_0402_5%
8 CNV_BRI_PRX_DTX <14> CNV_RF_RESET# 2
@ RZ529 1 2 0_0201_5% 9 10 @ RZ534 1 2 22_0402_5%
<14> CNV_PRX_DTX_N1 9 10 CNV_RGI_PTX_DRX <14> <18> CNV_RF_RESET#
@ RZ530 1 2 0_0201_5% 11 12 @ RZ535 1 2 22_0402_5%
<14> CNV_PRX_DTX_P1 11 12 CNV_RGI_PRX_DTX <14>
13 14 @ RZ536 1 2 22_0402_5% 75K PD at PCH side
13 14 CNV_BRI_PTX_DRX <14>
@ RZ527 1 2 0_0201_5% 15 16
1
<14> CNV_PRX_DTX_N0 @ RZ528 1 2 0_0201_5% 17 15 16 18 @ QZ17A
<14> CNV_PRX_DTX_P0 19 17 18 20 L2N7002DW 1T1G_SC88-6 +1.8V_PRIM_PCH
@ RZ526 1 2 0_0201_5% 21 19 20 22
<14> CLK_CNV_PRX_DTX_N @ RZ525 1 2 0_0201_5% 23 21 22 24
@ RZ376
<14> CLK_CNV_PRX_DTX_P 23 24
1
10K_0402_5%
25 26
CZ12 1 2 0.1U_0201_25V6K PCIE_PTX_C_DRX_P7 27 25 26 28
<15> PCIE_PTX_DRX_P7 27 28
CZ13 1 2 0.1U_0201_25V6K PCIE_PTX_C_DRX_N7 29 30
<15> PCIE_PTX_DRX_N7 29 30 PCH_CL_RST1# <14> +3.3V_ALW
31 32
31 32 PCH_CL_DATA1 <14>
33 34
100K_0402_5%
@ RZ381
2
<15> PCIE_PRX_DTX_P7 33 34 W LAN_COEX3 PCH_CL_CLK1 <14>
35 36 DZ1 CLKREQ_CNV_R
<15> PCIE_PRX_DTX_N7 35 36
1
37 38 W LAN_COEX2 W LAN_W IGIG60GHZ_DIS#_R 2 1
WLAN <16> CLK_PCIE_P6
39 37 38 40 W LAN_COEX1 W LAN_W IGIG60GHZ_DIS# <58>
41 39 40 42 W IGIG_32KHZ RZ56 1 2 0_0402_5% RB751S-40_SOD523-2
<16> CLK_PCIE_N6 41 42 SUSCLK <18,52,67,68>
3
43 44 PCH_PLTRST#_AND
43 44 BT_RADIO_DIS#_R PCH_PLTRST#_R <17,42,67,68>
45 46 DZ2
2
<16> CLKREQ_PCIE#6 PCIE_W AKE# 45 46 WLAN_WIGIG60GHZ_DIS#_R BT_RADIO_DIS#_R
47 48 2 1
<27,42,59,67,68> PCIE_W AKE# 47 48 BT_RADIO_DIS# <58>
49 50 5
@ CZ539 1 2 0.1U_0201_25V6K CNV_PTX_C_DRX_N1 51 49 50 52 RB751S-40_SOD523-2
<14> CNV_PTX_DRX_N1 51 52
@ CZ538 1 2 0.1U_0201_25V6K CNV_PTX_C_DRX_P1 53 54 @ QZ18B
<14> CNV_PTX_DRX_P1 53 54
55 56 1 2 L2N7002DW 1T1G_SC88-6
4
55 56 REFCLK_CNV <16>
6
@ CZ537 1 2 0.1U_0201_25V6K CNV_PTX_C_DRX_N0 57 58 @ RZ371 0_0402_5%
<14> CNV_PTX_DRX_N0 57 58
@ CZ536 1 2 0.1U_0201_25V6K CNV_PTX_C_DRX_P0 59 60 +3.3V_W LAN
<14> CNV_PTX_DRX_P0 59 60
61 62
<14> CLK_CNV_PTX_DRX_N
@ RZ524 1 2 0_0201_5% CLK_CNV_PTX_DRX_N_R 63 61 62 64 CLOSE TO PIN 2,4 CLOSE TO PIN 64,66 <18> CLKREQ_CNV
CLKREQ_CNV 2
@ RZ523 1 2 0_0201_5% CLK_CNV_PTX_DRX_P_R 65 63 64 66 @ RZ78 1 2 0_0402_5%
<14> CLK_CNV_PTX_DRX_P 65 66 ISH_UART0_RXD <19>
330U_D2E_6.3VM_R25M
67 @ RZ79 1 2 0_0402_5% 75K PD at PCH side
67 ISH_UART0_TXD <19>
0.01U_0402_16V7K
0.01U_0402_16V7K
0.1U_0201_10V6K
10U_0402_6.3V6M
0.01U_0402_16V7K
0.01U_0402_16V7K
0.1U_0201_10V6K
10U_0402_6.3V6M
@ RZ80 1 2 0_0402_5% 1
ISH_UART0_CTS# <19>
1
@ RZ81 1 2 0_0402_5% 1 1 1 1 @ QZ18A
ISH_UART0_RTS# <19>
1
@ CZ543
@ CZ532
@ CZ157
69 68 + L2N7002DW 1T1G_SC88-6
GND2 GND1
CZ542
CZ530
CZ531
CZ533
CZ534
CZ535
70 71 Reserve for CNVI
2
NPTH1 NPTH2 2 2 2 2 2
C BELLW _80148-4221 C
CONN@
CNV_RF_RESET# @ RZ3 1 2 0_0201_5% CNV_RF_RESET#_R
CLKREQ_CNV @ RZ4 1 2 0_0201_5% CLKREQ_CNV_R
WWAN/LTE +3.3V_WWAN
Change net name 3/20

NGFF slot_2 Key B @ RZ43
2 1 WWAN_FULL_PWR_EN
10K_0402_5%
100P_0402_50V8J
Change RZ43 to
depop 3/29 1
+3.3V_WWAN
CZ198
JNGFF2
1 2 2
<58> NGFF_CONFIG_3
3
5
7
1
3
5
2
4
6
4
6
8
WWAN_FULL_PWR_EN
WWAN_RADIO_DIS#_R
Change net name 3/20
WWAN_FULL_PWR_EN <17>
@RF@ RI27
1
1
2
0_0402_5%
2
SIM Card Push-Push
DZ5
<15> USB20_P8 7 8 WWAN_RADIO_DIS#_R JSIM1
9 10 2 1 @RF@ RI28 0_0402_5%
<15> USB20_N8 9 10 WWAN_RADIO_DIS# <58> SIM_DET_R SIM_DET
11 1 2 1 2
11 RB751S-40_SOD523-2 NC1 NC2 @ RZ522 0_0402_5%
UIM_DATA 3 4 UIM_CLK
DZ6 I/O CLK +SIM_PWR
12 HW_GPS_DISABLE#_R 2 1 DLW 21HN900HQ2L_4P 5 6 UIM_RESET
12 GPS_DISABLE# <58> USB3_PRX_DTX_N2 USB3_PRX_L_DTX_N2 VPP RST
13 14 3 4
<58> NGFF_CONFIG_0 13 14 <18> USB3_PRX_DTX_N2 3 4
1U_0201_10V6M
15 16 RB751S-40_SOD523-2 7 8
<58> WWAN_WAKE# 15 16 HW_GPS_DISABLE#_R GND1 VCC
B 17 18 B
17 18
1
19 20 USB3_PRX_DTX_P2 2 1 USB3_PRX_L_DTX_P2 9 10
19 20 UIM_RESET <18> USB3_PRX_DTX_P2 2 1 GND2 GND4
CZ37
USB3_PRX_L_DTX_N2 21 22
USB3_PRX_L_DTX_P2 23 21 22 24 UIM_CLK RF@ LI16 11 12
2
25 23 24 26 UIM_DATA GND3 GND5
USB3_PTX_L_DRX_N2 27 25 26 28 DLW 21HN900HQ2L_4P
USB3_PTX_L_DRX_P2 27 28 +SIM_PWR USB3_PTX_DRX_N2 CZ28 1
29 30 2 0.1U_0201_10V6K USB3_PTX_C_DRX_N2 3 4 USB3_PTX_L_DRX_N2
31 29 30 32 <18> USB3_PTX_DRX_N2 3 4 T-SOL_159-1201300600
33 31 32 34 CONN@
<15> PCIE_PRX_DTX_P8 35 33 34 36 USB3_PTX_DRX_P2 CZ29 1 2 0.1U_0201_10V6K USB3_PTX_C_DRX_P2 2 1 USB3_PTX_L_DRX_P2 CIS link OK
<15> PCIE_PRX_DTX_N8 37 35 36 38 <18> USB3_PTX_DRX_P2 2 1
CZ10 1 2 0.1U_0201_10V6K PCIE_PTX_C_DRX_N8 39 37 38 40 RF@ LI17
<15> PCIE_PTX_DRX_N8 PCIE_PTX_C_DRX_P8 39 40 PCH_PLTRST#_R
CZ11 1 2 0.1U_0201_10V6K 41 42
<15> PCIE_PTX_DRX_P8 41 42
43 44
45 43 44 46 PCIE_W AKE# CLKREQ_PCIE#2 <16> 1 2
<16> CLK_PCIE_N2 45 46
47 48 7/4 update @RF@ RI30 0_0402_5%
<16> CLK_PCIE_P2 47 48
49 50 1 2
51 49 50 52 W W AN_COEX3 1 2 W LAN_COEX3 @RF@ RI29 0_0402_5%
53 51 52 54 W W AN_COEX2 @ RZ128 1 2 0_0402_5% W LAN_COEX2 UIM_RESET
55 53 54 56 W W AN_COEX1 @ RZ129 1 2 0_0402_5% W LAN_COEX1
57 55 56 58 SIM_DET @ RZ130 0_0402_5% UIM_CLK
59 57 58 60
59 60 SUSCLK <18,52,67,68> CNV_COEX1 UIM_DATA
61 62 @RF@ RZ373 1 2 0_0201_5%
<58> NGFF_CONFIG_1 61 62 CNV_COEX2 CNV_COEX1 <14>
63 64 @RF@ RZ372 1 2 0_0201_5%
63 64 CNV_COEX3 CNV_COEX2 <14>
65 66 @RF@ RZ374 1 2 0_0201_5%
65 66 CNV_COEX3 <14>
@RF@ CZ39
@RF@ CZ38
@RF@ CZ40
67
<58> NGFF_CONFIG_2 67
33P_0402_50V8J
33P_0402_50V8J
33P_0402_50V8J
1 1 1
69 68
GND2 GND1
70 71
NPTH1 NPTH2 2 2 2
LOTES_APCI0071-P001A
CONN@ +3.3V_W W AN
STATE # CONFIG_0 CONFIG_1 CONFIG_2 CONFIG_3 Module Type

0.047U_0201_10V6K
0.047U_0201_10V6K
33P_0402_50V8J
33P_0402_50V8J
330U_D2E_6.3VM_R25M
22U_0603_6.3V6M
1 For RF Team request

1 1 1 1
1
CZ17
CZ18
+
0 0 0 0 0 SSD-SATA
CZ19
CZ21
CZ164
A A
CZ20
2
2 2 2 2 2
8 1 0 0 0 WWAN
14 1 0 1 1 HCA-PCIE C613 change to 0603

due to height limitation.
15 1 1 1 1 Cache DELL CONFIDENTIAL/PROPRIETARY
C615 footprint change to C_APXK2R5ARA331MF451 Security Classification Compal Secret Data Compal Electronics, Inc.
WLAN (w/ CNVi) / WWAN
Custom 1.0
5 4 3 2 1
5 4 3 2 1
Vinafix.com
D D
C C
Reserve
B B
A A
WIGIG / WIDI
5 4 3 2 1
5 4 3 2 1
Power Control for WLAN &WWAN Power Control for LAN

+3.3V_ALW +3.3V_LAN
+3.3V_WLAN_PWR +3.3V_WLAN
JUMP@ UZ7
UZ44 PJP36
Vinafix.com
1 14 +3.3V_WLAN_PWR 2 1 1 7
+3.3V_ALW VIN1_1 VOUT1_1 2 1 VIN1 VOUT1
2 13 2 8
VIN1_2 VOUT1_2 VIN2 VOUT2
C190
10U_0402_6.3V6M
JUMP_43X79
WLAN_PWR_EN 3 12 3 6
ON1 CT1 1 <18,58> SIO_SLP_LAN# ON CT 1
D D
1
100K_0402_5%
C191
+5V_ALW
4 11
VBIAS GND
1
100K_0402_5%
10U_0402_6.3V6M
470P_0402_50V7K
+3.3V_WWAN_PWR +3.3V_WWAN +5V_ALW 4 1
2 VBIAS 2
R128
C195
5 10 JUMP@ 5
ON2 CT2 GND1
R127
PJP37 9
6 9 +3.3V_WWAN_PWR 2 1 GND2
+3.3V_ALW
2
VIN2_1 VOUT2_1 2 1
1
2
100K_0402_5%
7 8
2
VIN2_2 VOUT2_2
10U_0402_6.3V6M
JUMP_43X79 AOZ1336DI_DFN8_2X2
R129
470P_0402_50V7K
470P_0402_50V7K
15 2 2 1
GPAD
C194
C192
C193
2 EM5209VF_DFN14_3X2
1 1 2
<58> 3.3V_WWAN_EN
+5V_HDD
+3.3V_ALW_PCH
100K_0402_5%
1
+3.3V_ALW
+3.3V_RUN
RN1
1
1
1
10K_0402_5%
10K_0402_5%
@RZ1385
20K_0402_5%
+3.3V_RUN
RZ375
100K_0402_5%
Free Fall Sensor
RZ379
2
1
RN2
2
2
2
FFS_INT2_Q <67>
10U_0402_6.3V6M
0.1U_0201_25V6K
<58> SLP_WLAN#_GATE
2
1 1
3
CN1
CN2
D QN1B
C 5 C
1 2 LGA1 2N7002KDW_SOT363-6
2 2 G
@ RZ71 0_0402_5% LNG2DM
HDD_FALL_INT <19>
2
DZ9 10 5 S
G
4
9 VDD_IO RES
VDD
6
1 3 SIO_SLP_WLAN#_Q 3 12 D
<18,58> SIO_SLP_WLAN# 3 INT 1 11 2 QN1A
D
WLAN_PWR_EN 4 SDO/SA0 INT 2 G

1 <7,18,23,24,25,26> DDR_XDP_WAN_SMBDAT SDA/SDI/SDO 2N7002KDW_SOT363-6
QZ15 2 1 6
<7,18,23,24,25,26> DDR_XDP_WAN_SMBCLK SCL/SPC GND1
L2N7002WT1G_SC-70-3 7 S
1
2 GND2 8
CS GND3 FFS_INT2 <19>
<58> AUX_EN_WOWL BAT54CW_SOT323-3
1 2 LNG2DMTR_LGA12_2X2
@RZ70 0_0402_5%
EC request to reserve OR gate for WLAN power enable
Power Control for M.2 slot 4. Source

Power Control for M.2 slot 3. Source +3.3V_ALW_R
Power Control for M.2 slot 5. Source UZ9

+3.3V_SSD3_PWR
JUMP@
PJP30
+3.3V_SSD3
UZ58
+3.3V_SSD4_PWR
JUMP@
PJP62
+3.3V_SSD4
+3.3V_ALW_R
1 14 2 1 1 7 2 1
B 2 VIN1_1 VOUT1_1 13 2 1 2 VIN1 VOUT1 8 2 1 B
VIN1_2 VOUT1_2 VIN2 VOUT2
10U_0402_6.3V6M
10U_0402_6.3V6M
1 JUMP_43X79 JUMP_43X79
3 12 3 6 1
<58> SLOT3_SSD_PWR_EN ON1 CT1 <58> SLOT4_SSD_PWR_EN ON CT
C200
1
100K_0402_5%
C206
+5V_ALW_R
4 11
VBIAS GND 2
470P_0402_50V7K
+3.3V_SSD5_PWR +3.3V_SSD5 +5V_ALW_R
4 1
VBIAS 2
RZ537
C207
5 10 5
<59> SLOT5_SSD_PWR_EN ON2 CT2 GND1
JUMP@ 9
6 9 PJP64 GND2
+3.3V_ALW_R
2
7 VIN2_1 VOUT2_1 8 2 1 2
VIN2_2 VOUT2_2 2 1 AOZ1336DI_DFN8_2X2
470P_0402_50V7K
470P_0402_50V7K
10U_0402_6.3V6M
15 2 2
GPAD JUMP_43X79
1
1
1
100K_0402_5%
100K_0402_5%
C201
C202
C203
EM5209VF_DFN14_3X2
1 1
RZ538
RZ539
2
Power Control for M.2 slot 6. Source
2
+3.3V_ALW
+3.3V_SSD6_PWR +3.3V_SSD6
UZ59 JUMP@
PJP63
1 7 2 1
2 VIN1 VOUT1 8 2 1
VIN2 VOUT2
10U_0402_6.3V6M
3 6 JUMP_43X79
<59> SLOT6_SSD_PWR_EN ON CT 1
C199
1
100K_0402_5%
470P_0402_50V7K
4 1
+5V_ALW VBIAS 2
RZ540
C209
5
GND1 9
GND2
A A
2
2
AOZ1336DI_DFN8_2X2
Title
WLAN (w/ CNVi) / WWAN
Custom 1.0
5 4 3 2 1
5 4 3 2 1
Vinafix.com
D D
C C
Reserve
B B
A A
PCIE device
5 4 3 2 1
5 4 3 2 1
1W x 1ch, 4ohm (Transducer spec is 8Ohm/0.5Watt per unit, there are two transducer units in one speaker box.)
Internal Speakers Header +3.3V_RUN_AUDIO

CONN@ +1.8V_RUN +5V_RUN_AUDIO
40 mils trace keep 20 mil spacing JSPK1
LA21
place close to pin41 place close to pin46
INT_SPK_L+ EMI@ LA6 1 2 BLM15PX330SN1D_2P INT_SPKR_L+ 1 7 @ RA201 1 2 0_0603_5% place close to pin20 +1.8V_RUN_AUDIO +3.3V_RUN_AUDIO_DVDD 2 1 +5V_RUN_PVDD_L 1 2
INT_SPK_L- EMI@ LA7 1 2 BLM15PX330SN1D_2P INT_SPKR_L- 2 1 G1 LA12 BLM15PX600SN1D_2P HCB2012VF-601T20_2P
INT_SPK_R+ INT_SPKR_R+ 2
10U_0603_10V6M
0.1U_0201_10V6K
0.1U_0201_10V6K
10U_0603_10V6M
0.1U_0201_10V6K
10U_0603_10V6M
0.1U_0201_10V6K
10U_0603_10V6M
EMI@ LA8 1 2 BLM15PX330SN1D_2P 3 1 1 1 1 600 Ohm/2A 1 1
INT_SPK_R- INT_SPKR_R- 3 +3.3V_RUN_AUDIO_IO
0.1U_0201_10V6K
10U_0603_10V6M
CA45
CA47
CA60
EMI@ LA9 1 2 BLM15PX330SN1D_2P 4 1 2 1
1
4
CA58
CA57
CA46
CA48
CA59
5 1 LA14 BLM15PX600SN1D_2P
<14> SMART_SPK_DET0# 5
1
CA55
CA56
0.1U_0201_10V6K
10U_0603_10V6M
6 8
6 G2
3
@ESD@ @ESD@ FOLLOW X10 H Dell GPIO map 2 2 2 2 2 2
1
1
2
AZ5125-02S.R7G_SOT23-3
CA10
CA61
DA6 DA7 ACES_50271-0060N-001
Vinafix.com
2
2
AZ5125-02S.R7G_SOT23-3
@EMI@ CA22
@EMI@ CA23
@EMI@ CA19
@EMI@ CA24
2
+5V_RUN_AUDIO 2
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
1
1 LA27
2 1 place close to pin40 +VDDA_AVDD1
D RA224 D
BLM15PX600SN1D_2P
2
10U_0603_10V6M
0.1U_0201_10V6K
2 1 +3.3V_RUN_AUDIO
1
1
CA8
10K_0402_5%
CA9
2
2
Close to UA1 pin42~45
Close to UA1 pin14

HDA_BIT_CLK_R
@EMI@ RA17
2 1 SPKR_R 1 2
SPKR <18>
1
DMIC_CLK
33_0402_5%
UA1 CA27 0.1U_0201_25V6K RA12 1K_0402_5%
AUD_PC_BEEP
68P_0402_50V8J
RF@ CA54
34 2 1 BEEP_R 1 2
1 PCBEEP BEEP <58>
6 CA28 0.1U_0201_25V6K RA13 1K_0402_5%
I2C_DATA 30 RING2
2
7 MIC2-L/RING2 SLEEVE/RING2 please keep 40 mils trace width

2 I2C_CLK
10P_0402_50V8J
@EMI@ CA33
31 SLEEVE
15 MIC2-R/SLEEVE AUD_HP_OUT_L/ AUD_HP_OUT_Rplease keep 15 mils trace width
<18> HDA_SYNC_R SYNC
1
36 LINE1-L 1 2 HP_OUT_L
HDA_BIT_CLK_R 14 LINE2-L CA43 10U_0603_10V6M
<18> HDA_BIT_CLK_R BCLK HP_OUT_R
place close to UA1 pin6 35 LINE1-R 1 2
2
HDA_SDOUT_R 17 LINE2-R CA44 10U_0603_10V6M

<18> HDA_SDOUT_R SDATA-OUT INT_SPK_L+
42
13 SPK-OUT-L+ SPKR_R
DC_DET/EPAD INT_SPK_L-
100P_0402_50V8J
Place RA9 close to codec 43
HDA_SDIN0_R SPK-OUT-L-
10K_0402_5%
1 2 16
<18> HDA_SDIN0 SDATA-IN
1
INT_SPK_R-
@ CA228
@ RA225
RA9 33_0402_5% 44
11 SPK-OUT-R-
Verb table configures as 1 JD mode with I2S-MCLK/GPO3 45 INT_SPK_R+
internal 47K pull high to save external rBOM.
2
10 SPK-OUT-R+
I2S-BCLK/DSD-SCLK 27 HP_OUT_L 2 1 AUD_HP_OUT_L
2
AUD_SENSE_A HPOUT-L 16.2_0402_1% RA7
9 26 HP_OUT_R 2 1 AUD_HP_OUT_R
NO DOCK I2S-OUT/DSD-R HPOUT-R 16.2_0402_1% RA8
12
C I2S-LRCK/DSD-L +3.3V_RUN_AUDIO_DVDD C
330P_0402_50V8J
EMI@ CA224
330P_0402_50V8J
EMI@ CA225
8 1 1 Change BOM Structure to EMI@ 1/21
I2S-IN
0.1U_0201_25V6K
Place CA70 close to codec BEEP_R
L2N7002WT1G_SC-70-3
100P_0402_50V8J
1
1
I2S-EN/SPDIF-OUT/GPIO2/DMIC-DATA34/DMIC-CLK-IN
CA226
10K_0402_5%
RA52 1 2 100K_0402_5%
1
1
D 2 2
@ CA227
@ RA209
4
AUD_HP_NB_SENSE <38> DMIC0 GPIO0/DMIC-DATA12
QA10
2
DMIC_CLK 1 DMIC_CLK_CODEC
0.1U_0201_25V6K
G 2 5
2
<38> DMIC_CLK GPIO1/DMIC-CLK
1
@ CA41
S EMI@ RA14 22_0402_5%

3
CA31 1 2 1U_0201_6.3V6M PD# 2
2
PDB
Add for solve downsize
2
pop noise and +3.3V_RUN_AUDIO_DVDD RA18 1 2 10K_0402_5% 48

AUD_SENSE_A JD1
detect issue 47
JD2 +RTC_CELL +VDDA_AVDD1
1 2 RF Request RF Request RF Request
CA35 2.2U_0402_6.3V6M
1 2 38 +5V_RUN_AUDIO +1.8V_RUN_AUDIO +1.8V_RUN +3.3V_RUN_AUDIO
RA44 100K_0402_5% VREF 1 2
1 2 39 RA213 @ 0_0402_5%
CA51 10U_0603_10V6M LDO1-CAP
CLASS-D POWER DOWN CONTROL CIRCUIT
1 2 32 33 1 2 RA214
CA25 10U_0603_10V6M MIC2-CAP 5VSTB/AUX_MODE 10K_0402_5%
+VDDA_AVDD1
RF@ CA69
1 2 40
AVDD1
33P_0402_50V8J
@ RA48 0_0402_5% SLEEVE 2 1 +MIC2-VREFO-R 29
MIC2-VREFO-R +1.8V_RUN_AUDIO
12P_0402_50V8J
RF@ CA63
68P_0402_50V8J
RF@ CA64
12P_0402_50V8J
RF@ CA65
68P_0402_50V8J
RF@ CA66
12P_0402_50V8J
RF@ CA67
68P_0402_50V8J
RF@ CA68
RA6 2.2K_0402_5% 20 1 1 1 1 1 1 1
RING2 2 1 +MIC2-VREFO-L 28 CPVDD/AVDD2
1 2 PD# RA5 2.2K_0402_5% MIC2-VREFO-L 3 +3.3V_RUN_AUDIO_DVDD
<58> NB_MUTE# DVDD
@ DA8 downsize,and add CA232,CA233
RB751S-40_SOD523-2 CA233 1 2 1U_0201_6.3V6K 18 +3.3V_RUN_AUDIO_IO 2 2 2 2 2 2 2
DVDD-IO
1 2 CA49 1 2 1U_0201_6.3V6K 25 41 +5V_RUN_PVDD_L
<18> HDA_RST#_R CPVEE PVDD1
@ RA50 0_0402_5%
CA232 1 2 1U_0201_6.3V6K 24 46
CBN PVDD2
Place CA29 close to Codec CA29 1 2 1U_0201_6.3V6K 23 49
only Samsung,Taiyo,Murata can use CBP G
1 2 21 37
CA52 10U_0603_10V6M LDO2-CAP AVSS1
1 2 19 22
CA53 10U_0603_10V6M LDO3-CAP AVSS2
B HP-Out-Right Nokia-MIC B
ALC3281-CG_MQFN48_6X6
HP-Out-Left iPhone-MIC
JUMP@
PJP17
1 2
+5V_RUN +5V_RUN_AUDIO
PAD-OPEN1x2m
2.5A +3.3V_RUN_AUDIO
JUMP@
PJP18
+3.3V_RUN 1 2 +3.3V_RUN_AUDIO Global Headset
1
PAD-OPEN1x1m
500mA RA219
10K_0402_5%
Universal Jack
Normal
2
CONN@
SLEEVE ESD@ LA11 1 2 BLM15PX330SN1D_2P SLEEVE_R JHP1 Open
RING2 ESD@ LA10 1 2 BLM15PX330SN1D_2P RING2_R 3
AUD_HP_OUT_R EMI@ LA16 1 2 BLM15PX330SN1D_2P AUD_HP_OUT_R1 1
AUD_HP_OUT_L EMI@ LA15 1 2 BLM15PX330SN1D_2P AUD_HP_OUT_L1 9
5 10
AUD_HP_NB_SENSE 6
CA2
EMI@
CA3
EMI@
place at AGND and DGND plane ESD@ 2 G 7
2
2 1 1 1 DA3 4 G 8
@ RA221 0_0402_5%
680P_0402_50V7K
680P_0402_50V7K
AZ5123-02S.R7G_SOT23-3
SINGA_2SJ3088-025111F
2 1 2 2
@ RA222 0_0402_5% Update symbol Ver. 0725
ESD@
RA220 100K_0402_5%
DA2 ESD@
CA12 680P_0402_50V7K
@ESD@
CA13 680P_0402_50V7K
@ESD@
2 1 DA1
AZ5125-02S.R7G_SOT23-3
CA1 ESD@
CA4 ESD@
@ RA223 0_0402_5%
AZ5125-02S.R7G_SOT23-3
220P_0402_50V8J
220P_0402_50V8J
1 1
2
2 1
1
2
@ RA226 0_0402_5% 2 2
Place CA12 & CA13
close to Audio Jack
1
A 2 1 A
@ RA227 0_0402_5%
@JUMP@
PJP19
2 1 1 2
@ RA228 0_0402_5%
PAD-OPEN1x1m
Title
Codec _ALC3281
Custom 1.0
5 4 3 2 1
5 4 3 2 1
Vinafix.com
D D
C C
Reserve
B B
A A
Audio Ampfilper
5 4 3 2 1
A B C D E
+3.3V_ALW
GPIO223 GPIO224 GPIO227 GPIO016 GPIO056 GPIO055
eSPI NA NA *PRIM_PW RGD NA NA PCH_RSMRST# CCG5_SMBDAT 1 2
2 1 +RTC_CELL_VBAT LPC SHD_IO0 SHD_IO1 SHD_IO2 SHD_IO3 SHD_CLK SHD_CS# RE302 2.2K_0402_5%
+RTC_CELL CCG5_SMBCLK
@ RE32 0_0402_5% * For Version B IC 1 2
0.1U_0201_10V6K
1 RE303 2.2K_0402_5%
CCG5_I2C_INT1#
CE11
GPIO204 GPIO011 GPIO100 GPIO021 GPIO067 1 2
+3.3V_ALW_UE1 eSPI NA NA NA SIO_RCIN# NA RE91 100K_0402_5%
LPC RSMRST# SIO_EXT_SMI# SIO_EXT_SCI# LPCPD# CLKRUN#
2
0.1U_0201_10V6K
1U_0201_10V6M
0.1U_0201_10V6K
JUMP@ PJP22
1 2 LOM_CABLE_DETECT# 1 2
+3.3V_ALW 1 1
1
CE13
CE14
CE23
@ RE505 100K_0402_5%
10U_0402_6.3V6M
PAD-OPEN1x1m PBAT_CHARGER_SMBDAT 1 2
1
RE37 2.2K_0402_5%
2
2 2
CE16
PBAT_CHARGER_SMBCLK 1 2
Vinafix.com UE1 RE43 2.2K_0402_5%
2
MEC5105_W FBGA169_11X11 SIO_SLP_SUS#_R 1 2
MEC5105 change CPN to SA00009GL30 F2 NDS3@ RE561 100K_0402_5%
GPIO033/RC_ID0 TYPEC_ID <59>
A2 J10 SYSTEM_ID <59>
+3.3V_ALW_UE1 VBAT GPIO034/RC_ID1/SPI0_CLK J13
1 GPIO036/RC_ID2/SPI0_MISO BOARD_ID <59> 1
RE314 100_0402_1% B7 E7
2 1 VTR_ANALOG GPIO003/SMB00_DATA/SPI0_CS# D7
BARREL_DISC <82> RP change to single Resistor
GPIO004/SMB00_CLK/SPI0_MOSI PSID_DISABLE# <82>
0.1U_0201_10V6K
0.1U_0201_10V6K
K2
VREF_ADC GPU_SMCLK
0.1U_0201_10V6K
22U_0603_6.3V6M
0.1U_0201_10V6K
1 1 1 1 G3 RUNPW ROK RE730 1 2 2.2K_0402_5%
GPIO057/VCC_PWRGD GPU_SMDAT
CE19
CE20
@ CE17
+3.3V_EC_PLL F1 H5 GPS_DISABLE# RE731 1 2 2.2K_0402_5%
1 VTR_PLL GPIO060/KBRST/48MHZ_OUT GPS_DISABLE# <52>
CE15
CE18
G11
GPIO104/UART0_TX HOST_DEBUG_TX <59> NGFF_CONFIG_1
H1 G12 RE732 1 2 100K_0402_5%
2 2 2 2 VTR_REG GPIO105/UART0_RX RTCRST_ON_POW ER ME_FWP <18> NGFF_CONFIG_2
B13 RE733 1 2 100K_0402_5%
2 G8 GPIO127/A20M/UART0_CTS# F10 CCG5_I2C_INT1# NGFF_CONFIG_0 RE734 1 2 100K_0402_5%
M9 VTR1 GPIO225/UART0_RTS# CCG5_I2C_INT1# <44> NGFF_CONFIG_3 RE735 1 2 100K_0402_5%
Close to pin H1 +VSS_PLL +3.3V_ALW_UE1 VTR2 PCIE_W AKE#_R
close to pin G8/M9 +1.8V_ALW_VTR3 N5 N13
VTR3 GPIO025/TIN0/nEM_INT/UART_CLK N12 PTP_DISABLE# PCIE_WAKE#_R <59>
PCH_DPW ROK_EC GPIO026/TIN1 PTP_DISABLE# <62>
DS3@ RE536 1 2 0_0402_5% FOLLOW X10 Brook Hollow F8 M11 1 2
<18> PCH_DPWROK RUN_ON_EC GPIO020 GPIO027/TIN2 SIO_SLP_A# <18,19> USB_POW ERSHARE_VBUS_EN 1
RF Request E8 H9 @ RE746 1 2 0_0201_5% 2 100K_0402_5%
<59> RUN_ON_EC GPIO045 GPIO030/TIN3 SIO_SLP_LAN# <18,54>
@ RE703 1 2 0_0402_5% M12 @ RE743 0_0201_5% RE700
+3.3V_ALW <19> SIO_EXT_W AKE# BT_RADIO_DIS# GPIO120 USB_POW ERSHARE_EN#
C2 L9 FOLLOW X10 H Dell GPIO map FOLLOW X10 H Dell GPIO map 1 2
<52> BT_RADIO_DIS# GPIO166 GPIO017/GPTP-IN5 VGA_IDENTIFY <27,28>
FOLLOW X10 H Dell GPIO map F9 M10 RE701 100K_0402_5%
<84,85> PBAT_PRES# SIO_SLP_SUS#_R GPIO175 GPIO151/ICT4 NGFF_CONFIG_1 <52>
DS3@ RE349 1 2 43K_0402_1% N4 N9
<18> SIO_SLP_SUS# GPIO230 GPIO152/GPTP-OUT3 NGFF_CONFIG_0 <52>
M8
K8 GPIO231 C11 PTP_DISABLE# 1 2
<18> AC_PRESENT GPIO233 GPIO156/LED0 BREATH_LED# <62>
FOLLOW BR D10 RE748 100K_0402_5%
GPIO157/LED1 BAT1_LED# <62> AC_DIS
<38> PANEL_MONITOR <18> SML1_SMBDATA
E11 D11 1 2
GPIO007/SMB03_DATA/PS2_CLK0B GPIO153/LED2 BAT2_LED# <62>
D8 E1 @ RE83 100K_0402_5%
<18> SML1_SMBCLK GPIO010/SMB03_CLK/PS2_DAT0B GPIO226/LED3 LCD_VCC_TEST_EN <38>
12P_0402_50V8J
RF@ CE59
68P_0402_50V8J
RF@ CE60
W W AN_W AKE#
M13 VCCDSW _EN GPS_DISABLE# 1 2
1 1 <52> WWAN_WAKE# GPIO110/PS2_CLK2
0.1U_0201_25V6K
1 2 K12 E5 RE12 100K_0402_5%
<18> SUSACK# W LAN_W IGIG60GHZ_DIS# L13 GPIO111/PS2_DAT2 GPIO005/SMB01_DATA/GPTP-OUT4 USH_EXPANDER_SMBDAT <59,65> W LAN_W IGIG60GHZ_DIS#
@ RE745 0_0402_5% B3 1 2
<52> WLAN_WIGIG60GHZ_DIS# GPIO112/PS2_CLK1A GPIO006/SMB01_CLK/GPTP-OUT7 USH_EXPANDER_SMBCLK <59,65>
@ CE66
FOLLOW X10 H Dell GPIO map K11 M7 RE8 100K_0402_5%
<7,18> SIO_PWRBTN# GPIO113/PS2_DAT1A GPIO012/SMB07_DATA/TOUT3 VCCDSW_EN <18>
1
2 2 VCCST_PW RGD_EC K10 M4 W W AN_W AKE# 1 2
GPIO114/PS2_CLK0A/nEC_SCI GPIO013/SMB07_CLK/TOUT2 PBAT_CHARGER_SMBDAT DGPU_PWROK <18,27>
Remove VCCST_PWRGD and RE308 N11 M3 RE38 10K_0402_5%
<59> LID_CL_SIO# GPIO115/PS2_DAT0A GPIO130/SMB10_DATA/TOUT1 PBAT_CHARGER_SMBCLK PBAT_CHARGER_SMBDAT <84,85> LED_MASK#
2 1 E10 N2 1 2
<62> CLK_TP_SIO_I2C_DAT
2
<54,58> SLP_WLAN#_GATE @ RE552 0_0402_5% C12 GPIO154/SMB02_DATA/PS2_CLK1B GPIO131/SMB10_CLK/TOUT0 N10 PBAT_CHARGER_SMBCLK <84,85> RE21 10K_0402_5%
<62> DAT_TP_SIO_I2C_CLK GPIO155/SMB02_CLK/PS2_DAT1B GPIO132/SMB06_DATA LED_MASK# NGFF_CONFIG_2 <52>
A12
GPIO140/SMB06_CLK/ICT5 GPU_SMDAT LED_MASK# <51,62>
E9 B6
<59> JTAG_TDI F6 GPIO145/SMB09_DATA/JTAG_TDI GPIO141/SMB05_DATA/SPI1_CLK/UART0_DCD# F7 GPU_SMCLK GPU_SMDAT <27> PCIE_W AKE#_R 1 2
<59> JTAG_TDO C8 GPIO146/SMB09_CLK/JTAG_TDO GPIO142/SMB05_CLK/SPI1_MOSI/UART0_DSR# B4 CCG5_SMBDAT GPU_SMCLK <27> RE35 10K_0402_5%
<59> JTAG_CLK GPIO147/SMB08_DATA/JTAG_CLK GPIO143/SMB04_DATA/SPI1_MISO/UART0_DTR# CCG5_SMBCLK CCG5_SMBDAT <44>
C5 C3
<59> JTAG_TMS JTAG_RST# GPIO150/SMB08_CLK/JTAG_TMS GPIO144/SMB04_CLK/SPI1_CS#/UART0_RI# CCG5_SMBCLK <44>
G13
JUMP@ PJP20 JTAG_RST# J4 I_BATT_R RE64 1 2 300_0402_5%
GPIO200/ADC00 I_SYS_R I_BATT <85>
1 2 E3 J5 RE312 1 2 300_0402_5%
+1.8V_PRIM +1.8V_ALW_VTR3 <77> TACH_FAN1
D1 GPIO050/FAN_TACH0/GTACH0 GPIO201/ADC01 J6
I_SYS <85,90>
1 <77> TACH_FAN2 GPIO051/FAN_TACH1/GTACH1 GPIO202/ADC02 DCIN3_EN <82>
PAD-OPEN1x1m FOLLOW X10 Brook Hollow LCD_TST M2 G2 0_0402_5% 2 1 @ RE318
<38> LCD_TST GPIO052/FAN_TACH2/LRESET# GPIO203/ADC03 TOUCHPAD_INTR# <17,62>
CE22 1 CE21 L10 H2
2 <77> PWM_FAN1 GPIO053/PWM0/GPWM0 GPIO204/ADC04 USB_POW ERSHARE_VBUS_EN USH_PWR_STATE# <65> 2
0.1U_0201_10V6K 0.1U_0201_10V6K L11 J2
2 <77> PWM_FAN2 GPIO054/PWM1/GPWM1 GPIO205/ADC05 USB_POW ERSHARE_EN# USB_POWERSHARE_VBUS_EN <44,71>
Close to pin N5 M5 J3
<62> PCH_RSMRST# J8 GPIO055/PWM2/SHD_CS#/(RSMRST#) GPIO206/ADC06 K3 USB_POWERSHARE_EN# <71>
2 <82> PS_ID GPIO056/PWM3/SHD_CLK GPIO207/ADC07 SLOT4_SSD_PWR_EN <54>
Change to pop <38> BIA_PWM_EC N1 D3
TBT_RESET_N_EC_R L8 GPIO001/PWM4 GPIO210/ADC08 LOM_CABLE_DETECT# AUX_EN_WOWL <54>
2 1 D2 LOM_CABLE_DETECT# <51>
Remove PJP21 <42> TBT_RESET_N_EC @ RE506 0_0402_5% N6 GPIO002/PWM5 GPIO211/ADC09 E2
<82,83> HW_ACAVIN_NB GPIO014/PWM6/GPTP-IN6 GPIO212/ADC10 BC_INT#_ECE1117 <62>
J9 G5
+3.3V_ALW <38> PANEL_BKEN_EC GPIO015/PWM7 GPIO213/ADC11 SLOT3_SSD_PWR_EN <54>
FOLLOW X10 H Dell GPIO map BEEP H11 F5
<56> BEEP SLP_W LAN#_GATE_R GPIO035/PWM8/CTOUT1 GPIO214/ADC12 DGFF_DP_HDMI_HPD <27>
1 2 D9 K4
WWAN_RADIO_DIS# <18,54> SIO_SLP_WLAN# AC_DIS GPIO133/PWM9 GPIO215/ADC13 DCIN1_EN <82>
2 1 @ RE569 0_0402_5% <82> AC_DIS
H12 L1
BCM5882_ALERT# GPIO134/PWM10/UART1_RTS# GPIO216/ADC14 PCH_PCIE_WAKE# <18,42,59>
RE10 100K_0402_5% 1 2 G10 L3
BT_RADIO_DIS# <54,58> SLP_WLAN#_GATE <65> BCM5882_ALERT# GPIO135/UART1_CTS# GPIO217/ADC15 LAN_WAKE# <18,51> I_BATT_R
2 1 @ RE570 0_0402_5%
H10 CE3 1 2 2200P_0402_50V7K
<59> MSCLK GPIO170/TFDP_CLK/UART1_TX CV2_ON_R
RE11 100K_0402_5% G9 H8 RE539 1 2 100_0402_5%
BC_DAT_ECE1117 <59> MSDATA GPIO171/TFDP_DATA/UART1_RX GPIO222/SER_IRQ CV2_ON <65> I_SYS_R
2 1 J7 CE4 1 2 2200P_0402_50V7K
RE365 100K_0402_5% A4 GPIO223/SHD_IO0 L6 SSD_SCP#
<56> NB_MUTE# EN_INVPW R GPIO022/GPTP-IN0 GPIO224/GPTP-IN4/SHD_IO1 SSD_SCP# <67,68>
RP change to single Resistor B2 L7 PRIM_PWRGD <89>
<38> EN_INVPWR RESET_IN# GPIO023/GPTP-IN1 GPIO227/SHD_IO2
2 1 C1 M6
CV2_ON_R +3.3V_ALW 100K_0402_5% RE362
IMVP_VR_ON_EC GPIO024/GPTP-IN2 GPIO016/GPTP-IN7/SHD_IO3/ICT3 VBUS1_ECOK <82,83>
1 2 N7 FOLLOW X10 H Dell GPIO map
RE736 100K_0402_5% FOLLOW X10 H Dell GPIO map <59> IMVP_VR_ON_EC K9 GPIO031/GPTP-OUT1 D6 BGPO0 1 2
1 2 IMVP_VR_ON_EC <22> 3.3V_RUN_GFX_ON N8 GPIO032/GPTP-OUT0 BGPO0 C7 @ RE749 0_0402_5%
<62> M_BIST GPI0040/GPTP-OUT2 GPIO164/VCI_OVRD_IN ACAV_IN <27,62,85>
RE737 100K_0402_5% Change GPIO map for RTC_DET# A5 RE59 close to UE2 at least 250mils
RUN_ON_EC VCI_OUT ALWON <86,87>
1 2 F13 D5
<82,83> VBUS3_ECOK GPIO121/PVT_IO0 GPIO163/VCI_IN0# VCI_IN1# POWER_SW_IN# <59,62> +PECI_VREF USB_POW ERSHARE_VBUS_EN
RE738 100K_0402_5% E13 B5 2 1 1 2
<82,83> AC_DISC# GPIO124/GPTP-OUT6/PVT_CS# GPIO162/VCI_IN1# VCI_IN2# +1.0V_VCCST
C13 D4 0_0402_5% @ RE59 RE702 @ 1M_0402_5%
TBT_RESET_N_EC_R <65> USH_DET# GPU_PW R_LEVEL GPIO125/GPTP-OUT5/PVT_CLK GPIO161/VCI_IN2# VCI_IN3#
0.1U_0201_10V6K
1 2 E12 E4
<27> GPU_PWR_LEVEL GPIO126/PVT_IO3 GPIO000/VCI_IN3# PCH_RSMRST#
RE95 100K_0402_5% 1 2
CE25
RTCRST_ON F11 RE342 10K_0402_5%
WWAN_RADIO_DIS# F12 GPIO122/BCM0_DAT/PVT_IO1 C6 SYS_PW ROK 1 2
<52> WWAN_RADIO_DIS# BC_DAT_ECE1117 GPIO123/BCM0_CLK/PVT_IO2 GPIO165/32KHZ_IN/CTOUT0 3.3V_WWAN_EN <54>
D12 @ RE56 10K_0402_5%
<62> BC_DAT_ECE1117
2
D13 GPIO046/BCM1_DAT F3 32KHZ_OUT @ CE54 1 2 10P_0402_50V8J I_SYS_R 1 2
<62> BC_CLK_ECE1117 GPIO047/BCM1_CLK GPIO221/GPTP-IN3/32KHZ_OUT @ RE313 10K_0402_5%
+3.3V_ALW F4 LCD_TST 1 2
<52> NGFF_CONFIG_3 GPIO041/SYS_SHDN# +PECI_VREF
@ RE57 2 1 1K_0402_5% B1 J11 RE20 100K_0402_5%
+3.3V_ALW2 SYSPWR_PRES GPIO044/VREF_VTT PECI_EC_R EN_INVPWR
K7 K13 RE60 1 2 33_0402_5% 1 2
H_PECI <7,14>
1
Remove RTC_DET# N3 GPIO011/nSMI GPIO042/PECI_DAT/SB-TSI_DAT J12 m3042_PCIE#_SATA 1 RE55 100K_0402_5%

<82,83> VBUS2_ECOK GPIO021/LPCPD# GPIO043/SB-TSI_CLK REM_DIODE1_N T309 PAD~D @
100K_0402_5%
1 2 USH_DET# K6 A8 CE24 1 2 2200P_0402_50V7K

<18,59> ESPI_RESET# GPIO061/LPCPD#/ESPI_RESET# DN1_DP1A REM_DIODE1_P
RE58
@ RE526 10K_0402_5% H7 A7 REM_DIODE1_N

BCM5882_ALERT# <18> ESPI_ALERT# GPIO063/SER_IRQ/ESPI_ALERT# DP1_DN1A REM_DIODE2_N REM_DIODE1_P REM_DIODE1_N <59>
1 2 K1 A10 CE26 1 2 2200P_0402_50V7K
GPIO064/LRESET# DN2_DP2A REM_DIODE2_P REM_DIODE2_N REM_DIODE1_P <59> +RTC_CELL
RE532 4.7K_0402_5% Remove WWAN_GPIO_CTRL G7 A9
REM_DIODE2_N <59>
2
<18,59> ESPI_CLK_5105 H6 GPIO065/PCI_CLK/ESPI_CLK DP2_DN2A B9 REM_DIODE3_N CE270 1 2 2200P_0402_50V7K REM_DIODE2_P

<18,59> ESPI_CS# GPIO066/LFRAME#/ESPI_CS# DN3_DP3A REM_DIODE3_P REM_DIODE3_N REM_DIODE2_P <59> VCI_IN1#
K5 B8 1 2
+3.3V_RUN <18,59> ESPI_IO0 GPIO070/LAD0/ESPI_IO0 DP3_DN3A REM_DIODE4_N REM_DIODE3_P REM_DIODE3_N <59>
3 L4 A11 CE27 1 2 2200P_0402_50V7K RE507 100K_0402_5% 3
<18,59> ESPI_IO1 GPIO071/LAD1/ESPI_IO1 DN4_DP4A REM_DIODE4_P REM_DIODE4_N REM_DIODE3_P <59> VCI_IN2#
G6 B10 1 2
GPU_PW R_LEVEL <18,59> ESPI_IO2 GPIO072/LAD2/ESPI_IO2 DP4_DN4A +VR_CAP REM_DIODE4_P REM_DIODE4_N <59>
2 1 L5 C10 RE508 100K_0402_5%
<18,59> ESPI_IO3 ENABLE_DS# GPIO073/LAD3/ESPI_IO3 VIN REM_DIODE4_P <59> VCI_IN3#
RE557 10K_0402_5% L2 C9 VSET_5105 <59> 12/7 1 2
M1 GPIO067/CLKRUN# VSET B11 RE750 100K_0402_5%
<59> DGPU_PWR_EN SYS_PW ROK 1 GPIO100/nEC_SCI VCP I_ADP <85>
2 G4 H3
VSS_ANALOG
<7,18> SYS_PWROK GPIO106/PWROK GPIO103/THERMTRIP2# THERMTRIP2# <59>
+3.3V_ALW @ RE548 0_0402_5% L12 B12 THERMTRIP1#
<82> DCIN2_EN GPIO107/nSMI THERMTRIP1# PROCHOT#_R1 THERMTRIP1# <27>
H13 1 2 100_0402_5%
VSS_ADC
RE288 +RTC_CELL_PCH +RTC_CELL
VSS_PLL
100K_0402_5%
VR_CAP
MEC_XTAL1 A1 GPIO160/PWM11/PROCHOT# PROCHOT# <7,27,83,85,90> @ RE551
XTAL1 1 2
2
MEC_XTAL2_R A3
VSS1
VSS2
VSS3
RE63
XTAL2 0_0402_5%
A6
A13
E6
H4
1+VR_CAP J1
C4
G1
RE94
1U_0201_10V6M
1
Material shortage SB00000QP00 1 2

+RTC_CELL_PCH change to SB00000T900 1/15 +RTC_CELL 75_0402_5% PCH_RTCRST# <18,19>
JTAG_RST# QE15
+VSS_PLL
1
D
PJ2301_SOT23-3
RTCRST_ON 2 QE12
1
1 3 G L2N7002W T1G_SC-70-3
S
D
1
1U_0201_10V6M
S
1
3
1
RE93
@SHORT PADS~D
100_0402_1%
1U_0201_10V6M
10K_0402_5%
CE31
2
1
1
@ JTAG1
@ RE65
G
2
1
100K_0201_5%
CE30
RE546
CE63
2
2
2
DE2
2
2
2 1
2
RB751S-40_SOD523-2
+3.3V_ALW
1
+3.3V_RUN D
RE543
QE17 2 RTCRST_ON_R 1 2 RTCRST_ON_R1 1 2RTCRST_ON_POW ER
L2N7002W T1G_SC-70-3 G @ RE747 0_0402_5% VGA_IDENTIFY 1 2
2
+3.3V_ALW
0.1U_0201_25V6K
10K_0402_5%
S 1M_0402_5% RE84 100K_0402_5%
22P_0402_50V8J
100K_0402_5%
RE67
@ CE64
1
1
RE541
MEC_XTAL2_R
CE65
For EMI request
100K_0402_5%
+1.8V_ALW_VTR3
2
RUNPWROK
2
ESPI_CLK_5105 FOLLOW X10 Brook Hollow
Connect to GND on DSC CARD
1
RE68
NC on UMA card.
1
1
4 4
33_0402_5%
1
@ RE290 RE549
@EMI@
32 KHz Clock
1
0_0402_5% 100K_0402_5% VGA_ID0

RE350
RUN_ON# 5
Discrete 0
2
2
Deep Sleep support <22> RUN_ON# L2N7002DW 1T1G_SC88-6

YE1
2
ENABLE_DS# QE2B
UMA 1
33P_0402_50V8J
MEC_XTAL1 1 2 MEC_XTAL2 8/28 schematic review

non Deep Sleep 1
4
6
@EMI@
1
1
10P_0402_50V8J
12P_0402_50V8J
@RE550 Deep Sleep 0

CE57
32.768KHZ_9PF_X1A000141000200 1
1
100K_0402_5% 2
<11,22,59,67,70,89> RUN_ON
2
L2N7002DW 1T1G_SC88-6
CE28
CE29
QE2A Security Classification Compal Secret Data Compal Electronics, Inc.

2
2 Title
1
EC MEC5106
Custom 1.0
A B C D E
A B C D E
2 1
0_0402_5% @ RE304
+RTC_CELL
+3.3V_ALW
1
100K_0402_5%
@ CE53
RE31
@ CE10 1 2
1 2 UE4 +3.3V_ALW
5
0.1U_0201_25V6K
1U_0201_10V6M 1 5
VCC
2
1 NC VCC
<58> IMVP_VR_ON_EC IN1 IMVP_VR_ON
1 2 4 2
<58,62> POWER_SW_IN# POWER_SW#_MB <19,77> SIO_SLP_S3# 2 OUT A 4
RE33 1K_0402_5%
GND
<18,19,42,59> SIO_SLP_S3# IN2 Y VCCST_PWRGD <7>
2.2U_0402_6.3V6M
3
GND
1
UE3
CE12
MC74VHC1G08DFT2G_SC70-5 74AUP1G07GW_TSSOP5
Vinafix.com
3
2
RF Request IMVP_VR_ON <90>
+3.3V_ALW 1 2
0_0402_5% @ RE280
1 +3.3V_ALW 1
100K_0402_5%
68P_0402_50V8J
1
1
RE25
2 1 RUN_ON <11,22,58,67,70,89>
RF@ CE61
<58> RUN_ON_EC
0_0402_5% @ RE292
2
RE26
2
LID_CL_SIO# 2 1 +3.3V_ALW
<58> LID_CL_SIO# LID_CL# <62,77> @ CE52
0.047U_0201_10V6K
10_0402_5% 1 2
1.8V
5
+1.8V_ALW_VTR3
CE8
0.1U_0201_25V6K
UE11
VCC
2
FOLLOW X10 Brook Hollow 1
1 5 IN1 4
UE1 1.8V(VTR3 WELL) NC VCC 2 OUT
GND
2 IN2
<58> DGPU_PWR_EN A 4
PU at DGFF card UE5
Y DGPU_PWR_EN_R <27>
3 MC74VHC1G08DFT2G_SC70-5
3
GND
74AUP1G07GW_TSSOP5
CONN@ +3.3V_RUN
JESPI
1 PCIE_WAKE# <27,42,52,67,68>
1 2
2 3
3 ESPI_IO0 <18,58>
4 ESPI_IO1 <18,58>
4 5 2 1 1 2
5 ESPI_IO2 <18,58> <58> PCIE_WAKE#_R PCH_PCIE_WAKE# <18,42,58>
6 0_0402_5% @ RE275 0_0402_5% @ RE274
6 7 ESPI_IO3 <18,58>
7 8 ESPI_CS# <18,58>
11 8 9 ESPI_RESET# <18,58>
Stuff RE275 and no stuff RE274 keep E5 design
12 GND1 9 10 Remove RE375 and RE560 Stuff RE274 and no stuff RE275 to save two GPIOs on EC(PCH_PCIE_WAKE# should be output with OD)
GND2 10 ESPI_CLK_5105 <18,58>
JXT_FP241AH-010GAAM
+3.3V_ALW +3.3V_ALW
2 2
LPC 80Port Debug LPC ESPI +3.3V_ALW RE343 CE62 REV RE79 CE40 REV R3754 C1465 REV
4.3K_0402_5%
1
1
2K_0402_5%
Change board ID to
240K 4700p Single Port ACE w/o AR 2K for PVT 3/6 240K 4700p 240K 4700p ***
RE79
1 +3.3V_RUN +3.3V_RUN
33K_0402_5%
1
RE300
130K 4700p Single Port ACE w/AR 130K 4700p X01(DVT1.0) 130K 4700p ***
RE343
2 +3.3V_RUN +3.3V_RUN 62K 4700p Dual Port ACE w/o AR 62K 4700p X01(DVT1.1) 8.2K 4700p 15"
2
Dual Port ACE w/AR
* 33K 4700p 33K 4700p X02 * 4.3K 4700p 17"
2
3 LPC_LAD0 ESPI_IO0 <58> TYPEC_ID <58> BOARD_ID <58> SYSTEM_ID
4700P_0402_25V7K
4700P_0402_25V7K
8.2K 4700p Dual Port ACE (w/AR +w/o AR) 8.2K 4700p X03 2K 4700p ***
4700P_0402_25V7K
1
1 1
CE62
4 LPC_LAD1 ESPI_IO1 4.3K 4700p 4.3K 4700p X00 1K 4700p ***
CE40
CE47
2
5 LPC_LAD2 ESPI_IO2 2K 4700p 2 * 2K 4700p A00 2
1K 4700p 1K 4700p
6 LPC_LAD3 ESPI_IO3
7 LPC_FRAME# ESPI_CS#
TypeC_ID rise time is measured from 5%~68%. BOARD_ID rise time is measured from 5%~68%. PANEL_ID rise time is measured from 5%~68%.
8 PCH_PLTRST# NA
9 GND GND
10 LPC_CLOCK ESPI_CLK
+3.3V_ALW
RP change to single Resistor
1
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10_0402_1%
RE71
RE739
RE740
RE741
RE742
1
10K_0402_5%
10K_0402_5%
10K_0402_5%
100K_0402_5%
@ RE74
@ RE75
CONN@
RE72
RE73
JDEG1
1 +EC_DEBUG_VCC
3 1 2 JTAG_TDI 3
JTAG_TDI <58> CHECK
2
2 3 JTAG_TMS RE69
3 JTAG_CLK JTAG_TMS <58>
0.1U_0201_25V6K
4 1 2
4 JTAG_TDO JTAG_CLK <58> +1.0VS_VCCIO +3.3V_ALW THERMTRIP2# <58>
5 RE86 8.2K_0402_5%
5 6 JTAG_TDO <58>
MSCLK 10K_0402_5% SIO_SLP_S3# <18,19,42,59>
6
1
SIO IT8306
+3.3V_ALW
CE36
7 MSDATA 1 2 @ QE11
7
2
8 HOST_DEBUG_TX
G
8
1
11 9 DEBUG_TX C
2
RE563 12 GND1 9 10 1 3 1 2 2
EXPANDER_ALERT# 1 2 10K_0402_5% GND2 10 1 2 RE70 2.2K_0402_5% B
S
<19> SBIOS_TX +1.0V_VCCST E
+3.3V_ALW JXT_FP241AH-010GAAM RE306 @ 0_0402_5% QE4
3
L2N7002WT1G_SC-70-3 LMBT3904WT1G_SC70-3
HOST_DEBUG_TX <58> Material shortage from SB000002R00
1 1 2 1 change to SB000013V00 1/15
MSDATA <58> <7,14,23,24,25,26> H_THERMTRIP#
0.1U_0201_25V6K
0.1U_0201_25V6K
0_0402_5% @ RE90
MSCLK <58>
CE340
CE341
2 1
2 2 0_0402_5% @ RE30
1
0.1U_0201_25V6K
USE DVT1.0 CPN : SA00009YF10

and apply new symbol 1/15
CE342
2 UE12
14 1 DP1/DN1 for CPU OTP on QE3, place QE3
VSTBY1 GPA0
24
VSTBY2 GPA1
3
6 VSET_5105 <58> close to CPU and CE35 close to QE3.
GPA2
0.1U_0201_25V6K
4 2
VCORE GPA3 DGPU_ALERT# <27> DN1a/DP1a for CPU VR(PU1100) on QE26, place QE26 DP3/DN3 for SODIMM(TOP) on QE104,
1
1.58K_0402_1%
7
GPA4 GC6_THM_ON <14>
1
<58,65> USH_EXPANDER_SMBCLK
12
SCL GPA5
5
TB_STAT# <85> close to CPU and CE339 close to QE26 place QE104 close to SODIMM(TOP) and CE272 close to
CE38
RE77
8
<58,65> USH_EXPANDER_SMBDAT
13 GPA6 9 DGFF_VGA_DIS# <27> REM_DIODE1_P
REM_DIODE1_P <58>
QE104 REM_DIODE3_P
REM_DIODE3_P <58>
2
SDA GPA7
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
QE26
2
WRST# 19 16 LMBT3904WT1G_SC70-3 QE3 QE104

WRST# GPE0 DP1_GPU_SEL# <31> 2 1 1
1
LMBT3904WT1G_SC70-3 LMBT3904WT1G_SC70-3
@ CE339
@ CE35
@ CE272
17
E
C C
A_CHIP_ID0 10 GPE2 18
B
2 2 2
A_CHIP_ID1 23 CHIP_ID0 GPE3 20 DP2_GPU_SEL# <31> B B
CHIP_ID1 GPE4 21 RTD3_SELECT 1 C 2 E 2 E
RTD3_SELECT <42> Channel Location
3
GPE5 22
EXPANDER_ALERT# 11 GPE6 SLOT5_SSD_PWR_EN <54> Rest=1.58K , Tp=96 degree REM_DIODE3_N
ALERT# 25 CPU REM_DIODE1_N <58> REM_DIODE3_N <58>
15 GPC0 28 SLOT6_SSD_PWR_EN <54> DP1/DN1 OTP
VSS GPC1 27 DGPU_SELECT# <29,38>
29 GPC2 26 DID2_GPIO1 <38> CPU
EPAD GPC3 DID2_GPIO2 <38> DP1A/DN1A VR DP4/DN4 for WWAN on QE6,
IT8306FN-CX-R_QFN28_4X4 place QE6 close to JNGFF1 and CE39 close to QE6
DP2A/DN2A M.2 2280 DN2A/DP2A for M.2 2280 on QE7, place QE7 REM_DIODE4_P
REM_DIODE4_P <58>
+3.3V_ALW
close to JNGFF3 and CE46 closeREM_DIODE2_P
to QE7
100P_0402_50V8J
+3.3V_ALW DP3/DN3 DIMM(TOP) REM_DIODE2_P <58> QE6
100P_0402_50V8J
@ CE39
1
1
C LMBT3904WT1G_SC70-3
1
1
3
10K_0402_5%
10K_0402_5%
@ CE46
2
E
DP4/DN4 WWAN
1
10K_0402_5%
@ RE565
@ RE566
2
B B
4 2 E 4
3
2
RE564
C
LMBT3904WT1G_SC70-3
1
QE7
2
REM_DIODE2_N REM_DIODE4_N
REM_DIODE2_N <58> REM_DIODE4_N <58>
2
A_CHIP_ID0
WRST# A_CHIP_ID1
QE26,QE3,QE104,QE7,QE6 change from SB000008P00 to SB000013V00
1
1U_0201_10V6M
1
10K_0402_5%
10K_0402_5%
CE343
RE567
RE568
2
Title
EC MEC5106 SUPPORT
A B C D E
5 4 3 2 1
Vinafix.com
D D
C C
Reserve
B B
A A
Secure & Reset IC
5 4 3 2 1
5 4 3 2 1
Vinafix.com
D D
C C
Reserve
B B
A A
LEDs(Controller)
5 4 3 2 1
A B C D
Touch Pad
+3.3V_RUN +3.3V_TP M BIST BATT_YELLOW#
JUMP@
PJP35
1 2 +3.3V_TP
Vinafix.com
PAD-OPEN1x1m @ DZ12
1 2
<27,58,85> ACAV_IN
4.7K_0402_5%
4.7K_0402_5%
1
3
RB751S40T1G_SOD523-2 R1=10K;R2=10K
RZ18
RZ19
2 1 M_BIST_R
1 <58> M_BIST R2 1
@ RZ1415 0_0402_5% QZ3
+3.3V_ALW BAT1_LED#_R 2 LMUN5111T1G_SC70-3
PS2 1 2
2
R1
RZ1482 1M_0402_5%
2 1 DAT_TP_SIO_R 1 2
<58> DAT_TP_SIO_I2C_CLK <58,62> PCH_RSMRST#
@ RZ22 0_0402_5% @ RZ1413 330K_0402_5%
1
2 1 CLK_TP_SIO_R C
<58> CLK_TP_SIO_I2C_DAT
1
@ RZ23 0_0402_5% 2 1 2 QZ22
CZ218 2.2U_0201_6.3V6M B LMBT3904W T1G_SC70-3
10P_0402_50V8J
10P_0402_50V8J
E
3
1
1
1 2
CZ80
CZ81
1 2 I2C1_SDA_TP_R RZ25 150_0402_5%
@ RZ346
<58,59> POWER_SW_IN#
0_0402_5%
2
1 2 I2C1_SCK_TP_R
@ RZ347 0_0402_5%
I2C From EC
+3.3V_TP +3.3V_TP
Battery LED
10K_0402_5%
10K_0402_5%
1
1
@ @
1
2.2K_0402_5%
2.2K_0402_5%
RZ116
RZ117
BATT_WHITE#
RZ20
RZ21
1 2
<58> BAT2_LED#
RZ361 240_0402_5%
2
2
2
1 2 I2C1_SDA_TP_R
<19> I2C1_SDA_TP BATT_YELLOW#
@ RZ26 0_0402_5% 1 2
I2C1_SCK_TP_R <58> BAT1_LED#
1 2 RZ28 200_0402_5%
<19> I2C1_SCK_TP
@ RZ29 0_0402_5%
2 2
I2C From PCH
Plan is for I2C to be driven by the EC for Win7 and Pre-OS (will utilize Intel I2C drivers for Win7)
For Win8.1 and 10 the EC will control TP over I2C Pre-OS and then the PCH will drive I2C when in Windows
Route PS2 from EC to the touch pad also for contingency plan if I2C has issues
Breath LED
QZ7
L2N7002W T1G_SC-70-3
3 1 BREATH_LED#_Q 1 2 BREATH_LED#_R
D
<58> BREATH_LED# BREATH_LED#_R <77>
RZ32 270_0402_5%
G
RSMRST circuit
2
MASK_BASE_LEDS#
+3.3V_ALW
@ CZ82
1 2
0.1U_0201_10V6K
5
VCC
<58,62> PCH_RSMRST# 1
2
IN1
OUT
4
PCH_RSMRST#_AND <7,18> To LED/B Conn
GND
<18,43,86> ALW_PWRGD_3V_5V IN2

UZ6
MC74VHC1G08DFT2G_SC70-5 +5V_ALW _R
3
Link CIS
3 3
0.1U_0201_10V6K
1
+3.3V_ALW_R
CZ527
@ CZ93
2 1 2
5
Change part number / foorprint 0.1U_0201_10V6K
Keyboard JLED1
VCC
1 1
<51,58> LED_MASK#
BATT_YELLOW # 2 1 IN1 4 MASK_BASE_LEDS#
Change part number / foorprint BATT_W HITE# 3 2 2 2 OUT
GND
JKBTP1 4 3 <59,77> LID_CL# IN2
1 5 4 4
<18> KB_DET# 2 1 6 5 UZ10
3
3 2 2 6 6 MC74VHC1G08DFT2G_SC70-5
4 3 7
5 4 4 G1 8
+5V_RUN
+3.3V_ALW
6 5 G2 9
7 6 6 G3 10
<58> BC_INT#_ECE1117 8 7 G4
<58> BC_DAT_ECE1117
9 8 8 CVILU_CF2006FV0RK-NH
FOLLOW X10 H Dell GPIO map 10 9 CONN@
<58> BC_CLK_ECE1117
2 1 11 10 10
<58> PTP_DISABLE#
@ RZ1484 0_0402_5% 12 11
+3.3V_TP DAT_TP_SIO_R 13 12 12 Footprint same with CF2006FV0RK-NH
CLK_TP_SIO_R 14 13
15 14 14
16 15
<17,58> TOUCHPAD_INTR# 17 16 16
I2C1_SDA_TP_R 18 17
I2C1_SCK_TP_R 19 18 18
20 19 LED Circuit Control Table
20 20
21
G1 22 LED_MASK# LID_CL#
G2 23
G3 24
G4
CVILU_CF2020FV0RK-NH
Mask All LEDs (Sniffer Function) 0 X
CONN@ Mask Base MB LEDs (Lid Closed) 1 0
4
+3.3V_TP +3.3V_ALW +5V_RUN 4
Do not Mask LEDs (Lid Opened) 1 1

PN Change to SP01002LT00
0.1U_0201_25V6K
0.1U_0201_25V6K
0.1U_0201_25V6K
Footprint same CF2020FV0RK-NH

1
1
@ CZ90
@ CZ91
@ CZ92
2
Place close to JKBTP1
Title
KB / TP / LED / LID
Custom 1.0
A B C D
A B C D
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1 1
2 2
Reserve
3 3
4 4
KB/TP/LED/LID
A B C D
5 4 3 2 1
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D D
C C
Reserve
B B
A A
KB/TP/LED/LID
5 4 3 2 1
5 4 3 2 1
USH CONN
CONN@
JUSH1
+3.3V_ALW +3.3V_M_TPM 1 2 28
+3.3V_M_TPM
@ RZ369 1 2 0_0402_5%
Vinafix.com
+3.3V_RUN
@ RZ367
1 2
0_0402_5%
+UZ12_TPM
follow naming rule
+19.5VB
1 2 +PWR_SRC_R 26
GND2
GND1
27
@ RZ89 0_0402_5% @ RZ85 0_0402_5% 25 26

+3.3V_ALW_PCH 24 25
10U_0402_6.3V6M
D +3.3V_M_TPM D
<58> CV2_ON POA_WAKE#_R 23 24
0.1U_0201_25V6K
1 1 @ RZ364 1 2 100_0402_5%
EC_FPM_EN 22 23
CZ75
@ RZ1483 1 2 0_0402_5%
21 22
CZ50
1 2
@ RZ368 0_0402_5% JUSH1 FOLLOW X10 USH schmatic 20 21
2 2 19 20
<15> USB20_N10 18 19
1 2 TPM_PIRQ# <15> USB20_P10 17 18
RZ69 10K_0402_5% 16 17
<58,59> USH_EXPANDER_SMBCLK 15 16
<58,59> USH_EXPANDER_SMBDAT 14 15
<58> BCM5882_ALERT# 13 14
12 13
11 12
+3.3V_ALW_R
10 11
+3.3V_ALW +3.3V_M_TPM 9 10
+5V_ALW_R
8 9
+3.3V_RUN
JUSH1 FOLLOW X10 USH schmatic 7 8
+5V_RUN
place CZ51,CZ52 as close as UZ12.1 PCH_SPI_CLK_2_R @ RZ114 1 2 0_0402_5% USH_RST#_R 6 7
5 6
<58> USH_PWR_STATE# 4 5
33_0402_5%
DZ8
3 4
2
CONTACTLESS_DET#_R
@EMI@
2 1
<14> CONTACTLESS_DET# 2 3
RZ63
USH_DET# 1 2
12P_0402_50V8J
RF@ CZ57
68P_0402_50V8J
RF@ CZ58
12P_0402_50V8J
RF@ CZ59
68P_0402_50V8J
RF@ CZ60
1 1 1 1 RB751S-40_SOD523-2
<58> USH_DET# 1
JUSH1 FOLLOW X10 USH schmatic
Remove DZ7, RZ87
1 HRS_TF31C-26S-0P5SH-800
0.1U_0201_25V6K
2 2 2 2 Update symbol Ver. 0725
1
@EMI@
CZ56
+3.3V_ALW
RF Request RF Request
2
C C
2
JUMP@
PJP391
PAD-OPEN1x1m
+3.3V_ALW_R
1
+3.3V_ALW_UZ12 1 2 USH_EXPANDER_SMBCLK
RZ8 4.7K_0402_5%
1 2 USH_EXPANDER_SMBDAT
0.1U_0201_10V6K
10U_0402_6.3V6M
RZ9 4.7K_0402_5%
1 1
CZ52
+3.3V_RUN
CZ51
1 2 USH_PWR_STATE#
1
2 2 RZ10 100K_0402_5%
@ RZ362
10K_0402_5% Change part number and need apply symbol 1/15
UZ12
1
2
1 2 TPM_GPIO0 29 VSB @ 1 2
<14,18,19> SIO_SLP_S0# @ RZ112 0_0402_5% 30 GPIO0/SDA 8 +UZ12_TPM RZ366 0_0402_5%
+3.3V_M_TPM USH_RST#_R Close to JUSH1
1 2 TPM_LPM# 3 GPIO1/SCL VDD1 14 +UZ12_VHIO @ RZ365 1 2 0_0402_5% +5V_ALW_R +5V_RUN +3.3V_RUN +3.3V_ALW_R
+3.3V_RUN
6 GPIO2/GPX VHIO1 22
0.047U_0201_10V6K
@ RZ363 0_0402_5%
GPIO3/BADD VHIO2
0.1U_0201_10V6K
0.1U_0201_10V6K
10U_0603_10V6M
1
2 33_0402_5% PCH_SPI_D1_2_R
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
RZ58 1 24 2 1 1 1
<17> PCH_SPI_D1_R1 2 33_0402_5% PCH_SPI_D0_2_R 21 LAD0/MISO NC1 7
CZ61
RZ59 1 1 1 1 1
<17> PCH_SPI_D0_R1 18 LAD1/MOSI NC2 10
@
CZ54
CZ53
CZ55
2
<19> TPM_PIRQ# LAD2/SPI_IRQ# NC3
CZ64
CZ66
CZ67
CZ68
15 11
LAD3 NC4 25 2 2 2
EMI@ RZ60 1 2 33_0402_5% PCH_SPI_CLK_2_R 19 NC5 26 For ESD solution 2 2 2 2
<17> PCH_SPI_CLK_R1 @ RZ61 1 2 0_0402_5% PCH_SPI_CS#2_R 20 LCLK/SCLK NC6 31
B <17> PCH_SPI_CS#2 17 LFRAME#/SCS# NC7 B
<17> PLTRST_TPM# 27 LRESET#/SPI_RST#/SRESET# 9
1 TPM_GPIO4 13 SERIRQ GND1 16
T284 @ PAD~D CLKRUN#/GPIO4/SINT# GND2
28 23 CZ53,CZ55 as close as UZ12.14
LPCPD# GND3 32
1
10K_0402_5%
GND4 33 CZ54 as close as UZ12.22 +5V_ALW_R +5V_RUN +3.3V_RUN +3.3V_ALW_R

RZ62 @
4
5 PP PGND 12 RF Request
TEST Reserved RF Request
need check EA before POP
68P_0402_50V8J
RF@ CZ69
68P_0402_50V8J
RF@ CZ71
68P_0402_50V8J
RF@ CZ72
68P_0402_50V8J
RF@ CZ73
NPCT750JABYX_QFN32_5X5
2
USH_EXPANDER_SMBCLK 1 2 1 1 1 1
@RF@CZ62 68P_0402_50V8J
USH_EXPANDER_SMBDAT 1 2
@RF@CZ63 68P_0402_50V8J 2 2 2 2
Pop Depop Comment

VDD - V_RUN Power
NPCT65x RZ89, RZ366, RZ62 RZ365, RZ367 VHIO - V_SPI Power
Option1 (recommended)
NPCT75x RZ89, RZ365 RZ367, RZ366, RZ62 VDD and VHIO - V_RUN power
Option2 (for Z1 sample [early sample])
NPCT75x RZ367, RZ366 RZ89, RZ365, RZ62 VDD and VHIO - V_SPI power
A A
Title
TPM/USH
5 4 3 2 1
5 4 3 2 1
Vinafix.com
D D
C C
Reserve
B B
A A
HDD/ODD/FFS Conn
5 4 3 2 1
5 4 3 2 1
+3.3V_SSD3
SSD +3.3V_SSD3
CLOSE TO PIN 62,64,66

NGFF slot_3 Key M
10K_0402_5%
2
0.01U_0402_16V7K
0.01U_0402_16V7K
0.1U_0201_10V6K
10U_0402_6.3V6M
330U_D2E_6.3VM_R25M
@ CN179
1
RN37
1 1
1
@ CN175
+
CN176
CN177
CN178
CONN@
+3.3V_SSD3
JNGFF3
2
2 2 2
@ SLOT3_DEVSLP 1 2
3 GND1 3P3VAUX1 4 Follow X10 H Dell GPIO map 180705_Roger
PCIE_PRX_DTX_N9 5 GND2 3P3VAUX2 6
Vinafix.com
<14> PCIE_PRX_DTX_N9 PCIE_PRX_DTX_P9 7 PERn3 NC2 8 @ RN219 1 2 0_0402_5%
<14> PCIE_PRX_DTX_P9 PERp3 NC3 SSD_SCP# <58,67,68>
9 10 1 2
0.22U_0201_6.3V6K 1 2 CN65 PCIE_PTX_C_DRX_N9 11 GND3 DAS/DSS# 12 @ RN217 0_0402_5% SATALED# <14,67,68>
<14> PCIE_PTX_DRX_N9 PCIE_PTX_C_DRX_P9 PETn3 3P3VAUX3
0.22U_0201_6.3V6K 1 2 CN66 13 14
<14> PCIE_PTX_DRX_P9 PETp3 3P3VAUX4
15 16
D PCIE_PRX_DTX_N10 17 GND4 3P3VAUX5 18 D
<14> PCIE_PRX_DTX_N10 PCIE_PRX_DTX_P10 19 PERn2 3P3VAUX6 20
<14> PCIE_PRX_DTX_P10 21 PERp2 NC4 22 +3.3V_SSD3
0.22U_0201_6.3V6K 1 2 CN67 PCIE_PTX_C_DRX_N10 23 GND5 NC5 24
<14>
<14>
PCIE_PTX_DRX_N10
PCIE_PTX_DRX_P10
0.22U_0201_6.3V6K 1 2 CN68 PCIE_PTX_C_DRX_P10 25 PETn2 NC6 26 CLOSE TO PIN 2,4
27 PETp2 NC7 28
PCIE_PRX_DTX_N11 GND6 NC8
0.01U_0402_16V7K
0.01U_0402_16V7K
0.1U_0201_10V6K
10U_0402_6.3V6M
29 30
<14> PCIE_PRX_DTX_N11 PCIE_PRX_DTX_P11 31 PERn1 NC9 32
PERp1 NC10 1 1
1
@ CN279
33 34
GND7 NC11
CN277
CN276
CN174
0.22U_0201_6.3V6K 1 2 CN69 PCIE_PTX_C_DRX_N11 35 36
<14> PCIE_PTX_DRX_N11 PCIE_PTX_C_DRX_P11 PETn1 NC12
0.22U_0201_6.3V6K 1 2 CN70 37 38
<14> PCIE_PTX_DRX_P11 SLOT3_DEVSLP <18>
2
39 PETp1 DEVSLP 40 2 2
PCIE_PRX_DTX_P12 41 GND8 NC13 42
<14> PCIE_PRX_DTX_P12 PCIE_PRX_DTX_N12 43 PERn0/SATA-B+ NC14 44
<14> PCIE_PRX_DTX_N12 45 PERp0/SATA-B- NC15 46
+3.3V_RUN <14> PCIE_PTX_DRX_N12 PCIE_PTX_C_DRX_P12 PETn0/SATA-A- NC17
0.22U_0201_6.3V6K 1 2 CN72 49 50
<14> PCIE_PTX_DRX_P12 PETp0/SATA-A+ PERST# PCH_PLTRST#_R <17,42,52,67,68>
51 52
GND10 CLKREQ# CLKREQ_PCIE#7 <16>
10K_0402_5%
53 54
<16> CLK_PCIE_N7 REFCLKN PEWake# PCIE_WAKE# <27,42,52,59,67,68>
2
55 56
RN200 <16> CLK_PCIE_P7 REFCLKP NC18
57 58
GND11 NC19
+3.3V_SSD3
CLOSE TO PIN 12,14,16,18

1
59 60 SUSCLK_R3 1 2 SUSCLK
NC1 SUSCLK(32kHz) SUSCLK <18,52,68>
0.01U_0402_16V7K
0.1U_0201_10V6K
10U_0402_6.3V6M
61 62 @ RN99 0_0402_5%
<14> M2_SLOT3_PEDET 63 PEDET(NC-PCIE/GND-SATA) 3P3VAUX7 64
GND12 3P3VAUX8 1 1
1
65 66
GND13 3P3VAUX9
CN282
CN280
CN281
67
70 GND14 68
PEDET Module Type
2
71 NPTH1 GND15 69 2 2
NPTH2 GND16
BELLW _SD-80159-4221
0 SATA Update symbol Ver. 0725
1 PCIE
C C
+3.3V_SSD4 +3.3V_SSD4

10K_0402_5%
SSD
2
0.01U_0402_16V7K
0.01U_0402_16V7K
0.1U_0201_10V6K
10U_0402_6.3V6M
330U_D2E_6.3VM_R25M
@ CN193
RN202 1
@ CN190
1 1
1
+
NGFF slot_4 Key M
CN191
CN192
CN188
1
2
2 2 2
@ SLOT4_DEVSLP
Change part number / foorprint +3.3V_SSD4
JNGFF4
1 2
3 GND3 3P3VAUX_1 4 Follow X10 H Dell GPIO map 180705_Roger
PCIE_PRX_DTX_N20 5 GND4 3P3VAUX_2 6
<14> PCIE_PRX_DTX_N20 PCIE_PRX_DTX_P20 7 PERn3 NC1 8 @ RN220 1 2 0_0402_5%
<14> PCIE_PRX_DTX_P20 SSD_SCP# <58,67,68>
9 PERp3 NC2 10 1 2
0.22U_0201_6.3V6K 1 2 CN180 PCIE_PTX_C_DRX_N20 11 GND5 DAS/DSS# 12 @ RN218 0_0402_5% SATALED# <14,67,68> +3.3V_SSD4
<14> PCIE_PTX_DRX_N20
0.22U_0201_6.3V6K 1 2 CN181 PCIE_PTX_C_DRX_P20 13 PETn3 3P3VAUX_3 14
<14> PCIE_PTX_DRX_P20
15 PETp3 3P3VAUX_4 16 CLOSE TO PIN 2,4
PCIE_PRX_DTX_N19 17 GND6 3P3VAUX_5 18
<14> PCIE_PRX_DTX_N19 PCIE_PRX_DTX_P19 19 PERn2 3P3VAUX_6
0.01U_0402_16V7K
0.01U_0402_16V7K
0.1U_0201_10V6K
10U_0402_6.3V6M
20
<14> PCIE_PRX_DTX_P19 21 PERp2 NC3 22 1 1
23 GND7 NC4
1
@ CN286
0.22U_0201_6.3V6K 1 2 CN182 PCIE_PTX_C_DRX_N19 24
25 PETn2 NC5
CN285
CN283
CN189
0.22U_0201_6.3V6K 1 2 CN183 PCIE_PTX_C_DRX_P19 26
27 PETp2 NC6 28
2
PCIE_PRX_DTX_N18 29 GND8 NC7 30 2 2
FFS_INT2_Q <54>
<14> PCIE_PRX_DTX_P18 33 PERp1 NC9 34 HDD_DET#
0.22U_0201_6.3V6K 1 2 CN184 PCIE_PTX_C_DRX_N18 35 GND9 NC10 36 HDD_DET# <14>
0.22U_0201_6.3V6K 1 2 CN185 PCIE_PTX_C_DRX_P18 37 PETn1 NC11 38
<14> PCIE_PTX_DRX_P18 SLOT4_DEVSLP <18>
39 PETp1 DEVSLP 40
+5V_HDD
B
<14> PCIE_PRX_DTX_P17 PCIE_PRX_DTX_N17 43 PERn0/SATA-B+ NC13 44 B
+3.3V_RUN 0.22U_0201_6.3V6K 1 2 CN186 PCIE_PTX_C_DRX_N17 47 GND11 NC15 48
0.22U_0201_6.3V6K 1 2 CN187 PCIE_PTX_C_DRX_P17 49 PETn0/SATA-A- NC16 50 +3.3V_SSD4
<14> PCIE_PTX_DRX_P17 PCH_PLTRST#_R <17,42,52,67,68>
51 PETp0/SATA-A+ PERST#
10K_0402_5%
52
53 GND12 CLKREQ# CLKREQ_PCIE#8 <16> CLOSE TO PIN 12,14,16,18
2
54
<16> CLK_PCIE_N8 PCIE_WAKE# <27,42,52,59,67,68>
55 REFCLKN PEWake#
RN203
56
<16> CLK_PCIE_P8
57 REFCLKP NC17
0.01U_0402_16V7K
0.1U_0201_10V6K
10U_0402_6.3V6M
58
GND13 NC18
1 1
1
1
CN288
CN287
CN289
2
67 68 SUSCLK_R4 1 2 SUSCLK 2 2
69 NC SUSCLK(32kHz) 70 @ RN205 0_0402_5%
<14> M2_SLOT4_PEDET 71 PEDET(NC-PCIE/GND-SATA) 3P3VAUX_7 72
73 GND14 3P3VAUX_8 74
75 GND15 3P3VAUX_9
PEDET Module Type 78
79
GND16
NPTH1 GND1
76
77
NPTH2 GND2
LOTES_AP-APCI0356-P001A~D
0 SATA CONN@
1 PCIE
+3.3V_ALW _R JUMP@
@ CZ540
1 2 +5V_HDD source 1
PJP32
2 2.0A +5V_HDD
0.1U_0201_10V6K UZ23 PAD-OPEN1x1m
+5V_ALW_R
UZ60 1 7
VIN1 VOUT1
5
SN74AHC1G08DCKR_SC70-5 2 8 +5V_HDD_UZ23 1 2
HDD_IFDET 1 VIN2 VOUT2 CZ129 0.1U_0201_10V6K
P
IN1 4 3 6 1 2
RUN_ON 2 O ON CT CZ130 470P_0402_50V7K
<11,22,58,59,70,89> RUN_ON IN2
G
1
4
3
A RZ541 VBIAS 5 A
1M_0201_5% GND1 9
GND2
HDD_IFDET Module Type

2
AOZ1336DI_DFN8_2X2
0 NVME
1 HDD DELL CONFIDENTIAL/PROPRIETARY

Title
SSD SLOT3 / 4
Custom 1.0
5 4 3 2 1
5 4 3 2 1
SSD
NGFF slot_5 Key M
Vinafix.com 1
CONN@
JNGFF5
2
+3.3V_SSD5 +3.3V_SSD5

D GND2 3P3VAUX2 D
0.01U_0402_16V7K
0.01U_0402_16V7K
0.1U_0201_10V6K
10U_0402_6.3V6M
330U_D2E_6.3VM_R25M
@ CN207
PCIE_PRX_DTX_N24 5 6
<15> PCIE_PRX_DTX_N24 PERn3 NC2 1
PCIE_PRX_DTX_P24 7 8 @ RN475 1 2
PERp3 NC3 SSD_SCP# <58,67,68> 1 1
1
@ CN203
9 10 1 2 0_0402_5% +
GND3 DAS/DSS# SATALED# <14,67,68>
CN204
CN205
CN206
0.22U_0201_6.3V6K 1 2 CN194 PCIE_PTX_C_DRX_N24 11 12 @ RN216 0_0402_5%
<15> PCIE_PTX_DRX_N24 PETn3 3P3VAUX3
0.22U_0201_6.3V6K 1 2 CN195 PCIE_PTX_C_DRX_P24 13 14
2
15 PETp3 3P3VAUX4 16 2 2 2
<15> PCIE_PRX_DTX_P23 21 PERp2 NC4 22
<15> PCIE_PTX_DRX_N23 PETn2 NC6
<15> PCIE_PTX_DRX_P23 PETp2 NC7
27 28
PCIE_PRX_DTX_N22 29 GND6 NC8 30
<15> PCIE_PTX_DRX_P22 PETp1 DEVSLP
39 40 +3.3V_SSD5
PCIE_PRX_DTX_N21 41 GND8 NC13 42
SLOT5 NO SATA so +,- different from SLOT4
<15> PCIE_PRX_DTX_N21 PCIE_PRX_DTX_P21 43 PERn0/SATA-B+ NC14 44 CLOSE TO PIN 2,4
<15> PCIE_PRX_DTX_P21 45 PERp0/SATA-B- NC15 46
2 CN200 PCIE_PTX_C_DRX_N21 GND9 NC16
0.01U_0402_16V7K
0.01U_0402_16V7K
0.1U_0201_10V6K
10U_0402_6.3V6M
0.22U_0201_6.3V6K 1 47 48
+3.3V_RUN <15> PCIE_PTX_DRX_N21 PETn0/SATA-A- NC17
0.22U_0201_6.3V6K 1 2 CN201 PCIE_PTX_C_DRX_P21 49 50 1 1
1
@ CN298
51 52
GND10 CLKREQ# CLKREQ_PCIE#9 <16>
10K_0402_5%
CN297
CN295
CN202
53 54
2
55 56
<16> CLK_PCIE_P9
2
REFCLKP NC18 2 2
RN208
57 58
GND11 NC19
1
59 60 SUSCLK_R5 1 2 SUSCLK
NC1 SUSCLK(32kHz) SUSCLK <18,52,67>
61 62 @ RN207 0_0402_5%
<14> M2_SLOT5_PEDET 63 PEDET(NC-PCIE/GND-SATA) 3P3VAUX7 64
65 GND12 3P3VAUX8 66
67 GND13 3P3VAUX9
70 GND14 68
PEDET Module Type 71 NPTH1
NPTH2
GND15
GND16
69
+3.3V_SSD5
BELLW _SD-80159-4221
C
0 SATA Update symbol Ver. 0725 CLOSE TO PIN 12,14,16,18 C
0.01U_0402_16V7K
0.1U_0201_10V6K
10U_0402_6.3V6M
1 PCIE 1 1
CN301
CN299
CN300
2
2 2
+3.3V_SSD6
+3.3V_SSD6
SSD
10K_0402_5%
@ RN210
0.01U_0402_16V7K
0.01U_0402_16V7K
0.1U_0201_10V6K
10U_0402_6.3V6M
330U_D2E_6.3VM_R25M
@ CN217
1
2
NGFF slot_6 Key M 1 1
1
@ CN219
+
CN220
CN221
CN216
2
2
CONN@ 2 2 2
1
+3.3V_SSD6
SLOT6_DEVSLP JNGFF6
1 2
B B
<14> PCIE_PRX_DTX_N16 PCIE_PRX_DTX_P16 7 PERn3 NC2 8 @ RN476 1 2
<14> PCIE_PRX_DTX_P16 PERp3 NC3 SSD_SCP# <58,67,68>
9 10 1 2 0_0402_5%
0.22U_0201_6.3V6K 1 2 CN208 PCIE_PTX_C_DRX_N16 11 GND3 DAS/DSS# 12 @ RN474 0_0402_5% SATALED# <14,67,68>
<14> PCIE_PTX_DRX_N16 PETn3 3P3VAUX3
<14> PCIE_PTX_DRX_P16 PETp3 3P3VAUX4
15 16
PCIE_PRX_DTX_N15 17 GND4 3P3VAUX5 18 +3.3V_SSD6
<14> PCIE_PRX_DTX_P15 21 PERp2 NC4 22 CLOSE TO PIN 2,4
0.01U_0402_16V7K
0.01U_0402_16V7K
0.1U_0201_10V6K
10U_0402_6.3V6M
<14> PCIE_PTX_DRX_P15 PETp2 NC7
27 28 1 1
1
PCIE_PRX_DTX_N14 GND6 NC8
@ CN310
29 30
<14> PCIE_PRX_DTX_N14 PERn1 NC9
CN309
CN306
CN218
PCIE_PRX_DTX_P14 31 32
2
0.22U_0201_6.3V6K 1 2 CN212 PCIE_PTX_C_DRX_N14 35 GND7 NC11 36 2 2
<14> PCIE_PTX_DRX_P14 PETp1 DEVSLP SLOT6_DEVSLP <18>
39 40
<14> PCIE_PRX_DTX_P13 PCIE_PRX_DTX_N13 43 PERn0/SATA-B+ NC14 44
+3.3V_RUN <14> PCIE_PTX_DRX_N13 PETn0/SATA-A- NC17
51 52
53 GND10 CLKREQ# 54 CLKREQ_PCIE#10 <16>
10K_0402_5%
55 56
<16> CLK_PCIE_P10 REFCLKP NC18
2
57 58 +3.3V_SSD6
GND11 NC19
RN211
CLOSE TO PIN 12,14,16,18
0.01U_0402_16V7K
0.1U_0201_10V6K
10U_0402_6.3V6M
1
59 60 SUSCLK_R6 1 2 SUSCLK 1 1
1
61 NC1 SUSCLK(32kHz) 62 @ RN213 0_0402_5%
<14> M2_SLOT6_PEDET PEDET(NC-PCIE/GND-SATA) 3P3VAUX7
CN312
CN311
CN313
63 64
65 GND12 3P3VAUX8 66
2
67 GND13 3P3VAUX9 2 2
70 GND14 68
PEDET Module Type 71 NPTH1
NPTH2
GND15
GND16
69
BELLW _SD-80159-4221
A 0 SATA Update symbol Ver. 0725 A
1 PCIE
Title
SSD SLOT5 / 6
Custom 1.0
5 4 3 2 1
5 4 3 2 1
Vinafix.com
D D
C C
Reserve
B B
A A
eMMC / UFS
5 4 3 2 1
5 4 3 2 1
Default short
+3.3V_RUN JUMP@ +3.3V_MV
1U_0201_10V6M
2
PJP69
0.1U_0201_25V6K
1 2
CR244
1U_0201_10V6M
2
+3.3V_MMI_AUX
CR245
CR246
PAD-OPEN1x2m +3.3V_MV
1
UR1
+3.3V_MV +3.3V_MMI_AUX
Vinafix.com
12 24 DV33_18
1 2
support D3 Hot(if D3 cold , need Add MOS on/of f 3V3AUX) +1.05V_VDD 18 HV_LC DV33_18 46 DV10
@ RR200 0_0603_5% 39 MV33 DV10 19 SDVDD1
40 HV_SWREG_1 SDVDD1 20 SDVDD2
45 HV_SWREG_2 SDVDD2 +1.05V_VDD
D AUX3V3 D
3 10 PCIE_PRX_C_DTX_P6CR204 2 1 0.22U_0201_6.3V6K
6 VDDRX HSOP 11 PCIE_PRX_C_DTX_N6CR206 2 1 PCIE_PRX_DTX_P6 <15> LR1
0.22U_0201_6.3V6K
9 VDDCMU HSON 37 REG_OUT PCIE_PRX_DTX_N6 <15> 1 2
16 VDDTX REG_OUT_1 38 2.2UH_HPC252012NF-2R2M_1.3A_20%
<17> PLTRST_MMI# SDV10 REG_OUT_2
30
0.22U_0201_6.3V6K 1 2 CR203 PCIE_PTX_C_DRX_P6 31 VDD_LN1
10U_0402_6.3V6M
0.1U_0201_25V6K
+3.3V_MV <15> PCIE_PTX_DRX_P6 1 2 CR205 PCIE_PTX_C_DRX_N6 VDD_LN0 42
0.22U_0201_6.3V6K GPIO0
<15> PCIE_PTX_DRX_N6 RTS5243 GPIO_0 1
2
1 48 MEDIACARD_IRQ#
CR214
CR215
<16> CLK_PCIE_P1 PERST# WAKE#
<16> CLK_PCIE_N1
4
HSIP
QFN48 SD_D2
27 SD_1_D2 1 2 SD_1_D2_R
5 26 SD_1_D3 @ RR228 1 2 0_0402_5% SD_1_D3_R
1
7 HSIN SD_D3 25 SD_1_CMD_R @ RR229 1 2 0_0402_5% SD_1_CMD 2
1 2 EN_SWR 1 2 8 REFCLKP SD_CMD 28 SD_1_P1 @ RR230 0_0402_5%
@ RR231 0_0402_5% @ RR232 0_0402_5% SD_1_CD# 47 REFCLKN LN1_P 29 SD_1_N1
43 SD_CD# LN1_N 34
EN_SWR: SDWP
SD_WP SCS
SCS
1: Internal SWR output enable EN_SWR 41 33 SD_1_P0
EN_SWR LN0_P 32 SD_1_N0
0: Internal SWR output disable LN0_N
+3.3V_MMI_AUX 2
<16> CLKREQ_PCIE#1 CLKREQ#
MISO 14
MOSI 15 MISO 44 RREF RR205 1 2 6.2K_0402_1%
SCK 17 MOSI RREF 35
1 2 MEDIACARD_IRQ# SD_1_D1 @ RR233 1 2 0_0402_5% SD_1_D1_R 21 SCK HG_SWREG_1 36
RR211 10K_0402_5% MEDIACARD_IRQ# <19> SD_1_D0 @ RR234 1 2 0_0402_5% SD_1_D0_R 22 SD_D1/RCLK_N HG_SWREG_2 13 GPIO0 2 1
SD_D0/RCLK_P GND +3.3V_MMI_AUX
SD_1_CLK_R 23 49 10K_0402_5% RR201
SD_CLK E-PAD
RTS5243-GR_QFN48_6X6
QR1
L2N7002WT1G_SC-70-3
SDWP 1 3 SDWP_Q
S
G
2
C C
<14> HOST_SD_WP#
+1.05V_PRIM
1U_0201_10V6M
EMI depop location

@ CR255
1
SD_1_CLK_R RR213 1 EMI@ 2 10_0402_5%SD_1_CLK
@EMI@ CR200
5P_0402_50V8C
2
1
Change CPN from SA00007XR00 to
SA00008R600 3/12 +1.05V_VDD
@ UR4
2
1
2 VIN1
+5V_ALW VIN2
7
VIN thermal VOUT
6 1A 1 2
@ RR227 0_0603_1%
3
0.1U_0201_25V6K
VBIAS
2
@ CR256
4 5
<11,22,58,59,67,89> RUN_ON ON GND
1
Voltage=3.3V
EM5201V_DFN3X3-8-X
B B
+3.3V_MV +1.05V_VDD
Close PIN18 Close PIN9 Close PIN16 Change part number / foorprint
Close PIN40 Close PIN12 JSD1
SDVDD1 4
4.7U_0402_6.3V6M
1 SDVDD2 14 VDD/VDD1
1U_0201_6.3V6M
1U_0201_6.3V6M
0.1U_0201_10V6K
2 VDD2
2
+3.3V_MMI_AUX +3.3V_CARD_SPI SD_1_CMD

CR222
CR223
2 1 2 2 1
100P_0402_50V8J
0.1U_0201_10V6K
0.1U_0201_10V6K
SD_1_CLK 5 CMD
22U_0603_6.3V6M
CR230
CR221
1 1
10U_0402_6.3V6M
0.1U_0201_10V6K
0.1U_0201_25V6K
0.1U_0201_25V6K
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
1 2 CLK
CR217
CR229
CR219
CR220
1 1
0.1U_0201_10V6K
2
2 +3.3V_CARD_SPI +3.3V_CARD_SPI SD_1_CD#
CR218
RR235 @ 0_0402_5% 17
CR234
CR235
CR224
CR225
CR227
CR228
1 2 1 1 2 SDWP_Q 18 CARD DETECT
2 2 WRITE PROTEC
1
2 2 SD_1_D0 7
10K_0402_5%
10K_0402_5%
DAT0/RCLK+
2
SD_1_D1 8
10K_0402_5%
0.1U_0201_25V6K
DAT1/RCLK-
2
SD_1_D2_R
RR236 @
RR237 @
CR236 @
SPI ROM 512K recommand from sourcer 9
DAT2
2
SD_1_D3_R
RR238 @
1 27
@UR3 W25X40CLSSIG_SO8 SD_1_P0 11 CD/DAT3 NPTH2 26
SD_1_N0 12 D0+ NPTH1
Close PIN3 Close PIN31
close to pin8
1
1
SCS 1 8 SD_1_P1 16 D0- 19
1
CS# VCC SD_1_N1 15 D1+ GND1 20
1U_0201_6.3V6M
1U_0201_6.3V6M
MISO 2 7 D1- GND2 21

2 2 1 2 2 1 LN1_P/LN1_N are Differential signal pair
100P_0402_50V8J
100P_0402_50V8J
0.1U_0201_10V6K
0.1U_0201_10V6K
DO(IO1) HOLD# 3 GND3 22

CR239
CR242
3 6 SCK 6 VSS1 GND4 23

Zdiff of Differential Signal pair shoule be 100ohm
CR237
CR238
CR240
CR241
WP# CLK 10 VSS2 GND5 24

10K_0402_5%
VSS3 GND6
2
1 1 2 1 1 2 4 5 MOSI 13 25
GND DI(IO0) VSS4 GND7
T-SOL_156-1110302600
RR239
CONN@
1
+3.3V_MMI_AUX
A A
Close PIN45
Close PIN6 Close PIN30
4.7U_0402_6.3V6M
1
1U_0201_6.3V6M
1U_0201_6.3V6M
0.1U_0201_10V6K
2
CR247
CR248
2 2 1 2 2 1
100P_0402_50V8J
100P_0402_50V8J
0.1U_0201_10V6K
0.1U_0201_10V6K
CR251
CR254
CR249
CR250
CR252
CR253
1
2
1 1 2 1 1 2
Title
Card reader
Custom 1.0
5 4 3 2 1
5 4 3 2 1
+5V_ALW +5V_USB_PW R3 +5V_USB_PW R3

For ESD request +5V_USB_PW R3
ESD@ DI4 UI3 EMI@ LI7 JUSB3
CI16 2 1 0.1U_0201_10V6K USB3_PTX_C_DRX_N4 USB3_PRX_DTX_N4 9 10 1 1 USB3_PRX_DTX_N4 1 12 CHR_USB20_N3 3 4 USB20_N3_R USB3_PTX_C_DRX_P4 9
<18> USB3_PTX_DRX_N4 VIN VOUT STDA_SSTX+
CI13 2 1 0.1U_0201_10V6K USB3_PTX_C_DRX_P4 1
<18> USB3_PTX_DRX_P4 VBUS
150U_B2_6.3VM_R35M
10U_0402_6.3V6M
USB3_PRX_DTX_P4 8 9 2 2 USB3_PRX_DTX_P4 2 USB3_PTX_C_DRX_N4 8
1 <15> USB20_N3 DM_OUT STDA_SSTX-
3 CHR_USB20_P3 2 1 USB20_P3_R USB20_P3_R 3
1 <15> USB20_P3 DP_OUT D+
USB3_PTX_C_DRX_N4 USB3_PTX_C_DRX_N4 +5V_ALW CHR_USB20_P3
CI77
CI76
7 7 4 4 + 10 7
13 DP_IN 11 CHR_USB20_N3 MCM1012B900F06BP_4P USB20_N3_R 2 GND5 10
USB3_PRX_DTX_N4 USB3_PTX_C_DRX_P4 USB3_PTX_C_DRX_P4 <15> USB_OC3# FAULT# DM_IN USB3_PRX_DTX_P4 D- GND1
6 6 5 5 6 11
<18> USB3_PRX_DTX_N4 USB3_PRX_DTX_P4 2 2 ILIM_SEL3 STDA_SSRX+
GND2
RI82 2 1 4 1 2 4 12
Vinafix.com
<18> USB3_PRX_DTX_P4 ILIM_SEL USB3_PRX_DTX_N4 GND6 GND3
3 3 10K_0402_5% @ RI84 0_0402_5% 5 13
5 15 1 2 STDA_SSRX-
GND4
<44,58,71> USB_POW ERSHARE_VBUS_EN EN ILIM_L
8 16 RI79 2 1 @ RI87 0_0402_5% ACON_TCR2C-9U1U91
ILIM_HI 22.1K_0402_1% CONN@
Close to JUSB3
2
PESD5V0U2BT_SOT23-3
6 Update symbol Ver. 0919
D <58,71> USB_POW ERSHARE_EN# CTL1 D
DI5 ESD@
AZ1045-04F_DFN2510P10E-10-9 7 9
8 CTL2 NC 14
CTL3 GND 17
Thermal Pad
SLGC55544CVTR_TQFN16_3X3
1
JUSB3
+5V_ALW _R +5V_USB_PW R1 +5V_USB_PW R1

+5V_USB_PW R1
UI1 JUSB1
1 12 USB3_PTX_C_DRX_P1 9
VIN VOUT 1 SSTX+
VBUS
150U_B2_6.3VM_R35M
10U_0402_6.3V6M
2 USB3_PTX_C_DRX_N1 8
1 <15> USB20_N1 DM_OUT SSTX-
3 USB20_P1_R 3
1 <15> USB20_P1 DP_OUT D+
+5V_ALW_R
CI32
CI14
+ 10 CHR_USB20_P1 7
13 DP_IN 11 CHR_USB20_N1 USB20_N1_R 2 GND5 10
<15> USB_OC1# FAULT# DM_IN USB3_PRX_RD_DTX_P1 D- GND1
6 11
2 2 RI13 2 1 ILIM_SEL1 4 4 SSRX+ GND2 12
10K_0402_5% ILIM_SEL USB3_PRX_RD_DTX_N1 5 GND6 GND3 13
+3.3V_ALW _R JUMP@ +USB2_repeater_VDD 5 15 SSRX- GND4
2
PESD5V0U2BT_SOT23-3
+USB2_repeater_VDD PJP27 16 RI14 2 1 SINGA_2UB1593-120111F~D
ILIM_HI
DI2 ESD@
PAD-OPEN1x1m 22.1K_0402_1% CONN@
1 2 USB2_A_EQ1 2 1 +USB2_repeater_VDD 6
<58,71> USB_POW ERSHARE_EN# CTL1
@ RI62 4.7K_0402_5% +3.3V_ALW _PCH 7 9
CTL2 NC
0.01U_0402_16V7K
0.1U_0201_16V6K
1 2 USB2_A_DE0 Default short 8 14
@ RI63 4.7K_0402_5% 1 1
UI4 LInk CIS ok Close to JUSB1 CTL3 GND 17
1
Thermal Pad
CI60
1 2 USB2_A_EQ0 2 1 1
VDD1
CI61
@ RI64 4.7K_0402_5% RI94 0_0603_5% 13 SLGC55544CVTR_TQFN16_3X3

1 2 USB2_A_DE1 VDD2
DS3@
JUSB1
C 2 2 C
@ RI65 4.7K_0402_5%
1 2 USB2_TEST USB2_A_EQ1 15 4 USB2_B_EQ1
@ RI66 4.7K_0402_5% USB2_A_DE0 16 A_EQ1/SDA_CTL B_EQ1/I2C_ADDR1 3 USB2_B_DE0
1 2 USB2_B_EQ1 USB2_A_EQ0 17 A_DE0/SCL_CTL B_DE0/I2C_ADDR0 2 USB2_B_EQ0
@ RI69 4.7K_0402_5% USB2_A_DE1 18 A_EQ0/NC B_EQ0/NC 6 USB2_B_DE1
1 2 USB2_B_DE0 A_DE1/NC B_DE1/NC
@ RI72 4.7K_0402_5% CI62 2 1 0.1U_0201_10V6K USB3_PTX_C_RD_DRX_P1 19 12 USB3_PTX_RD_DRX_P1 CI63 2 1 0.1U_0201_10V6K USB3_PTX_C_DRX_P1
USB2_B_EQ0 <18> USB3_PTX_DRX_P1 USB3_PTX_C_RD_DRX_N1 A_INp A_OUTp USB3_PTX_RD_DRX_N1 CI64
1 2 CI65 2 1 0.1U_0201_10V6K 20 11 2 1 0.1U_0201_10V6K USB3_PTX_C_DRX_N1
<18> USB3_PTX_DRX_N1 A_INn A_OUTn
@ RI73 4.7K_0402_5%
1 2 USB2_B_DE1 For ESD request
@ RI74 4.7K_0402_5% USB3_PRX_RD_DTX_P1 9 22 USB3_PRX_C_RD_DTX_P1 CI66 2 1 0.1U_0201_10V6K ESD@ DI1 EMI@ LI3
USB3_PRX_RD_DTX_N1 B_INp B_OUTp USB3_PRX_C_RD_DTX_N1 CI67 USB3_PRX_DTX_P1 <18> USB3_PRX_RD_DTX_N1 9 10 USB3_PRX_RD_DTX_N1 CHR_USB20_N1 USB20_N1_R
8 23 2 1 0.1U_0201_10V6K USB3_PRX_DTX_N1 <18> 1 1 3 4
B_INn B_OUTn
USB3_PRX_RD_DTX_P1 8 9 2 2 USB3_PRX_RD_DTX_P1
USB_PW R_SHR_VBUS_RHT_EN2 5 CHR_USB20_P1 2 1 USB20_P1_R
7 PD# 10 USB3_PTX_C_DRX_N1 7 4 USB3_PTX_C_DRX_N1
7 4
USB2_TEST 14 REXT GND1 21 MCM1012B900F06BP_4P
TEST/NC GND2
4.99K_0402_1%
24 25 USB3_PTX_C_DRX_P1 6 6 5 5 USB3_PTX_C_DRX_P1
I2C_EN GPAD
2
2
2K_0402_5%
0_0402_5%
@ @ 1 2
RI75
RI77
3 3 @ RI60 0_0402_5%
PS8713BTQFN24GTR2-A_TQFN24_4X4
RI76
1 2
8 @ RI61 0_0402_5%
CPN: SA00005OR30
1
MPN: PS8713BTQFN24GTR2-A2 AZ1045-04F_DFN2510P10E-10-9

PCB footprint: PS8713BTQFN24GTR2_TQFN24_4X4
B B
+USB3_repeater_VDD +5V_ALW _R +5V_USB_PW R2 +5V_USB_PW R2
+5V_USB_PW R2 UI2 JUSB2

1 2 USB3_A_EQ1 1 12 USB3_PTX_C_DRX_P3 9
@ RI78 4.7K_0402_5% VIN VOUT 1 SSTX+
1 2 USB3_A_DE0 2 USB3_PTX_C_DRX_N3 8 VBUS
<15> USB20_N2 DM_OUT USB20_P2_R SSTX-
150U_B2_6.3VM_R35M
10U_0402_6.3V6M
@ RI81 4.7K_0402_5% 1 3 3
USB3_A_EQ0 +5V_ALW_R <15> USB20_P2 DP_OUT CHR_USB20_P2 D+
1 2 1 10 7
DP_IN GND5
CI1
CI3
@ RI80 4.7K_0402_5% + 13 11 CHR_USB20_N2 USB20_N2_R 2 10
USB3_A_DE1 <15> USB_OC2# FAULT# DM_IN USB3_PRX_RD_DTX_P3 D- GND1
1 2 +3.3V_ALW _R JUMP@ +USB3_repeater_VDD 6 11
@ RI83 4.7K_0402_5% PJP28 RI67 2 1 ILIM_SEL2 4 4 SSRX+ GND2 12
1 2 USB3_TEST PAD-OPEN1x1m 2 2 10K_0402_5% ILIM_SEL USB3_PRX_RD_DTX_N3 5 GND6 GND3 13
@ RI85 4.7K_0402_5% 2 1 +USB3_repeater_VDD 5 15 SSRX- GND4
2
0.1U_0201_16V6K
PESD5V0U2BT_SOT23-3
1 2 USB3_B_EQ1 16 RI71 2 1 SINGA_2UB1593-120111F~D
ILIM_HI
0.01U_0402_16V7K
CI69
DI3 ESD@
@ RI86 4.7K_0402_5%
USB3_B_DE0
+3.3V_ALW _PCH Default short LInk CIS ok 22.1K_0402_1% CONN@
1 2 1 1 6
UI5 <58,71> USB_POW ERSHARE_EN# CTL1
@ RI88 4.7K_0402_5% 7 9
CTL2 NC
CI68
1 2 USB3_B_EQ0 2 1 1 8 14
@ RI89 4.7K_0402_5% RI95 0_0603_5% 13 VDD1 CTL3 GND 17 DI3 17" follow 15"
Close to JUSB2
1
1 2 USB3_B_DE1 2 2 VDD2 Thermal Pad CPN for X1 code 1/21
DS3@
@ RI90 4.7K_0402_5% SLGC55544CVTR_TQFN16_3X3
USB3_A_EQ1 15 4 USB3_B_EQ1
USB3_A_DE0 16 A_EQ1/SDA_CTL B_EQ1/I2C_ADDR1 3 USB3_B_DE0
JUSB2
USB3_A_EQ0 17 A_DE0/SCL_CTL B_DE0/I2C_ADDR0 2 USB3_B_EQ0
USB3_A_DE1 18 A_EQ0/NC B_EQ0/NC 6 USB3_B_DE1
A_DE1/NC B_DE1/NC
CI70 2 1 0.1U_0201_10V6K USB3_PTX_C_RD_DRX_P3 19 12 USB3_PTX_RD_DRX_P3 CI71 2 1 0.1U_0201_10V6K USB3_PTX_C_DRX_P3
<18> USB3_PTX_DRX_P3 A_INp A_OUTp
CI72 2 1 0.1U_0201_10V6K USB3_PTX_C_RD_DRX_N3 20 11 USB3_PTX_RD_DRX_N3 CI73 2 1 0.1U_0201_10V6K USB3_PTX_C_DRX_N3
<18> USB3_PTX_DRX_N3 A_INn A_OUTn
For ESD request
USB3_PRX_RD_DTX_P3 9 22 USB3_PRX_C_RD_DTX_P3 CI74 2 1 0.1U_0201_10V6K ESD@ DI6 EMI@ LI4
Parade_PS8713B USB3_PRX_RD_DTX_N3 8 B_INp
B_INn
B_OUTp
B_OUTn
23 USB3_PRX_C_RD_DTX_N3 CI75 2 1 0.1U_0201_10V6K
USB3_PRX_DTX_P3
USB3_PRX_DTX_N3
<18>
<18>
USB3_PRX_RD_DTX_N3 9 10 1 1 USB3_PRX_RD_DTX_N3 CHR_USB20_N2 3 4 USB20_N2_R
USB3_PRX_RD_DTX_P3 8 9 2 2 USB3_PRX_RD_DTX_P3
USB_PW R_SHR_VBUS_RHT_EN3 5 CHR_USB20_P2 2 1 USB20_P2_R
7 PD# 10 USB3_PTX_C_DRX_N3 7 4 USB3_PTX_C_DRX_N3
A_EQ0 A_EQ1 B_EQ0 B_EQ1 Recommended EQ USB3_TEST REXT GND1
7 4
14 21 MCM1012B900F06BP_4P
TEST/NC GND2
4.99K_0402_1%
24 25 USB3_PTX_C_DRX_P3 6 6 5 5 USB3_PTX_C_DRX_P3
I2C_EN GPAD
2
2
2K_0402_5%
0_0402_5%
0 0 0 0 loss up to 9.5dB @ @ 1 2
RI91
RI93
3 3 @ RI68 0_0402_5%
PS8713BTQFN24GTR2-A_TQFN24_4X4
RI92
A 1 2 A
0 1 0 1 loss up to 4.5dB CPN: SA00005OR30 8 @ RI70 0_0402_5%
1
MPN: PS8713BTQFN24GTR2-A2 Change CPN 1/25

1 0 1 0 loss up to 13dB AZ1045-04F_DFN2510P10E-10-9
PCB footprint: PS8713BTQFN24GTR2_TQFN24_4X4
1 1 1 1 loss up to 7.5dB
Both A_EQ&B_EQ have internal pull-down 150k

Title
USB2/USB3 TYPEA
Custom 1.0
5 4 3 2 1
5 4 3 2 1
Vinafix.com
D D
C C
Reserve
B B
A A
USB2/USB3 TYPEA
5 4 3 2 1
5 4 3 2 1
Vinafix.com
D D
C C
Reserve
B B
A A
USB2/USB3 DB
5 4 3 2 1
5 4 3 2 1
Vinafix.com
D D
C C
Reserve
B B
A A
Dock
5 4 3 2 1
5 4 3 2 1
Vinafix.com
D D
C C
Reserve
B B
A A
USB2
5 4 3 2 1
5 4 3 2 1
Vinafix.com
D D
C C
Reserve
B B
A A
USB2
5 4 3 2 1
5 4 3 2 1
DGFF FAN CPU FAN

Vinafix.com CONN@
ACES_50271-0040N-001
CONN@
ACES_50271-0040N-001 +3.3V_RUN
D 1 1 D
PW M_FAN2 2 1 PW M_FAN1 2 1 PW M_FAN2 2 1
<58> PW M_FAN2 TACH_FAN2 2 <58> PW M_FAN1 TACH_FAN1 2
3 3 10K_0402_5% RZ504
<58> TACH_FAN2 3 <58> TACH_FAN1 3 PW M_FAN1
+5V_RUN 4 +5V_RUN 4 2 1
4 4 10K_0402_5% RZ505
10U_0402_6.3V6M
0.1U_0201_25V6K
10U_0402_6.3V6M
0.1U_0201_25V6K
5 5
BZX384-B5V6 SC76-2
GND1 GND1
1
1 1 6 1 1 6
BZX384-B5V6 SC76-2
GND2 GND2
1
CZ508
CZ506
CZ507
TACH_FAN2 2 1
@ DZ21
JFAN2 JFAN1
CZ505
10K_0402_5% RZ507
DZ20
TACH_FAN1 2 1
2 2 2 2 10K_0402_5% RZ508
2
2
Power Button CONN

JPB1
C POW ER_SW #_MB 1 C
<19,59,77> POW ER_SW #_MB 1
+5V_ALW _R 2
2
+3.3V_ALW _R 3
3
BREATH_LED#_R 4
<62> BREATH_LED#_R 4
5
5
6
<59,62> LID_CL# 6
7
GND1
8
GND2
HRS_TF31-6S-0P5SH
CONN@
Update symbol 11/29
Fiducial Mark
@ FD1
1 CLIP2 CLIP1
1 1
FIDUCIAL MARK~D P1 @RF@ P1 @RF@ Power Switch for debug
@ FD2 YDM_DH792_1P-T YDM_DH792_1P-T
1
Change from RF@ to @RF@
B FIDUCIAL MARK~D B
1 2
<19,59,77> POW ER_SW #_MB 1 2
100P_0402_50V8J
@ FD3
1 1
@ CZ541
@ H1 @ H3 @ H4 @ H5 @ H6 @ H7 @ H8 @ H9 @ H11
FIDUCIAL MARK~D H_3P2 H_3P2 H_2P8 H_3P2 H_2P5 H_3P7 H_3P7 H_3P2 H_3P2
@ PW RSW 1
@ FD4 2 @SHORT PADS~D
1
1
FIDUCIAL MARK~D
Place on Bottom
@ FD5
1
FIDUCIAL MARK~D @ H12 @ H13 @ H14 @ H15 @ H16 @ H17 @ H18 @ H19 @ H20 @ H21 @ H22 @ H23 De-pop for MP 3/20
H_3P7 H_3P7 H_3P2 H_3P2 H_2P5 H_2P8 H_2P5 H_2P8 H_2P0N H_3P2 H_3P2 H_2P8X2P0N @ SW 3
@ FD6 POW ER_SW #_MB 2 1
<19,59,77> POWER_SW#_MB
1
1
FIDUCIAL MARK~D 4 3
Change to NPTH Change to NPTH SKRBAAE010_4P

De-pop after MP
A A
PWRBTN / /SCREW / FAN
5 4 3 2 1
5 4 3 2 1
Vinafix.com
D D
C C
Reserve
B B
A A
DC INTERFACE & Sequence
5 4 3 2 1
5 4 3 2 1
Vinafix.com
D D
C C
Reserve
B B
A A
XDP/CMC/APS...debug
5 4 3 2 1
5 4 3 2 1
Vinafix.com
D D
C C
Reserve
B B
A A
Google Debug & INAs
5 4 3 2 1
5 4 3 2 1
Vinafix.com
D D
C C
B B
A A

Title
Reserve
1.0
LA-H281P
5 4 3 2 1
5 4 3 2 1
PD1
SX34-SMA2
PJPDC1
1 EMI@ PL1 2 1
1 2 NB_PSID 9A Z80 10M 1812_2P +19.5V_DC_IN
2 3
3 4
1 2
S1 PQ10
+19.5V_DC_IN_SS S2 PQ11
+19.5V_SDC_IN
DC_IN+ Source 4 5
5 6
EMI@ PL2 SI7149DP-T1-GE3_POWERPAKSO8-5 SI7149DP-T1-GE3_POWERPAKSO8-5
9A Z80 10M 1812_2P 1 1
6 7 +19.5V_DCIN_JACK 1 2 2 2
7 8 3 5 5 3
0.022U_0603_50V7K
8 9
@EMI@ PC2103
100K_0402_5%
100K_0402_5% 100K_0402_5%
VZ0603M260APT_0603
0.1U_0402_25V6
EMB80P03JS_SOT-23-3
EMB80P03JS_SOT-23-3
9 10
1
1500P_0402_50V7K
10 11
1
PQ12
PQ13
PR1
PR2
1M_0402_5%
1000P_0402_50V7K
330K_0402_5%
1
4
11
1
PD2
PC1
PC3
1
Vinafix.com
2
3
3
S S
ACES_50493-0110N-001
PR3
PR4
1000P_0402_50V7K
2
1
G G
PC4
2 2
2
CONN@ @
2
D D
PC2
1
1
1
100K_0402_5%
2
PR7
D EMI@ 4/3 For EMI test(15" pop) D
PR6
EMI@
Normal floating
1
1M_0402_5%
OVP pull low
2
PR9
10K_0402_5%
+3.3V_VDD_PIC
PR8
<83> LPS_OFF1
+3.3V_ALW +3.3V_ALW
1
100K_0402_5%
BATDRV_GATE <82,85>
0_0402_5%
EMI Part (47.1)
1M_0402_5%
2
PR70
@ @ PR11 For Peak Shift use
2.2K_0402_5%
PR2162
6
1 2 PQ1A
1 2
PR2143
<58,82> AC_DIS
0_0402_5% 2
PQ2A
PR10
@ PQ2108 PD11 2
1
EMI@ PL4 @ FDV301N_G_NL_SOT23-3 PR12 L2N7002DW1T1G_SC88-6 BAT54CW-7-F SOT-323
1
BLM15BX102SN1D_2P 33_0402_5%
1
3
3
NB_PSID PS_ID
S
2 1 3 1 1 3 1 2
S
PS_ID <58>
@
PR17
PQ14
PQ3B
PQ2B
100K_0402_1%
3
6
FDV301N_G_NL_SOT23-3 +3.3V_VDD_PIC 2 1 5 5
G
G
<58,83> VBUS1_ECOK
2
2
PC5 @
PR14
0.1U_0402_10V7K
1 2 PR13
PQ3A
0_0402_5%
4
@ESD@ 1 2 2
5
PD3 PR74
100K_0402_5%
1
2
AZ5125-02S.R7G_SOT23-3 C 1 1 2
0.1U_0402_25V6
<58,83> HW_ACAVIN_NB
P
B 0_0402_5%
1
2 PQ16 4
PR18
O
1
2
PC6
B LMBT3904WT1G_SC70-3 A 100K_0402_5%
G
E
15K_0402_1%
PQ1B <58,82,83> AC_DISC#

1
3
2
@ PR15 PU1
PR16
2
1
TC7SH08FU_SSOP5~D
PR21
<58> DCIN1_EN 1 2 4 3 1 2
0_0402_5% 0_0402_5%
1
100K_0402_5%
5
2
@ @ @
+5V_ALW
PR20
PR2161 PQ2109A PD4
1
100K_0402_5%
2
0_0402_5% L2N7002DW1T1G_SC88-6 SS5P10-M3-86A_TO277A3
2
PR22
@ 2
PR23 1
100K_0402_1%
1
1
2 0_0402_5% 3
PR19
+20V_VBUS_DC_SS1
2
1
+3.3V_VDD_PIC PQ17 PQ18

S3 S4
1
1
AOSP21357_SO8 AOSP21357_SO8
1 8 8 1
2
2 7 7 2
C +3.3V_VDD_PIC @ PR24 3 6 6 3
C
0.022U_0603_50V7K
1
1
1 2 5 5
100K_0402_5%
100K_0402_5% 100K_0402_5%
EMB80P03JS_SOT-23-3
EMB80P03JS_SOT-23-3
PSID_DISABLE# <58>
+3.3V_ALW
PR25
1500P_0402_50V7K
1
0_0402_5%
PQ19
PQ20
+3.3V_VDD_PIC
PR26
1M_0402_5%
Disconnect
330K_0402_5%
4
4
1
1
PC11
PC12
3
3
detect
S S
PR28
PR29
2
2
G G
2 2
2
1
1
100K_0402_1%
200K_0402_1%
2
1
221K_0402_1%
D D
PR2145
PR2147
1 2
1
1
1
PR2149
PU2004A
100K_0402_5%
@ PR2148
PR31
PR32
LM393DGKR_VSSOP8
8
@ @ 1M_0402_1%
2
3 @
P
1
1
1M_0402_5%
BARREL_DISC <58>
2
2 O PR34
+3.3V_VDD_PIC
220P_0402_50V8J
-
G
10K_0402_5%
PR33
Normal floating
100K_0402_1%
100P_0402_50V8J
1
1
200K_0402_1%
PC2104
1 OVP pull low

4
1
1
PR2144
@
2 PR2146
PC2105
1
100K_0402_5%
PC2106 <83> LPS_OFF2 BATDRV_GATE <82,85>
@ 1200P_0402_50V7K
2
3
2
PR71
@
2
3
From PD, Active low PD14 BAT54CW-7-F SOT-323
@
3
@ PQ2109B @ 3
PQ5B
<44,83> VBUS_C_CTRL_P1# PD12 5
PQ4A
L2N7002DW1T1G_SC88-6 1 2 BAT54CW-7-F SOT-323
6 1
5 <58,82> AC_DIS
4
2
PQ4B
6
9/29 Disable detection function @
PR36
4
@ L2N7002DW1T1G_SC88-6 PR35 @
PQ6A
PR38
1 2 4 3 1 2 2
PQ6B
PQ5A
<58> DCIN2_EN
2 1 5 2
100K_0402_5%
<58,83> VBUS2_ECOK
2
0_0402_5% 0_0402_5%
1
PR75
PR39
221K_0402_1%~D
0.1U_0402_25V6
2 5
1 0_0402_5%
1
1
2
2
100K_0402_5%
1
@
PR40
PC13
PR42
PR41 100K_0402_5% <58,82,83> AC_DISC#
1
0_0402_5%
2
2
1
+3.3V_VDD_PIC
1
EMI@ PL5
5A_Z80_0805_2P +3.3V_ALW
1 2 +20V_VBUS_1
EMI@ PL6
5A_Z80_0805_2P PD6
B +20V_TBTA_VBUS 1 2 SS5P10-M3-86A_TO277A3
B
2
1
3
0.1U_0603_25V7K
100K_0402_5%
1
1000P_0402_50V7K
100P_0402_50V8J
100P_0402_50V8J
1 1
1
1
PC7
PC9
EMI@ PC10
+20V_VBUS_DC_SS2
PR27
S5 PQ22
S6 PQ23
PC8
2 2 AOSP21357_SO8 AOSP21357_SO8
EMI@
@EMI@
1 8 8 1
2 7 7 2
@EMI@
3 6 6 3
0.022U_0603_50V7K
1
1
5 5
PR43
100K_0402_5%
100K_0402_5% 100K_0402_5%
EMB80P03JS_SOT-23-3
EMB80P03JS_SOT-23-3
1500P_0402_50V7K
1
PQ24
PQ25
PR44
1M_0402_5%
330K_0402_5%
EMI Part
4
1
1
PC18
PC19
3
3
S S
PR46
PR47
2
2
G G
2 2
2
2
D D
1
1
1
1
100K_0402_5%
PR48
PR50
EMI Part Normal floating
1
1M_0402_5%
OVP pull low
2
2
PR52
EMI@ PL7 10K_0402_5%
+3.3V_VDD_PIC
PR51
<83> LPS_OFF3
5A_Z80_0805_2P
+20V_VBUS_2 BATDRV_GATE <82,85>
1 2
2 2
2
EMI@ PL8 From PD, Active low PD15 BAT54CW-7-F SOT-323
6
1
100K_0402_5%
5A_Z80_0805_2P
+20V_TBTB_VBUS 1 2 3
<44,83> VBUS_C_CTRL_P2#
PR72
PQ7A
3
1 2
PD13
0.1U_0603_25V7K
100K_0402_5%
<58,82> AC_DIS
2
1
PQ8B
BAT54CW-7-F SOT-323
1000P_0402_50V7K
100P_0402_50V8J
100P_0402_50V8J
1 1
1
6 1
1
5
EMI@ PC14
@EMI@ PC16
EMI@ PC17
PR45
@
PQ7B
3
@
@EMI@ PC15
PR54 PR55
2
4
6
2 2 L2N7002DW1T1G_SC88-6 @
PQ9A
PR53
2
1 2 4 3 1 2 2
PQ9B
<58> DCIN3_EN
2 1 5
PQ8A
<58,83> VBUS3_ECOK
2
0_0402_5% 0_0402_5%
1
100K_0402_5%
221K_0402_1%~D
0.1U_0402_25V6
5
0_0402_5%
4
2
A A
1
1
PR76
PR57
PC20
PR58
1
1 2
100K_0402_5%
@
PR59
PR60 100K_0402_5%
1
<58,82> AC_DIS 0_0402_5% <58,82,83> AC_DISC#

2
+3.3V_VDD_PIC
100K_0402_5%
1
2
PR2163
PWR_SRC_ILIMIT(6) removed
PWR_SRC_ON (3) removed +3.3V_ALW DELL CONFIDENTIAL/PROPRIETARY
1
PWR_SRC_ON_PC (6) removed

+PWR_SRC removed Compal Electronics, Inc.
Add AC_DIS pull down resister
11/30 Title
Add PC34,PC35,PD18,PD19
PR2,PR17 change from 1M to 330K THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC_IN/TBTA/TBTB
PU2B-->PU4B AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
1.0
PQ17A-->PQ17 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-H281P
5 4 3 2 1
5 4 3 2 1
+3.3V_VDD_PIC
DCIN_AC_Detector +3.3V_ALW
10K_0402_1%
PR2036
1 2
+19.5V_DC_IN
2
@
PR2037
221K_0402_1%~D
PR2003
0_0402_5%
1
137K_0402_1%
100K_0402_5%
+3.3V_ALW +3.3V_ALW
0.01U_0402_25V7K~D
2
@
PR2038
10K_0402_1%
Vinafix.com @ <58,82> HW_ACAVIN_NB
PR2041
1
1
PC2015
2
PR2039
2
2
@
1
@ PR2005 PR2151
287K_0402_1%
AC_DISC# <58,82>
1
PR2042
PQ2007A
D <58,82> VBUS1_ECOK 100K_0402_5% 100K_0402_5% D
1.8M_0402_1% 2
PR2040
1
1 2
1
PU2004B +3.3V_ALW +3.3V_ALW
1
3
LM393DGKR_VSSOP8 @ CMPOUT <85>
2
1.26V(need < VCC-2V)
5
PQ2007B
1500P_0402_50V7K
P
+
2
(>16.52V) 7 DCIN_ACOK 5 PR2007
O
6
6 100K_0402_5%
-
3
PR2008 PQ2002A
PC2003
4
6
@ 100K_0402_5% L2N7002DW1T1G_SC88-6 PQ2003B
23.7K_0402_1%
1200P_0402_50V7K
100P_0402_50V8J~D
220P_0402_50V8J~D
4
1
2 L2N7002DW1T1G_SC88-6
84.5K_0402_1%
1
1
1
5
PR2053
PC2016
PC2017
1
@ 2
PR2056
PC2018
1
+3.3V_ALW
4
3
PQ2003A
1
PQ2001B L2N7002DW1T1G_SC88-6
6
2
PQ2001A 5 @
PR2009
L2N7002DW1T1G_SC88-6 PR2010
6
1 2 2 100K_0402_5%
4
0_0402_5%
1
2
@
PROCHOT# <7,27,58,85,90>
1
PQ2004A
If Cypress is sure CC disconnect will detect disconnect 1 2 +3.3V_ALW
1
L2N7002DW1T1G_SC88-6 D
within 700us, these comparators can be eliminated. @
PR2014
0_0402_5% 2
PQ2010
L2N7002WT1G_SC70-3
2
G
S
3
PR2016
+20V_TBTA_VBUS 100K_0402_5%
+3.3V_VDD_PIC <58,82> VBUS2_ECOK
1
2
PR2019 Vbus1_AC_Detector
0_0402_5%
3
221K_0402_1%~D
PQ2004B
0.01U_0402_25V7K~D
1
@ L2N7002DW1T1G_SC88-6
2
5
PR2025
221K_0402_1%~D
1
2
PC2007
287K_0402_1%
1
PR2024
137K_0402_1%
4
PR2022
C C
2
@ +3.3V_ALW
PR2023
1
PR2030 VBUS1_ACOK#
1
1M_0402_1% @
2
1 2 PR2018
2
PU2001A 100K_0402_5%
3
PQ2006B
6
1.26V(need < VCC-2V) LM393DGKR_VSSOP8
3 L2N7002DW1T1G_SC88-6 PQ2005A
P
+ 1 VBUS1_ACOK 5
(>16.52V) L2N7002DW1T1G_SC88-6
+20V_TBTB_VBUS
1
2 O 2
- <58,82> VBUS3_ECOK
G
23.7K_0402_1%
4
+3.3V_ALW
1
+3.3V_VDD_PIC
84.5K_0402_1%
1200P_0402_50V7K
100P_0402_50V8J~D
220P_0402_50V8J~D
1
1
2
PR2032
Vbus2_AC_Detector
1
2
PR2020
PR2033
PC2010
1
PC2011
0_0402_5%
PR2021
PC2009
221K_0402_1%~D
2
100K_0402_5%
0.01U_0402_25V7K~D
2
1
@
1
2
PR2029
221K_0402_1%~D
1
2
PC2008
287K_0402_1%
1
PR2028
137K_0402_1%
6
PR2026
3
PQ2006A @
PR2027
1
PR2031 VBUS2_ACOK# PQ2005B
1
L2N7002DW1T1G_SC88-6 2 VBUS_C_CTRL_P1# <44,82,83> 1M_0402_1% L2N7002DW1T1G_SC88-6
2
1 2 5
1
PU2001B
4
8
(>16.52V) 1.26V(need < VCC-2V) LM393DGKR_VSSOP8 PQ2012B
5
P
+ 7 VBUS2_ACOK 5
6 O L2N7002DW1T1G_SC88-6
-
G
23.7K_0402_1%
4
1
84.5K_0402_1%
1200P_0402_50V7K
100P_0402_50V8J~D
220P_0402_50V8J~D
4
1
PR2034
1
PR2035
PC2013
1
PC2014
PC2012
2
2
2
6
B
PQ2012A B
2 VBUS_C_CTRL_P2# <44,82,83>
OVP pull high to 3.3V_VDD_PIC because WH need to concern battery mode to latch LPS,
1
and need to remove all source to reset LPS function
S3 OVP S5 OVP
LPS_OFF1 <82,83> LPS_OFF3 <82> LPS_OFF_BATT <83,85>
+3.3V_VDD_PIC
+3.3V_VDD_PIC
6
+20V_TBTA_VBUS +3.3V_VDD_PIC +20V_TBTB_VBUS +3.3V_VDD_PIC
PR2152 PR2153 PR2154
PD2004 PD2005 S3_OVP 1 2 2 1 2 5 1 2 2
49.9K_0402_1%
49.9K_0402_1%
1
RB751V-40_SOD323-2 RB751V-40_SOD323-2 PQ2110A PQ2110B PQ2112A

0_0402_5%
1
L2N7002DW1T1G_SC88-60_0402_5%
4
L2N7002DW1T1G_SC88-6 0_0402_5%
1
1
1 2 1 2 L2N7002DW1T1G_SC88-6
PR2158
PR2159
287K_0402_1%
137K_0402_1%
287K_0402_1%
137K_0402_1%
1
@ @ @
@ PR2054 @ PR2055
PR2047
PR2048
PR2051
PR2050
1.8M +-1% 0402 1.8M +-1% 0402

2
1 2 1 2
2
PU2003A
2
PU2003B
2
2
8
LM393DGKR_VSSOP8 LM393DGKR_VSSOP8
(>5.64V) 3 (>5.64V) 5
P
+ 1 S3_OVP + 7 S5_OVP
O O LPS_OFF1 <82,83> LPS_OFF2 <82> LPS_OFF_BATT <83,85>
2.2U 25V M X5R 0402
2.2U 25V M X5R 0402

1
2 6
82.5K_0402_1%
82.5K_0402_1%
10U 10V M X5R 0402
10U 10V M X5R 0402
- -
G
G
84.5K_0402_1%
84.5K_0402_1%
100P_0402_50V8J
100P_0402_50V8J
0.1U 25V M X5R 0402
0.1U 25V M X5R 0402

1
1
PR2059
PC2021
PC2022
PR2060
PC2025
PC2026
4
4
1
3
PC2019
PR2061
PC2020
PC2023
PR2062
PC2024
+3.3V_VDD_PIC
+3.3V_VDD_PIC PR2155 PR2156 PR2157
2
2
2
S5_OVP 1 2 2 1 2 5 1 2 5
2
2
221K_0402_1%~D
1
221K_0402_1%~D
PQ2111A PQ2111B PQ2112B
0_0402_5%
1
L2N7002DW1T1G_SC88-60_0402_5%
4
L2N7002DW1T1G_SC88-6 0_0402_5%
4
PR2063
PR2064
@ @ @
3
PR2066
PR2065
2
5 1 2 VBUS_C_CTRL_P2
A A
5 1 2 VBUS_C_CTRL_P1 PQ2009B
6
PQ2008B L2N7002DW1T1G_SC88-6
4
0_0402_5%
6
4
0_0402_5% @
@ 2 VBUS_C_CTRL_P2# <44,82,83>
2 VBUS_C_CTRL_P1# <44,82,83> PQ2009A
PQ2008A L2N7002DW1T1G_SC88-6
1
1

Title
AC DET/LPS circuit
1.0
LA-H281P
5 4 3 2 1
5 4 3 2 1
+COINCELL
EMI Part (47.1)
COIN RTC Battery
EMI@ PL9
1
9A Z80 10M 1812_2P
RTC_DET# <17>
1 2 +19.5VB_DGFF PR61
+19.5VB 1K_0402_5%
+3.3V_RTC_LDO
Vinafix.com CONN@
10U_0805_25V6K
0.1U_0603_25V7K
82P_0402_50V8J
2
PC30
1 JRTC1
100U_D3L_25VM_R60M
+COINCELL
1
D 1
PC23
1
1
+ 2 2
PC21
PC22
G PQ26 2
2Z4012
D
RF@
D
2
@ 3
2
GND
1
2
10M_0402_5%
@ @ S L2N7002WT1G_SC70-3 4
3
GND
PR64
ACES_50271-0020N-001
2
ESD Diodes
PD8
1
BAS40CW_SOT323-3
ESD (47.2) +RTC_CELL
1
1
1
ESD@ ESD@ PC24
PD9 PD10 4.7U_0402_6.3V6M
2
AZ5A25-02R_SOT523-3 AZ5A25-02R_SOT523-3
Move to power schematic
EMI Part (47.1)
2
3
EMI@ PL11 +3.3V_ALW
FBMJ4516HS720NT_2P downsize from 1U_0603 to 4.7U_0402
1 2
Primary Battery Connector
EMI@ PL12
EMI Part (47.1)
1
FBMJ4516HS720NT_2P
100K_0402_5%
+13.5VB_BATT_C 1 2
+13.5VB_BATT
PR62
CONN@
2
PBATT1
1 PR65 100_0402_5%
2200P_0402_50V7K
1 PBAT_CHARGER_SMBCLK <58,85>
Changed 2 1 2
Battery 2 PBAT_CHARGER_SMBDAT <58,85>
3
3 PBAT_PRES# <58,85>
1
C Connector 4 C
EMI@ PC25
Z4304 PR66 100_0402_5%

(same as 4 5 Z4305 1 2
Berlinetta) 5 6 Z4306
2
6 7 PR67 100_0402_5%
7 8 1 2
8 9
9 10
10 11
GND1 12
GND2
DEREN_40-42251-01001RHF
GND GND
+5V_Vbus circuit
PQ2100 +5V_VBUS1
+20V_VBUS_1 EMB12P03V_EDFN8-5 PQ2104
+5V_VBUS2
1
2
+20V_VBUS_2 EMB12P03V_EDFN8-5
1
3 5
2
1
3 5
1M_0402_1%
1
0.022U_0402_25V7K
PQ2101
PR2100
1
1
PR2101
EMB80P03JS_SOT-23-3
PC2100
PQ2105
1M_0402_1%
1
0.022U_0402_25V7K
300K_0402_1%
EMB80P03JS_SOT-23-3
PR2104
4
PR2105
PC2102
300K_0402_1%
4
3
S
2
2
G
2
3
2
2
G
2
2
D
1
B D B
PR2134
1
100K_0402_1% PR2142
100K_0402_1%
2
2
PR2108
1
6
100K_0402_1% PR2109
6
PR2150 100K_0402_1%
PQ2102A
PQ2106A
1 2 2 PR2106
<44> CCG5_VBUS_5V_ON1#
2
<44> CCG5_VBUS_5V_ON2# 1 2 2
1
0_0402_5%
1
@ 0_0402_5%
@
Check parts, couldn't read
from Merle's screen
capture. Package is
correct, symbol is wrong.
Check parts. Package is correct,
schematic symbol is wrong. Check parts. Package is correct,
schematic symbol is wrong.
Check parts. Package is correct,

schematic symbol is wrong.
A A
DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc.

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL BATT/DGFF/RTC/5V_VBUS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
5 4 3 2 1
A B C D
Iada=0~9.23A(180W) +19.5VB
PQ700 ADP_I = 40*Iadapter*Rsense

+19.5VB_CHARGER
SI7149DP-T1-GE3_POWERPAKSO8-5 PR700
1 0.005_1206_1% EMI@ PL700
2 1UH_6.6A_20%_5X5X3_M
5 3 +19.5V_SDC_IN_CR 1 4 2 1
+19.5V_SDC_IN
1
2 3 EMI Part (47.1)
1M_0402_5%
100K_0402_5%
1
5
PJP700
EMB80P03JS_SOT-23-3
Vinafix.com
<82> BATDRV_GATE
PR731
PR733
2 1
PR701
3
S
PAD-OPEN 43x118 4.02K_0402_1%
2
1 G 1
2 LPS_OFF_BATT_R <43> @JUMP@ BATDRV 1 2 4
0.01U_0402_25V7K
AONS32306_DFN5X6-8-5
1
D PJP700 no short (-npm)
100K_0402_5%
1
PQ701
1
PQ705
PR734
PC725
+20V_VBUS_DC_SS1
3
2
1
1
1M_0402_5%
PD700
Normal floating 2
2
PR735
PR732
OVP pull low 1 10_0402_1%
CSSN_1
CSSP_1
LPS_OFF_BATT <83> +19.5V_DC_IN_SS BATSRC 1 2
2
3
PR702
100_0402_1%
BAT54CW-7-F SOT-323 2 1
PD701
+13.5VB_BATT
1
1
2 PR703
0_0402_5% @ @ PR704
1 0_0402_5%
8/22 for charger ACP/ACN leakage current issue, PC701
2200P_0402_50V7K
+20V_VBUS_DC_SS2
10U_0805_25V6K
10U_0805_25V6K
change LPS circuit placement 3 PC700 0.1U_0402_25V6 PC702
0.1U_0402_25V6
2
1 2 1 2 1 2
1
PC710
PC704
PC705
EMI@ PC703
BAT54CW-7-F SOT-323 0.1U_0402_25V6 0.01U_0402_25V6
@ PD702
1
AC Det (typ 2.4V) PR705
CSSN_2
CSSP_2
2
+19.5V_SDC_IN 10_1206_5% MM3Z22VST1G_SOD323-2
Max:16V
EMI@
1 2
Typ :15.58V
Min :15.16V
4.12K_0603_1%
274K_0402_1%
2
PC706
1
2
1
BQ24780_REGN 1 2
PC707 PU700 EMI Part (47.1)
PR706
PR707
1U_0603_25V6K
ACDRV
ACP
ACN
2 1 +DCIN 28 2.2U_0402_10V6K
VCC
BQ24780_REGN
PR709 3 24 0.047U_0603_25V7M~D PQ702
2
1
CMSRC REGN
5
49.9K_0402_1% PR708
2 1 ACDET_CHG 6 PC708 +13.5VB_CHG
2
2.2_0603_5% 2
AON6380_DFN5X6-8-5
ACDET 25 1 2 2 1
PC709 BTST
1 2 11
2 1 @ PR710 0_0402_5% SDA
2200P_0402_25V7K 1 2 12 26 UGATE_CHG 4
SCL HIDRV
1
PR712 GNDA_CHG
@ PR711 0_0402_5%
ACOK_CHG 5
EMI Part (35.33) +13.5VB_BATT
100K_0402_1% ACOK 27
<58,84> PBAT_CHARGER_SMBDAT PHASE
7 PR715
3
2
1
@ IADP PL701 0.01_1206_1%
PR713 <58,84> PBAT_CHARGER_SMBCLK
2
8 23 2.2UH_7.8A_20%_7X7X3_M
1 2 @ IDCHG LODRV LX_CHG 1 2 1 4
<27,58,62> ACAV_IN +3.3V_ALW
@ PR717 0_0402_5% 1 PR714 2 9
PMON
1
1 2 2 3
4.7_1206_5%
<58> I_ADP
1
20K_0402_1%
0_0402_5% LGATE_CHG
3.92K_0402_1%
PR716 0_0402_5% 10 22 PQ703
PR720
PROCHOT# GND
5
PR721
CSOP_1 CSON_1
EMI@
PR722
121K_0402_1% @1 2
<58> I_BATT PR719 0_0402_5%
100P_0402_50V8J
100P_0402_50V8J
10U_0805_25V6K
AON6314_DFN5X6-8
<58,90> I_SYS
2
13 21
2
CMPIN
1
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
2
24.9K_0402_1%
2
2
CMPIN ILIM
1
PC714
PC715
PC716
ILIM_CHG SNUB_CHG
PC711
PC712
PR723
PC713
14 4
6
<83> CMPOUT
1
GNDA_CHG CMPOUT 20
680P_0402_50V7K
1
2
SRP
PQ704A
PC717
@
15 19
2
GNDA_CHG
2
BATPRES# SRN 2
TB_STAT# <59,85>
3
2
1
2 PROCHOT#_R
EMI@
<7,27,58,83,90> PROCHOT#
1
@ PR718 0_0402_5% 16 18 BATDRV
1
TB_STAT# BATDRV
1 2 29 17BATSRC
<58,84> PBAT_PRES# PWPD BATSRC
1
PC718 PC719 PC720
2.74K_0402_1%
@ PR724 0_0402_5% PR725 0.1U_0402_25V6 0.1U_0402_25V6 0.1U_0402_25V6
PR726
10K_0402_5% BQ24780SRUYR_QFN28_4X4 1 2 1 2 1 2
Current limit 2 1
Charger :7.5A Vilim=1.5V +3.3V_ALW GNDA_CHG
2
PJP701 PR727
3
6 Cell 97WH and 4Cell 64WH, 1 2 10_0402_1% GNDA_CHG GNDA_CHG 3
SRP_1 2 1
Max Boost Charger :7.8A, Vilim=0.39V <59,85> TB_STAT#
Discharge max current:8.5A(1C) GNDA_CHG

PAD-OPEN1x1m PR728
10_0402_1%
JUMP@
SRN_1 2 1
PR729 2016/7/22
0_0402_5% For Temp voltage test ,
2 1 CMPIN
+DC_IN setting for ACAVIN_NB need less than 17.55V ,
so change PR737 from SD034665380
@ PR730 (S RES 1/16W 665K +-1% 0402) to
100K_0402_1% SD034634380(S RES 1/16W 634K +-1% 0402)
2 1
+3.3V_ALW
CMP_REF=2.3V (CMP_REF=2.3V
+DC_IN>17V then ACAV_IN_NB high +DC_IN>17.6V then ACAV_IN_NB high
for 3cell battery 13.05V for 4cell battery 17.4V[Miramar setting])
4 4
Crane and Miramar setting
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Charger
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
1.0
LA-H281P
A B C D
A B C D E
Vinafix.com
1 1
PR109
499K_0402_1%
+19.5VB ENLDO_3V5V 1 2
@
PR101
+19.5VB
PJP100 PC110
1
1 2 +19VB_3V BST_3V1 2 1 2
499K_0402_1%
PR108
PAD-OPEN 1x2m~D 0.1U_0603_25V7K
0_0603_5%
2200P_0402_50V7K
JUMP@
1
PU100
2
@EMI@ PC100
@EMI@ PC111
10U_0805_25V6K
10U_0805_25V6K
BS
IN4
IN3
IN2
IN1
0.1U_0402_25V6
1
1
LX_3V 6 20 PL100
PC108
PC107
LX3 LX2 1.5UH_9A_20%_7X7X3_M
2
7 19 LX_3V 1 2
GND1 LX1 +3.3V_ALWP
8 SY8288BRAC_QFN20_3X3 18 @
@EMI@ PR100
GND2 GND3 PR104
4.7_1206_5%
9 17 1 2
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
PG LDO +3.3V_ALW2
1
PC101
PC103
PC104
PC106
PC105
PC102
10 16 PR105
@
NC NC2 1 0_0402_5%
2 +3.3V_RTC_LDO 3V_ALW
OUT
NC1
EN2
EN1
2
21
FF
GND4
TDC 5.73A
1SNUB_3V2
PR107 0_0402_5%
Peak Current 8.19A
11
12
13
14
15
100K_0402_5% 3.3V LDO 150mA~300mA
680P_0402_50V7K
1 2
Current limit :12A
@EMI@
PC109
+3.3V_ALW
1
PC113
Vout is 3.234V~3.366V TYP MAX
ENLDO_3V5V
4.7U_0402_6.3V6M Choke DCR 14.0mohm , 15.0mohm
2
PGOOD_3V
2 2
@ PC112 PR106
PR102
1000P_0402_50V7K 1K_0402_5%
PGOOD_3V 1 2 EN_3V_5V 3V_FB 1 2 1 2 PJP101
ALW_PWRGD_3V_5V <18,43,62> +3.3V_ALWP 1 2 +3.3V_ALW
PGOOD_5V 1 2 1 2
0_0402_5% JUMP_43X118
@ PR103 JUMP@
0_0402_5%
PJP103
+19.5VB +5V_ALWP 1 2 +5V_ALW
1 2
PJP102 PR111
@ PC115 JUMP_43X118
1 2 +19VB_5V BST_5V 1 2 1 2 JUMP@

0_0603_5%
2200P_0402_50V7K
JUMP@
PU101
5
1
@EMI@ PC114
@EMI@ PC116
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
1
output MLCC size change from 0805 to 0603
BS
IN4
IN3
IN2
IN1
82P_0402_50V8J
RF@ PC138
PC117
PC118
1
LX_5V 6 20 PL101
2
LX3 LX2 2.2UH_7.8A_20%_7X7X3_M

7 19 LX_5V 1 2 +5V_ALWP
2
GND1 LX1
3 8 18 3
GND2 GND3
1
PC119
PR112
4.7_1206_5%
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
1
1
9 17 1 2
EMI@
PC120
PC121
PC122
PC123
PC124
PC125
PR110 PG VCC
100K_0402_5% 10 16
2
1 2 NC NC1 4.7U_0402_6.3V6M
+3.3V_ALW
OUT
LDO
EN2
EN1
1SNUB_5V2
21
FF
GND4
11
12
13
14
15
PGOOD_5V SY8288CRAC_QFN20_3X3
680P_0402_50V7K
+5V_ALW2
EMI@
PC126
5V LDO 150mA~300mA
EN_3V_5V
2
ENLDO_3V5V
1
PC127
4.7U_0402_6.3V6M
2
5V_ALW
TDC 6.7A
Peak Current 6.7 A
@
PR113 Current limit :12A
<58,87> ALWON
1 2 PC128 PR114 TYP MAX
1000P_0402_50V7K 1K_0402_5%
FB_5V 1 2 1 2
Choke DCR 21.0mohm , 23.0mohm
0_0402_5%
EN_3V_5V
1M_0402_1%
4.7U_0402_6.3V6M
1
1
PR115
PC129
4 4
2
@
2
EN1 and EN2 dont't floating

DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc.
Title
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
5V_ALW/3V_ALW
1.0
A B C D E
A B C D E
Vinafix.com
1
PR510 1
499K_0402_1%
+19.5VB ENLDO_3VR5VR 1 2
PR514
+19.5VB
PJP503 PC531
1
1 2 +19VB_3VR BST_3VR 1 2 1 2
499K_0402_1%
PR512
0_0603_5%
2200P_0402_50V7K
JUMP@
1
PU501 @
2
@EMI@ PC524
@EMI@ PC528
10U_0805_25V6K
10U_0805_25V6K
BS
IN4
IN3
IN2
IN1
0.1U_0402_25V6
1
1
LX_3VR 6 20 PL501
PC532
PC530
LX3 LX2 1.5UH_9A_20%_7X7X3_M
2
7 19 LX_3VR 1 2
GND1 LX1 +3.3V_ALW_RP
8 18
EMI@ PR511
SY8288BRAC_QFN20_3X3
GND2 GND3
9 17
4.7_1206_5%
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
PG LDO
1
PC525
PC523
PC522
PC521
PC529
PC520
10 16
NC NC2
3V_ALW_R
OUT
NC1
EN2
EN1
2
21
FF
GND4
TDC 5.44A
1SUNB_3VR
2
@ PR515
Peak Current 7.77A
11
12
13
14
15
100K_0402_5% 3.3V LDO 150mA~300mA
680P_0402_50V7K
1 2
Current limit :12A
EMI@ PC527
+3.3V_ALW_R
1
ENLDO_3VR5VR
PC533
Vout is 3.234V~3.366V TYP MAX
4.7U_0402_6.3V6M Choke DCR 14.0mohm , 15.0mohm
2
PGOOD_3VR
@ PR508
2 2
0_0402_5% PC526 PR513
PGOOD_3VR 1 2 1000P_0402_50V7K 1K_0402_5%
ALW_PWRGD_3VR_5VR EN_3VR_5VR FB_3VR 1 2 1 2 +3.3V_ALW_RP PJP502
1 2 +3.3V_ALW_R
PGOOD_5VR 1 2 1 2
JUMP_43X118
@ PR509 JUMP@
0_0402_5%
PJP501
+5V_ALW_RP 1 2 +5V_ALW_R
+19.5VB PR501
1 2
PJP500 PC501 JUMP_43X118
1 2 +19VB_5VR BST_5VR 1 2 1 2 JUMP@

0_0603_5%
2200P_0402_50V7K
JUMP@ @
PU500
5
1
@EMI@ PC500
@EMI@ PC502
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
1
output MLCC size change from 0805 to 0603
BS
IN4
IN3
IN2
IN1
PC503
PC504
LX_5VR 6 20 PL500
2
LX3 LX2 2.2UH_7.8A_20%_7X7X3_M

7 19 LX_5VR 1 2
GND1 LX1 +5V_ALW_RP
3 3
8 18
GND2 GND3
1
PC505
PR502
4.7_1206_5%
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
1
1
9 17 1 2
@EMI@
PC506
PC507
PC508
PC509
PC510
PC511
@ PR500 PG VCC
100K_0402_5% 10 16
2
1 2 NC NC1 4.7U_0402_6.3V6M
1SNUB_5VR
+3.3V_ALW_R
OUT
LDO
EN2
EN1
2
21
FF
GND4
11
12
13
14
15
PGOOD_5VR SY8288CRAC_QFN20_3X3
680P_0402_50V7K
@EMI@
EN_3VR_5VR
PC512
5V LDO 150mA~300mA
2
ENLDO_3VR5VR
1
PC513

LA-H281PR10_MB_TR_0409C (1)

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LA-H281PR10_MB_TR_0409C (1)

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Available Formats

A B C D E

eSPI@ : eSPI interface

PCB 26K LA-H281P REV0 MB AR 3

DP MUX1 1440 Pins

2 PS175 HDMI CannonLake-H 2

mDP 1.2 mDP

FAN CONN Universal Jack P.56

Date: Tuesday, April 09, 2019 Sheet 2 of 103

PORT 5 10/100/1G LOM

Port 1 JUSB1 SATA 0B SLOT6 SSD PORT 6 MMI(Card reader)

PORT 7 M.2 Slot-1 (WLAN/Wigig)

Port 6 NA SATA 5 NA PORT17~20 SLOT4 SSD 2280/ Optane

Date: Tuesday, April 09, 2019 Sheet 3 of 103

+3.3V_RUN +LCDVDD +1.8V_PRIM +2.5V_MEM

Timing Diagram for S5 to S0 mode Power Button

VCCSRAM_1P0 SIO_SLP_S5# SIO_SLP_S5#

+3.3V_ALW +3.3V_ALW_DSW SIO_SLP_S4# SIO_SLP_LAN#

+3.3V_ALW @SIO_SLP_WLAN# TLV62130 +1.0VS_VCCIO

Date: Tuesday, April 09, 2019 Sheet 5 of 103

Trace width=5 mils

DMI_CRX_PTX_P1 E6 C6 DMI_CTX_PRX_P1 DMI_CTX_PRX_P1 <15>

Place near JXDP1.47 CFG16 SVID NOT Present

XDP@ RC128 1 2 1K_0402_5%

XDP@ RC115 2.2K_0402_5%

RC132 150_0402_5% CPU_XDP_TRST# 1 2 0

BT27 XDP_OBS1 @ RC240 1 2 0_0402_5% XDP_OBS1_R

VCCST_PWRGD 1 2 VCCST_PWRGD_CPU H13 BPM#_2 BT30

H_THERMTRIP# 1 2 H_THERMTRIP#_R J31

<14,23,24,25,26,59> H_THERMTRIP# THERMTRIP#

@ RC319 1 PROC_TRST# PAD~D @ T179

@ RC171 0_0402_5% H_CATERR# BM30

VR_SVID_CLK 1 2 DELL CONFIDENTIAL/PROPRIETARY

Issued Date 2017/01/01 Title

Trace width=12-15 mils

CPU_DP1_P0 K36 D29 EDP_TXP0

PLACE CAP BACKSIDE

PAD~D @ T18 1 B30 BL31 1

VSS_A36 @ RC178 1 2 0_0402_5%

CFL change form +VCCGT to +VCC_CORE

CFL-H CFL-H CFL-H

Vinafix.com 0_0402_5% 2 1 @ RH66

1 CH13 change from 12P to 15P

RP change to single Resistor

256Mb Flash ROM +3.3V_SPI

GPD8/SUSCLK BF44 PCH_BATLOW# SUSCLK <52,67,68> PCH_BATLOW# 1 2

GPP_B23 PCH_PWROK AY42 BG44 LAN_WAKE# +3.3V_RUN

<20> VCCDSW_EN_GPIO DS3@ RH312 51_0402_5%

<19,58> PCH_RTCRST# NDS3@ DH1 PCH_JTAG_TDI 1 2

PCH_DPWROK 1 2 PCH_RSMRST#_AND de-pop for MP

@CH346 0.033U_0402_16V7 @RH631 100K_0201_5%

4 C MEM_SMBDATA 3 4 @CH348 0.033U_0402_16V7

1 2 UART2_TXD BBS_BIT6 BA26 BA20 MEM_INTERLEAVED LCD_CBL_DET# RC370 1 2 10K_0201_5%

Vendor JAE FOXCON TBD TBD

TYPEC_CON_SEL1 LOW LOW HIGH HIGH

B TYPEC_CON_SEL2 LOW HIGH LOW HIGH B

+3.3V_ALW_PCH +3.3V_ALW_PCH Check ME about wire to board PN

TBT_ID DIMM TYPE AR_DET# CONN@

CPU_TRST# CPU_XDP_TRST# <7>

TRIGGER_IN CPU_2_PCH_TRIGGER <10>

Change to DS3 4/1

AD49 AW4 G44 U24

1 1 1 1 1 1 1 VSS37 VSS109 VSS180 VSS231

AE4 VSS39 VSS111 B48 J26 VSS182 VSS233 V22

AK27 VSS66 VSS138 BF49