Introduction

Why Testing?
• To determine the presence of fault(s) in a
given circuit.
– No amount of testing can guarantee that a
circuit (chip, board or system) is fault-free.
– We carry out testing to increase our
confidence in proper working of the circuit.

• Verification is an alternative to testing,

used to verify the correctness of a design.
– Simulation-based approach.
– Formal methods.
 Verification v/s Testing

Verifies correctness of Verifies correctness of

design. manufactured h/w.
Performed by simulation, Two-part process:
h/w emulation, or formal 1. Test generation
methods. 2. Test application

Performed once prior to Test application

manufacturing. performed on every
manufactured device.
Responsible for quality of Responsible for quality of
design. devices.

Levels of Testing
• Testing can be carried out at various
levels:
– Chip level
– Board level
– System level
• Cost :: Rule of 10
– It costs 10 times more to test a device as
we move to the next higher level in the
product manufacturing process.
 What is Testing?
 Testing is process of determining whether a piece of hardware
Functioning correctly (PASS) or defective (FAIL)
 Why do we need to test Integrated Circuit (IC)?
 Because defects occur in manufacturing process

Pass:
Manufacturing Shippping
Testing
Process

Defects Fail: Reject

Testing is a Decision
 Why is Testing Important?
 1. Guarantee IC quality
 Reduces test escapes
 Not only functionally correct but also reliable IC

 2. Shorten Time to Market

 Prototype testing to debug silicon
 Improve efficiency of production test
 Diagnose defective IC to improve yield

 3. Enhance Profit
 Reduce test cost
 Fix defective chips if possible (like memory)
 Reduce yield loss
 Stages of IC Product
Design

Debug Verification
feedback
Fabrication

Prototype Test
Good Testing is
Key to Success Mass Production
good IC
Production Test Customer

failing IC returned IC
Diagnosis

diagnosed faults
Failure Analysis

Pictures of defects feedback to design,

& their root causes test & fab
 Why Testing is Difficult ?
• Test application time can grow exponentially
for exhaustive testing of circuits.
– For a combinational circuit with 50 inputs, we
need
250 = 1.1 x 1015 test patterns.
• Test generation of sequential circuits are even
more difficult.
– Lack of controllability and observability of flip-
flops.
• Functional testing may not be adequate for the
detection of physical faults.

How To Do Test?
• Fault Modeling
– Identify target faults
– Limit the scope of test generation

• Test Generation
– Automatic or Manual

• Fault Simulation
– Assess completeness of tests
 Basic Testing Principle

Input patterns Circuit Output response

Under
Test

Golden response
Comparator

Good / Bad

Traditional Design Flow

• Conduct testing after design

Design for
Testability

Yes

Design Too large

Testability Testability
Specification Design or
Improvement?
too slow? Analysis
No
No
Yes
Done
 Fault Modeling

Why Fault Models?

• Actual number of physical defects in a
circuit are too many.
– Not possible to consider individually.
– Difficult to count and analyze.
• Some logical fault models are considered.
– A fault model identifies targets for testing.
– Drastically reduces the number of faults.
– Makes analysis possible.
– Effectiveness measurable by experiments.
 Fault Models
• Stuck-at faults
• Bridging faults
• Transistor stuck-on / stuck-open faults
• Functional faults
• Memory faults
• PLA faults
• Delay faults
• State transition faults

Levels of Abstraction in Circuits

Behavioral Description

Functional Description
Increasing
Structural Description level of
abstraction
Switch-level Description

Geometric Description
 Why Fault Modeling?
 1. Fault model quantify test quality
 Defects are hard to handle
 How many possible defects in a circuit ? Way too many
 Number of faults can be easily calculated in a circuit

 2. Fault models makes test automation possible

 Automatic test pattern generation (ATPG)
 generate test patterns
 Fault simulation
 evaluate test quality
 Automatic diagnosis
 locate defects

Automatic Tools Need Fault Model

 Test Patterns and Test Sets
 Test patterns, also known as (aka): Test Vectors
 Input Boolean values for specific fault
 Expected output often included (but not required)
 Example: b stuck-at zero fault
a
 Test pattern a=1, b=1
b
 Test Set = A set of test patterns
 Example: ab= {11, 00}

 Test Length = Number of test patterns in a test set

 Example: ab= {11, 00}, TL=2

Shorter TL = Lower Test Cost

 Fault Coverage (FC)
number of detected faults
Fault Coverage   100%
number of total faults
 Between 0-100%
 FC is most widely used quantitative measure of test set quality
 Higher fault coverage implies more effective tests
0-70%  not good
 70-95%  sometimes acceptable

 95-100%  good

(Standard depends on company and products)

 In Brown & Williams model,
 Defect Level = 1-Y (1-FC)

Higher FC = Higher Quality

• Stuck-at Fault Model:
– Some line(s) in the circuit are permanently
stuck at logic 0 or logic 1.
– Denoted as s-a-0 & s-a-1, or as a/0 & a/1 for
some line ‘a’.
– A fanout stem and fanout branches are
considered different lines.
c j
a d g h
z
i
b e
f k

• Stuck-at fault model can detect many

realistic physical faults.
– Look at a TTL NAND gate.
– Investigate effects of physical defects.
– Most of them will map to gate-level stuck-at
faults.
• We classify two categories of stuck-at
faults:
– Single stuck-at faults
– Multiple stuck-at faults
 Single Stuck-at Fault
• Three properties define a single stuck-at
fault.
– Only one line of the circuit is faulty at a time.
– The faulty line is permanently set to 0 or 1.
• Not of intermittent nature
– The fault can be at an input or output of a gate or
module.
• How many faults possible?
– For a circuit with k lines, the total number of
single stuck-at faults possible is 2k.
• Most widely used fault model in the industry.

• Why single stuck-at faults?

– Simpler to handle computationally.
– Reasonably good fault coverage.
• A test set for detecting single stuck-at faults
detects a large percentage of multiple stuck-
at faults as well.
– It is technology independent.
• Can be applied to TTL, ECL, CMOS, etc.
– It is design style independent.
• Gate array, standard cell, full custom, etc.
 Multiple Stuck-at Faults
• Stuck-at faults can be simultaneously
present on more than one line of the circuit.
• How many faults possible?
– The total number of single and multiple stuck-at
faults in a circuit with k lines is 3k–1.
– Difficult to handle in practice.
• Single fault tests cover a very large number
of multiple faults.
– Found through simulation studies.
 Example: 2-input XOR gate realized using
NAND gates

• 12 fault sites
• 24 single stuck-at faults
• 312-1 = 5,31,441 multiple stuck-at faults

c j
a d
g h
z
i
b e
f k

Bridging Faults
• Two or more normally distinct points (lines)
are shorted together.
– Logic effect depends on technology
Wired-AND for TTL
A f A f

B g B g

Wired-OR for ECL

A f A f

B g B g

CMOS ?
 Single Stuck-at Fault Model
 Single Stuck-at Fault (SSF) model
 One signal line in Boolean network of logic gates is fixed to logic
0 or 1, independent of logic values on other signal lines
 Notations: node x stuck-at fault
 x/0, x/1,
 x s@0, x s@1
 x SA0, x SA1
 Number of faults is linear to circuit size
 2 faults (stuck-at one, stuck-at zero) per node
 2n SSF in a circuit of n nodes
 Most commonly studied fault model

SSF is Scalable for Large Circuits

 Single Stuck-at Fault Example
 Example: SSF table of two input AND gate
 Total six faults: a/0, a/1, b/0, b/1, c/0, c/1
 Test set ab = {01,11,10}
 100% SSF fault coverage, detects all SSF
 Minimum test length =3 for 100% SSF fault coverage
a
c
b

Input Fault-free Faulty Output Value with SSF

ab Output a/0 a/1 b/0 b/1 c/0 c/1
00 0 0 0 0 0 0 1
01 0 0 1 0 0 0 1
11 1 0 1 0 1 0 1
10 0 0 0 0 1 0 1
*erroneous output values highlighted
 Manger asked you to pick 2patterns…

Q: Based on SSF model, which patterns do you pick ?

What is maximum fault coverage?
A:
a
c
b

Input Fault-free Faulty Output Value with SSF

ab Output a/0 a/1 b/0 b/1 c/0 c/1
00 0 0 0 0 0 0 1
01 0 0 1 0 0 0 1
11 1 0 1 0 1 0 1
10 0 0 0 0 1 0 1
 Fault Modeling
 Fault Models
 Stuck-at fault
 Number of single stuck-at faults is linear to circuit size : 2n
 Multiple stuck-at faults are exponential in number
 Fault masking means two faults cancel each other
 BIST Outline
 Part 1
 Introduction
 Test Pattern Generation
 Part 2 (Next chapter)
 Output Response Analysis
 BIST Architecture
 Problems and solutions
 Conclusions
 Built-in Self Test
 Definition
 Capability of hardware/software to carry out explicit test of itself
 Levels of BIST
 System-level self test
 system self test of mainframe computer
 Board-level self test
 so we can replace a bad board in a system
 Chip-level self test
 focus of this lecture
 Categories of Chip-level BIST
 Based time of test
 On-line BIST
 On-line testing while chip in normal operation
 e.g. error detection and correction for RAM
 Off-line BIST
 Off-line testing while chip not in normal operation
 Focus of this talk
System on Chip (SOC)
 Based on CUT
 Logic BIST Logic Memory
 Memory BIST CPU DRAM

IP cores
L-BIST M-BIST

GPU FLASH
L-BIST L-BIST M-BIST
 Architecture of BIST
 Three components: BIST Controller, TPG, ORA
 Three I/O Pins: Start BIST, BIST Done, Pass/Fail

Chip
Test Pattern
Generation (TPG)

Circuit Under Test

(CUT)

BIST Done
Output Response BIST
Pass/Fail
Analyzer (ORA) Controller
Start BIST
 Why BIST?
 1. Save ATE cost
 Smaller test pattern storage
System on Chip (SOC)
 Fewer DFT pins
 Slower tester speed Logic Memory
 2. Better IC quality CPU DRAM
 Test speed higher than ATE

IP cores
 3. Easier integration of tests
L-BIST M-BIST

 Intellectual Property (IP) cores

 4. Easier test access GPU FLASH
L-BIST L-BIST M-BIST
 Test embedded memory in SOC
 5. Enable on-line testing
 Ensure reliability

BIST Has Many Unique Advantages

 Disadvantages of BIST
 1. Area Overhead
 Yield loss due to BIST circuitry
 2. Performance degradation
 Extra hardware
 3. Extra design effort
 Test point insertion, BIST insertion, verification …
 4. Lack information for debug and diagnosis
 Need to bypass BIST when diagnosis
 5. Long test length but fault coverage may not good enough
 Random test patterns not as good as ATPG patterns
 Mixed solution (BIST + ATE) is often needed

BIST can NOT Solve All Problems

 BIST Part1 - TPG
 Introduction
 Test Pattern Generation (TPG)
 Deterministic: ROM, Algorithm, Counter
 Pseudo Random:
 Linear Feedback Shift Register (LFSR)
 Cellular Automata (CA)
 ROM/Algorithm as TPG
 ROM as TPG TPG
 Store test patterns in ROM
CUT
 Very expensive for chip-level BIST
 Maybe doable for system-level BIST
 e.g. self test program in BIOS (Basic Input/Output System)

 Algorithm as TPG
 Test pattern generation based on certain mathematical rule
 Suitable for regular structure like memory, FPGA
 Not very useful for random logic

No Good for Logic BIST

 Shift Counters as TPG
 Generates regular test sequences
 Such as walking sequence for interconnect testing
 Advantage: Linear test time
 Disadvantage: Too regular, not useful for random logic
cycle Walking Sequence
1 1 0 0 0 0 0 0 0
2 0 1 0 0 0 0 0 0 S. C.
3 0 0 1 0 0 0 0 0
4 0 0 0 1 0 0 0 0 CUT
5 0 0 0 0 1 0 0 0
6 0 0 0 0 0 1 0 0
7 0 0 0 0 0 0 1 0
8 0 0 0 0 0 0 0 1
Bridging faults between lines
can be detected
line 1 2 3 4 5 6 7 8
 Binary Counters as TPG
 N-stage binary counters
 Generate test patterns in sequence B. C.
 from 0 to 2N-1, or from 2N-1 to 0
CUT
 Advantage
 Simple design

 Exhaustive test is high quality

 Disadvantages
 Exhaustive test length is very long

 No randomness, deterministic pattern sequence

 e.g. Need 2N-1 test length to reach a 1 at MSB
 Large area overhead (compared to LFSR)

Need Random Counter for Logic BIST

 Introduction
 BSIT components: TPG, ORA, and controller
 Pros: reduced pins, tester cost, on-line testing
 Cons: area overhead, performance degradation, lower FC
 Test Pattern Generation
 Deterministic: ROM, Algorithm, Counter
 Linear Feedback Shift Register
 LFSR consist of unit delays (flip-flops, FF) and feedback (XOR )
 Two applications of LFSR:

1. LFSR without external input +

 Used for TPG FF FF FF FF

 aka Autonomous LFSR

2. LFSR with external input

 Used for ORA +

External input
+ FF FF FF FF

 =XOR
 “Linear” because XOR is mod-2 addition
 Two Types of Autonomous LFSR
 Autonomous LFSR is Modular Counter
 Very small area, generate pseudo random outputs
 Two structures:
 Type 1: Standard Form (aka external XOR) LFSR
 Type 2: Modular Form ( aka internal XOR) LFSR

Type-1 Standard LFSR Type-2 Modular LFSR

+
Q3 Q2 Q1 Q0 Q0 Q1 Q2 + Q3

LFSR is Good for TPG

VLSI Test 13.2 © National Taiwan University
 Type-1, Standard Form LFSR
 Three ways to describe LFSR
1. Next state equation: Q3 + = Q3  Q0
 Q3+ means next state of FF Q3
2. Recurrence equation: qm = qm-1  qm-4
3. Characteristic polynomial: f(x) = x4 + x3 + 1
 Most popular.

+ output bit stream

(q0 is first)
q0 q1 q2 q3 q4 q5 q6 q7
FF FF FF FF
0 0 0 1 1 1 1 0
Q3 Q2 Q1 Q0
1 0 0 0 q4 =q3  q0
q5 =q4  q1
…
qm =qm-1  qm-4
 NOTE: Modular-2 arithmetic:  + - are same
 11=0; 01=1; 10=1; 00=0
 State Sequence of x4+x3+1 LFSR
 Seed = Initial state of LFSR state Q3 Q2 Q1 Q0
seed
0 1 0 0 0
 must be non-zero
1 1 1 0 0
 Total 24-1 = 15 distinct states 2 1 1 1 0
 All-zero state not included 3 1 1 1 1
 Periodical. 4 0 1 1 1
 Cycle length Lc= 15 5 1 0 1 1
6 0 1 0 1
7 1 0 1 0
8 1 1 0 1
9 0 1 1 0
10 0 0 1 1
11 1 0 0 1
12 0 1 0 0
13 0 0 1 0
14 0 0 0 1
Back to seed after 15 cycles 15 (=0) 1 0 0 0
 State Diagram

f(x) = x4 + x3 + 1 0000
1000 0001
1100
0010

1110 0100

cycles through 24-1 states

1111
if the seed is not all-0 1001

0111 0011

1011 0110
0101 1101
1010
 Pseudo Random Pattern Generator (PRPG)
 Pseudo random. NOT truly random state Q3 Q2 Q1 Q0
q0
 Serial PRPG: q0, q1, q2, q3, … 0 1 0 0 0
q1
1 1 1 0 0
 Periodical. Lc= 15 q2
2 1 1 1 0
 Parallel PRPG: (Q3 Q2 Q1 Q0) 3 1 1 1 1 q3
 Each output shifted by one cycle 4 0 1 1 1 q4
5 1 0 1 1 q5
 Phase difference =1
6 0 1 0 1 q6
7 1 0 1 0 q7
PRPG q8
8 1 1 0 1
9 0 1 1 0 q9
10 0 0 1 1 q10
11 1 0 0 1 q11
12 0 1 0 0 q12
13 0 0 1 0 q13
Circuit Under Test
14 0 0 0 1 q14
(CUT)
15 (=0) 1 0 0 0 q15

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 BIST Part 2
 Part 1
 Introduction
 Test Pattern Generation
 Part 2
 Output Response Analysis
 BIST Architecture
 Issues with BIST
 Conclusions
 Output Response Analyzer
 What is ORA?
Compress CUT output responses into a small signature
 Compare signature with gold signature to determine pass or fail
 ORA also called signature analyzer
 What is good ORA? (very difficult to meet all requirements)
 1. Signature as small as possible
 2. Correct Pass/Fail decision (i.e. low aliasing)
 3. Small area
 4. Diagnosis support

output
Test responses signature Pass/fail
Pattern CUT ?
ORA =
Generator
Gold
signature
 Aliasing
 Aliasing occurs when
 signaturefaulty output = signaturegood output (gold signature)
 Aliasing  Fault coverage loss  Test escapes
 Defective circuits pass tests (Very bad!)

Many-to-one
Output Space mapping Signature Space
Faulty output

Faulty output

No aliasing Bad signatures

Faulty output

Good output Gold signature

Faulty output Aliasing

 BIST Part 2
 Introduction
 Pattern Generation
 Output Response Analysis
 BIST Architecture
 Problems and Solutions
 Fault Coverage Not Enough
 Structure Dependency
 Linear Dependency
 Random Pattern Resistant Fault
 Long Test Length
 “X” Unknown Output Responses
 Diagnosis/Debug
 High Test Power
 Concluding Remarks