Post Exposure Bake

• Deep UV Exposure Bake

– Temperature Uniformity
– PEB Delay
• Conventional I-Line PEB

Semiconductor Manufacturing Technology © 2001 by Prentice Hall

by Michael Quirk and Julian Serda
 Amine Contamination of DUV Resist
leading to “T-top” Formation
Region of Neutralized
unexposed photoresist
photoresist Resist T-topping

}
H+ PAG H+
PAG
H+ PAG H+
PAG Development
H+
PAG H+
PAG
H+ H+
PAG

H+ PAG H+

Acid-catalyzed
reaction of
exposed resist
(post PEB)

Semiconductor Manufacturing Technology Figure 15.1 © 2001 by Prentice Hall

by Michael Quirk and Julian Serda
 Reduction of Standing Wave Effect due to PEB
Standing Unexposed Exposed
waves photoresist photoresist
PAC PAC PAC PAC PAC
PAC PAC PAC
PAC
PAC PAC
PAC PAC
PAC PAC PAC
PAC PAC
PAC PAC PAC
PAC PAC
PAC
PAC PAC
PAC PAC PAC PAC PAC
PAC PAC PAC
PAC
PAC PAC PAC
PAC PAC

(a) Exposure to UV light (b) Striations in resist

PAC PAC
PAC
PAC
PAC
PAC PAC
PAC
PAC
PAC PAC

PAC PAC
PAC PAC

PAC PAC

(c) PEB causes PAC diffusion (d) Result of PEB

Semiconductor Manufacturing Technology Figure 15.2 © 2001 by Prentice Hall

by Michael Quirk and Julian Serda
 Develop

• Negative Resist
• Positive Resist
• Development Methods
• Resist Development Parameters

Semiconductor Manufacturing Technology © 2001 by Prentice Hall

by Michael Quirk and Julian Serda
 Photoresist Development Problems

Resist Substrate

X X Ö X
Under Incomplete Correct Severe
develop develop develop overdevelop

Semiconductor Manufacturing Technology Figure 15.3 © 2001 by Prentice Hall

by Michael Quirk and Julian Serda
 Negative Resist Crosslinking

UV

Exposed resist

Crosslinks
Unexposed resist

Semiconductor Manufacturing Technology Figure 15.4 © 2001 by Prentice Hall

by Michael Quirk and Julian Serda
 Development of Positive Resist

Resist exposed to light

dissolves in the Unexposed
develop chemical. positive resist

Crosslinked
resist

Semiconductor Manufacturing Technology Figure 15.5 © 2001 by Prentice Hall

by Michael Quirk and Julian Serda
 Development Methods

• Continuous Spray Development

• Puddle Development

Semiconductor Manufacturing Technology © 2001 by Prentice Hall

by Michael Quirk and Julian Serda
 Resist Development with Continuous Spray

Spray
Vapor Resist Develop- Edge-bead
Load Station Prime Coat Rinse Removal Transfer Station

Wafer Transfer System

Vacuum chuck
To vacuum
pump Spindle
connected to
spin motor
Soft Cool Cool Hard
Bake Plate Plate Bake

(a) Wafer track system (b) Developer spray dispenser

Semiconductor Manufacturing Technology Figure 15.6 © 2001 by Prentice Hall

by Michael Quirk and Julian Serda
 Puddle Resist Development

Puddle
formation Developer
dispenser

(a) Puddle dispense (b) Spin-off excess developer

(c) DI H2O rinse (d) Spin dry

Semiconductor Manufacturing Technology Figure 15.7 © 2001 by Prentice Hall

by Michael Quirk and Julian Serda
 Resist Development Parameters

• Developer Temperature
• Developer Time
• Developer Volume
• Normality
• Rinse
• Exhaust Flow
• Wafer Chuck

Semiconductor Manufacturing Technology © 2001 by Prentice Hall

by Michael Quirk and Julian Serda
 Hard Bake

• Characteristics of Hard Bake:

– Post-Development Exposure
– Evaporates Residual Solvent in Photoresist
– Hardens the Resist
– Improves Resist-to-Wafer Adhesion
– Prepares Resist for Subsequent Processing
– Higher Temperature than Soft Bake, but not
to Point Where Resist Softens and Flows
• Resist Hardening with Deep UV
Semiconductor Manufacturing Technology © 2001 by Prentice Hall
by Michael Quirk and Julian Serda
 Softened Resist Flow at High Temperature

Photoresist

Semiconductor Manufacturing Technology Figure 15.8 © 2001 by Prentice Hall

by Michael Quirk and Julian Serda
 Develop Inspect

• Post-Develop Inspection to Find Defects

• Find Defects before Etching or Implanting
• Prevents Scrap
• Characterizes the Photo Process by
Providing Feedback Regarding Quality of
the Lithography Process
• Develop Inspect Rework Flow

Semiconductor Manufacturing Technology © 2001 by Prentice Hall

by Michael Quirk and Julian Serda
 Automated Inspection Tool for Develop Inspect

Photograph courtesy of Advanced Micro Devices, Leica Auto Inspection station

Semiconductor Manufacturing Technology Photo 15.1 © 2001 by Prentice Hall

by Michael Quirk and Julian Serda
 Develop Inspect Rework Flow

UV light
Resist Mask
HMDS

1. Vapor prime 2. Spin coat 3. Soft bake 4. Align and expose 5. Post-exposure bake

O2

Rejected wafers

Plasma
Strip and clean 8. Develop inspect 7. Hard bake 6. Develop

Rework

Ion implant Passed wafers Etch

Semiconductor Manufacturing Technology Figure 15.9 © 2001 by Prentice Hall

by Michael Quirk and Julian Serda
 Advanced Lithography

• Next Generation Lithography

– Extreme UV (EUV)
– SCALPEL
– Ion Projection Lithography (IPL)
– X-Ray
• Advanced Resist Processing
– Development Trends of Photoresist and
Lithography
– DESIRE Process

Semiconductor Manufacturing Technology © 2001 by Prentice Hall

by Michael Quirk and Julian Serda
 Photolithography Improvements

1. Reduction in wavelength of the UV light source.

2. Increase in numerical aperture.
3. Chemically amplified DUV resists
4. Resolution enhancement techniques (e.g., phase-shift
masks and optical proximity correction).
5. Wafer planarization (chemical mechanical
planarization, or CMP) to reduce surface topography.
6. Advances in photolithography equipment (e.g., stepper
and step-and-scan).

Semiconductor Manufacturing Technology Table 15.2 © 2001 by Prentice Hall

by Michael Quirk and Julian Serda
 Concept for Extreme Ultraviolet Lithography

Step-and-scan 4×
High power reflection reticle Multilayer
laser coated mirrors

EUV

¼ image
of reticle
Plasma

Target Step-and-scan
material wafer stage
Vacuum chamber

Redrawn from International SEMATECH's Next Generation Lithography Workshop Brochure

Semiconductor Manufacturing Technology Figure 15.10 © 2001 by Prentice Hall

by Michael Quirk and Julian Serda
 Concept of SCALPEL
Electron beam

Step-and-scan
reticle stage

Electrostatic
lens system
(4:1 reduction)

Step-and-scan
wafer stage

Vacuum chamber

Redrawn from International SEMATECH's Next Generation Lithography Workshop Brochure

Semiconductor Manufacturing Technology Figure 15.11 © 2001 by Prentice Hall
by Michael Quirk and Julian Serda
 Ion Projection Lithography
Ion source
Ion beam
Mask

Electrostatic
lens system
(4:1 reduction)
Reference
plate

Step-and-scan
wafer stage

Vacuum chamber

Redrawn from International SEMATECH's Next Generation Lithography Workshop Brochure

Semiconductor Manufacturing Technology Figure 15.12 © 2001 by Prentice Hall
by Michael Quirk and Julian Serda
 X-ray Spectrum

Hard X-rays Soft X-rays UV Spectrum

EUV DUV MUV

0.1 nm 1 nm 10 nm 100 nm

Synchrotron Excimer laser Hg

source lamp

Semiconductor Manufacturing Technology Figure 15.13 © 2001 by Prentice Hall

by Michael Quirk and Julian Serda
 Concept of X-ray Photomask
Gold plated chrome
Silicon wafer pattern X-ray absorbers
Glass frame Window etched into
lower membrane

Membrane

Scanning X-rays are directed toward a

production wafer through a photomask
similar to this one.

Redrawn from C. Y. Chang and S. M. Sze, ULSI Technology, edited by

C. Y. Chang and S. M. Sze (New York: McGraw-Hill 1996) p.314

Semiconductor Manufacturing Technology Figure 15.14 © 2001 by Prentice Hall

by Michael Quirk and Julian Serda
 Development Trends of Photoresist and Lithography

Negative photoresist 1970s 10 mm Contact Printer

1.2 mm Scanning Aligner

Positive photoresist
(DNQ-Novolak) 1980s
1 mm G-line Stepper

0.40 mm I-line Stepper

PSM, OAI
Chemical amplification 1990s 0.35 mm
DUV Stepper

0.18 mm DUV Step and Scan

EUV Step and Scan

Advanced photoresist 2000s 0. 13 mm
top surface imaging SCALPEL

2010 0. 1 mm IPL, X-ray

Semiconductor Manufacturing Technology Figure 15.15 © 2001 by Prentice Hall

by Michael Quirk and Julian Serda
 Top Surface Imaging

UV
Exposed resist Exposed Crosslinked

Unexposed
resist

(a) Normal exposure process (b) Post exposure bake

O2 plasma
develop
HMDS Silylated
exposed resist
Si Si

(c) Vapor phase silyation (d) Final developed pattern

Semiconductor Manufacturing Technology Figure 15.16 © 2001 by Prentice Hall

by Michael Quirk and Julian Serda