CMS COLLEGE OF ENGINEERING

ERNAPURAM, NAMAKKAL – 637003

DEPARTMENT OF BIOMEDICAL ENGINEERING

BM3412 ANALOG AND DIGITAL INTEGRATED

CIRCUITS LABORATORY

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Reg. No. : ……………………………………

Branch : ……………………………………

Year & Semester : ……………………………………

 CMS COLLEGE OF ENGINEERING
ERNAPURAM, NAMAKKAL – 637003

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Certified that this is the bonafide record of work done in BM3412 ANALOG AND DIGITAL

INTEGRATED CIRCUITS LABORATORY by Mr./Ms...................................................... of

FOURTH SEMESTER of BIOMEDICAL ENGINEERING during the academic year 2023-2024.

STAFF-IN-CHARGE HEAD OF DEPARTMENT

Submitted for the University Practical Examination held on ............................ his/her

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INTERNAL EXAMINER EXTERNAL EXAMINER

 INDEX
Page
Exp. No. Date Name of the Experiment No. Mark Sign.
1
 INVERTING AMPLIFIER:-
CIRCUIT DIAGRAM:-

Rf

+15v

R1=10K 2 7
-
IC 741
Signal
Generator + 3 + 4
6
+
~
Vin CRO
-15v
- -

TABULATION:

Theoretical Gain Practical Gain

S.No Rf (KΩ) Vin (Volts) Vout (Volts) A = -Rf / R1 A = V0 / Vin
1. 1K
2. 10K
3. 33K
4. 100K

MODEL GRAPH:
Vin

INPUT

Time (ms)

Vout

OUTPUT

Time (ms)

2
EXP.NO:01
DESIGN OF INVERTING, NON INVERTING AMPLIFIER
DATE: AND COMPRATOR

AIM:
To design the Inverting, Non-Inverting and Differential Amplifiers using
Op-amp IC741 and test their performance.

APPARATUS REQUIRED:

S.NO COMPONENTS RANGE QUANTITY

1. IC 741 01
1KΩ, 33KΩ EACH 01
2. RESISTORS
10KΩ, 100 KΩ. EACH 02
3. DIGITAL TRAINER KIT --- 01
4. SIGNAL GENERATOR (0-3)MHz 01
5. CATHODE RAY OSCILLOSCOPE (0-30)MHz 01
6. CONNECTING WIRES --- FEW

THEORY:
Op-amp in open-loop configuration has a very few application because
of its enormous open-loop gain. Controlled gain can be can be achieved by taking a
part of output signal to the input with the help of feedback. This is called as Closed-
Loop Configuration. The three basic types of closed-loop amplifier configuration
are: 1. Inverting amplifier.
2. Non-inverting amplifier.
3. Differential amplifier.
The entire configuration can be operated with either AC or DC input.

INVERTING AMPLIFIER:-

If the input signal is applied to the inverting terminal through an input

resistance, a part of output is feedback to the inverting terminal through feedback
resistance Rf and the non-inverting terminal grounded, then the configuration is said
to be Inverting Amplifier. It provides 1800 phase shift or polarity reversal for the
given input.

Rf
The circuit closed-loop voltage gain is Avcl .
R1

3
 NON-INVERTING AMPLIFER:-
CIRCUIT DIAGRAM:-

Rf

+15v
R1=10K 2 7
-
IC 741
+ 3 + 4
6
+
Signal V i n CRO
Generator - -15v
-

TABULATION:

Vin Vout Theoretical Gain Practical Gain

S.No Rf (KΩ) A = 1+(Rf / R1) A = V0 / Vin
(Volts) (Volts)
1. 1K
2. 10K
3. 33K
4. 100K

MODEL GRAPH:

Vin

INPUT

Time (ms)

OUTPUT

Vout
Time (ms)

4
THEORY – (NON-INVERTING AMPLIFIER):-
If the input signal is given to non inverting terminal & the feedback
from output is connected to inverting terminal of an op-amp through a potential
divider network, then it is called as Non-Inverting Amplifier Configuration. It
operates in a same way as a voltage follower (unity gain buffer), except that the
output voltage is potentially divided before it is fedback to the inverting input
terminal. No phase shift or change in the circuit closed loop polarity occurs voltage
Rf
Avcl 1
gain is R1

PROCEDURE-(INVERTING & NON-INVERTING AMPLIFIER):-

1. Select R1 as a constant value and choose a value of Rf.
2. Connect the circuit as per as the circuit diagram.
3. Apply the constant amplitude input voltage to the circuit.
4. Measure the output voltage amplitude for different value of Rf from CRO.
5. Calculate the practical gain for different value of Rf & compare it with
theoretical gain.
6. Practical gain & theoretical gain should be approximately equal.
7. Plot the graph of the input wave versus output wave for any one practical case.

5
 COMPARATOR :-
CIRCUIT DIAGRAM:-

TABULATION:

Amplitude Frequency Theoretical Practical

S.No reference voltage
reference
voltage
1.

2.

3.

6
 THEORY-(COMPARATOR):-

A Comparator is a circuit which compares signal on one input of op-amp with a reference
voltage on the other input. In a simplest form it is nothing more than an open loop
op-amp with two analog input and a digital output. Output of comparator may be (+) or (-)
saturation voltage, depending upon which input is larger. Comparators are widely used
in the circuits such as digital interfacing, Schmitt triggers, discriminators,
voltage level detectors and oscillators.
Output of this circuit can be +ve or –ve Vsat depending upon the condition mentioned below:

PROCEDURE:
1. Refer the Pin Diagram of op-amp IC741 & assemble the basic comparator in inverting
configuration circuit as per circuit diagram on the breadboard.
2. Set the DC power supply to provide +VCC & -VEE by making necessary adjustment
& Apply VCC & VEE = ±15V at respective pins of op-amp IC 741.
3. Set the function generator to provide 2V (p-p) sine wave at 500HZ & Apply this
AC input at pin 2 (INV) of op-amp IC741.
4. Set the DC power supply to provide 0.5V reference voltage by making necessary.
adjustment & Apply this reference voltage signal at pin 3 (NI) of op-amp IC 741.
5. Observe the output of this circuit on CRO/DSO.
6. Measure the output voltage swing .Note the readings in the observation table.
7. Plot the output voltage waveforms.

RESULT:
Thus the Inverting, Non-Inverting and Comparator are designed and
their performance was successfully tested using op-amp IC 741.
7
 INTEGRATOR:-
CIRCUIT DIAGRAM:-
Cf=0.01uf

Rf 15k
+15v
R1=1.5k 2 - 7
6
Signal IC 741
Generat+ors +
3 4 +
V~
1.5K RL=10k
in Rcomp CRO
-15v
-

TABULATION:
Frequency Output Voltage Gain = 20 log (V0 /Vin)
S.No
(Hz) (Volts) (dB)
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.

MODELGRAPH:

8
EXP.NO:02
DESIGN OF INTEGRATOR AND DIFFERENTIATOR
DATE:

AIM:
To design an Integrator and Differentiator using op-amp IC 741 and to test their
performance.

APPARATUS REQUIRED:

S.NO COMPONENTS RANGE QUANTITY

1. IC 741 --- 01
100 Ω, 1.5KΩ Each 02
2. RESISTORS
10KΩ, 15KΩ Each 01
0.1μf, 0.01μf Each 01
3. CAPACITOR
0.001μf, 05
4. DIGITAL TRAINER KIT --- 01
5. SIGNAL GENERATOR (0-3)MHz 01
6. CATHODE RAY OSCILLOSCOPE (0-30)MHz 01
7. CONNECTING WIRES --- FEW
THEORY – (INTEGRATOR):-
A circuit in which the output voltage waveform is the integral of the
input voltage waveform is the integrator or integration amplifier; Such a circuit is
obtained by using basic inverting amplifier configuration, if the feed back resistor Rf
is replaced by a capacitor Cf. The Output voltage expression is given as
t
1
VO Vin dt C.
R1 C f o

The frequency of input at which the gain is 0 db is given as fb

2 R1 C f
The point up to which the gain is constant & maximum is called as gain limiting
frequency & given as fa Where Rf is the feedback resistor used to correct
2 Rf C f
the stability & roll-off problems. Between fa & fb the circuit acts as an integrator and
it is similar to a LPF. Integrator is most commonly used in analog computers, A/D
converter & signal wave shaping circuits.
Integrator as LPF (Characteristics of integrator)
Design of integrator with a lower frequency (Break Frequency) limit of
integration at fa = 1 KHz & the frequency at which 0dB results fb = 10 KHz.
PROCEDURE:
1. From the given frequency fa & fb, the values of Rf, Cf, R1 & Rcomp are
calculated as given in the design procedure.
2. Connect the circuit as shown in the circuit diagram.
3. Apply the sinusoidal input as the constant amplitude to the inverting terminal
of op-amp.
4. Gradually increase the frequency & observe the output amplitude.
5. Calculate the gain with respect to frequency & plot its graph.
9
CIRCUIT DIAGRAM:
Cf=0.005μf

Rf 1.5k
+15v
R1=100Ω C1=0.1μf 2 - 7 6
IC 741
+ 3 + 4 +
Signal ROM=100Ω R3=10K CRO
Generators -15v
-

0
TABULATION:

1. Frequency (Input)
2. Input Voltage (Vin peak)
3. Input Time Period (tVin)
4. Output Voltage (Vout peak)
5. Output Time Period (tVo)

MODEL GRAPH:
(i) SINE WAVE INPUT

10
THEORY- (DIFFERENTIATOR):-
A differentiator or differentiation amplifier is a circuit which performs
the mathematical operation of differentiation; that is, the output waveform is the
derivative of the input waveform. The differentiator may be constructed from the
basic inverting amplifier if an input resistor R1 is replaced by capacitor C1. The
differentiation is very useful to find the rate at which a signal varies with time. For
maintaining the stability of differentiator, a series resistor R1 is connected with input
capacitor C1. the circuit will provide differentiation function but only over a limited
frequency range & over this range differentiator tend to oscillate (or) poor stability

results. The expression for output voltage is f 1

PROCEDURE:
1. Select fa equal to the highest frequency of the input signal to be differentiated.
Calculate the component values of C1 & Rf.
2. Choose fb = 20fa & calculate the values of R1 & Cf, so that R1C1=Rf Cf.
3. Connect the components as shown in the circuit diagram.
4. Apply a sinusoidal & square wave input to the inverting terminal of op-amp
through R1 C1.
5. Observe the shape of the output signal for the given input in CRO.
6. Note down the reading and plot the graph of input versus output wave for both
cases.
(ii) SQUARE WAVE INPUT

11
DESIGN PROCEDURE-(INTEGRATOR):-
Design of integrator to integrate at cut-off frequency 1 KHz.
1
Take fa =
2 Rf C f
= 1KHz.
Always take Cf < μf and

Let Cf = 0.01μf

1
Rf =
2 C f fa

Rf = 15.9KΩ ≡

Rf = 15KΩ

1
Take fb = = 10KHz.
2 R1C f
1
R1 = = 1.59KΩ.
2 f bC f

R1 ≡ 1.5KΩ
R1Rf
R = R1 // Rf = ≡ R1, Assume RL = 10KΩ
comp
R1 R f

Rcomp = 1.5KΩ

DESIGN PROCEDURE-(DIFFERENTIATOR):-
Design a differentiator to differentiate an input signal that varies in frequency
from 10Hz to 1KHz. Apply a sine wave & square wave of 2Vp-p & 1KHz frequency
& observe the output.
To find Rf & C1
Given: fa = 1KHz.
1
fa =
2 Rf C1

fa = 1KHz.

Assume C1 = 0.1μf

Rf = 1.59KΩ ≡ 1.5KΩ

12
To find R1 & Cf
Select fb = 20fa with R1 C1 = Rf Cf
1
fb = 20KHz =
2 R1C1

R1 = 79.5Ω ≡ 100Ω

R1C1 6
Cf = = 82 X 0.1X10
Rf 1.5K

Cf = 0.005μf.

Rom ≡ R1 // Rf = 100Ω

SINE WAVE INPUT:

Vp-p = 2V f=1KHz
Vp = 1V,
Vin = Vp sin t
= sin (2 )(103)t
dVin
Vo = -Rf c1
dt
d
= -(1.5KΩ) (0.1μf) [sin [(2 )(103)t]
dt
= -(1.5KΩ) (0.1μf) (2 ) (103) cos [(2 )(103)t]
= - 0.94 cos [(2 )(103)t]

RESULT:
Thus an Integrator and Differentiator using op-amp are designed and their
performance was successfully tested using op-amp IC 741.

13
 LOWPASS FILTER:-
CIRCUIT DIAGRAM:-
R1=27K RF=20K

+15v
2 - 7
Signal IC 741
Generator 1.5K
+ 6
3 4
+ +
RL=10K
Vin ~ 0.1uf
-15v
CRO
-

TABULATION:
Frequency Output Voltage Gain = 20 log (V0 /Vin)
S.No
(Hz) (Volts) (dB)
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.

MODEL GRAPH:

14
EXP.NO:03
DESIGN AND ANALYSIS OF ACTIVE FILTERS USING
DATE: OPAMP

AIM:
To design an Active Lowpass and Band Pass Filter using op-amp and to test
their performance

APPARATUS REQUIRED:

S.NO COMPONENTS RANGE QUANTITY

1. IC 741 --- 02
1.5 KΩ,22KΩ, 27KΩ EACH 02
2. RESISTORS
10KΩ 01
3. CAPACITORS 0.1μf, 0.01μf 01
4. DIGITAL TRAINER KIT --- 01
5. SIGNAL GENERATOR (0-3)MHz 01
6. CATHODE RAY OSCILLOSCOPE (0-30)MHz 01
7. CONNECTING WIRES --- FEW

THEORY – (ACTIVE LPF):-

A filter circuit which allows only low frequency range up to a higher

cut-off frequency fH is called as Low Pass Filter. An active filter uses transistor and
components such as resistor & capacitor for its design. An active filter offers the
following advantages over a passive filter.
1. Gain & frequency adjustment flexibility.
2. No loading problem because of high input impedance & low output impedance.
3. More economical because of variety of op-amps and absence of inductors.

From the frequency response, when f<fH; the gain is maximum lAl. When

f=f ; the gain is 70.7% of the maximum gain A and when f f the gain drops or
H H;
2
rolls off. The frequency range from 0 to fH is called as Passband & fH to is called
as Stopband. Out of Butterworth, chebyshev & cauer filters, Butterworth filter is
preferred because it has flat pass band as well as flat stop band (flat-flat) filter.

15
 CIRCUIT DIAGRAM - (HIGH PASS FILTER):-
R1=27K RF=22K

+15v
2 7
-
Signal 0.1μf IC 741
Generator 6
3 + 4 +
+
RL=10K
Vin ~ 1.5K -15v
CRO
-

TABULATION:
Frequency Output Voltage Gain = 20 log (V0 /Vin)
S.No
(Hz) (Volts) (dB)
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.

MODEL GRAPH:

16
THEORY- (ACTIVE HPF):-
An active high pass filter is simply formed by interchanging the
frequency determining resistor and capacitor in lowpass filter. A filter circuit which
allows only high frequency range greater then a lower cut-off frequency fL is called
as HIGH PASS FILTER. From the frequency response, when f<fL; the gain
gradually increases from the lowest value. When f = fL; the gain reaches 70.7% of the
A
maximum gain and when f > fL, the gain is maximum lAl. The frequency range
2
from 0 to fL is called as Stopband & fL to is called as Passband. (This is exactly
opposite to active LPF)The order of the filter tells the roll-off rate at stop band. Order
n = 1 indicates -20dB / dec (-6db / octave); Order n = 2 indicates -40dB / dec & so on.
Higher the order of the filter, better the quality will be & complex the circuit will be.

DESIGN PROCEDURE: (ACTIVE HPF):

Design a HPF at cutoff frequency fL of 1KHZ & P.B gain of 2. Follow the same
procedure as LPF & interchange the R & C position with capacitor first & resistor in
parallel.
Vo Af ( f / f L )
In high pass filter Theoretical gain is given as =
Vin 1 ( f / f H )2
PROCEDURE - (LPF & HPF):
1. Connect the circuit as shown in the circuit diagram.
2. Select the corresponding cut-off frequency (higher or lower) and determine the
value of C&R. select the value of R1 & Rf depending on desired passband
gain Af..
3. Apply a constant voltage input sinusoidal signal to the non-inverting terminal
of op-amp.
4. Tabulate the output voltage Vo with respect to different values of input
frequency.
5. Calculate passband gain and plot the graph of frequency versus voltage gain &
check the graph to get approximately the same characteristic as shown in the
model graph.

17
CIRCUIT DIAGRAM: (BANDPASS FILTER)
R1=27K RF=20K
R1=27K RF=20K

+15v
+15v
2 7
2 7
-
- IC 741
Signal 6
Generator
0.1 uf
IC 741 3 + 4
+ 3 + 4
6 1.5K
+
0.01uf -15v CRO
Vin ~ 1.5K -15v RL=10K -

TABULATION:
Frequency Output Voltage Gain = 20 log (V0 /Vin)
S.No
(Hz) (Volts) (dB)

MODEL GRAPH:

18
THEORY – (ACTIVE BANDPASS FILTER):-

A filter which has a pass band between two cut-off frequencies fH & fL
is called as Bandpass filter. Where fH > fL BPF is basically of two types
(i) Wide band pass filter. (ii) Narrow band pass filter.
Based on figure of merit or quality factor Q, the types are classified as follows. If
Q<10, selectivity is poor & allows higher bandwidth & such BPF is called as wide
BPF.
If Q > 10, selective is more and allows only narrow bandwidth & such
BPF is called as Narrow BPF. Relationship between Q & center frequency fC is
given as

fc fc
Q & fc
BW fH fL

When frequency fL < f < fH then gain is maximum. At f < fL the gain is
gradually increasing (positive roll-off) from lower value & at f > fH the gain is
gradually decreasing (Negative roll-off) & exactly when f = fL & f = fH the gain is
A
70.7% of maximum gain .
2
PROCEDURE:
1. Select the lower and higher cut-off frequency and calculate the value of R & C
for the given frequencies.
2. Design for LPF & HPF separately and then combine the circuit by first placing
the HPF followed by a LPF (i.e) HPF in series with LPF.
3. Connect the circuit as shown in the circuit diagram.
4. Apply a constant voltage input sinusoidal signal to the non-inverting terminal
of op-amp.
5. Tabulate the output voltage Vo with respect to different values of input
frequency.
6. Calculate passband gain and plot the graph of frequency versus voltage gain &
check the graph to get approximately the same characteristic as shown in the
model graph.

19
 DESIGN PROCEDURE - (ACTIVE BPF):-
Design a BPF to pass a band of 1KHz to 10KHz with a passband gain of 4.
1. Select the highest cut-off frequency of LPF as fH = 10 KHz and the lowest cut-
off frequency of HPF as fL = 1 KHz.
2. Design the HPF first by taking fL = 1KHz. Assume the value of C < 1μf.
Let C = 0.1μf.
3. Calculate R from the expression.
1 1
FL = ; Therefore R1 =
2 RC 2 f LC
1
R= ;
2 (1KHz)(0.1X10 6 )
R = 1.59KΩ ≡ R=1.5KΩ
4. Then design the LPF by taking fH = 10KHz. Assume the value of C < 1μf. Let
C = 0.01μf.
1 1
5. Calculate R from the expression fH = ; Therefore R =
2 RC 2 fH C
1
R= ;
6
2 (10KHz)(0.01X10 )

R = 1.59KΩ ≡ R=1.5KΩ

6. Calculate the values of Rf & R1 with the use of pass band gain.
Overall P.B gain of BPF = 4 = 2 (HPF) X 2 (LPF)

Therefore for both HPF & LPF the value of Rf = R1 to obtain a individual
Rf
P.B gain of 2. Af = (1+ ) = 2 (for HPF)
R1
Rf
Af = (1+ ) = 2 (for LPF)
R1
Let Rf = R1 = 22KΩ.

fc fc
7. Q of the filters is calculated as =
B.W fH fL

Where fC = is the center frequency.

8. Cascade HPF & then LPF to form BPF.

Calculate the practical gain dB using 20 log (Vo/Vin)
f
And Theoretical gain is Vo = AfT ( f )
Vin

20
 DESIGN PROCEDURE (ACTIVE LPF):
Design a LPF at cutoff frequency fH of 1KHz with a passband gain of 2.
1. Choose the given value of fH = 1KHz.

2. Select the value of C < 1μf

1
3. Assume C = 0.1μf. Calculate R from FH =
2 RC
1
R=
2 fH C

1
R= = 1.5KΩ
2 X1X103 X 0.1 f
R = 1.5KΩ C = 0.1μf

4. Determine the value of R1 & Rf from pass band gain of the filter.
Rf
Af = 1 + = 2.
R1
Therefore Rf =R1 to select Af = 2.
Assume Rf = R1 = 22KΩ & Assume RL = 10KΩ

5. Calculate the practical gain in dB using Gain (dB)=20log (Vo/Vin);

Vo Af
Theoretical gain is given as =
Vin 1 ( f / f H )2
Af – P.B gain.
f – Input frequency.
fH – Higher cut-off frequency of LPF.

RESULT:
Thus an Active Lowpass, High pass and Band Pass Filters are designed
and tested using op-amp IC 741.

21
SCHMITT TRIGGER:-
CIRCUIT DIAGRAM:-
+15v
ROM=R1//R2 - 7
10KΩ IC 741
3 + 4
6
+
-15V RL=10K +
Vin
~ R2=100K
CRO
-
R1
10K

TABULATION:

O/P
I/P Voltage I/P Time VUT (UTP) VLT (LTP) O/P Time
Voltage
(Volts) (ms) (Volts) (Volts) (ms)
(ms)

MODEL GRAPH:

22
EXP.NO:04
SCHMITT TRIGGER USING OPERATIONAL
DATE: AMPLIFIER

AIM:
To design a Schmitt trigger using op-amp IC 741 and to test their characteristics.

APPARATUS REQUIRED:

S.NO COMPONENTS RANGE QUANTITY

1. IC 741 --- 01
100Ω, 100KΩ, EACH 01
2. RESISTORS
10KΩ, 47KΩ, EACH 03
3. DRB (0-10)MΩ 01
4. CAPACITORS 0.01μf, 0.1μf 01
5. DIODE 1N4007 02
6. DIGITAL TRAINER KIT --- 01
7. SIGNAL GENERATOR (0-3)MHz 01
7. CATHODE RAY OSCILLOSCOPE (0-30)MHz 01
8. CONNECTING WIRES --- FEW

THEORY-(SCHMITT TRIGGER):-

A circuit which converts a irregular shaped waveform to a square wave

or pulse is called a Schmitt trigger or squaring circuit. The input voltage Vin triggers
the output Vo every time it exceeds certain voltage levels called upper threshold
voltage VUT and lower threshold voltage VLT. The threshold voltages are obtained by
using the voltage divider. A comparator with positive feedback is said to exhibit
hysteresis, a dead band condition. The hysteresis voltage is the difference between
VUT & VLT.
There are two types of Schmitt trigger based on where the irregular wave is
given. They are, Inverting & non-inverting Schmitt trigger. Schmitt trigger finds
application in wave shaping circuits. The other name given to Schmitt trigger is
regenerative comparator.

23
DESIGN PROCEDURE:-
1. Select the desire value of Vut & Vlt with same magnitude & opposite polarity.
Let Vut = 1V & Vlt = -1V.

2. For Op-amp 741C ± Vsat ≡ ±13V to ± 14V. And assume Vref = 0, Since the
another end of R1 is grounded.

3. if Vo = +Vsat the voltage at the positive terminal will be (voltage from

potential divider R1 & R2).
R1
Vut = Vref + (Vsat - Vref )
R1 R2
Therefore Vref = 0.
R1
= Vut (+ V sat).
R1 R2
R1
4. Similarly Vlt will be Vlt = ( ) – Vsat.
R1 R2
5. Sub Vut & assume R1 or R2 & find the other component value.
R1
1V = (13)
R1 R2
R1 + R2 = 13R1
R2 = 12R1 if R1 = 10K then R2 = 120K ≡100K.

6. Calculate ROM by
R1R2 (10K )(100K ) .
ROM = R1 // R2 =
R1 R2 110K
1000K
ROM = ≡ 10KΩ. & select RL = 10KΩ (Assumption)
110K
7. Calculate hystersis voltage
Vhy = Vut – Vlt
R1
= [+Vsat – (-Vsat)]
R1 R2
10K
= [26V] Since Vsat = 13V
110K
= 0.0909 [26V]
Vhy = 2.363V

24
PROCEDURE:
1. Design the value of circuit components and select VUT & VLT as given in the
design procedure.
2. Connect the circuit as shown in the circuit diagram.
3. Apply the input signal to the input terminal of op-amp & set VUT & VLT
values.
4. Note down the readings from the output waveform.
5. Plot the graph & show the relationship between Input sine wave & Output
square wave.

RESULT:
Thus a Schmitt trigger are designed and tested using op-amp IC 741.

25
CIRCUIT DIAGRAM:

+15v

3 7
+IC 741
Rf=1K

- 4
6
+15v
R2=1K
-15v
R1=1K 2 7
-
IC 741
6
RG 22K 3 + 4
+ R1=1K
V1 -15v

-
~ R2=1K
+

+15v R1=1K V
-
2 7
-
IC 741
6
+ 3 + 4
V2

-
~ -15v

26
EXP.NO:05
INSTRUMENTATION AMPLIFIER USING
DATE: OPERATIONAL AMPLIFIER

AIM:
To construct and test the CMRR of an instrumentation amplifier using op-amp
IC741.

APPARATUS REQUIRED:

S.NO COMPONENTS RANGE QUANTITY

1. IC 741 03
1KΩ. 06
2. RESISTORS
22KΩ 01
3. DIGITAL TRAINER KIT --- 01
4. SIGNAL GENERATOR (0-3)MHz 02
5. CATHODE RAY OSCILLOSCOPE (0-30)MHz 01
6. CONNECTING WIRES --- FEW

THEORY:

An instrumentation amplifier is the intermediate stage of a instrumentation

system. The signal source of the instrumentation amplifier is the output of the
transducer. Many transducers output do not have the ability or sufficient strength to
drive the next following stages. Therefore, instrumentation amplifiers are used to
amplify the low-level output signal of the transducer so that it can drive the following
stages such as indicator or displays.
The major requirements of a instrumentation amplifier are precise,low-
level signal amplification where low-noise, low thermal and time drifts, high input
resistance & accurate closed-loop gain, low power consumption, high CMRR & high
slew rate for superior performance.

27
 TABULATION:

COMMON MODE GAIN CALCULATION AC

Vo
Ac =
RG VI V2 Vo V1 V2
S.No
(KΩ) (Volts) (Volts) (Volts)
2

1.

2.

3.

4.

5.

DIFFERENTIAL MODE GAIN AD & CMRR CALCULATION.

V1 V2 Vo Vo CMRR =
S.No RG (KΩ) Ad =
20 log ( Ad Ac )(dB)
(Volts) (Volts) (Volts) V1 V2

1.

2.

3.

4.

5.

28
PROCEDURE:
1. Select the entire resistor with same value of resistance R. Let RG be the gain
varying resistor with different values of resistance for simplicity let RG, be a
constant value.
2. Connect the circuit as shown in the circuit diagram.
3. Give the input V1 & v2 to the non-inverting terminals of first & second op-
amp respectively.
4. By varying the value of RG, measure the output voltage for common mode and
differential mode operation. Since RG is selected as constant value, provide
different input value of V1 & V2.
5. Calculate the differential mode gain Ad and common mode gain Ac to
Ad
calculate the CMRR as CMRR=20 log .
Ac

RESULT:
Thus an instrumentation amplifier was constructed and CMRR is
tested using op-amp IC 741.

29
RC PHASE SHIFT OSCILLATOR:-
CIRCUIT DIAGRAM:-

Rf=1MΩ
+15v
R1=33K 2 - 7
IC 741
3 + 4
6
R1//Rf
33K -15v
+
CRO
C=0.1μf C=0.1μf0 C=0.1μf
-

R=3.3K R=3.3K R=3.3K

TABULATION:.

OBSERVED OUTPUT WAVEFORM

Amplitude Design Frequency
Time period Frequency (Hz)
(volts)
(ms) (Hz)

MODEL GRAPH:

Vout

OUTPUT Time (ms)

30
EXP.NO:06
RC PHASE SHIFT AND WIEN BRIDGE OSCILLATOR
DATE: USING OPERATIONAL AMPLIFIER

AIM:
To design RC Phase Shift and Wien Bridge Oscillator using op-amp IC
741 and to test its performance.
APPARATUS REQUIRED:

S.NO COMPONENTS RANGE QUANTITY

1. IC 741 --- 01
1.5KΩ 3.3KΩ, 33KΩ, EACH 03
2. RESISTORS
10 KΩ 22 KΩ, 1MΩ, EACH 01
3. CAPACITORS 0.1μf 03
4. DIGITAL TRAINER KIT --- 01
5. CATHODE RAY OSCILLOSCOPE (0-30)MHz 01
6. CONNECTING WIRES --- FEW

THEORY:
RC phase shift oscillator produces 360° of phase shift in two parts. Firstly,
each and every RC pair in the feedback network produces 60° phase shift and totally
there were three pairs, thus producing 180° Phase shift and secondly, the feedback
input is given to the inverting terminal of op-amp to produce another 180° phase shift
and a total phase shift of 360°.
1
The frequency of oscillation is given by f0 = ; If an inverting

amplifier is used, the gain must be atleast equal to 29 to ensure the oscillations with
constant amplitude that is, AV < 1. Otherwise the oscillation will die out.
DESIGN PROCEDURE:
Design a RC phase shift oscillator to oscillate at 200Hz.
1. Select fo = 200Hz.
2. Assume C = 0.1μf & determine R from fo.
1 1
fo = =R= = 3.3K.
2 6RC 2 6 f oc
3. To prevent the loading of amp because it is necessary that R1>>10R.
Therefore R1=10R=33K.
4. At this frequency the gain must be atleast 29 (i.e)Rf / R1 =29.
Therefore Rf = 29R1.
Rf = 29 (33K) = 957KΩ.
Therefore use Rf = 1MΩ.

31
WIEN BRIDGE OSCILLATOR:-
CIRCUIT DIAGRAM:-

R1=10K Rf=22K
+15v
2 - 7
IC 741
+ 6
3 4
R=1.5K C=0.1uf
-15v +
CRO
R=1.5K -
C=0.1uf

TABULATION:

OBSERVED OUTPUT WAVEFORM

Amplitude Design Frequency
Time period Frequency (Hz)
(volts)
(ms) (Hz)

MODEL GRAPH:

Vout

OUTPUT Time (ms)

32
PROCEDURE- (RC PHASE SHIFT):-
1. Select the given frequency of oscillation f0 = 200Hz.
1
2. Assume either R or C to find out the other using formula f0 = .
2 6RC
3. The gain is selected such that Rf / R1 = 29K. Assume Rf or R1 to find the other.
4. Connect the circuit as per as the circuit diagram.
5. Measure the amplitude frequency of the output signal plot the graph.

THEORY – (WIEN BRIDGE):-

A bridge circuit with two components connected in series and parallel
combination is used to archived the required of phase shift of 0 0. When the bridge is
balanced the phase shift of 00 is achieved and the feedback signal is connected to the
positive terminal; of Op-amp. So the Op-amp is acting as a non-inverting amplifier
and the feedback network do not provide any phase shift.
The major drawback of wien bridge oscillator is difficulty in balancing
the bridge circuit. This occurs because of drift in component values due to external
1
and internal disturbances. The frequency of oscillation is given as f0 = .
2 RC
DESIGN PROCEDURE:

(i) Select frequency f0 = 1KHz.

1
(ii) Use f0 = , A = 1+(Rf / R1) = 3. To find R & Rf.
2 RC
(iii) Therefore Rf = 2R1 & assume C = 0.1μf & find R from
1
R= = 1.59KΩ.
2 f oC
(iv) Assume R1 = 10K & find Rf from Rf = 2R1
Therefore Rf = 20K ≡ 22KΩ
PROCEDURE:
1. Select the given frequency of oscillation f0 = 1 KHz.
1
2. Assume either R or C to find out the other using formula . Also
2 RC
determine the value of other components as given in design procedure.
3. Connect the circuit as per as the circuit diagram.
4. Measure the amplitude and frequency of the output signal to plot the graph.

RESULT:

Thus RC Phase Shift and Wien Bridge Oscillator were designed and
tested using op-amp IC 741.
33
 CIRCUIT DIAGRAM - (ASTABLE):

+5V
6.8K HI

RA

3.3K 7 8 4 3
RB IC 555
5
6 2 1 +
CRO Vo
-
Vc C=0.1μf 0.01uf

TABULATION:

DESIGN VALUE OBSERVED VALUE

Amplitude
Waveforms
(volts) tH tL t F tH tL t F
(ms) (ms) (ms) (Hz) (ms) (ms) (ms) (Hz)

Output
waveform

Capacitor
waveform
(Capacitor
voltage Vc)

34
EXP.NO:07
MULTIVIBRATORS USING IC555 TIMERS
DATE:

AIM:
To Design and test Astable and Monostable multivibrator using 555 timer IC.

APPARATUS REQUIRED:

S.NO COMPONENTS RANGE QUANTITY

1. IC 555 --- 01

2. RESISTORS 3.3KΩ,6.8KΩ,10KΩ. EACH 01

3. CAPACITORS 0.1μf, 0.01μf. EACH01

4. DIGITAL TRAINER KIT --- 01
5. SIGNAL GENERATOR (0-3)MHz 01
6. CATHODE RAY OSCILLOSCOPE (0-30)MHz 01
7. CONNECTING WIRES --- FEW

THEORY:
When the power supply VCC is connected, the external timing capacitor „C”
charges towards VCC with a time constant (RA+RB) C. During this time, pin 3 is high
(≈VCC) as Reset R=0, Set S=1 and this combination makes Q = 0 which has
unclamped the timing capacitor „C‟.
When the capacitor voltage equals 2/3 VCC, the upper comparator triggers the
control flip flop on that Q =1. It makes Q1 ON and capacitor „C‟ starts discharging
towards ground through RB and transistor Q1 with a time constant RBC. Current also
flows into Q1 through RA. Resistors RA and RB must be large enough to limit this
current and prevent damage to the discharge transistor Q1. The minimum value of RA
is approximately equal to VCC/0.2 where 0.2A is the maximum current through the
ON transistor Q1.
During the discharge of the timing capacitor C, as it reaches V CC/3, the lower
comparator is triggered and at this stage S=1, R=0 which turns Q =0. Now Q =0
unclamps the external timing capacitor C. The capacitor C is thus periodically
charged and discharged between 2/3 VCC and 1/3 VCC respectively. The length of
time that the output remains HIGH is the time for the capacitor to charge from 1/3
VCC to 2/3 VCC.
The capacitor voltage for a low pass RC circuit subjected to a step input of VCC
volts is given by VC = VCC [1- exp (-t/RC)]
Total time period T = 0.69 (RA + 2 RB) C
f = 1/T = 1.44/ (RA + 2RB) C

35
MODEL GRAPH:

(a) : Square wave output

(b) : Capacitor voltage of Square wave output

36
DESIGN PROCEDURE:-
Design of Astable multivibrator of operation frequency = 1 KHz & duty cycle of 30%
using 555 timer IC.
Given Frequency=1000Hz
Duty cycle=30%
D= T low/T high = RB/RA+2RB*100-------------------------------------(1)
T high =0.69(RA+RB)C
T low = 0.69 RBC
From equation 1
0.30 T high = T low
0.30 * 0.69(RA+RB)C = 0.69 RBC
0.201(RA+RB)C = 0.69 RBC
0.483 RB-0.207 RA= 0 ----------------------------------------------- (2)
given f=1khz we know that T=1/f
T=1ms
T= T high + T low
0.69(RA+RB)C +0.69 RBC= 1ms.
0.69(RA+RB) +0.69 RB = 1ms./C
Let C=0.1μF
0.69RA+0.69RB +0.69 RB = 1ms./0.1*10-6
0.69RA+1.38RB = 10 4 -------------------------------------------------------------------------------- (3)

Solving equation 2 & 3 we get

RA=6.8K
RB= 2.674K ≡3.3KΩ

Procedure:
1. Calculate the component values using the design procedure.
2. Connect the circuit as shown in the circuit diagram.
3. Observe and note down the output waveform.
4. Measure the frequency of oscillations and duty cycle and then compare with
the given values.
5. Plot both the waveforms to the same time scale in a graph.

37
MONOSATBLE MULTIVIBRATOR:-
CIRCUIT DIAGRAM:-

HI

+5V
10K

7 8 4 3
IC 555
5
6 2 1 +
0.1uf CRO Vo
Vc
Trigger -
Input
0.01uf
Vin

TABULATION:

Amplitude Time period

S.No Waveforms
(volts) (ms)

1. Input waveform

2. Output waveform

Capacitive waveform
3.
(Capacitor voltage Vc)

MODEL GRAPH:

38
THEORY- (MONOSATBLE):-
A Monostable Multivibrator, often called a one-shot Multivibrator, is a pulse-
generating circuit in which the duration of the pulse is determined by the RC network
connected externally to the 555 timer. In a stable or stand by mode the output of the
circuit is approximately Zero or at logic-low level. When an external trigger pulse is
given, the output is forced to go high ( VCC). The time for which the output remains
high is determined by the external RC network connected to the timer. At the end of
the timing interval, the output automatically reverts back to its logic-low stable state.
The output stays low until the trigger pulse is again applied. Then the cycle repeats.
The Monostable circuit has only one stable state (output low), hence the name
Monostable. Normally the output of the Monostable Multivibrator is low.

DESIGN PROCEDURE:-
Let, RA = 10K
Out put pulse width tp = 10μs
tp=1.1RAC
C= 0.909μF
C=0.1μF

PROCEDURE:-
1. Calculate the value of R & C using design procedure.
2. Connect the circuit as shown in the circuit diagram.
3. Apply Negative triggering pulses at pin 2 of frequency 1 KHz.
4. Observe the output waveform and measure the pulse duration.
5. Theoretically calculate the pulse duration as Thigh=1.1 RAC

RESULT:
Thus the Astable and Monostable multivibrator is designed and tested using
555 timer IC.

39
40
 EX. NO: 8)a
STUDY OF LOGIC GATES
DATE:

AIM: -
To study about logic gates and verify their truth tables.

APPARATUS REQUIRED: -

SL No. COMPONENT SPECIFICATION QTY

1. AND GATE IC 7408 1
2. OR GATE IC 7432 1
3. NOT GATE IC 7404 1
4. NAND GATE 2 I/P IC 7400 1
5. NOR GATE IC 7402 1
6. X-OR GATE IC 7486 1
7. NAND GATE 3 I/P IC 7410 1
8 Bread Board 1

THEORY:

Circuit that takes the logical decision and the process are called logic gates. Each gate has one
or more input and only one output.
OR, AND and NOT are basic gates. NAND and NOR are known as universal gates. Basic gates
form these gates.
AND GATE

The AND gate performs a logical multiplication commonly known as AND function. The
output is high when both the inputs are high. The output is low level when any one of the inputs is low.
OR GATE

The OR gate performs a logical addition commonly known as OR function. The output is
high when any one of the inputs is high. The output is low level when both the inputs are low.
NOT GATE

The NOT gate is called an inverter. The output is high when the input is low. The output is
low when the input is high.
X- OR GATE

The output is high when any one of the inputs is high. The output is low when both the inputs
are low and both the inputs are high.
NAND GATE

The NAND gate is a contraction of AND-NOT. The output is high when both inputs are low
and any one of the input is low .The output is low level when both inputs are high.
NOR GATE

The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. The
output is low when one or both inputs are high.

PROCEDURE
(i) Connections are given as per circuit diagram.
(ii) Logical inputs are given as per circuit diagram.
(iii) Observe the output and verify the truth table.
AND GATE:

SYMBOL: PIN DIAGRAM:

OR GATE:
 NOT GATE :
SYMBOL: PIN DIAGRAM:

X-OR GATE :
SYMBOL : PIN DIAGRAM :
2- INPUT NAND GATE

SYMBOL PIN DIAGRAM

3- INPUT NAND GATE

NOR GATE
RESULT:

Thus the logic gates were studied and their truth tables have been verified.
 EX. NO: 8)b
DESIGN OF ADDER AND SUBTRACTOR
DATE:

AIM:
To design and construct half adder, full adder, half substractor and full substractor circuits and
verify the truth table using logic gates.

APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY

1. AND GATE IC 7408 1
2. X-OR GATE IC 7486 1
3. NOT GATE IC 7404 1
4. OR GATE IC 7432 1
5. BREADBOARD - 1

THEORY:

HALF ADDER:

A half adder has two inputs for the two bits to be added and two outputs one from the sum ‘ S’
and other from the carry ‘ C’ into the higher adder position. Above circuit is called as a carry signal
from the addition of the less significant bits sum from the X-OR Gate the carry out from the AND gate.

FULL ADDER:

A full adder is a combinational circuit that forms the arithmetic sum of input; it consists of three
inputs and two outputs. A full adder is useful to add three bits at a time but a half adder cannot do so. In
full adder sum output will be taken from X-OR Gate, carry output will be taken from OR Gate
 HALF SUBTRACTOR:

The half subtractor is constructed using X-OR and AND Gate. The half subtractor has two input and two outputs.
The outputs are difference and borrow. The difference can be applied using X-OR Gate, borrow output can be
implemented using an AND Gate and an inverter.

FULL SUBTRACTOR:

The full subtractor is a combination of X-OR, AND, OR, NOT Gates. In a full subtractor the
logic circuit should have three inputs and two outputs. The two half subtractor put together gives a full
subtractor .The first half subtractor will be C and A B. The output will be difference output of full
subtractor. The expression AB assembles the borrow output of the half subtractor and the second term
is the inverted difference output of first X-OR.

PROCEDURE:

(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.

(iii) Observe the output and verify the truth table.

LOGIC DIAGRAM

HALF ADDER

TRUTH TABLE

A B CARRY SUM

0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0

K-Map for SUM K-Map for CARRY

SUM = A’B + AB’ CARRY = AB

LOGIC DIAGRAM:

FULL ADDER
FULL ADDER USING TWO HALF ADDER

TRUTH TABLE:

A B C CARRY SUM

0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1

K-Map for SUM:

SUM = A’B’C + A’BC’ + ABC’ + ABC

 K-Map for CARRY:

CARRY = AB + BC + AC

LOGIC DIAGRAM:

HALF SUBTRACTOR

TRUTH TABLE:
A B BORROW DIFFERENCE

0 0 0 0
0 1 1 1
1 0 0 1
1 1 0 0
 K-Map for DIFFERENCE: K-Map for BORROW:

DIFFERENCE = A’B + AB’ BORROW = A’B

LOGIC DIAGRAM:
FULL SUBTRACTOR

FULL SUBTRACTOR USING TWO HALF SUBTRACTOR:

TRUTH TABLE:
A B C BORROW DIFFERENCE

0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 1 0
1 0 0 0 1
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

K-Map for Difference:

Difference = A’B’C + A’BC’ + AB’C’ + ABC

K-Map for Borrow:

Borrow = A’B + BC + A’C

RESULT: -

Thus the half adder, full adder, half subtractor and full subtractor circuits were designed
and their truth tables verified.
 EX. NO: 9
DESIGN AND IMPLEMENTATION OF MULTIPLEXER AND
DATE:
DEMULTIPLEXER

AIM:
To design and implement multiplexer and demultiplexer using logic gates and study of IC
74150 and IC 74154.

APPARATUS REQUIRED:
Sl.No. COMPONENT SPECIFICATION QTY.
1. 3 I/P AND GATE IC 7411 2
2. OR GATE IC 7432 1
3. NOT GATE IC 7404 1
2. IC TRAINER KIT - 1
3. PATCH CORDS - 32

THEORY:
MULTIPLEXER:
Multiplexer means transmitting a large number of information units over a smaller number of
channels or lines. A digital multiplexer is a combinational circuit that selects binary information from
one of many input lines and directs it to a single output line. The selection of a particular input line is
controlled by a set of selection lines. Normally there are 2 n input line and n selection lines whose bit
combination determine which input is selected.
The function of Demultiplexer is in contrast to multiplexer function. It takes information from
one line and distributes it to a given number of output lines. For this reason, the demultiplexer is also
known as a data distributor. Decoder can also be used as Demultiplexer.
In the 1: 4 demultiplexer circuit, the data input line goes to all of the AND gates. The data select
lines enable only one gate at a time and the data on the data input line will pass through the selected
gate to the associated data output line.

PROCEDURE:

(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.

(iii) Observe the output and verify the truth table.

PIN DIAGRAM FOR IC 74150:

CIRCUIT DIAGRAM FOR 4X1 MULTIPLEXER:

TRUTH TABLE:

S1 S0 Y = OUTPUT
0 0 D0
0 1 D1
1 0 D2
1 1 D3

BLOCK DIAGRAM FOR 4:1 MULTIPLEXER:

FUNCTION TABLE:

S1 S0 INPUTS Y
0 0 D0 → D0 S1’ S0’
0 1 D1 → D1 S1’ S0
1 0 D2 → D2 S1 S0’
1 1 D3 → D3 S1 S0

Y = D0 S1’ S0’ + D1 S1’ S0 + D2 S1 S0’ + D3 S1 S0

BLOCK DIAGRAM FOR 1:4 DEMULTIPLEXER:

FUNCTION TABLE:

S1 S0 INPUT

0 0 X → D0 = X S1’ S0’

0 1 X → D1 = X S1’ S0

1 0 X → D2 = X S1 S0’

1 1 X → D3 = X S1 S0

D0 = X S1’ S0’

D1 = X S1’ S0

D2 = X S1 S0’

D3 = X S1 S0
LOGIC DIAGRAM FOR DEMULTIPLEXER:
TRUTH TABLE:

INPUT OUTPUT

S1 S0 I/P D0 D1 D2 D3

0 0 0 0 0 0 0

0 0 1 1 0 0 0

0 1 0 0 0 0 0

0 1 1 0 1 0 0

1 0 0 0 0 0 0

1 0 1 0 0 1 0

1 1 0 0 0 0 0

1 1 1 0 0 0 1

PIN DIAGRAM FOR IC 74154:

RESULT: -

Thus the Multiplexer/Demultiplexer circuits were designed and their logic was verified
.
 EX. NO: 10
CONSTRUCTION AND VERIFICATION OF 4 BIT RIPPLE
DATE:
COUNTER AND MOD10/MOD 12 RIPPLE COUNTER

AIM:
To design and verify 4 bit ripple counter and Mod 10/ Mod 12 ripple counter.

APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY.

1. JK FLIP FLOP IC 7476 2
2. NAND GATE IC 7400 1
3. IC TRAINER KIT - 1
4. PATCH CORDS - 30

THEORY:

A counter is a register capable of counting number of clock pulse arriving at its clock input.
Counter represents the number of clock pulses arrived. A specified sequence of states appears as
counter output. This is the main difference between a register and a counter. There are two types of
counter, synchronous and asynchronous. In synchronous common clock is given to all flip flop and in
asynchronous first flip flop is clocked by external pulse and then each successive flip flop is clocked by
Q or Q output of previous stage. A soon the clock of second stage is triggered by output of first stage.
Because of inherent propagation delay time all flip flops are not activated at same time which results in
asynchronous operation.
PROCEDURE:

(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.

(iii) Observe the output and verify the truth table.

PIN DIAGRAM FOR IC 7476:

LOGIC DIAGRAM FOR 4 BIT RIPPLE COUNTER:

TRUTH TABLE:

CLK QD QC QB QA

0 0 0 0 0

1 1 0 0 0

2 0 1 0 0
 3 1 1 0 0

4 0 0 1 0

5 1 0 1 0

6 0 1 1 0

7 1 1 1 0

8 0 0 0 1

9 1 0 0 1

10 0 1 0 1

11 1 1 0 1

12 0 0 1 1

13 1 0 1 1

14 0 1 1 1

15 1 1 1 1

LOGIC DIAGRAM FOR MOD - 10 RIPPLE COUNTER:

TRUTH TABLE:

CLK QD QC QB QA

0 0 0 0 0

1 1 0 0 0

2 0 1 0 0

3 1 1 0 0

4 0 0 1 0

5 1 0 1 0

6 0 1 1 0

7 1 1 1 0

8 0 0 0 1

9 1 0 0 1

10 0 0 0 0
TRUTH TABLE:

CLK QD QC QB QA

0 0 0 0 0

1 1 0 0 0

2 0 1 0 0

3 1 1 0 0

4 0 0 1 0

5 1 0 1 0

6 0 1 1 0

7 1 1 1 0

8 0 0 0 1

9 1 0 0 1

10 0 1 0 1

11 1 1 0 1

12 0 0 0 0

RESULT: -

Thus the 4bit ripple counter and Mod counter circuits were designed and their logic was
verified.
70