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Physical IP Development on FinFET

Conference Paper · January 2014

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 Physical IP Development On FinFET
– There’s Nothing Planar About It!

Navraj Nandra
September 19th 2014

© Synopsys 2014 1
 Agenda

Introducing FinFET Devices

FinFETs On Physical IP
New Design Methodology
Summary

© Synopsys 2014 2 Confidential

 Acronyms
PPA = Power, Performance, Area
Physical IP Devices
 Logic libraries DIBL = Drain Induced Barrier Lowering
EM = Electromigration
 Embedded SRAMS
SCE = Short Channel Effects
 Interface IP RDR = Restricted Design Rules
– USB PHY DPT = Double Patterning Technology
– DDR PHY NBTI / PBTI = Negative (Positive) Bias
– PCI Express PHY Temperature Instability
– HDMI PHY HCI = Hot Carrier Injection
– MIPI PHY PODE = Poly Over Diffusion Edge
– SERDES PDK = Process Design Kit
RDF = Random Dopant Fluctuation

© Synopsys 2014 3
 Evolution of Transistor Scaling
1000

Leff
L=Node
100
Size, nm

10
L used to be in sync
with technology node
L quickly accelerated
then saturated
Will fall behind
1

© Synopsys 2014 4 Synopsys Confidential

 Scaling and Innovation

Innovation in materials and

architecture pushed by reaching
the limit of existing solutions

Cu Strain High-K FinFET Si NanoWire

180nm 90nm 45nm 22nm < 7nm

© Synopsys 2014 5 Synopsys Confidential
Scaling: From Moore ... To Koomey’s
Moore’s Law and Dennard Scaling
– Historic benefits from Moore’s Law and Dennard scaling: Cost,
Functionality, Performance and Power improve dramatically with each
technology generation
– Most of these benefits have diminished

Improvement per Moore/ Now

generation Dennard

Density 2x <2x
Performance 2x Flattening
Clock scaling 50% 4%
Power/transistor -50% -21%
Power density 0% 58%

The scaling benefits have diminished. Sources:

Dennard, historical ITRS, ITRS 2011

© Synopsys 2014 6 Synopsys Confidential

 Scaling: From Moore ... To Koomey
“Koomey’s Law”
• Energy efficiency doubles every year and half:
“…at a fixed computing load, the amount of battery you need will fall by a factor
of two every year and a half…”
• Efficiency scaling can be enabled by factors other than technology scaling

Energy efficiency scaling: Instructions per μJ. (Source: LaMarca (Intel), Intel Developer
Forum 2012). It reflects trends shown in publications by J Koomey (LBNL)

© Synopsys 2014 7 Synopsys Confidential

Planar Scaling…Diminishing Returns

Vg
• Increasing gate to channel coupling is key:
- Better control of SCE
Gate
- Lower DIBL
Vs
Vgs Cg Vgd
Vd - Higher ION/IOFF for fixed VDD, or lower
VDD to achieve target ION/IOFF
Source Drain
Vds

• Increasing sub-threshold leakage The Solution:

• Increasing gate leakage Thin Body +
• Decreasing mobility Double Gates
Multi Gates

© Synopsys 2014 8 Synopsys Confidential

 Effect of Tsi on Leakage

Source: Prof. Tsu-Jae King-Liu, FinFET History, Fundamental and Future, June 2012

© Synopsys 2014 9 Synopsys Confidential

 Fin Width Requirement

• To adequately
suppress DIBL,
Lg/Wfin

• Challenge for
lithography!

Source: Prof. Tsu-Jae King-Liu FinFET, History, Fundamental and Future, June 2012

© Synopsys 2014 10 Synopsys Confidential

How FinFETs Work
Field Effect Transistors: Gate(s) Control Of The Channel

“Multiple” gate controls channel

 Reduces SCE

© Synopsys 2014 11 Synopsys Confidential

FinFET Advantage: Intel’s Perspective
Reduced Leakage Current Lower Operating Voltage Faster Device

Source: Mark Bohr, Intel Developer Forum 2011

• Benefit of Intel’s FinFET with respect to Intel’s 32nm planar technology

– Tri-Gate transistors provide 37% delay improvement at low voltage
– Tri-Gate transistors operate at lower voltage, ~50% active power reduction

© Synopsys 2014 12 Synopsys Confidential

FinFET Design Considerations
Gate Length
• Fin Width
– Determines short channel effects
• Fin Height

Source
– Limited by etch technology
– Tradeoff: layout efficiency vs. design flexibility
• Fin Pitch
– Determines layout area
– Limits S/D implant tilt angle

Drain
– Tradeoff: performance vs. layout efficiency

Fin Height

Pfin Fin Width

© Synopsys 2014 13 Synopsys Confidential

 FinFET Advantages & Considerations
Improved Characteristics; Impacts Circuit Design

Gate Length

Source
Advantages
 Lower leakage
 Less variability

Drain
 Lower voltage

Fin Height

Pfin Fin Width

© Synopsys 2014 14 Synopsys Confidential

 FinFET Advantages & Considerations
Improved Characteristics; Impacts Circuit Design

Gate Length

Considerations

Source
 Quantized widths
 No body biasing
 Higher parasitics

Drain
 Aging

Fin Height

Pfin Fin Width

© Synopsys 2014 15 Synopsys Confidential

 FinFET Device Complexity

Silicide contact

Gate
Gate

Rdiff Rext/LDD

Gate
Oxide

Heavily-doped S/D Extension Channel

S/D regions Region Region

© Synopsys 2014 16 Synopsys Confidential

Detailed Capacitance Components
Caps Name Domain

Ccc Gate to top of fin diffusion Cf Extraction

TC TC Gate to diffusion inside Cc1, Spice

Ct channel Cc2 Model
Gate
Cf Source to drain diffusion Csd Spice
Cc1 Cc2
Model
Diff Fin Fin Diff
Csd Gate to substrate inside Cg Spice
channel Model
Cdiff Cfin Cg (in channel) Side View Gate to substrate Cg2 Extraction
between fins
Gate to diffusion between Cf2 Extraction
Cg2 fins
Dif Dif Fin to substrate Cfin Spice
f Gat
e
f Model
Cf2
Bulk diffusion to substrate Cdiff Spice
Model
Field Cfp Field poly to diffusion Cfp Extraction
Poly Top View

Gate to trench contact Ct Extraction

Contact to contact Ccc Extraction
© Synopsys 2014 17 Synopsys Confidential
 FinFET Modeling
With BSIM-CMG
XG

Rgeltd
Cge,ov
MG

Cgs,f Rii
Cgd,f
Cgs,ov IG
Cgd,ov
Igs Igd
Igcs Igb Igcd
XS Rs Rd XD
IS Ids ID

Ies Igidl+Iii Ied

Igisl

Cds,f XB

Similar model topology as planar BSIM4…. But more complex

© Synopsys 2014 18 Synopsys Confidential

 Agenda

Introducing FinFET Devices

FinFETs On Physical IP
New Design Methodology
Summary

© Synopsys 2014 19 Confidential

FinFET Impact On Physical IP
High level view…

Physical IP
• Logic libraries
• Embedded SRAMS DPT impacts M2/M3
 Routing
• Interface IP

FinFET impact below M1

 Circuit optimization

© Synopsys 2014 20 Synopsys Confidential

 Sub-Lithographic Fin Patterning
Sidewall Image Transfer (SIT) and Self-Aligned Double Patterning (SADP)

1. Deposit & pattern sacrificial layer 3. Etch back mask layer

to form “spacers”

SiGe SiGe
SOI SOI

BOX BOX

4. Remove sacrificial layer;

2. Deposit mask layer (SiO2 or Si3N4)
etch SOI layer to form fins

SiGe
SOI fins

BOX BOX

Note that fin pitch is 1/2 that of patterned layer

© Synopsys 2014 21 Synopsys Confidential

 Self-Aligned Spacer

• A spacer is a film layer formed on the sidewall of a pre-patterned feature

• Since there are two spacers for every line, the line density doubles

- First pattern
- Deposition of mask material
- Etching to from sidewall spacers
- Removal of first pattern
- Etching using remaining spacers as
mask
- Removal of spacer, leaving final
pattern

© Synopsys 2014 22 Synopsys Confidential

Spacer Lithography
Rinse and Repeat

Photo-lithographically
defined sacrificial
structures
1st Spacers 2nd Spacers 3rd Spacers

2n lines after n iterations of spacer lithography!

© Synopsys 2014 23 Synopsys Confidential

 Double Patterning Technology

• Double exposure: a sequence of two separate exposures of

the same photo-resist layer using two different photo-masks

Photoresist coating

First exposure

Second exposure
at different locations

Development of both
exposures in the photoresist

© Synopsys 2014 24 Synopsys Confidential

 Advantage of Spacer Lithography
Spacer lithography
uniform Wfin

Conventional litho.
nonuniform Wfin

SEM image of
FinFET with
acer-defined fins

Source: Prof. Tsu-Jae King-Liu FinFET, History, Fundamental and Future, June 2012
© Synopsys 2014 25 Synopsys Confidential
FinFET Logic Libraries  Highlights

• Faster than planar; lower leakage & dynamic power

– Lower leakage enables lower VTH @ fixed leakage
– Lower VTH enables lower VDD
– Lower VDD leads to lower dynamic power: Pd= fCV2

• Higher drive for same silicon area

– Effective transistor width of 9T FinFET cell is close to
12T planar cell

© Synopsys 2014 26 Synopsys Confidential

 CPU Area-Speed Trade-Off
In Logic Libraries

28-nm 12T

16FF 9T

• 9T performance far exceeds 28HPM 12T

• Tall cells don’t help much; short libraries for density & lower power
• Complexities of DPT and routing in general

© Synopsys 2014 27 Synopsys Confidential

 Logic Library Heights vs Transistor Widths
High Speed Cell Heights
~0.7 ~0.7 1.0

Same BEOL

40-nm 28-nm 20-nm 14/16-nm

© Synopsys 2014 28 Synopsys Confidential

 FinFET Stress Proximity Effects

Nested FinFET Isolated FinFET

S S
G
SiGe

G D

SiGe
D

STI
-1289 MPa +53 MPa

Isolated pFinFETs relax the stress

Nested pFinFETs have strong stress (Driving current drops in half!)

© Synopsys 2014 29 Synopsys Confidential

 FinFET Challenges
In Logic Libraries

• ‘Quantized width’ and

‘quantized length’ challenges
• Lonely FinFETs
Lonely FinFET
 Degrade performance 
Increase variability
• Potential self-heating S
G
• Model complexity D

• Further challenges: 
STI
Layout compaction 
Routability
Lonely FinFET is not stressed
Note: Isolate FinFET challenges from Device drive current drops
double patterning challenges
© Synopsys 2014 30 Synopsys Confidential
 New Design Styles
In Logic Libraries

• Cell height / width multiple of Fin /gate pitch

• Power rail width and layout dictated by special rules
• DPT rules prevent use of M1 at the chip level
• PODE addresses lonely FinFET effect

Fin
Pitch

Gate Pitch

© Synopsys 2014 31 Synopsys Confidential

 FinFET SRAMs  Highlights

• Higher performance, lower leakage

• Good static noise margin at low Vdd
• Operates at lower Vdd

Precharge & equilazer

Pass gate

Pull ups

Guard ring strap

© Synopsys 2014 32 Synopsys Confidential

 FinFET SRAMS  Challenges

Body Effect Quantization

Static noise margin or bigger bitcell

Write margin issues

Source: Jong-Ho Lee Seoul National University Thesis

© Synopsys 2014 33 Synopsys Confidential

 Solutions: Read/Write Assist Schemes
In Embedded SRAMS

At least four techniques published in 2014:

TSMC, Samsung, Renesas and Synopsys

• Reliability Aware Negative Bitline Solution

• Programmable Assist Solution is key

Prashant Dubey et. al., “A 500mV to 1.0V 128Kb SRAM in Sub 20nm Bulk-FinFET
using auto-adjustable write assist”, 27th IEEE International VLSI Design Conf. 2014

© Synopsys 2014 34 Synopsys Confidential

Impact of NBTI on Threshold & Delay

Source: NBTI Modeling in the framework of temp. variation, Hamdioui, DATE 2010

© Synopsys 2014 35 Synopsys Confidential

 SRAM: Better Soft Error Rate

Source: Yi-Pin Fang and Anthony S. Oates

IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 11, NO. 4, DECEMBER 2011

© Synopsys 2014 36 Synopsys Confidential

Detect Defects In FinFET Transistors
In Embedded SRAMS

Resistive shorts between Fins Step 1. Defect injection & fault modeling
Step 2. Test sequence & optimal PVT
Step 3. Test algorithm synthesis
Step 4. FinFET Enhanced SMS 5*

Resistive opens on Fins

New addressing mechanisms
Fully programmable background patterns
Programmable test operations
Stress conditions

*Synopsys Star Memory System

© Synopsys 2014 37 Synopsys Confidential

 Impact On Circuit Schematics
Interface IP
• Key parameters: gm, gd, Ft, Fmax,
matching, noise
• PMOS/NMOS drive strength
• Device matching better
• W/L mapped to L and # fins
• New designs needed for high
speed blocks
• Aging simulation is important

gm/gds of bulk and FinFET

© Synopsys 2014 38 Synopsys Confidential

 Impact On Layout
Interface IP

• Smaller devices get hot

• New tools for EM and IR
• High speed divider causes self heating
• DRC complex
• Metal stack has impact
• Need full RCC simulations

© Synopsys 2014 39 Synopsys Confidential

 Impact On Development Style
Interface IP

vdd33 vdd33

• Lower power supply 1.8 V Pullup

Predriver P1

• High voltage tolerance

• Power-aware .lib files 5V

• Power gating
protection P2
circuit R=45Ω

• .lib files to support EM

• In-house ESD is a must R=45Ω
vdd25 N2

1.8 V Pulldown
Predriver N1

© Synopsys 2014 40 Synopsys Confidential

 Key Points – FinFETs on Physical IP
Logic Libraries
• Short (7.5T) libraries will be key to achieving highest density, lowest power
• PODE addresses lonely FinFET effect
Embedded SRAMS
• New assist circuitry helps with low Vdd, body bias and 𝜷 quantization
• Synopsys developed flow to detect defects in FinFET cells
Interface IP
• Create optimized FinFET schematics by including process info. (inc. NBTI)
• Start layout earlier in the design process; new modeling in .lib files
• In order to meet PPA, new architectures to be developed

© Synopsys 2014 41 Synopsys Confidential

 Agenda

Introducing FinFET Devices

FinFETs On Physical IP
New Design Methodology
Summary

© Synopsys 2014 42 Confidential

 The Need  The Solution

DDR4, LPDDR4  Higher I/O speeds using single-ended interface

USB 3.0  Must support all 4 speeds
IP Specs

 Meet electrical compliance

PCI Express  8 Gb/s but support new low power modes

Physical IP  Scales (area, power) without performance degradation

Aggressive schedules  Supports design on an early PDK
Market

SOC  Works on first instantiation in SoC

The Solution: Advanced Silicon Design Methodology

© Synopsys 2014 43 Synopsys Confidential

1. Process Qualification Vehicle
Monitor / evaluate speed, leakage, parasitic R, C, random & systematic
variability & lithography induced variability effects

• Timing Structures
– Inverter, NAND and NOR Oscillators
– Multiple capacitive & metal loads, multiple Vts
Device
HSRF1P
– Preferred height, #fingers, P/N ratios, #fins HDRF2SP Aging

• Power Structures (Vt/Channel) HDSP Ringo

 Chains of Inverter for dynamic & static power
• Layout effects: Logic
Macro
 Lonely FinFET, WPE, Endcap, Body Effect,
NBTI/End of Life
PLL

© Synopsys 2014 44 Synopsys Confidential

2. CAD Flow
Example 1: Density Viewer

Actual Max
density =
54.2%

© Synopsys 2014 45 Synopsys Confidential

2. CAD Flow
Example 2: EM Back Annotation

Current Back-
Annotated on
Schematic

EM occurs deep in the hierarchy, need bottom-up analysis

© Synopsys 2014 46 Synopsys Confidential

3. Simulation To Silicon Correlation
DDR - pre-bit deskew delay line (BDL)

• DDR PHY formats timing to/from SDRAM

• Delay line accuracy within 15 ps
• BDL Also acts as a process monitor

© Synopsys 2014 47 Synopsys Confidential

 4. Silicon Success: DDR PHY FINFET
SS / Min V / 125C TT / Nom V / 25C FF / Max V / -40C

© Synopsys 2014 48 Synopsys Confidential

 4. Silicon Success: USB 2.0 PHY; 6 Gb/s SERDES
USB passed logo certification; FinFET designed for power, area

Key USB USB USB

Test Results 2.0 3.0
Eye Diagrams Pass Pass

ATE Tests Pass Pass

Functional Pass Pass

USB PHY 28-nm FinFET % savings

2.0 Macro Area 0.38 mm2 0.19 mm2 50%

2.0 HS Power 56 mW 46 mW 18%

3.0 Macro Area 0.77 mm2 0.43 mm2 44%

3.0 SS Power 84 mW 66 mW 21%

Note: Specific area and power figures are process dependent

© Synopsys 2014 49 Synopsys Confidential

 Key Points – Design Methodology

In order to meet:
• Time-to-market requirements
• Early (changing) PDK
• Next protocol generation, improvement in PPA
• Silicon success on first instantiation in SoC

 Investment in an advanced design methodology

is paramount

© Synopsys 2014 50 Synopsys Confidential

 Agenda

Introducing FinFET Devices

FinFETs On Physical IP
Design Methodology
Summary

© Synopsys 2014 51 Confidential

 Summary
There’s nothing planar about FinFET’s

• FinFET advantages to Physical IP

 Improved electrical and technology parameters yielding
significant performance advantages
• New design approaches can handle limitations:
– Assist circuits, high voltage tolerance
– Redesign (when necessary) to meet PPA
• Advanced design methodology ensures silicon
success on first instantiation
• Synopsys provides silicon proven FinFET Physical
IP

© Synopsys 2014 52 Synopsys Confidential

So, When it Comes to FinFET…
• It is “almost” business as usual for SoC designers
• However, the complexity lies within IP development
• The basic flow has not changed, but the models and
layout details used to build the IP are more complex
• Having confidence in the IP is critical
• And…experience counts

© Synopsys 2014 53 Synopsys Confidential

 Thank You

© Synopsys 2014 54
© Synopsys 2014 55
© Synopsys 2014 56
© Synopsys 2014 57
 Thank You

© Synopsys 2014 58
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