Study on performance Evaluation of CMOS Inverter

using Surrounded channel Junctionless Field Effect

Transistor
Namita Das
Central Institute of Technology Kokrajhar Deemed to be University
Kaushik Chandra Deva Sarma (  kcd.sarma@cit.ac.in )
Central Institute of Technology Kokrajhar Deemed to be University

Research Article

Keywords: Junction less, eld effect, Surrounded channel, CMOS Inverter, rise time, fall time, propagation
delay and Noise margin

Posted Date: March 31st, 2023

DOI: https://doi.org/10.21203/rs.3.rs-2501177/v1

License:   This work is licensed under a Creative Commons Attribution 4.0 International License.
Read Full License
 Studyon performance Evaluation of CMOS
Inverter using Surrounded channel Junctionless
Field Effect Transistor
Namita Das, Kaushik Chandra Deva Sarma

Department of Instrumentation Engineering

Central Institute of Technology Kokrajhar, Assam, India

Abstract: The paper present here analyses the modeling and performance of CMOS inverters using
surrounded channel Junction less field effect transistor (SCJLFET). A mathematical model for different
parameters like low input voltage and high input voltage, low output voltage and high output voltage,
power dissipation, noise margin, rise time, fall time, propagation delay of the CMOS inverter circuit
has been established. To design the model for various parameters, potential models at the channel
source boundary and the potential at the channel drain boundary are considered. The variations in the
voltage transfer characteristics, output current and the power dissipation with respect to the input
voltage for steady-state conditions and transient states were evaluated for different gate dielectrics, gap
lengths and gate oxide thicknesses. The models were compared with technology computer aided design
(TCAD) simulation results for validation. The noise margin, rise time, fall time and propagation delay
of the SCJLFET based Complementary metal oxide semiconductor (CMOS) inverter is evaluated and
compared with those of a conventional junction less transistor. It has been observed that the SCJLFET
exhibits an improvement in the noise margin and propagation delay compared with conventional
junction less transistors.

Keywords: Junction less, field effect, Surrounded channel, CMOS Inverter, rise time, fall time,
propagation delay and Noise margin.

I.INTRODUCTION

As the VLSI design is advancing towards the end of Moore's law with MOS based devices reaching its
scaling limit, concept of Junction less Transistor (JLT) has been introduced to move further into the
nanoscale regime. VLSI devices are reaching towards scaling limit due to on-going downscaling. The
limitations observed in bulk MOSFET at very small dimension led to the invention of several new
devices such as the SOI devices, strained Si devices, and device with high-k dielectric etc. With the
invention of new device structures it is possible to scale down the devices further into the nanometer
regime. However, the presence of the junction in these devices imposes few other limitations in scaling
down beyond a certain point in nanoscale regime. This is due to a space charge region which is always
present in a junction. Necessity to overcome the limitations of junction, gave new dimension to the
MOSFET technology, which results in the formulation of Junctionless FET or simply Junctionless
Transistor or JLT [1-2]. Scaling down semiconductor devices aids CMOS technology to obtain better
dynamic read only memory chip density and more momentum in circuit applications. However scaling
down conventional MOSFET faces various problems in the channel region because the channel is
controlled not only by the gate but also by the source and drain regions. The development barrier to the
short channel effect (SCE), which degrades the performance of conventional MOS transistors. To
enhance the performance parameters multi gate transistor devices have better control over the channel.
With different multi gate MOSFET technologies it has become easier to scale down devices to the nano
regime. However presence of junctions in all these advanced technology devices limits the short
channel effect and also challenges doping profile. The demerits of all the devices can be further
minimized by using a device called junction less transistor (JLT). Such device does not have any p-n
junctions. Throughout the source-channel-drain path JLT has a uniform doping profile [1-17]. JLT is
performed under switching operation by the work function difference between the gate and the silicon
substrate of the device. JLT reduced the SCE. Complexity of the fabrication is also reduced used in JLT
and also it suffers from mobility degradation which results in a lower drain current. To enhance the
mobility in the device we have proposed a new structure and that is a surrounded channel junction less
field effect transistor (SCJLFET) [18]. As we all know that transistors are used in various digital
circuits.

In this paper it is reported about the study on performance Evaluation of different parameters of
CMOS Inverter by using Surrounded channel Junction less Field Effect Transistor. In this paper
mathematical models for various performance evaluations of parameters of the device were developed.
Validation of the mathematical models were done by comparison with a TCAD simulation results.

II.MODEL DERIVATION

Figure 1. (a)
Figure 1. (b)

FIGURE 1. CMOS inverter using SCJLFET (a) P Channel and N Channel SCJLFET (b) Its
circuit symbol. Vin and Voutare input and output voltage respectively. Vddand GND are supply
voltage and ground respectively. toxis oxide thickness and tsiis substrate thickness. Lsis source
length, LDis drain length.

Figure1. shows a CMOS inverter using surrounded channel junction less field effect transistor
(SCJLFET). The resistances of different regions of the body of the device are as follows:

For the depletion region where the variation of the resistances are
𝑊𝑑1

𝑅𝑑1 = 2
𝑞𝜇𝑝 𝑤(𝑡𝑔+ 2𝑡𝑜𝑥 )

𝐿
𝑅𝑑2 = 𝑊𝑑2
𝑞𝜇𝑝 𝑤
2

𝑊𝑑3
2
𝑅𝑑3 =
𝑞𝜇𝑝 𝑤(𝑡𝑔 + 2𝑡𝑜𝑥 )

Where,

𝑊𝑑 is the depletion width given as [19],

4tsi si tox qN a + ox t si2 qN a − 8 ox si (gs − 0 )

Wd = tsi − for P-channel device
ox qN a

4t si si tox qN d + ox t si2 qN d + 8 ox si (gs − 0 )

Wd = tsi − for N-channel device
ox qN d

𝑊 is the width of the device

𝑞 is the charge of one electron

µ is the mobility
 𝑅2
𝑅𝑒𝑞 = 𝑅1 + 2
+ 𝑅3 is the carrier density of the depleted regions

Let us consider the non depleted regions where the variation of the resistances given by

𝐿𝑠
𝑅𝑛𝑑1 = 𝑡𝑠𝑖
𝑞𝜇𝑛 𝑤
2

𝐿
𝑅𝑛𝑑2 = 𝑡𝑠𝑖
𝑞𝜇𝑛 𝑤( − 𝑊𝑑2 )
2

𝐿𝐷
𝑅𝑛𝑑3 = 𝑡𝑠𝑖
𝑞𝜇𝑛 𝑤 2

(𝐿𝑠− 𝑊𝑑1 )
𝑅𝑛𝑑4 =
𝑞𝜇𝑛 𝑤(𝑡𝑔 + 2𝑡𝑜𝑥 )

(𝐿𝐷− 𝑊𝑑3 )
𝑅𝑛𝑑5 =
𝑞𝜇𝑛 𝑤(𝑡𝑔 + 2𝑡𝑜𝑥 )

(𝐿𝑠− 𝑊𝑎𝑐𝑐1 )
𝑅𝑛𝑑6 =
𝑞𝜇𝑛 𝑤(𝑡𝑔 + 2𝑡𝑜𝑥 )

(𝐿𝐷− 𝑊𝑎𝑐𝑐1 )
𝑅𝑛𝑑7 =
𝑞𝜇𝑛 𝑤(𝑡𝑔 + 2𝑡𝑜𝑥 )

And,

𝑅2
𝑅𝑒𝑞 = 𝑅1 + + 𝑅3
2

Where,

𝐿𝐷 is the drain length

𝐿𝑠 is the source length
𝑡𝑠𝑖 is the thickness of the silicon layer
𝑡𝑜𝑥 is the thickness of the oxide layer
𝑡𝑔 is the thickness of the gate region

Substrate is heavily doped; the approximate carrier density of the non depleted region of the n channel
JLT is given by [17]

𝑁𝑑 𝑁𝑑 2
𝑛𝑛 = + √ + 𝑛𝑖 2
2 4
The carrier density of the depleted region of the n channel JLT is given by

𝑛𝑖 2
𝑝𝑛 =
𝑁𝑑 𝑁𝑑 2
+√ + 𝑛𝑖 2
2 4

The carrier density of the non depleted region of the p channel JLT is given by

𝑁𝑎 𝑁𝑎 2
𝑝𝑝 = + √ + 𝑛𝑖 2
2 4

The carrier density of the depleted region of the p channel JLT is given by

𝑛𝑖 2
𝑛𝑝 =
𝑁𝑎 𝑁𝑎 2
+√ + 𝑛𝑖 2
2 4

Where 𝑛𝑖 denotes the intrinsic carrier concentration.

Therefore the channel potential is given by [20-22]

𝐿
−(𝐿𝐷 + 𝐺 )
𝑐𝜆2 2
)
(𝑐𝜆2 + 𝑉𝐷𝑆 − 𝐿 𝑒 𝜆
−(𝐿𝑠 − 𝐺 )
2
𝑥
𝑒 𝜆
∅𝑜 (𝑥) = 𝐿𝐺) 𝐿 𝐿 𝑒𝜆
(𝐿𝐷 + −2(𝐿𝑠 − 𝐺 ) −(𝐿𝐷 + 𝐺 )
2 2 2
𝑒 𝜆 −𝑒 𝜆 𝑒 𝜆

[ ]
𝐿
−(𝐿𝐷 + 𝐺 )
𝑐𝜆2 2
)
(𝑐𝜆2 + 𝑉𝐷𝑆 − 𝐿 𝑒 𝜆
−(𝐿𝑠 − 𝐺 ) 𝐿
−(𝐿𝑠 − 𝐺 )
𝑒 𝜆
2
2 𝑐𝜆2 −𝑥
− 𝐿𝐺) 𝐿 𝐿 {𝑒 𝜆 − 𝐿 } 𝑒 𝜆 − 𝑐𝜆2
(𝐿𝐷 + −2(𝐿𝑠 − 𝐺 ) −(𝐿𝐷 + 𝐺 ) −(𝐿𝑠 − 𝐺 )
2 2 2 2
𝑒 𝜆 −𝑒 𝜆 𝑒 𝜆 𝑒 𝜆

[{ } ]
𝑥 −𝑥
𝜑𝑜 (𝑥) = 𝐴𝑒 𝜆 − 𝐵𝑒 𝜆 − 𝐶𝜆2
 𝐿
−𝐿𝐷 − 𝐺 −𝐿
𝑐𝜆2 2 )
(𝑐𝜆2 + 𝑉𝐷𝑆 − 𝐿 𝑒 𝜆
−(𝐿𝑠 − 𝐺 )
2
𝑥
𝑒 𝜆
𝜑𝑂 (𝐿) = 𝐿𝐺) 𝐿 𝐿 𝑒𝜆
(𝐿𝐷 + −2(𝐿𝑠 − 𝐺 ) −(𝐿𝐷 + 𝐺 )
2 2 2
𝑒 𝜆 −𝑒 𝜆 𝑒 𝜆

[ ]
𝐿
−𝐿𝐷 − 𝐺 −𝐿
𝑐𝜆2 2 )
(𝑐𝜆2 + 𝑉𝐷𝑆 − 𝐿 𝑒 𝜆
−(𝐿𝑠 − 𝐺 )
𝑒 𝜆
2 −2𝐿𝑠 +𝐿𝐺 −𝐿 𝐶𝜆2 −𝑥
− 𝐿𝐺) 𝐿 𝐿 {𝑒 𝜆 − 𝐿 } 𝑒 𝜆 − 𝐶𝜆2
(𝐿𝐷 + −2(𝐿𝑠 − 𝐺 ) −(𝐿𝐷 + 𝐺 ) −(𝐿𝑠 − 𝐺 )
2 2 2 2
)
(𝑒 𝜆 −𝑒 𝜆 𝑒 𝜆 𝑒 𝜆

[{ } ]
𝐿 −𝐿
′𝑒 𝜆 ′𝑒 𝜆
𝜑𝑂 (𝐿) = 𝐴 −𝐵 − 𝐶′𝜆2

For p-channel JLT

𝑥 −𝑥
𝜑𝑜 (𝑥) = 𝐴𝑒 𝜆 − 𝐵𝑒 𝜆 − 𝐶𝜆2
𝐿 −𝐿
′𝑒 𝜆 ′𝑒 𝜆
𝜑𝑂 (𝐿) = 𝐴 −𝐵 − 𝐶′𝜆2

&

𝜑0 (0) = 𝐴 − 𝐵 − 𝐶𝑝 𝜆2

Where,

𝐴 − 𝐵 − 𝜑0 (0)
𝐶𝑃 =
𝜆2

&

𝐿 𝐿
−𝐿𝐷 − 𝐺 −𝐿 −𝐿𝐷 − 𝐺 −𝐿
𝐶𝜆2 2 𝐶𝜆2 2
𝐶𝜆2 +𝑉𝐷𝑆 − 𝐿𝐺 𝑒
𝜆 𝐶𝜆2 +𝑉𝐷𝑆 − 𝐿𝐺 𝑒
𝜆
−(𝐿𝑠 − ) −(𝐿𝑠 − )
2 𝑥 2
( 𝑒 𝜆 ) ( 𝑒 𝜆 )
𝜑0 (𝐿) − 𝐿𝐺 𝐿𝐺 𝐿𝐺 𝑒 𝜆 + [{ 𝐿𝐺 𝐿𝐺 𝐿𝐺 }
𝐿𝐷 + −2(𝐿 −
𝑠 2 ) −(𝐿 +
𝐷 2 ) 𝐿𝐷 + −2(𝐿 −
𝑠 2 ) −(𝐿 +
𝐷 2 )
2 − ) 2 − )
(𝑒 𝜆 𝑒 𝜆 𝑒 𝜆 (𝑒 𝜆 𝑒 𝜆 𝑒 𝜆

[ ]
−2𝐿𝑠 +𝐿𝐺 −𝐿 𝐶𝜆2
− 𝐿
𝜆
−(𝐿𝑠 − 𝐺 ) −𝑥
2
{𝑒 𝑒 𝜆 }𝑒 𝜆 ]
𝐶𝑃 ′ =
𝜆2

Voltage Transfer characteristics of the CMOS inverter is shown below in figure 2.

Figure 2. Voltage Transfer characteristics of inverter

Input Low:
To find input low the p-channel JLT is considered to be non-saturated & n-channel JLT is considered to
be saturated.
Idpnonsat = Idnsat
At saturation,
𝜑𝑔𝑠𝑛 = 𝑉𝑔𝑠𝑛 − 𝑉𝑓𝑏𝑛 = 0

Or

Idnsat = Idpoff

Therefore,

𝜑0 (𝐿) − 𝜑0 (0)
𝐼𝑑𝑝 =
𝑅𝑝𝑒𝑞

𝜑0 (𝐿)−𝜑0 (0)
&𝐼𝑑𝑛𝑠𝑎𝑡 =
𝑅𝑛𝑒𝑞

Therefore,

𝜑0 (𝐿) − 𝜑0 (0) 𝜑0 (𝐿) − 𝜑0 (0)

=
𝑅𝑛𝑒𝑞 𝑅𝑝𝑒𝑞

𝑅2
𝑅𝑝𝑒𝑞 = 𝑅𝑑𝑝𝑒𝑞 = 𝑅1 + + 𝑅3 (1)
2

In the case of sub-threshold mode we obtained,

𝑅𝑛𝑑1
𝑅1 = ||𝑅𝑑1
2
𝑅2 = 𝑅𝑑2

𝑅𝑛𝑑3
𝑅3 = ||𝑅𝑛𝑑3
2

Or,

𝑅𝑛𝑑1 𝑅𝑑1
𝑅1 =
2𝑅𝑑1 + 𝑅𝑛𝑑1

𝑅2 = 𝑅𝑑2

𝑅 𝑅
&𝑅3 = 2𝑅 𝑛𝑑3+𝑅𝑑3
𝑑3 𝑛𝑑3

Therefore, by putting the values of𝑅𝑛𝑑1 ,𝑅𝑑1 , 𝑅𝑑2 , 𝑅𝑛𝑑3 and 𝑅𝑑3 in the above relations we get,
𝑊𝑑1
𝐿𝑠
{ 2 }
2 2 𝑡𝑠𝑖
𝑞 𝜇 𝑛 𝜇𝑝 𝑊 (𝑡 +2𝑡𝑜𝑥 )
2 𝑔
𝑅1 = 𝑊𝑑1 (2)
2 𝐿𝑠
{2[ ]+ 𝑡 }
𝑞𝜇𝑝𝑊 (𝑡𝑔 +2𝑡𝑜𝑥 ) 𝑞𝜇𝑛 𝑊 𝑠𝑖
2

𝐿
𝑅2 = 𝑊 (3)
𝑞𝜇𝑝 𝑊 𝑑2
2

&
𝑊𝑑3 𝐿𝐷
{ 2 }
𝑡
𝑞2 𝜇𝑛 𝜇𝑝 𝑊2 𝑠𝑖 (𝑡𝑔 +2𝑡𝑜𝑥 )
𝑅3 = 𝑊𝑑3
2
(4)
2 𝐿𝐷
{2[ ]+ 𝑡 }
𝑞𝜇
𝑝𝑊(𝑡𝑔 +2𝑡𝑜𝑥 ) 𝑞𝜇𝑛 𝑊 𝑠𝑖
2

Therefore putting the values of equation (2), (3) & (4) in equation (1) we get,
𝑊𝑑1 𝑊𝑑3 𝐿𝐷
𝐿𝑠
{ 2
𝑡𝑠𝑖 } { 2
𝑡 }
2
𝑞 𝜇𝑛 𝜇𝑝 𝑊 2
2 𝑔
(𝑡 +2𝑡𝑜𝑥 ) 𝐿 𝑞 2 𝜇𝑛 𝜇𝑝 𝑊 2 𝑠𝑖 (𝑡𝑔 +2𝑡𝑜𝑥 )
2
𝑅𝑝𝑒𝑞 = 𝑅𝑑𝑝𝑒𝑞 = 𝑊𝑑1 + 𝑊𝑑2 + 𝑊𝑑3
𝐿𝑠 𝑞𝜇𝑝 𝑊 𝐿𝐷
{2 [ 2
]+ 𝑡 } 2 {2 [ 2
]+ 𝑡 }
𝑞𝜇𝑝𝑊 (𝑡𝑔 +2𝑡𝑜𝑥 ) 𝑞𝜇𝑛 𝑊 𝑠𝑖 𝑞𝜇𝑝𝑊(𝑡 +2𝑡 ) 𝑞𝜇𝑛 𝑊 𝑠𝑖
2 𝑔 𝑜𝑥 2

Also,
𝑅2
𝑅𝑛𝑒𝑞 = 𝑅𝑛𝑑𝑛𝑒𝑞 = 𝑅1 + + 𝑅3 (5)
2

By considering bulk current mode we have,

 𝑅𝑛𝑑1
𝑅1 = || (𝑅𝑑1 + 𝑅𝑛𝑑4 )
2

𝑅2 = 𝑅𝑛𝑑2 ||𝑅𝑑2

𝑅𝑛𝑑3
𝑅3 = ||(𝑅𝑑3 + 𝑅𝑛𝑑5 )
2

Therefore the values of each above mention resistances are given by

𝐿𝑠
𝑅𝑛𝑑1 = 𝑡𝑠𝑖
𝑞𝜇𝑛 𝑊
2

𝑊𝑑1
2
𝑅𝑑1 =
𝑞𝜇𝑝 𝑊(𝑡𝑔 + 2𝑡𝑜𝑥 )

𝐿
𝑅𝑛𝑑2 = 𝑡𝑠𝑖
𝑞𝜇𝑛 𝑊( − 𝑊𝑑2 )
2

𝐿
𝑅𝑑2 = 𝑊𝑑2
𝑞𝜇𝑝 𝑊
2

𝐿𝐷
𝑅𝑛𝑑3 = 𝑡𝑠𝑖
𝑞𝜇𝑛 𝑊
2

𝑊𝑑3
2
𝑅𝑑3 =
𝑞𝜇𝑝 𝑊(𝑡𝑔 + 2𝑡𝑜𝑥 )

(𝐿𝑠 − 𝑊𝑑1 )
𝑅𝑛𝑑4 =
𝑞𝜇𝑛 𝑊(𝑡𝑔 + 2𝑡𝑜𝑥 )

(𝐿𝐷 − 𝑊𝑑3 )
𝑅𝑛𝑑5 =
𝑞𝜇𝑛 𝑊(𝑡𝑔 + 2𝑡𝑜𝑥 )

Therefore,

𝐿𝑠 𝑊𝑑1 𝑞𝜇𝑛 𝑊(𝑡𝑔 +2𝑡𝑜𝑥 )+2(𝐿𝑠 −𝑊𝑑1 )(𝑞𝜇𝑝 𝑊{𝑡𝑔 +2𝑡𝑜𝑥 })

𝑅1 = + (6)
2𝑞𝜇𝑛 𝑊𝑡𝑠𝑖 2𝑞 2 𝜇𝑛 𝜇𝑝 𝑊 2 (𝑡𝑔 +2𝑡𝑜𝑥 )2

𝐿
𝑅2 = 𝑡 𝑊 (7)
𝑞𝜇𝑛 𝑊( 𝑠𝑖 −𝑊𝑑2 )+𝑞𝜇𝑝 𝑊 𝑑2
2 2
 𝑊
𝐿𝐷 𝑑3 {𝑞𝜇𝑛 𝑊(𝑡𝑔 +2𝑡𝑜𝑥 )+(𝐿𝐷 −𝑊𝑑3 )(𝑞𝜇𝑝 𝑊(𝑡𝑔 +2𝑡𝑜𝑥 )}
𝑅3 = 𝑡 𝑊
2
(8)
2𝑞𝜇𝑛 𝑊 𝑠𝑖 𝑑3 {𝑞𝜇𝑛 𝑊(𝑡𝑔 +2𝑡𝑜𝑥 )+(𝐿𝐷 −𝑊𝑑3 )𝑞𝜇𝑝 𝑊(𝑡𝑔 +2𝑡𝑜𝑥 )}+𝐿𝐷 𝑞 2 𝜇𝑛 𝜇𝑝 𝑊 2 (𝑡𝑔 +2𝑡𝑜𝑥 )2
2 2

Therefore, putting the values of equations (6), (7) & (8) in equation (5) we get,

𝑅𝑛𝑒𝑞 = 𝑅𝑛𝑑𝑛𝑒𝑞
𝐿𝑠 𝑊𝑑1 𝑞𝜇𝑛 𝑊(𝑡𝑔 + 2𝑡𝑜𝑥 ) + 2(𝐿𝑠 − 𝑊𝑑1 )(𝑞𝜇𝑝 𝑊{𝑡𝑔 + 2𝑡𝑜𝑥 })
=[ + 2 ]
2𝑞𝜇𝑛 𝑊𝑡𝑠𝑖 2𝑞 2 𝜇 𝜇 𝑊 2 (𝑡 + 2𝑡 ) 𝑛 𝑝 𝑔 𝑜𝑥

𝐿
+[ 𝑡𝑠𝑖 𝑊𝑑2
]
𝑞𝜇𝑛 𝑊 ( − 𝑊𝑑2 ) + 𝑞𝜇𝑝 𝑊
2 2
𝑊𝑑3
𝐿𝐷 {𝑞𝜇𝑛 𝑊(𝑡𝑔 + 2𝑡𝑜𝑥 ) + (𝐿𝐷 − 𝑊𝑑3 )(𝑞𝜇𝑝 𝑊(𝑡𝑔 + 2𝑡𝑜𝑥 )}
2
+[ 𝑡𝑠𝑖 𝑊𝑑3 2]
2𝑞𝜇𝑛 𝑊
2 2
{𝑞𝜇𝑛 𝑊(𝑡𝑔 + 2𝑡𝑜𝑥 ) + (𝐿𝐷 − 𝑊𝑑3 )𝑞𝜇𝑝 𝑊(𝑡𝑔 + 2𝑡𝑜𝑥 )} + 𝐿𝐷 𝑞 2 𝜇𝑛 𝜇𝑝 𝑊 2 (𝑡𝑔 + 2𝑡𝑜𝑥 )

[(𝐴′ − 𝐴)𝑉𝑑𝑠𝑝 − (𝐵 ′ − 𝐵)𝜑𝑔𝑠𝑝 − (𝐶𝑝′ − 𝐶𝑝 )] 𝑛𝑝 = [(𝐴′ − 𝐴)𝑉𝑑𝑠𝑛 − (𝐶𝑛′ − 𝐶𝑛 )]𝑛𝑛 [(𝐴′ − 𝐴)(𝑉𝑑𝑑 −
𝑉𝑜𝑢𝑡 ) − (𝐵 ′ − 𝐵)(𝑉𝑑𝑑 − 𝑉𝑖𝑛 − 𝑉𝑓𝑏𝑝 ) − (𝐶𝑝′ − 𝐶𝑝 )] 𝑛𝑝 = [(𝐴′ − 𝐴)(𝑉𝑜𝑢𝑡 ) − (𝐶𝑛′ − 𝐶𝑛 )𝑛𝑛 (9)

𝐼𝑑𝑛 (𝑉𝑜𝑢𝑡 ) = 𝐼𝑑𝑝 (𝑉𝑖𝑛, 𝑉𝑜𝑢𝑡 )

𝜕𝐼𝑑𝑝
𝑑𝑉𝑜𝑢𝑡 𝜕𝑉𝑖𝑛
= 𝜕𝐼
= −1
𝑑𝑉𝑖𝑛 𝑑𝐼𝑑𝑛
− 𝜕𝑉𝑑𝑝
𝑑𝑉𝑜𝑢𝑡 𝑜𝑢𝑡

(𝑛𝑛 +𝑛𝑝 )
or,(𝐵 ′ − 𝐵) = −(𝐴′ − 𝐴) (10)
𝑛𝑝

or,

(𝐴′ − 𝐴)𝑉𝑑𝑑 ((𝑛𝑛 + 2𝑛𝑝 ) − (𝐴′ − 𝐴)(𝑛𝑛 + 𝑛𝑝 )𝑉𝑖𝑛 − (𝐴′ − 𝐴)(𝑛𝑛 + 𝑛𝑝 )𝑉𝑓𝑏𝑝 − {(𝐶𝑝′ − 𝐶𝑝 )𝑛𝑝 − (𝐶𝑛′ − 𝐶𝑛 )𝑛𝑛
(𝐴′ − 𝐴)(𝑛𝑛 − 𝑛𝑝 )
= 𝑉𝑜𝑢𝑡

𝑉𝑖𝑛 = (𝑉𝑑𝑑 − 𝑉𝑓𝑏𝑝 ) = 𝑉𝐼𝐿

Similarly we can find out the values of different parameters of CMOS inverter such as input high,
output high, output low, noise margin, rise time and propagation delay.

Input high of the circuit is

 (𝐴′ − 𝐴)𝑃𝑝 𝑉𝑑𝑑 − (𝐴′ − 𝐴)𝑃𝑝 (𝑉𝑖𝑛 − 𝑉𝑓𝑏𝑝 ) − {(𝐶𝑝′ − 𝐶𝑝 )𝑃𝑝 − (𝐶𝑛′ − 𝐶𝑛 )𝑃𝑛 }
𝑉𝑜𝑢𝑡 = [ ]
(𝐴′ − 𝐴)(𝑃𝑛 + 𝑃𝑝 )

Output low of the circuit is

(𝐴′ − 𝐴)𝑛𝑝 𝑉𝑑𝑑 + (𝐵 ′ − 𝐵)𝑛𝑝 𝑉𝑓𝑏𝑝 − (𝐶𝑝′ − 𝐶𝑝 )𝑛𝑝 + (𝐶𝑛′ − 𝐶𝑛 )𝑛𝑛

𝑉𝑜𝑢𝑡 = [ ] = 𝑉𝑂𝐿
(𝐴′ − 𝐴)(𝑛𝑛 + 𝑛𝑝 )

Output high of the circuit is

(𝐴′ − 𝐴)𝑃𝑝 𝑉𝑑𝑑 − (𝐵′ − 𝐵)𝑃𝑛 𝑉𝑓𝑏𝑛 − (𝐶𝑝′ − 𝐶𝑝 )𝑃𝑝 + (𝐶𝑛′ − 𝐶𝑛 )𝑃𝑛
𝑉𝑜𝑢𝑡 = [ ] = 𝑉𝑂𝐻
(𝐴′ − 𝐴)(𝑃𝑛 + 𝑃𝑝 )

The noise margin of the circuit is given as:

Noise margin for logic 1 voltage

𝑉𝑁𝑀𝐻 = 𝑉𝑂𝐻 − 𝑉𝐼𝐻

(𝐴′ − 𝐴)𝑃𝑝 𝑉𝑑𝑑 − (𝐵′ − 𝐵)𝑃𝑛 𝑉𝑓𝑏𝑛 − (𝐴′ − 𝐴)(𝑃𝑛 + 𝑃𝑝 )𝑉𝑓𝑏𝑛 − (𝐶𝑝′ − 𝐶𝑝 )𝑃𝑝 + (𝐶𝑛′ − 𝐶𝑛 )𝑃𝑛
=[ ]
(𝐴′ − 𝐴)(𝑃𝑛 + 𝑃𝑝 )

Noise margin for logic zero voltage

𝑉𝑁𝑀𝐿 = 𝑉𝐼𝐿 − 𝑉𝑂𝐿

(𝐴′ − 𝐴)𝑛𝑛 𝑉𝑑𝑑 − (𝐵 ′ − 𝐵)𝑛𝑝 𝑉𝑓𝑏𝑝 − (𝐴′ − 𝐴)(𝑛𝑛 + 𝑛𝑝 )𝑉𝑓𝑏𝑝 + (𝐶𝑝′ − 𝐶𝑝 )𝑛𝑝 − (𝐶𝑛′ − 𝐶𝑛 )𝑛𝑛
=[ ]
(𝐴′ − 𝐴)(𝑛𝑛 + 𝑛𝑝 )

The fall time of the circuit is

𝑡𝐻𝐿
𝐿𝑠 𝑊𝑑1 𝑞𝜇𝑛 𝑊(𝑡𝑔 + 2𝑡𝑜𝑥 ) + 2(𝐿𝑠 − 𝑊𝑑1 )(𝑞𝜇𝑝 𝑊{𝑡𝑔 + 2𝑡𝑜𝑥 }) 𝐿
= ([ + 2 ]+[ ]
2𝑞𝜇𝑛 𝑊𝑡𝑠𝑖 2𝑞 2 𝜇𝑛 𝜇𝑝 𝑊 2 (𝑡𝑔 + 2𝑡𝑜𝑥 )
𝑡 𝑊
𝑞𝜇𝑛 𝑊 ( − 𝑊𝑑2 ) + 𝑞𝜇𝑝 𝑊 𝑑2
𝑠𝑖
2 2
𝑊𝑑3
𝐿𝐷 {𝑞𝜇𝑛 𝑊(𝑡𝑔 + 2𝑡𝑜𝑥 ) + (𝐿𝐷 − 𝑊𝑑3 )(𝑞𝜇𝑝 𝑊(𝑡𝑔 + 2𝑡𝑜𝑥 )} 𝐶𝑜𝑢𝑡
2
+[ 2 ]) (𝐴′ [ln {𝑉𝑜
2𝑞𝜇𝑛 𝑊
𝑡𝑠𝑖 𝑊𝑑3
{𝑞𝜇𝑛 𝑊(𝑡𝑔 + 2𝑡𝑜𝑥 ) + (𝐿𝐷 − 𝑊𝑑3 )𝑞𝜇𝑝 𝑊(𝑡𝑔 + 2𝑡𝑜𝑥 )} + 𝐿𝐷 𝑞2𝜇 2 − 𝐴)
2 2 𝑛 𝜇𝑝 𝑊 (𝑡𝑔 + 2𝑡𝑜𝑥 )
(𝐶𝑛′ − 𝐶𝑛 ) (𝐶𝑛′ − 𝐶𝑛 )
− } − ln {𝑉1 − }]
(𝐴′ − 𝐴) (𝐴′ − 𝐴)

The rise time of the circuit is

 𝑊𝑑1
𝐿𝑠
{ 2
𝑡𝑠𝑖 }
2
𝑞 𝜇𝑛 𝜇𝑝 𝑊 2
2 𝑔
(𝑡 +2𝑡𝑜𝑥 ) 𝐿
𝑡𝐿𝐻 = 𝑊𝑑1 + 𝑊𝑑2
𝐿𝑠 𝑞𝜇𝑝 𝑊
{2 [ 𝑞𝜇 2
]+ 𝑡 } 2
𝑝𝑊 (𝑡𝑔 +2𝑡𝑜𝑥 ) 𝑞𝜇𝑛 𝑊 𝑠𝑖
( 2
𝑊𝑑3 𝐿𝐷

{ 2
𝑡 }
𝑞 2 𝜇𝑛 𝜇𝑝 𝑊 2 𝑠𝑖 (𝑡𝑔 +2𝑡𝑜𝑥 )
2
𝐶𝑜𝑢𝑡 (𝐶𝑝′ − 𝐶𝑝 )
+ [ln {𝑉𝑑𝑑 − 𝑉1 − }
𝑊𝑑3
𝐿𝐷 (𝐴′ − 𝐴) (𝐴′ − 𝐴)
{2 [ 𝑞𝜇 2
]+ 𝑡 }
𝑞𝜇𝑛 𝑊 𝑠𝑖
𝑝𝑊(𝑡𝑔 +2𝑡𝑜𝑥 ) 2 )
(𝐶𝑝′ − 𝐶𝑝 )
− ln {𝑉𝑑𝑑 − 𝑉𝑜 − }]
(𝐴′ − 𝐴)

The propagation delay of the circuit is given by

𝑡𝑃𝐻𝐿
𝐿𝑠 𝑊𝑑1 𝑞𝜇𝑛 𝑊(𝑡𝑔 + 2𝑡𝑜𝑥 ) + 2(𝐿𝑠 − 𝑊𝑑1 )(𝑞𝜇𝑝 𝑊{𝑡𝑔 + 2𝑡𝑜𝑥 }) 𝐿
= ([ + 2 ]+[ ]
2𝑞𝜇𝑛 𝑊𝑡𝑠𝑖 2 2
2𝑞 𝜇𝑛 𝜇𝑝 𝑊 (𝑡𝑔 + 2𝑡𝑜𝑥 )
𝑡𝑠𝑖 𝑊
𝑞𝜇𝑛 𝑊 ( − 𝑊𝑑2 ) + 𝑞𝜇𝑝 𝑊 𝑑2
2 2
𝑊𝑑3
𝐿𝐷 {𝑞𝜇𝑛 𝑊(𝑡𝑔 + 2𝑡𝑜𝑥 ) + (𝐿𝐷 − 𝑊𝑑3 )(𝑞𝜇𝑝 𝑊(𝑡𝑔 + 2𝑡𝑜𝑥 )} 𝐶𝑜𝑢𝑡
2
+[ 2 ]) (𝐴′ [ln {𝑉𝐼
2𝑞𝜇𝑛 𝑊
𝑡𝑠𝑖 𝑊𝑑3
{𝑞𝜇𝑛 𝑊(𝑡𝑔 + 2𝑡𝑜𝑥 ) + (𝐿𝐷 − 𝑊𝑑3 )𝑞𝜇𝑝 𝑊(𝑡𝑔 + 2𝑡𝑜𝑥 )} + 𝐿𝐷 𝑞 2 𝜇𝑛 𝜇𝑝 𝑊 2 (𝑡𝑔 + 2𝑡𝑜𝑥 ) − 𝐴)
2 2
(𝐶𝑛′ − 𝐶𝑛 ) (𝐶𝑛′ − 𝐶𝑛 )
− } − ln {𝑉𝑂𝐻 − }]
(𝐴 − 𝐴)
′ (𝐴′ − 𝐴)

𝑊𝑑1
𝐿𝑠
{ 2
𝑡𝑠𝑖 }
2
𝑞 𝜇𝑛 𝜇𝑝 𝑊 2
2 𝑔
(𝑡 +2𝑡𝑜𝑥 ) 𝐿
𝑡𝑃𝐿𝐻 = 𝑊𝑑1 + 𝑊𝑑2
𝐿𝑠 𝑞𝜇𝑝 𝑊
{2 [ 𝑞𝜇 2
]+ 𝑡 } 2
𝑝𝑊 (𝑡𝑔 +2𝑡𝑜𝑥 ) 𝑞𝜇𝑛 𝑊 𝑠𝑖
( 2
𝑊𝑑3 𝐿𝐷

{ 2
𝑡 }
𝑞 2 𝜇𝑛 𝜇𝑝 𝑊 2 𝑠𝑖 (𝑡𝑔 +2𝑡𝑜𝑥 )
2
𝐶𝑜𝑢𝑡 (𝐶𝑝′ − 𝐶𝑝 )
+ [ln {𝑉𝑑𝑑 − 𝑉𝑂𝐻 − }
𝑊𝑑3
𝐿𝐷 (𝐴′ − 𝐴) (𝐴′ − 𝐴)
{2 [ 𝑞𝜇 2
]+ 𝑡 }
𝑞𝜇𝑛 𝑊 𝑠𝑖
𝑝𝑊(𝑡𝑔 +2𝑡𝑜𝑥 ) 2 )
(𝐶𝑝′ − 𝐶𝑝 )
− ln {𝑉𝑑𝑑 − 𝑉𝐼 − }]
(𝐴′ − 𝐴)

Therefore the propagation delay is given as

𝑡𝑃𝐻𝐿 + 𝑡𝑃𝐿𝐻
𝑡𝑝 =
2

As well as power loss can be obtained by using the following equation

𝑃𝑑 = 𝑉𝑜𝑢𝑡 𝐼𝑑𝑠

III. RESULTS
A comparison of variation of output current and power losswith input voltage for different values of
temperature and work functionare shown in the figures given below. Figure 3. (a) shows the
comparison of the output current variation with the input voltage for different ranges of temperature.
With increase in the temperature the output current increases due to reduced channel resistance.

Figure 3.(a) Output current versus Input voltage for different ranges of temperature.

Figure 3. (b) Output current versus Input voltage for different values of work functions.

Figure 3. (b) shows the comparison of the output current variation with the input voltage for different
values of work function. Here it shows the reduced in the work function results in the decrease in the
depletion region width due to which output current increases with the increase in the input voltage.
Figure 3. (c) Power loss versus Input voltage for different ranges of temperature.

Figure 3. (c) shows the comparison of the power loss variation with the input voltage for different
ranges of temperature. With lower temperature channel resistance is higher which causes on state
power loss to be higher as seen from the figure.

Figure 3. (d) Power loss versus Input voltage for different values of work functions.

Figure 3. (d) aboveshows the comparison of the power loss variation with the input voltage for different
values of work function. With higher work function of gate the depletion region width is more which
results in higher channel resistance and causes the on state power loss to be higher. It is clear from the
figure.
Figure 3. (e) Output voltage versus Input voltage for different ranges of temperature.

Figure 3. (e) shows the comparison of the output voltage variation with the input voltage for different
ranges of temperature. With reduced temperature output voltage increases with the increase in the input
voltage results as output resistance will be higher. However, Noise margin will be lower for higher
temperature.

Figure 3. (f) Output voltage versus Input voltage for different values of work functions.

Figure 3. (f) shows the comparison of the output voltage variation with the input voltage for different
values of work function. With increase in the work function depletion region width increases which
causes higher channel resistance and higher output voltage and noise margin also.

TABLE I

NOISE MARGIN OF CMOS INVERTER OF DIFFERENT RANGES OF TEMPERATURE

Temperature(K) SCJLFET Conventional
JLFET
NMH(V) NML(V) NMH(V) NML(V)
200 K 0.95 0.64 0.53 0.237
300 K 0.82 0.51 0.41 0.128
400 K 0.71 0.4 0.32 0.11
500 K 0.6 0.31 0.21 0.098
600 K 0.49 0.23 0.12 0.084

TABLE II

NOISE MARGIN OF CMOS INVERTER OF DIFFERENT VALUES OF WORK FUNCTION

Work Function SCJLFET Conventional

(eV) JLFET
NMH(V) NML(V) NMH(V) NML(V)
5.0eV 0.45 0.14 0.092 0.081
5.1eV 0.54 0.22 0.13 0.094
5.2eV 0.63 0.33 0.22 0.102
5.3eV 0.71 0.42 0.34 0.113
5.4eV 0.82 0.51 0.41 0.128

The transient responses of the output current, voltage and power are shown in Figure 4. (a) and 4. (b)
for different values of work function and ranges of temperature. Table III and IV present the rise time

and fall time comparisons of the SCJLFET and conventional JLFET for different work function and
ranges of temperature. Table V and VI compare the propagation delays of the SCJLFET and the
conventional JLFET for different work function and ranges of temperature. As can be seen from the
figures and tables higher temperature causes the kinetic energy of the carriers to rise which results in
lower rise time, fall time and propagation delay for higher temperature. Higher workfunction of gate
increases the gate controllability as well as faster switching. As a result rise time, fall time and
propagation delay are lower for higher workfunction of gate.
Figure 4. (a) Voltage transient for different ranges of temperatures.

Figure 4. (b) Voltage transient for different work functions.

TABLE III

RISE TIME AND FALL TIME OF CMOS INVERTER FOR DIFFERENT RANGES OF
TEMPERATURE

TEMPERATURE (K) SCJLFET Conventional JLFET

Rise time (ns) Fall time (ns) Rise time (ns) Fall time (ns)
200 K 0.054 0.053 0.067 0.063
300 K 0.042 0.047 0.059 0.054
400 K 0.027 0.026 0.045 0.041
500 K 0.015 0.014 0.035 0.034
600 K 0.003 0.002 0.027 0.025

TABLE IV

RISE TIME AND FALL TIME OF CMOS INVERTER FOR DIFFERENT VALUES OF
WORK FUNCTION

WORK FUNCTION SCJLFET Conventional JLFET

(eV)
Rise time (ns) Fall time (ns) Rise time (ns) Fall time (ns)
5.0 eV 0.085 0.086 0.106 0.108
5.1 eV 0.076 0.077 0.095 0.98
5.2 eV 0.066 0.065 0.083 0.085
5.3 eV 0.057 0.056 0.072 0.074
5.4 eV 0.042 0.047 0.059 0.54

TABLE V
PROPAGATION DELAY OF CMOS INVERTER FOR DIFFERENT RANGES OF
TEMPERATURE

TEMPERATURE (K) SCJLFET CONVENTIONAL JLFET

200 K 0.031ns 0.051ns
300 K 0.023ns 0.041 ns
400 K 0.015ns 0.037 ns
500 K 0.006ns 0.024 ns
600 K 0.001ns 0.013 ns

TABLE VI

PROPAGATION DELAY OF CMOS INVERTER FOR DIFFERENT VALUES OF WORK

FUNCTION

WORK FUNCTION (eV) SCJLFET CONVENTIONAL JLFET

5.0 eV 0.071ns 0.091ns
5.1 eV 0.059ns 0.079ns
5.2 eV 0.047ns 0.068 ns
5.3 eV 0.034ns 0.051 ns
5.4 eV 0.023ns 0.041 ns

IV. CONCLUSION

The performance evaluation of a CMOS inverter using surrounded channel junction less field effect
transistor (SCJLFET) is reported in this paper. In this study a CMOS inverter based on SCJLFET is
designed. Mathematical models have been developed for various inverter circuit parameters. The
models were compared with the TCAD simulations for validation. Furthermore, the noise margin, rise
time, fall time and propagation delay of the SCJLFET were compared with those of the conventional
junction less transistor and improvements in the parameters of the SCJLFET were observed.

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