Journal of Electrical and Electronics Engineering

Towards Improving Clock Domain Crossing Verification for SoCs

GUPTA Vrinda1, KASIM Mohammad2, JEBIN Mohandas3
1,2
National Institute of Technology Kurukshetra, India,
1
Department of Electronics and Communication Engineering, 2School of VLSI and Embedded System Design,
1,2
Kurukshetra, 136119 Haryana, India, 1vrindag16@nitkkr.ac.in, 2kasim_31811220@nitkkr.ac.in
3
Intel Technology India Private Limited, Karnataka, India,
Department of PESG Fast,
Karnataka, India, 3jebin.mohandas@intel.com

Abstract – Moore‘s law has been motivating the
semiconductor industry to churn out multi-clock
(mostly unrelated) complex system on chip (SoC)
designs. Data/signals that crosses such unrelated or
asynchronous clock domains are more likely to be
sampled before they are stable, and can cause issues
like metastability. Such clock domain crossing (CDC)
signals must be synchronized between the domains
using a valid synchronizer, and must be verified in
some way exhaustively before quality sign-off. If not
verified appropriately or detected late in the design
cycle, these crossings will result into chip re-spins and
prove too costly, as sometimes the product itself will be
out of market. The typical challenge in flat netlist-
based CDC verification checks is huge run time,
memory consumption & millions of violations to debug
counts. In this paper, therefore, a hierarchical CDC
verification methodology has been implemented for
system-on-chip integrated circuits. This hierarchical
approach improves the CDC verification for SoC in
terms of memory consumption, time taken for sign-off
without compromising quality.
Keywords: SoC; metastability; clock domain crossing;
synchronization; reset domain crossing; glitch.
I. INTRODUCTION
Earlier ASIC/Custom chip designs use to have only
one or two clocks that used to drive the entire chip.
Following the road-map of Moore's law, the attempt of
putting more number of transistors on same silicon size
is continuing. By putting more on single chip, one is
putting more unrelated things being driven by different
clocks which leads to data crossing clock domains,
which is now a very common scenario. Data crossing
the clock domains further leads to different issues like
metastability, data loss and glitch etc. which can be
clubbed and termed as clock domain crossing (CDC)
issue [1]. This CDC problem is continuing to increase in
modern system-on-chip (SoC) as one is making more
complex systems. Therefore, solutions are needed to scale
down the problem as design complexity grows with the
increase in complexity of current system-on-chips. The
traditional register transfer level (RTL) verification
techniques like Functional simulation, Timing analysis, and
many other complex formal techniques cannot guarantee
fabricated chips free of CDC and reset domain crossing
(RDC) errors, and glitches. Some of the CDC and RDC
related faults responsible for chip re-spins if not verified,
are as follows [1], [2].
 Metastability due to setup and hold-time
violations in CDC path.
 Metastability due to asynchronous RDC.
 Glitch propagation due to convergence and
divergences of crossover paths.
 Clock jitter.
For a complex design like SoC, it is very common to
have multiple independent clock domains, and so there
exists huge number of CDC crossing paths in design
where the data can face CDC issues like metastability,
data loss, data incoherency etc. Data crossing the clock
domains are vulnerable to CDC issues and can cause
functional failure of chip. It is very hard or impossible to
detect such CDC issues at simulation level [3]. There is
no way one can be sure that this issue can be prevented
by this method or that method. But one can try to reduce
the detrimental effects of such issue on chips with the
help of synchronizers. Different synchronizers are
proposed for different scenarios of data crossing the
clock domains, and thus it becomes very crucial to verify
the correctness of synchronizer [4]. Several design
automation tools are available which aid in finding
missing synchronizers, reconvergence of synchronized
signals, divergences in the crossover, etc. [5], [6].
Besides, research works are available that reports
System Verilog Assertions (SVA) for finding CDC
faults in simulation [7], [8]. CDC verification of SoC
has multidimensional challenges like huge run time,
memory consumption & million violation counts.
Considering all challenges, one should try to improve
the CDC verification techniques for SoCs.
An attempt has been made in this paper to
understand CDC concept together with its issues of

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 JEEE, Volume 14, Number 2, October 2021
concern, available synchronization techniques, CDC
tools, and its limitations. Besides, CDC verification
methodology flow for SoC has been provided. A
hierarchical approach has been implemented in the
present paper to improve CDC verification for SoCs.
The hierarchical methodology leverages the advantages
of available CDC verification techniques. It results in
low memory utilization and less time for sign-off by
reducing the run time.
II. BACKGROUND AND RELATED WORK
A. Clock Domain Crossing (CDC)
For any pair of sequential elements, i.e., flip-flop to
flip-flop, flip-flop to latch, latch to flip-flop, etc., that
have different launching and capturing clock, the
designer does not know exactly how much edge
difference exists there between the clocks. Even in cases
wherein the phase is known, design engineer cannot do
setup / hold, or max. / min. checks, because phase
relation is not constant. Such scenarios are termed as
Clock Domain Crossing (CDC). In these scenarios, it is
very difficult to avoid metastability, or stop glitch to
propagate in the design, and it finally leads to chip
failure. A simple CDC case is shown in Figure 1. Input
data ‘Din’ is launched by the ‘CLK1’ (TX-flop) clock
domain and should be captured properly by ‘CLK2’
(RX-flop) clock domain. Depending on the clock
relationships between ‘CLK1’ and ‘CLK2’, one might
get different problems when input data travels from
input of TX-flop to output of RX-flop. If data at input of
RX-flop changes between the setup-hold window of
RX-flop, then it may lead to metastability. Hence, one
needs special CDC checks to ensure that the data at the
input of RX-flop never lands in the setup and hold
window of RX-flop. This is the fundamental and the only
check required for CDC sign-off [1], [9], [10].
So, in cases, when designer does not have a
relationship between ‘CLK1’ and ‘CLK2’, metastability
can occur. However, there are many different ways for
avoiding this metastability or enabling synchronization.
For synchronization, one can take advantage of the
design architecture or different clock relationships.
Therefore, the designer must be aware of design
architecture and clock relationships to effectively
perform CDC checks.
When the CDC tools were designed, it was not
common to have a design where resets were more than
one/two in a block. So, during the development of the
tool, it was assumed that if TX-flop has asynchronous
reset asserted, then every RX-flop would be in reset. So,
while considering CDC checks with a tool, the tool
checks for the clock events in sequential elements, and
never checks for the reset events. Hence, RDC check
got into existence when designs were made more
complex.
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Fig. 1 Simple design with CDC
B. Reset Domain Crossing (RDC)
The design engineer would never want a signal at the
output of the RX-flop element to be metastable. The
possible case when the signal at the output of capturing
sequential element can go in the metastable state is
based on the clock event at TX-flop and RX-flop. But
that’s not the only possibility, it can also go to metastable
state based on asynchronous reset events at TX-flop
which CDC tools never check. For any pair of sequential
elements, if TX-flop has asynchronous reset, then the
event at the output of TX-flop is not only based on the
activity of 'CLK1', but also it is to be dictated based on
the activity of 'RST1' (asynchronous reset). If the output
TX-flop changes based on the clock event, then the
crossing checks that are done for that falls under CDC
checks. If the output of TX-flop changes asynchronously
because of the reset, then the crossing checks that are
done for that comes under RDC checks [11] [12].
A simple RDC case is shown in Figure 2. The TX-
flop and RX-flop have resets 'RST1' and 'RST2'
respectively. 'RST1' and 'RST2' are not the same or have
any defined relationship. Assume a scenario when
'RST1' is asynchronously asserted, but 'RST1' is not in
reset. Besides, also assume 'CLK2' is active so that RX-
flop will be sampling the output of TX-flop. So, when
an asynchronous assertion is active on ‘RST1’
regardless of the state clock ‘CLK1’, the output of TX-
flop will change. In that case, if output at TX-flop falls
between the setup-hold window of 'CLK2', it can make
the output of RX- flop go into a metastable state. So, in
RDC check, one checks that if reset of TX-flop and RX-
flop are not same, or both have an asynchronous
relationship with each other and with the clocks.
Fig. 2 Simple design with RDC
 JEEE, Volume 14, Number 2, October 2021
It checks if the output of TX-flop changes with active
reset regardless of 'CLK1' falls between the setup-hold
window of RX-flop, which can cause the output to be
metastable, is synchronized or not to ensure output is
reliable. Thus, RDC is still a CDC problem, but due to
tool limitations, the industries conduct RDC checks
separately.
Few important points about RDC checks are as
follows.
 Even if RX-flop has no reset pin, the check is still a
valid check, because if there is a free-running clock
at RX-flop, then asynchronous reset on TX-flop can
still lead to metastability at the output of RX-flop if
the output from TX-flop is changing in between
setup-hold window of RX-flop. So, one must do
RDC checks based on the activity of asynchronous
reset at TX-flop regardless of reset is present at RX-
flop or not.
 Even if ‘CLK1’ and ‘CLK2’ are equal or
synchronous, RDC problem still exists, because the
problem is not based on the clock event. One can
have a synchronous system that can have multiple
asynchronous resets coming in. So, if reset on TX-
flop is asserted, but reset on RX-flop is not active,
in that case, while clocks are actively running,
metastability can still be injected. So, RDC is still a
problem even if CDC is not being a problem.
 In order to solve RDC, there are many ways to do it.
Number of synchronization methods exists. There is
not one particular solution to the problem. As
synchronization occurs in different ways, so, tools
also need to understand the way synchronization
has occurred.
C. Related Work
Multiple efforts have been made for performing
CDC verification for a design in VLSI industry. In
literature resources, important works on
verification of CDC issues exists [13], [14]. The
authors herein describes two methods for verifying CDC
interfaces. In one, rule base model checker is applied for
verifying the protocol specification based onA.
generated rule through Property Specifiation Language
(PSL) properties from the Signal Transition Graph
(STG). In the second method, the correctness of data
transfers, and duplicate data or missing data is verified.
Another important work is reported, wherein the authors
have proposed a novel SAT-based method to verify
CDC protocols [15]. The focus here is on modeling
multiple clocks by assigning a state variable for each
clock which takes the value 0 or 1 at each verification
tick. The assumption here is that setup and hold–time
are zero for any sequential flip-flop.
Modern SoCs have many clock domains at different
interface, so it uses different synchronizers. A solution
has been described in one of the research work for
preventing synchronization delay by overlapping it with
computational cycles [16]. In this paper, the correctness
of the method has been validated through a field-
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programmable gate array (FPGA) implementation and
applying it to several synthesized benchmarking circuits.
The outcome of this method shows an average saving of
135% and 204% in area and about 100% in power costs
as compared to other existing speculative method
discussed in the paper. In another work, a novel
approach has been devised for analyzing the behavior
and performance of synchronizers [17]. In this, the time
to voltage gain of a synchronizer has been formulated
and the results have proven that the gain increases
exponentially in the synchronizer circuit as a function of
time from the regenerative feedback.
A number of factors have been identified affecting
the performance measure of synchronizer like process
technology, operating conditions, and circuit design
[18]. The authors in this paper have made an attempt to
prove that such global constraints apply to entire
integrated circuit, whereas other factors can be tuned for
an individual synchronizer in the design. Furthermore, a
method has been proposed here in the paper for
improving the synchronizers i.e., selection of minimum
size flip-flop cells, avoiding scan and reset, minimizing
routing, choosing a high performance flavor and
minimum threshold voltage (VTH), and by reducing jitter
in coherent clock domain crossings. The literature also
contains SAL model based checker being used for
verifying the correctness of a simple CDC interfacing
circuit [19]. In this paper, the CDC interface is modelled
with SAL based model. The paper also provides a proof
verifying the compliance of the circuit with the basic
invariant. Besides this, some other works in literature
has suggested use of SMV model checker for
verification of multiple clock designs [20], [21].
III. CDC ISSUES
If data / signal crossing the clock domain is not
properly synchronized, then it may lead to one of the
many CDC issues depending on the architecture of the
design. Few common CDC issues are discussed in the
following sub-sections.
A. Metastability
Metastability in electronics is the ability of a dgital
electronic system to persist for an unbounded time or
bounded time in an unstable equilibrium or metastable
state [22-25]. The circuit may be unable to settle into a
stable ‘0’ or ‘1’ logic level within the time required for
proper circuit operation. In digital design, anything other
than logic 0 or logic 1, say 0.8VDD, 0.5VDD, or
0.2VDD is not resolved to logic ‘0’ or logic ‘1’in the
time that one is supposed to sample, then the operation
of that system becomes unstable/unpredictable. As
shown in Figure 3, CLK1=C1 and CLK2=C2 are
asynchronous clocks and A is the output of TX-flop.
Here, signal ‘A’ changes very close to the active edge of
C2, and it falls between the setup hold window of RX-
flop which causes output of RX-flop to be unstable for
an indefinite period of time or output of RX-flop is in
 JEEE, Volume 14, Number 2, October 2021
metastable state. After indefinite time, output will settle
to logic ‘1’ or logic ‘0’ based on how the unstable state
is resolved.
Fig.3 CDC signal with metastability [9]
Therefore, metastability is something that designers
try to avoid because it causes power related failure, as
well as functional error depending upon architecture. At
the end of metastable state, the flip-flop will eventually
settle down to logic’0’ or logic ‘1’. The time required to
settle depends on the technology of RX-flop, i.e.,
factors like gain of transistors, keeper sizing, and
capacitances, etc. The settling time (td) can thus be
computed and used for finding mean time between
failures (MTBF). Equation that governs determination of
MTBF is shown below.
MTBF α 1 / (td *fin *fclk) (1)
Where, td is settling time that flip-flop takes to
settle to stable value after it enters metastable state,
fin is frequency of input data, and fclk is the
frequency of clock sampling the input data. MTBF
indicates estimation of time that one has before
RX_flop enters metastable state.
B. Data Loss
If clock and data frequency of TX-flop is very high
compared to the clock frequency of RX-flop, then it may
lead to data loss if not synchronized properly. To avoid
this loss of data, the output data of TX-flop should
remain stable for some minimum period of time such
that the setup and hold time requirements are met with
respect to at least one active edge of destination clock.
Figure 4 (a) represents the meta-stability effect when
active clock edges of C1 and C2 are close to each other
(green in color) and not so close to each other (pink in
color). When the active edges are close to each other,
and if input data is held constant for a minimum time
such that timing requirements are matched to at least one
active edge of destination clock, then data will be
captured in 2nd destination clock cycle. But if clock
edges are not close, then data is captured in 1 st
destination clock cycle. The important thing here is that
each transition that happens at source should be captured
at destination to avoid data loss. Consider the case
where data bus is crossing domains and the frequency of
source clock is two times faster than the destination
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clock. Both have same phase. In Figure 4 (b), 0101111
sequence is the output of TX-flop at the active edge of
‘C1’, and that is sampled by RX-flop. The output of RX-
flop will be ‘0011’. Here the transition from 0 to 1
which was there on third active edge of source clock
‘C1’ is not captured by the destination flop and hence
data is lost.
Fig. 4(a) Metastability effect at output and data loss [9]
Fig.4.(b) Data loss for bus on crossing domain [9]
C. Data Incoherency
To understand the data incoherence issue, consider an
example where a data bus is crossing the clock domain
and each bit of data bus is synchronized separately with
double sync (2 D FF connected back to back). Now if
bits on data bus falls in the setup-hold window of
clock at receiver domain, then depending on how it is
resolved by double sync, output at each receiving bit of
data bus can come after N or N-1 or N+1 cycles, and
thus it may lead to incorrect data at the receiver end. In
such case, data coherency is missed, and it may lead to
functional errors. A case of data incoherency is shown in
Figure 5. X [0:1] is a 2-bit output data bus of source
which is clocked by ‘C1’, and Y [0:1] is the output data
bus of destination which is clocked by ‘C2’. Herein,
take “00” and “11” as two valid values generated by
source clock ‘C1’ for a data bus X. Now, let us assume a
transition of 1 → 0 on both the bits of X, and destination
clock C2 has perfectly captured both in the first cycle
such that Y becomes “00”. Next, during the transition
from 0 → 1 on both the bits of signal X, the rising edge
of clock C2 comes close to the transition on signal X
due to which intermediate value of “10” on Y[0:1] is
obtained which is an invalid state, and hence in this case
data coherency is missed.
 JEEE, Volume 14, Number 2, October 2021

Fig.5. Loss of data coherency [9] Fig. 6. Block diagram of a SoC

IV. HIERARCHICAL CDC VERIFICATION FLOW

CDC hierarchical analysis is ideal for IP-based SoCs

and large complex designs. It is the best choice for
analyzing design with many clocks, reset and many
clock domaincrossing. Typically, the IP in IP-based SoC
flow is available before the top-level design and setup.
Figure 6 shows the SoC view. The IP groups run block-
level CDC analysis and generate abstract block models
that they then deliver to the integration team who uses
these abstract models in the top-level CDC analysis.
This abstract model is specified in a Tcl based file
format called SDC (synthesis design constraints). This
abstract model should be picked and used at SoC level
in order to save run time considerably by avoiding the
need of re-reading & synthesizing the IP as IPs whose
abstract is available can be directly used in CDC checks.
This SDC file is imported into hierarchical bottom up
analysis flow. Figure 7 shows a very generic flow for
hierarchical CDC verification. Flow of CDC tools can
be looked in as three different stage of checks as
described below.
 Validate design setup
This stage checks RTL design file by compiling it, and
all the top-level design constraints information related to
clock and reset for correctness.
 Validate block setup and analyse block
This stage specifies and validates block setup and
generates a clock report at the block-level to ensure all
constraints are specified. This stage also generates an
abstract model for that block which is to be used in next
stage for CDC verification at SoCs level. It contains all
the necessary information about the block to verify and
debug issues during block integration in the SoCs.
 Hierarchical analysis at top level
After reviewing at block level violation and fixing any
issue, hierarchical analysis at top level is performed.
This CDC hierarchical top-level analysis includes the Fig. 7. Hierarchical CDC flow
abstract information generated for each block during
block level analysis.
that subsystem. It can be seen that hierarchical CDC is
consuming very less run time, less memory utilization
V. RESULTS AND DISCUSSION
(resources), and a smaller number of violation count
compared to flat CDC. Overall, hierarchical CDC
Table 1 shows the results obtained by running both
improves the quality of the result and thereby catches
flat CDC and hierarchical CDC checks on a subsystem
actual CDC issue in the design.
of an SoC by using an abstract model of all IPs used in

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 JEEE, Volume 14, Number 2, October 2021

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