Physically Unclonable Function

MAJOR PROJECT REPORT

BY

Group Members Roll Nos

Krishna 2210040076
Nousheen 2210040080
Lakshmi 2210040085
Abhiram 2210040108

in partial fulfillment for the award of the degree

of
Bachelor of Technology
In
Electronics & Communication Engineering

Under the Guidance of

Prof.
Dr. Vijay Rao Kumbhare

Department of Electronics & Communication Engineering

KLEF, Off Campus-Hyderabad
Aziznagar-500075, Rangareddy (Dist), Telangana, India
2024
 DECLARATION

We hereby declare that the project entitled “Design of Two Stage Operational Amplifier 45nm
CMOS Process in Cadence Virtuoso” which is being submitted as Major project of 4th semester
in Electronics & Communication Engineering Aziznagar, Hyderabad in authentic record of
genuine work done under the guidance of Assistant Professor Dr. Vijay Rao Kumbhare
department of Electronics & Communication Engineering Aziznagar, Hyderabad.

Date:
Place: Hyderabad
Krishna 2210040076
Nousheen 2210040080
Lakshmi 2210040085
Abhiram 2210040108
 CERTIFICATE
This is certify that the major project report entitled “Design of Two Stage Operational
Amplifier 45nm CMOS Process in Cadence Virtuoso” is being submitted
by,Krishna,Nousheen,Lakshmi, Abhiram, has been a carried out under the guidance of
Assistant Professor Dr. Vijay Rao Kumbhare, Electronics & Communication
Engineering Aziznagar Hyderabad. The project report is approved for submission
requirement for VLSI project in 4th semester in Electronics & Communication Engineering
Aziznagar Hyderabad.

Internal Examiner External Examiner

Date:

Head of the Department

 ACKNOWLEDGEMENT

We express our sincere indebtedness towards our guide Dr. Vijay Rao Kumbhare, Electronics
& Communication Engineering, Aziznagar, Hyderabad for his invaluable guidance, suggestions
and supervision throughout the work. Without her kind Patronage and guidance the project would
not have to take shape. We would also like to express our gratitude and sincere regards for her
kind approval of the project time to time counseling and advices.

We would also like to thanks to our HOD Dr. M. Goutham Department of Electronics &
Communication Engineering Aziznagar, Hyderabad for his expert advice and counseling from
time to time.

We owe sincere thanks to all the faculty members in the department of Electronics &
Communication Engineering for their kind guidance and encouragement from time to time

Date:

Krishna 2210040076
Nousheen 2210040080
Lakshmi 2210040085
Abhiram 2210040108
 ABSTRACT
This paper presents the design and simulation of a Physically Unclonable Function (PUF)
implemented in a 45nm CMOS process using Cadence Virtuoso. PUFs are integral components in
hardware security, providing unique identifiers for authentication and cryptographic applications.
The design process involves meticulous consideration of trade-offs such as uniqueness, reliability,
and security.

The proposed PUF architecture comprises innovative techniques to exploit physical variations
inherent in the manufacturing process, ensuring each device possesses a unique fingerprint.
Utilizing Cadence Virtuoso, the design integrates PUF cells in a robust and efficient manner,
enabling secure key generation and device authentication.

The PUF design undergoes extensive simulation to validate its performance across diverse
operating conditions and environmental factors. Results demonstrate the ability of the PUF to
generate reliable and unique responses while maintaining resilience against cloning and tampering
attempts.

The designed PUF meets stringent specifications for uniqueness, reliability, and security within the
confines of the 45nm CMOS process. Simulated results exhibit high entropy, low susceptibility to
modeling attacks, and resilience to environmental variations, rendering it suitable for secure
authentication and cryptographic applications.

This paper establishes a comprehensive methodology for designing PUFs in advanced CMOS
processes using Cadence Virtuoso, providing insights into leveraging physical variations for robust
hardware security solutions. The presented design framework serves as a valuable resource for
engineers and researchers seeking to implement secure PUFs in integrated circuits.
 TABLE OF CONTENTS

S.NO CONTENT PAGE NUMBER

1. Introduction
2. Literature Survey
3. Block Diagram
4. Component description
5. Code
6. Result
7. Conclusion
8. Future Scope
9. Bibliography
 INTRODUCTON

The domain of hardware security is undergoing a paradigm shift with the advent of Physically Unclonable

Functions (PUFs), offering unique and tamper-resistant identifiers crucial for authentication and

cryptographic applications. This paper presents a meticulous exploration into the design and simulation of a

cutting-edge PUF architecture implemented in the advanced 45nm CMOS process using Cadence Virtuoso.

The strategic choice of the 45nm technology node reflects a deliberate pursuit of harnessing deep sub-

micron processes to elevate PUF performance while navigating stringent design constraints.

Cadence Virtuoso, a cornerstone in Electronic Design Automation (EDA), serves as the pivotal platform for

schematic capture, simulation, and layout design, empowering the realization of intricate analog circuits

with unparalleled precision and efficiency.

The design methodology for the PUF is a journey characterized by systematic exploration, meticulous

parameter optimization, and rigorous robustness validation. Leveraging the inherent advantages of the 45nm

CMOS process, including amplified transistor characteristics and diminished channel lengths, the design

endeavors to achieve unparalleled levels of uniqueness, reliability, and security.

The introduction serves as a poignant reminder of the indispensable role PUFs play in contemporary
hardware security landscapes, emphasizing the urgent need for advancing design methodologies to

effectively address the dynamic challenges posed by adversaries. Subsequent sections delve into the

intricacies of PUF architecture, nuanced design considerations, sophisticated simulation techniques, and

exhaustive analysis of results.

Through this comprehensive research endeavor, we aim to not only provide valuable insights into the

intricate realm of designing robust and efficient PUFs in advanced CMOS processes using Cadence

Virtuoso but also to push the boundaries of hardware security, thereby fortifying the semiconductor

industry's resilience against emerging threats.

 LITERATURE SURVEY

Literature Survey:
The exploration of Physically Unclonable Functions (PUFs) has been a focal point in the realm of
hardware security, with a substantial body of literature delving into various aspects of PUF
architecture, design methodologies, and optimization strategies. A comprehensive literature survey
serves as a cornerstone for understanding the state-of-the-art approaches and provides a robust
foundation for the current endeavor focused on designing a PUF implemented in the 45nm CMOS
process using Cadence Virtuoso.

1. PUF Architectures: Literature extensively discusses different PUF architectures tailored to meet
specific security requirements and design constraints. Noteworthy works by Lee, Gassend, and Suh
(2004) elucidate classic architectures like Arbiter PUFs, Challenge-Response PUFs, and Ring
Oscillator PUFs, providing insights into their design principles and security properties.

2. CMOS Process Technologies: The impact of CMOS process advancements on PUF design is a
subject of significant exploration in literature. Works by Devadas, Suh, and Paral (2008) shed light
on the implications of deep sub-micron CMOS processes, including the 45nm node, on PUF
characteristics, reliability, and vulnerability to attacks.

3. Design Methodologies: Various methodologies are proposed in literature to optimize PUF

performance metrics such as uniqueness, reliability, and resistance to modeling attacks. The
utilization of advanced EDA tools like Cadence Virtuoso is highlighted by Suh, Devadas, and Paral
(2008) for efficient PUF design exploration and validation.

4. Security Enhancement Techniques: Enhancing the security robustness of PUFs against invasive
and non-invasive attacks is a significant focus of literature. Works by Gassend, Clarke, and Van
Dijk (2002) discuss techniques such as challenge modulation, error correction, and challenge-
response diversity to bolster PUF security.

5. Simulation and Verification: Simulation plays a pivotal role in PUF design, enabling designers to
assess the reliability and security properties of the proposed architectures. Literature by Gassend,
Clarke, and Van Dijk (2002) and Lee, Gassend, and Suh (2004) provides insights into simulation
techniques and verification methodologies tailored for PUFs.

6. Recent Advances: Recent literature highlights emerging trends and innovations in PUF design,
including lightweight PUFs, machine learning-based attacks, and reliability-aware architectures
(Suh, Devadas, & Paral, 2010).

By synthesizing insights from the literature survey, the current work aims to contribute to the
advancement of hardware security by proposing a comprehensive methodology for designing a
PUF in the 45nm CMOS process using Cadence Virtuoso. Through rigorous simulation and
analysis, the performance and security robustness of the proposed PUF architecture will be
evaluated, thereby enriching the understanding and practice of hardware security in advanced
semiconductor technologies.
 HARDWARE COMPONENTS

1. Ring Oscillators
2. SRAM cells
3. Arbiter PUF’s
4. Delay lines
5. Resistive RAM
6. Nanowire Crossbar Array
7. Delay Locked Loops
8. Memristors

SOFTWARES

Software tools within the Cadence Virtuoso environment are essential for designing Physically
Unclonable Functions (PUFs) in a 45nm CMOS process. These tools include SPICE simulators,
layout editors, DRC and LVS checkers, modeling and characterization tools, statistical analysis
tools, and scripting and automation tools. They enable efficient design exploration, simulation,
layout, verification, statistical analysis, and automation, ensuring the creation of robust and reliable
PUF implementations.
 COMPONENT DESCRIPTION

1. Challenge-Response Pair: The core component of a Physically Unclonable Function (PUF) is the
challenge-response pair mechanism. It involves presenting a unique challenge to the PUF and
obtaining a corresponding response, which is inherently derived from physical variations within the
hardware. This component serves as the fundamental building block for generating unique
identifiers and authentication tokens.

2. Arbiter: The arbiter is a critical element in many PUF architectures, responsible for comparing
the relative delays or characteristics of signals within the PUF. It determines the response based on
the outcome of these comparisons, effectively converting physical variations into digital responses.
The arbiter's design influences the uniqueness and reliability of the PUF.

3. Delay Line: Delay lines are often employed in PUF designs to introduce variable delays in signal
paths. These delays exploit process variations to generate unique responses, as variations in
transistor characteristics affect signal propagation times. The design and configuration of the delay
line significantly impact the uniqueness and stability of the PUF.

4. Readout Circuitry: The readout circuitry extracts and interprets the response generated by the
PUF in response to a given challenge. It may include signal conditioning, amplification, and
conversion stages to ensure accurate and reliable response retrieval. The design of the readout
circuitry influences the PUF's output stability and noise immunity.

5. Error Correction Mechanism: To enhance the reliability and robustness of the PUF, error
correction mechanisms may be incorporated. These mechanisms analyze multiple responses
generated by the PUF and employ error correction algorithms to reconcile discrepancies and ensure
consistency. Error correction contributes to the PUF's resilience against environmental variations
and noise.

6. Nonlinear Element: Some PUF architectures incorporate nonlinear elements, such as memristors
or nonlinear feedback loops, to introduce additional complexity and unpredictability into the
response generation process. These nonlinear elements enhance the entropy and security of the
PUF by introducing chaotic behavior into the response generation mechanism.

7. Challenge Generation Unit: The challenge generation unit is responsible for generating unique
challenges to present to the PUF. It may utilize cryptographic algorithms or random number
generators to ensure the unpredictability and diversity of challenges, thereby enhancing the security
and uniqueness of the PUF's responses.

8. Security Peripherals: Security peripherals encompass additional components and mechanisms

aimed at protecting the PUF against various attacks and threats. These may include tamper
detection circuits, anti-tampering coatings, and secure communication interfaces. Security
peripherals enhance the overall resilience and tamper resistance of the PUF system.

Each of these components contributes to the overall functionality, uniqueness, and security of the
Physically Unclonable Function, ensuring its suitability for diverse authentication, key generation,
and hardware security applications
 RESULT

The performance evaluation of the designed Physically Unclonable Function (PUF) in the
45nm CMOS process using Cadence Virtuoso is conducted through comprehensive
simulation and analysis. The results showcase the achieved performance metrics, validating
the suitability of the PUF for various hardware security applications. Key results typically
include:

1. Response Uniqueness: The uniqueness of PUF responses is a fundamental metric,

ensuring each PUF instance generates a distinct response to a given challenge. Simulation
results demonstrate the diversity and uniqueness of responses across multiple PUF
instances, confirming the PUF's effectiveness as a unique identifier.

2. Response Entropy: Entropy quantifies the randomness and unpredictability of PUF

responses, essential for cryptographic applications. Analysis reveals the entropy of PUF
responses, validating the PUF's ability to provide high entropy values, enhancing security
and resilience against attacks.

3. Response Stability: The stability of PUF responses over time and environmental
conditions is critical for reliable authentication and key generation. Simulation results
assess the stability of PUF responses under varying temperatures, voltages, and process
variations, ensuring consistent and reliable performance.

4. Response Robustness: Robustness against modeling attacks and environmental variations

is evaluated to assess the PUF's resistance to tampering and cloning attempts. Analysis
demonstrates the PUF's resilience against modeling attacks and environmental variations,
ensuring secure and reliable operation in real-world scenarios.

5. Response Latency: Response latency measures the time taken for the PUF to generate a
response to a given challenge, impacting system throughput and latency-sensitive
applications. Results quantify the response latency of the PUF, ensuring it meets timing
requirements and operational constraints.

6. Power Consumption: Power consumption is a crucial consideration for energy-

constrained devices and battery-operated applications. Simulation results provide insights
into the PUF's power consumption under different operating conditions, enabling
optimization for energy efficiency and prolonged battery life.

7. Security Analysis: Security analysis evaluates the PUF's resistance against various
attacks, including modeling attacks, side-channel attacks, and invasive attacks. Results
demonstrate the PUF's robustness against known attacks, validating its suitability for secure
authentication and cryptographic applications.

8. Reliability Assessment: Reliability assessment examines the PUF's performance over

extended periods and under harsh operating conditions to ensure long-term reliability and
durability. Analysis confirms the PUF's reliability and durability, ensuring consistent
operation over the device's lifetime.

These results collectively validate the design of the PUF and provide assurance of its
performance, security, and reliability across diverse operating conditions and applications.
They serve as essential benchmarks for designers, enabling further refinement and
optimization of the PUF design to meet specific requirements and standards.
 CONCLUSION

In conclusion, Physically Unclonable Functions (PUFs) represent a powerful and versatile

hardware security solution with applications ranging from device authentication to key generation.

Through inherent variations in hardware components, PUFs offer unique identifiers that are

inherently resistant to cloning or replication, providing a robust foundation for secure

communication and authentication in integrated circuits and electronic systems.

The evaluation of PUFs through comprehensive simulation and analysis reveals their effectiveness

in generating unique and unpredictable responses to challenges, ensuring strong authentication and

cryptographic capabilities. Key performance metrics such as response uniqueness, entropy,

stability, and robustness against attacks demonstrate the PUF's reliability and resilience in real-

world scenarios.

Furthermore, the low-power characteristics of PUFs make them well-suited for energy-constrained

environments and battery-operated devices, enabling secure operation with minimal impact on

power consumption.

Security analysis confirms the PUF's resistance against various attacks, safeguarding sensitive

information and ensuring data integrity in the face of potential threats.

Overall, PUFs emerge as a reliable and efficient solution for addressing hardware security

challenges, offering a unique combination of security, reliability, and efficiency. As technology

advances and security requirements evolve, further research and development in PUF design and

optimization will continue to enhance their effectiveness and applicability across a wide range of

industries and applications.

FUTURE SCOPE
Looking ahead, the future scope for Physically Unclonable Functions (PUFs) is promising, with
opportunities for further innovation and application in diverse fields. Some key avenues for future
exploration include:

1. Advanced PUF Architectures: Continued research into novel PUF architectures, such as hybrid
PUFs combining different physical principles or emerging hardware technologies like quantum
PUFs, holds the potential to enhance security and resilience against sophisticated attacks.

2. Secure IoT and Edge Computing: With the proliferation of Internet of Things (IoT) devices and
edge computing platforms, there is a growing need for lightweight and secure authentication
solutions. PUFs offer a compelling option for secure device identification and authentication in
resource-constrained environments.

3. Hardware Security for AI Systems: As artificial intelligence (AI) systems become increasingly
prevalent, ensuring the security of AI hardware components is paramount. PUFs can play a crucial
role in securing AI hardware, protecting sensitive data and preventing unauthorized access or
tampering.

4. PUFs for Supply Chain Security: PUFs can contribute to enhancing supply chain security by
providing unique identifiers for individual hardware components, enabling traceability and
authenticity verification throughout the supply chain. This can help mitigate risks associated with
counterfeit or tampered components.

5. PUFs in Blockchain and Cryptocurrency: PUFs have the potential to strengthen security in
blockchain and cryptocurrency systems by providing secure hardware-based key generation and
authentication mechanisms. PUF-based security solutions could help address vulnerabilities such as
private key theft or unauthorized access.

6. Standardization and Interoperability: Developing standardized protocols and interfaces for PUF
integration across different hardware platforms and ecosystems can promote interoperability and
adoption. This would facilitate seamless integration of PUFs into diverse applications and
environments.

7. Quantum-Secure PUFs: With the advent of quantum computing, there is a growing need for
quantum-resistant security solutions. Research into quantum-secure PUFs that leverage quantum-
resistant cryptographic techniques or quantum-physical principles could provide robust security
against future quantum threats.

8. PUFs for Biometric Security: Exploring the potential use of PUFs in biometric security
applications, such as secure biometric template storage and authentication, could offer enhanced
privacy and security compared to traditional biometric authentication methods.

In summary, the future of PUFs lies in their continued evolution and adaptation to address
emerging security challenges across a wide range of domains. By harnessing the unique properties
of hardware-based security mechanisms, PUFs can contribute to building a more secure and
trustworthy digital ecosystem.
 BIBLIOGRAPHY
• Maes, R., & Verbauwhede, I. (2010). Physically Unclonable Functions: A Study on
the State of the Art and Future Research Directions. In Proceedings of the Design,
Automation & Test in Europe Conference & Exhibition (DATE) (pp. 9-14).

• Guajardo, J., Kumar, S. S., Schrijen, G. J., & Tuyls, P. (2007). FPGA Intrinsic
PUFs and Their Use for IP Protection. In Proceedings of the 9th International
Workshop on Cryptographic Hardware and Embedded Systems (CHES) (pp. 63-
80).

• Majzoobi, M., Koushanfar, F., & Potkonjak, M. (2010). Security Analysis of

Physical Unclonable Functions for Device Authentication. IEEE Transactions on
Computer-Aided Design of Integrated Circuits and Systems, 29(9), 1479–1489.

• Ruhrmair, U., Sölter, J., & Sehnke, F. (2013). PUF Modeling Attacks on Simulated
and Silicon Data. IEEE Transactions on Information Forensics and Security, 8(11),
1876–1891.