HANUMANTH REDDY
Combinational circuit
❖ The output of a combinational
circuit depends solely on the
present combination of inputs.
In other words, its past inputs
don't affect the current output.
❖ Since output does not depend
on the time instant, no
feedback is required for its
next output generation.
❖ It is faster and better in
performance as compared to
that of Sequential circuit.
❖ combinational circuit less
complex as compared to
sequential circuit.
❖ Building blocks of
combinational circuit are its
logic gates.
❖ These circuits are ideal for
performing logical operations
(AND, OR, NOT) and
arithmetic operations (adders,
subtractors) due to their
speed and simplicity.
❖ Combinational circuits are
mainly used for arithmetic as
well as Boolean operations.
❖ Encoder, Decoder,
Multiplexer, etc.
DIGITAL INTERVIEW Q&A
Sequential circuit
❖ The output of a sequential
circuit relies on both the
current input and the circuit's
previous state. This previous
state is essentially stored
information from past inputs.
❖ The output relies on its
previous feedback so output
of previous input is being
transferred as feedback used
with input for next output
generation.
❖ Sequential circuits are
comparatively slower and has
low performance.
❖ The implementation of
feedback makes sequential
circuit more complex.
❖ The building blocks of a
sequential circuit are the logic
gates along with flip flops.
❖ Sequential circuits excel in
storing and manipulating
data. They form the building
blocks of memory devices,
registers, and counters. They
are essential for creating
more complex digital
systems.
❖ Flip-flops and Counters.
 HANUMANTH REDDY
LATCH
• Level-triggered
• Responds to changes in the
input signal as soon as they
occur.
• Built from logic gates
• May have an enable signal to
control when it responds to
the input.
• Faster because they react
immediately to input changes
• Often used in asynchronous
circuits for data capture or
holding temporary values.
• Like a light switch. Turns on
(changes state) immediately
when flipped up or down
(change in input).
• Latches are simpler to design
than flip-flops but require
more attention to avoid timing
hazards in circuits.
• Latches are often used for
design flipflops, temporary
storage, and holding signals
during specific operations.
day-2 DIGITAL INTERVIEW Q&A
FLIP FLOP
• Edge-triggered
• Changes state only on a specific
edge (rising or falling) of a clock
signal.
• Can be built from latches with
clock
• Requires a clock signal to
function.
• Generally slower than latches
due to the clock dependency.
• More common in synchronous
circuits where precise timing is
crucial.
• Like a turnstile at a metro
station. Only allows passage
(changes state) when a token
(clock pulse) is inserted.
• Flip-flops can be further
classified into various types like
D flip-flop, JK flip-flop, etc., each
with specific functionalities.
• They are used in memory
elements, counters, registers,
and many other digital
components.
HANUMANTH REDDY day-3
MULTIPLEXER
• A multiplexer is a combinational
circuit that selects one of several
input signals and forwards it to a
single output line based on the
control signals applied to its select
lines.
• The number of select lines[N]
determines the number of input
lines [2N] and one output line,
• The selection of the input line to be
transmitted to the output is
determined by the binary value on
the select lines.
• It implements a Boolean function
where each select line represents a
variable, and the output
corresponds to the selected input.
• Multiplexers output the selected
input signal directly.
• Multiplexers are used in various
applications, including data
routing, data selection, signal
switching, and address decoding in
memory systems and
communication systems.
DIGITAL INTERVIEW Q&A
ENCODER
• An encoder is a combinational circuit
that converts a set of input signals
into a coded output, where each
combination of input signals
corresponds to a unique binary code.
• The number of input lines is [2N]
determines the number [N] output
lines
• When a particular input combination
is present, the corresponding binary
code is generated on the output
lines.
• It essentially compresses the input
information into a more compact
form, reducing the number of output
lines required.
• Encoders output a binary code
representing the active input line(s).
• Encoders are commonly used in
applications such as data
transmission, data compression,
address generation, and control
systems where efficient data
representation is crucial.
 HANUMANTH REDDY
SOP (Sum of Products)
• SOP:- A way to represent a Boolean
expression using minterms (product
terms where all variables are ANDed
together).
• SOP focuses on conditions that make
the output a 1 (minterms),
• SOP uses AND (product) for
minterms and OR (sum) to combine
them.
• SOP expression results in a 1 output
• SOP uses Σ (sigma) for sum
• SOP says: "output is 1 WHEN these
specific conditions (all variables
ANDed) are true."
• In SOP, simplification involves
identifying redundant terms and
removing them to minimize the
expression.
• It directly applies De Morgan's
Theorem.
• X (SOP) = Σ m(1, 3, 6) =
A’.B’.C + A’.B.C + A.B.C’
• SOP: An example of a SOP
expression is
f(A,B,C)=𝐴⋅𝐵+𝐴’⋅𝐶+𝐵⋅𝐶
day-4 DIGITAL INTERVIEW Q&A
POS (Product of Sums)
• POS:- A way to represent a Boolean
expression using maxterms (sum
terms where all variables are ORed
together).
• POS focuses on conditions that
make the output a 0 (maxterms).
• POS uses OR (sum) for maxterms
and AND (product) to combine
them.
• POS results in a 0 output.
• POS uses Π (pi) for product.
• POS says: "output is 0 WHEN any of
these conditions (all variables
ORed) are true."
• In POS, simplification involves
identifying redundant terms and
removing them to minimize the
expression.
• De Morgan's Theorem needs to be
applied before converting
expressions into POS form.
• X (POS) = Π M(0,5,7) =
(A+B+C).(A’+B+C’).(A’+B’+C’)
• POS: An example of a POS
expression is
f(A,B,C)=(𝐴+𝐵)⋅(𝐴’+𝐶)⋅(𝐵+𝐶).
 HANUMANTH REDDY
2’s Complement
▪ Represents positive numbers the
same as unsigned binary. To get a
negative number, take the one's
complement (invert all bits) of the
positive version and add 1.
▪ Sign bit is inherent in the number
itself (0 for positive, 1 for
negative).Only one representation
for zero.
▪ Addition and subtraction are
performed using the same adder
circuit! Negate a number by taking
its two's complement.
▪ Simpler and faster.
▪ More efficient hardware utilization
due to simpler arithmetic
operations.
▪ +5 in binary as 0101
▪ -5 in binary as [0101 –> 2’s =1011
▪ Add 14{1110} and -13= {-1101}
[i] 2’s of -1101 = 0011
[ii] 1110 + 0011 = 1 0001 [drop carry
it’s positive]
[iii] +0001 {+1} [result]
day-5 DIGITAL INTERVIEW Q&A
Signed Magnitude
▪ Splits the number into sign bit (0 for
positive, 1 for negative) and
magnitude (absolute value in binary).
▪ Explicitly uses a sign bit, leading to
two representations for zero (+0 and
-0).
▪ Requires separate circuits for
addition and subtraction, considering
the sign bit during calculations.
▪ Can be more complex.
▪ Needs dedicated circuits for
handling signs, increasing hardware
requirements.
▪ -5 in binary is 1101
▪ 5 in binary is 0101
▪ Add 5 , 3
[i] 5=0101 ; 3 = 0011
[ii] 0101+0011
[iii] 1000 [In Signed Magnitude, the
result is also -1, but here, it doesn't
represent overflow. It's the correct result
of the addition.]
 HANUMANTH REDDY day-6
Ripple Carry Adder
Built from cascading full adders, where the carry
output from one adder becomes the carry input
for the next.
The final sum depends on the ripple effect of
each carry bit being calculated one after another.
This delay increases with the number of bits
being added.
Due to the simpler design, RCAs require less
power compared to CLAs.
Low-power applications, adding small numbers
of bits.
RCA is relatively easier to modify or extend since
each stage is dependent only on the carry-out of
the previous stage.
It is suitable for applications where speed is not
critical or for small adders where the propagation
delay is acceptable.
Advantages – simplicity, less hardware, regular
structure.
Disadvantages – slow propagation, limited
parallelism, high power consumption
DIGITAL INTERVIEW Q&A
Carry Lookahead Adder
Uses additional logic to anticipate carry bits
based on the input bits. This eliminates the
ripple effect, leading to faster addition.
Requires additional circuitry to calculate carry
bits independently, making it more complex
than RCAs.
Due to the additional logic, CLAs consume
more power than RCAs.
High-performance applications, adding large
numbers of bits.
CLA is more complex to modify or extend due
to its parallel carry computation approach,
which involves interdependencies among
multiple stages.
It is ideal for applications requiring high-speed
addition of large numbers of bits.
Si = Pi ⊕ Gi ; C i+1= CiPi + Gi
Gi = Ai.Bi where G is called carry generator
Pi = Ai ⊕ Bi where P is called carry
propagator
Advantages – Fast performance, parallelism,
low power consumption.
Disadvantages – Complexity, area overhead,
lesss modular.
 HANUMANTH REDDY day-7 DIGITAL INTERVIEW Q&A

EDGE-TRIGGERING LEVEL SENSITIVE TRIGGERING

➢ In edge-triggered systems, the input ➢ In level-triggered systems, the output

signal transitions at specific edges of the changes state when the input signal is
clock signal, typically rising edge or at a specified logic level (typically high
falling edge. or low).

➢ The output of the circuit changes state ➢ The output remains in its changed state
only when the specified edge of the as long as the input signal maintains
clock signal occurs, regardless of the that logic level.
duration of the input signal.

➢ It's particularly useful in synchronous ➢ Level triggering is commonly used in

digital systems where changes occur asynchronous circuits where the output
precisely at the rising or falling edge of a needs to follow the input signal
clock signal. continuously.

➢ Edge-triggered flip-flops include D flip- ➢ Latches are often level-triggered,

flops, JK flip-flops, and T flip-flops. including SR latch, D latch, and JK latch.

➢ Edge-triggered systems are less prone to ➢ LEVEL-triggered systems are MORE

glitches compared to level-triggered prone to glitches compared to edge-
systems. triggered systems.

➢ Precise timing, single events ➢ Continuous monitoring

 HANUMANTH REDDY
Synchronous Reset
• In a synchronous reset, the reset signal is
synchronized with the clock signal.
• The reset is applied only at specific clock
edges.
• Synchronous resets are typically
implemented using flip-flops or registers
with the reset signal being gated by the
clock signal.
• It ensures that the reset operation occurs
at a defined point in the clock cycle,
eliminating glitches & timing hazards
associated with asynchronous resets.
• preferred in synchronous digital designs
where timing constraints are critical and
synchronous operation is required.
• synchronous resets are preferred for their
predictability and robustness.
• Applications:
✓ Most synchronous circuits.
✓ State machines
✓ Digital signal processing
✓ Microprocessor & Microcontroller
day-8 DIGITAL INTERVIEW Q&A
Asynchronous Reset
• In an asynchronous reset, the reset signal is
[highest priority] not synchronized with the
clock signal.
• Instead, it can be asserted (set to active
state, usually logic low) at any time,
regardless of the clock state.
• Asynchronous resets are typically
implemented using flip-flops or latches
with dedicated reset inputs.
• Asynchronous resets are simple to
implement but can introduce timing
hazards, as the reset signal can potentially
interfere with the normal operation of the
circuit.
• They are often used when a quick and
immediate reset is required, regardless of
the current state of the clock.
• Asynchronous resets are used when a reset
is needed before the clock is available or
for initializing outputs.
• Applications:
➢ Initializing circuits before the clock is
running (e.g., FPGAs).
➢ Glitch filtering
 HANUMANTH REDDY day-9 DIGITAL INTERVIEW Q&A

S-R flipflop J-K flipflop

• It has two inputs, Set (S) and Reset (R), and
two outputs, Q and Q'. The outputs change
state based on the inputs.
• It can be in one of two stable states: SET
(Q=1, Q'=0) or RESET (Q=0, Q'=1).
• When both inputs are low (0, 0), the
previous state is maintained.
• When S=1 and R=0, the flip-flop sets to 1
(Q=1).
• When S=0 and R=1, the flip-flop resets to
0 (Q=0).
• When both inputs are high (1, 1), it enters
an undefined state or metastable state.
• It has two inputs, J and K, and two outputs, Q
and Q'. It's an extension of the SR flip-flop,
solving the "race" condition.
• It has three inputs: J (set), K (reset), and
clock (C).
• It can be in one of two stable states: SET
(Q=1, Q'=0) or RESET (Q=0, Q'=1).
• When J=K=0, the previous state is
maintained.
• When J=1 and K=0, the flip-flop sets to 1
(Q=1).
• When J=0 and K=1, the flip-flop resets to 0
(Q=0).
• When J=K=1, the flip-flop toggles its state
(Q changes to its complement).
• Operation is synchronous, meaning the
state changes only occur on clock
transitions.

S R Q Q’

0 0 0 1
J K Q(n+1) State
0 1 0 1 0 0 Qn No Change
0 1 0 RESET
1 0 1 0 1 0 1 SET
1 1 Qn’ TOGGLE
1 1 ∞ ∞
Applications: Versatile flip-flop used in counters,
Applications: Used in memory storage, data shift registers, and control circuits due to its ability
transfer, and control circuits where a single bit of to toggle, hold, or complement outputs.
data needs to be stored. Example: Used in frequency dividers, digital
Example: Used in binary counters, shift registers, clocks, and sequence generators.
and frequency dividers.
 HANUMANTH REDDY day-9 DIGITAL INTERVIEW Q&A

D flipflop T flipflop

• It has a single data input (D), a clock input
(CLK), and two outputs, Q and Q'.
• It captures the input and changes its state
only at the rising (or falling) edge of the clock
signal.
• It can be in one of two stable states: SET
(Q=1, Q'=0) or RESET (Q=0, Q'=1).
• When the clock signal transitions, the D
input is transferred to the output.
• It's commonly used in shift registers,
counters, and memory storage.
• It has a single input (T), a clock input (CLK), and
two outputs, Q and Q'.
• It toggles its output state whenever the clock
transitions occur.
• It toggles its output state (Q) whenever T is
high (1) and clock transition occurs.
• When T=0, the flip-flop maintains its
current state.
• When T=1 and clock transitions, the output
toggles (Q changes to its complement).

Clock D Q Q’

↓»0 0 0 1 T Q Q (t+1)

↑»1 0 0 1 0 0 0

↓»0 1 0 1 0 1 1

↑»1 1 1 0 1 0 1

1 1 0
Applications: Commonly used for synchronizing
signals, delaying signals, and as storage
Applications: Used for frequency division, binary
elements in registers and memory units.
counters, and waveform generation.
Example: Used in synchronous circuits for clock
Example: Used in mod-2 counters and frequency
synchronization, in data storage elements such
dividers
as registers and latches.
 HANUMANTH REDDY
Binary code
• Standard way to represent information
using 0s and 1s.
• Each bit position has a weight (1, 2, 4,
8...), so changing a bit can cause a larger
jump in value.
• Simpler to convert between decimal and
binary.
• Binary code is widely used in digital
computation and storage systems where
each digit's positional value matters.
• In binary code, transitioning from one
value to the next might involve multiple bit
changes
• Binary code follows a regular counting
sequence where each bit has a value
based on its position and the base (2).
• Ex:- Binary code of 01101 is 01001
• Advantages:-simplicity, widely used, easy
implementation & conversion.
• Disadvantages:-Glitch prone, sensitivity
to errors
day-10 DIGITAL INTERVIEW Q&A
Gray code
• Gray code, also known as reflected binary
code, is a binary numeral system
• A special type of binary code where adjacent
values differs by only one bit leading to a
unique bit pattern.
•
• Conversion between decimal and gray code
can be slightly more complex
• Useful in situations where glitches or noise
might cause misreading’s during transitions
between binary values.
• Used in rotary encoders, position sensors etc.
to ensure smooth transitions.
• Gray code, transitioning between consecutive
values involves only one-bit change.
• For example, in Gray code, the sequence
from 0 to 7 is: 000, 001, 011, 010, 110, 111,
101, 100. Each adjacent pair of numbers
differs by only one bit.
• Ex:- Gray code of 01001 is 01101
• Advantages:- error resilience, sequential
ordering, smooth transitions.
• Disadvantages:- complexity design,
conversion overhead, less intuitive.
 HANUMANTH REDDY
Synchronous Counter
▪ All flip-flops (circuits that store
binary data) are triggered
simultaneously by the same clock
signal.
▪ Generally faster because all flip-flops
change state at the same time.
▪ Less prone to errors due to the
simultaneous flip-flop updates.
▪ Design can be more complex,
especially for counters with a large
number of flip-flops or custom
counting sequences.
▪ Can be designed for various counting
sequences (up/down, modulo-n).
▪ Also known as parallel counter.
▪ synchronous counters are faster,
more reliable, and flexible, but more
complex.
▪ Synchronous counters have
consistent propagation delays across
all stages since all flip-flops are
triggered simultaneously by the
clock signal. This makes them easier
to predict and analyze in terms of
timing.
▪ Advantages: higher speed,
synchronized operation,
▪ Disadvantages: complex circuit, high
power consumption, limited
scalability.
day-11 DIGITAL INTERVIEW Q&A
Asynchronous Counter
▪ The first flip-flop receives the main
clock, but subsequent flip-flops use the
output of the previous flip-flop as
their clock signal. This creates a
cascading effect.
▪ Slower because each flip-flop waits for
the output of the previous one to change
before it can change its own state. This
creates a delay that accumulates with
more flip-flops.
▪ The delay between flip-flops can cause
glitches or inconsistencies in the
counting sequence, especially at high
speeds.
▪ Typically limited to fixed counting
sequences (up/down).
▪ Also known as ripple counter due to the
cascading effect.
▪ Asynchronous counters are simpler and
easier to design, but slower and more
prone to errors.
▪ Asynchronous counters load new values
sequentially, with each flip-flop updating
its state based on the output of the
previous flip-flop.
▪ Advantages:- simplicity, low power
consumption, scalability.
▪ Disadvantages: timing issues,
propagation delay, complex timing
analysis.
 HANUMANTH REDDY day-12
Johnson counter
• The inverted output (Q') of the last flip-flop is
fed back to the input of the first flip-flop.
• It can count in both directions (up and down)
depending on how the feedback is configured.
• Transitions between states involve toggling
only one bit at a time, resulting in smoother
transitions.
• It requires additional logic gates for feedback
to generate the sequence of states.
• Used in applications requiring bidirectional
counting or for generating non-overlapping
clock signals.
• Generally more complex due to bidirectional
counting capability and additional feedback
logic.
• It produces a sequence of all 2^n states,
making it more efficient. (Imagine a ripple
effect where all bits change state).
• Johnson counters are also known as twisted
ring counters or creeping counters.
[D0 = Q’]
• Total number of used and unused states in
n-bit Johnson counter: //if n=4
• no. of used states=2n // 2*4 = 8
• number of unused states=2n – 2*n // 24-
2*4 =8.
DIGITAL INTERVIEW Q&A
Ring counter
• The output (Q) of the last flip-flop is fed back
to the input of the first flip-flop.
• : It can only count in one direction (typically in
a loop).
• Transitions involve shifting the entire
sequence by one position, potentially causing
a more abrupt change in the output
• It can be implemented using just flip-flops and
connections between them.
• Commonly used in applications such as shift
register-based delay lines or cyclic redundancy
checks.
• Simpler in design as it operates in a single
direction and doesn't require additional
feedback.
• It circulates a single '0' or '1' bit around the
ring, resulting in 2^(n-1) distinct states for n
flip-flops. (Think of shifting a single bit)
.
• No. of states in Ring counter = No. of flip-flop
used
• 4 states are: [D0 = Q]
1000
0100
0010
0001
 HANUMANTH REDDY day-13
Mealy Machine
❖ Output depends on both the current
state and the current input.
❖ Reacts faster to changes in input
(output can change in the same clock
cycle).
❖ Requires fewer states for equivalent
functionality compared to Moore
machines. (More efficient design in
some cases)
❖ Considered more complex to design
due to the dependence on both state
and input for output.
❖ Asynchronous output generation.
❖ Output is associated with the transition
between states.
❖ Suitable for applications where output
changes need to be responsive to input
changes and where minimizing output
delay is critical.
DIGITAL INTERVIEW Q&A
Moore Machine
❖ Output depends only on the current
state, not the current input.
❖ Output has a one-clock cycle delay
compared to changes in input.
❖ Requires more states for equivalent
functionality compared to Mealy
machines.
❖ Considered easier to design due to the
reliance solely on the current state for
output.
❖ Synchronous output and state
generation.
❖ Output is associated with the state
itself.
❖ Suitable for applications where output
changes are primarily determined by
the current state and where
synchronization with state transitions is
preferred.
 HANUMANTH REDDY day-14
Over lapping
• Permits sequences to partially overlap..
• End of one sequence becomes start of
another: In an overlapping FSM, the final bits
of a detected sequence can be used as the
starting bits for a new sequence. This allows
for continuous detection without requiring a
complete reset between sequences.
• More complex design: Overlapping FSMs tend
to be more intricate as they need to account
for transitions between sequences within the
state transitions themselves.
• Example: Imagine a traffic light controller. The
red-to-green transition can be the start of a
green-to-yellow sequence, creating an
overlap.
• This means that while one transition is in
progress, another one can be initiated.
• This can lead to concurrent transitions and
potentially complex behavior, especially in
systems where multiple inputs can trigger
state changes simultaneously.
DIGITAL INTERVIEW Q&A
Non -Over lapping
• Demands a clear separation between detected
sequences.
• Once a sequence is identified, the FSM needs
to reset and wait for a new, independent
sequence to begin.
• Complete detection required before next
sequence: A non-overlapping FSM requires the
entire first sequence to be detected before it
can begin processing a new sequence. Any
overlap between sequences is considered
irrelevant.
• Simpler design: Non-overlapping FSMs are
generally simpler to design as they focus
solely on identifying individual sequences
without worrying about potential overlaps.
• Example: A vending machine might have a
non-overlapping sequence detector for a
specific coin combination. It wouldn't care if
the coin sequence is interrupted by other
denominations.
• This ensures that only one transition occurs at
a time, simplifying the behavior of system and
making it easier to analyze and understand.
• Non-overlapping FSMs are often used in
applications where precise control over state
transitions is required, or where concurrent
transitions could lead to undesirable behavior.
 HANUMANTH REDDY day-15
Clock Glitch
• A temporary fluctuation in the clock
signal. Imagine a brief spike or dip in
the voltage level representing a logical
0 or 1.
• Caused by:
o Issues with the power supply
o Faulty clock driver circuits
o Electromagnetic interference
• Typically very short-lived (nanoseconds
or less)
• May not always cause problems,
especially if the glitch duration is
insignificant compared to the circuit's
timing requirements. But in critical
circuits, even a brief glitch can lead to
unexpected behavior.
• Like a momentary power flicker in your
house. Lights might dim for a split
second, but most devices will be
unaffected.
• Can cause the circuit to misread data or
enter an unexpected state. Imagine a
hiccup in the rhythm that the circuit
relies on to function.
Causes of Clock Glitch:
• Noise
• Poor Circuit Design
• Cross-Talk
• Transition Issues
Effects of Clock Glitch:
• Setup/Hold Time Violations
• Logic Errors
• Data Corruption
DIGITAL INTERVIEW Q&A
Clock Hazard
• A condition within the clock design that
can potentially cause glitches.
• Arises from unequal propagation delays
in different parts of the clock
distribution network.
• Imagine two signals feeding a logic
gate, but one arrives slightly earlier
than the other due to different path
lengths. This can create an ambiguous
output for a short period.
• Not a guaranteed glitch, but creates the
possibility of one if certain input
conditions are met.
• Like having wires of different lengths
going to multiple light switches in a
room. Flipping one switch first might
cause a brief flicker in another bulb
before everything stabilizes.
• Can create a brief glitch on the clock
signal itself, leading to similar problems
as a clock glitch. Think of it as a
weakness in the design that makes the
circuit prone to hiccups.
Causes of Clock Hazards:
• Propagation Delays
• Circuit Design
• Asynchronous Inputs
Effects of Clock Hazards:
• Logic Errors
• Inconsistent Outputs
• Unreliable Performance
 HANUMANTH REDDY day-16
PLA
• Programmable AND and OR Arrays: Both the AND
array and the OR array in a PLA are programmable.
This allows for a high degree of flexibility in the
implementation of logic functions.
• Customizable Logic: Because both arrays are
programmable, PLAs can implement any
combinational logic function with fewer
restrictions, allowing for more complex logic
designs.
• Flexibility: PLAs offer the most flexibility in terms
of logic design, as both the product terms and the
sum terms can be fully customized.
• Potentially Slower: The flexibility comes at the
cost of potentially slower operation because of the
complexity of programmable connections.
• Complex Logic Functions: Used in applications
where complex logic functions are required and
where flexibility is paramount.
• Custom Designs: Ideal for custom digital logic
designs that require unique and varied logic
functions.
• More Complex Design: Designing with PLAs can be
more complex due to the need to program both
the AND and OR arrays, which might require more
design and verification effort.
DIGITAL INTERVIEW Q&A
PAL
• Programmable AND Array, Fixed OR Array: The
AND array is programmable, but the OR array is
fixed. This means that while the number of
product terms can be varied, the way they are
combined is pre-determined by the fixed OR gates.
• Fixed Logic Structure: The fixed OR array limits
the flexibility compared to a PLA but simplifies the
programming and can lead to faster logic
evaluation.
• Predefined OR Gates: The fixed OR array typically
limits the number of output functions that can be
generated directly, potentially requiring additional
logic levels to achieve more complex functions.
• Faster Operation: The fixed OR array can result in
faster operation since it simplifies the logic
evaluation process.
• Less Flexible: While still programmable, PALs offer
less flexibility than PLAs due to the fixed nature of
the OR array, making them suitable for less
complex or more repetitive logic functions.
• Simpler Logic Functions: Used in applications
where the logic functions are relatively simple or
where speed is more critical than flexibility.
• High-Speed Applications: Suitable for high-speed
logic designs where the fixed OR array can
optimize performance.
• Simpler Design: PALs generally offer a simpler
design process because the fixed OR array reduces
the complexity of the programming.
 HANUMANTH REDDY day-17
Setup Time
• Represents the minimum amount of
time the data signal needs to be
stable (at either a high or low
voltage level) before the active
edge of the clock signal arrives.
• Think of it as the data needing to be
prepared and in place for the clock
to register it correctly.
• If the data isn't stable for long
enough before the clock edge
(violating setup time), the data might
be misinterpreted by the circuit.
• Setup time is like the subject
needing to be in position and ready
to smile before the photographer
clicks the shutter.
• Setup time: Data must be stable
before the clock edge.
• Timing: It is checked before the
clock edge (typically the rising or
falling edge) and is a constraint that
ensures the data is valid and can be
correctly sampled by the clock edge.
• Violation Consequence: If setup
time is violated, the flip-flop may not
latch the correct data, leading to
incorrect or indeterminate states
(also known as metastability).
• Setup Time: Affects the maximum
operating frequency of the circuit; it
is a factor in determining the clock
cycle time.
DIGITAL INTERVIEW Q&A
Hold Time
• Represents the minimum amount of
time the data signal needs to remain
stable (at the same voltage level)
after the active edge of the clock
signal has passed.
• Once the clock has captured the
data, the data needs to hold steady
for a minimum duration to ensure
accurate storage.
• If the data changes state too soon
after the clock edge (violating hold
time), the circuit might again
misinterpret the data.
• Hold time is like the subject
needing to hold their smile for a
moment after the shutter clicks to
ensure a clear picture.
• Hold time: Data must be stable
after the clock edge
• Timing: It is checked after the clock
edge and is a constraint that
ensures the data remains valid for a
sufficient duration after the clock
edge.
• Violation consequence: If hold time
is violated, the flip-flop may latch
incorrect data or enter a metastable
state because the data may change
too quickly after the clock edge.
• Hold Time: Typically less critical
than setup time in terms of
frequency, but crucial for data
integrity immediately after the clock
edge.
 HANUMANTH REDDY day-18
RAM
(Random Access Memory)
➢ RAM: Volatile memory. This means
data is temporary and erased once the
computer shuts down. Imagine it as a
whiteboard - you can write on it (store
data) and erase it (lose data) easily.
➢ RAM: Read and write access. CPU can
constantly read from and write data to
RAM as needed during program
execution.
➢ RAM: Much faster than ROM. RAM
allows for rapid data retrieval, essential
for smooth program operation.
➢ RAM: Stores data currently being
used by the CPU. This includes running
programs, opened files, and the
operating system itself.
➢ RAM: Generally, more expensive per
unit of storage than ROM.
➢ RAM acts as your computer's
workspace, constantly changing as you
work
➢ Includes Dynamic RAM (DRAM) and
Static RAM (SRAM). DRAM needs to
be refreshed thousands of times per
second, while SRAM does not but is
more expensive.
➢ Used in desktops, laptops,
smartphones, and other devices for
running applications, operating
systems, and temporary data storage.
DIGITAL INTERVIEW Q&A
ROM
(Read-Only Memory)
➢ ROM: Non-volatile memory. Data
persists even when the power is off.
Think of it like a permanent marker on
the whiteboard - the information stays
there.
➢ ROM: Read-only access. Data can only
be read, not modified by the user.
➢ ROM: Slower access speeds compared
to RAM.
➢ ROM: Stores permanent instructions
needed for the computer to boot up
and function. Examples include BIOS
firmware, which initializes hardware
during startup, and microcode for
device controllers.
➢ ROM: Less expensive than RAM due to
its simpler design.
➢ ROM holds the essential, unchanging
instructions it needs to function.
➢ Includes Programmable ROM (PROM),
Erasable Programmable ROM
(EPROM), Electrically Erasable
Programmable ROM (EEPROM), and
Flash memory. Each type varies in how
and if it can be rewritten.
➢ Used in devices to store the firmware,
such as in microcontrollers, embedded
systems, game consoles, and other
electronic devices where permanent
data storage is necessary.
 HANUMANTH REDDY day-19
Volatile Memory
❖ Memory that requires power to maintain the
stored information. When the power is turned
off, all data is lost.
❖ RAM (Random Access Memory) such as DRAM
(Dynamic RAM) and SRAM (Static RAM).
❖ Data is retained only as long as the device is
powered.
❖ Used for temporary storage that requires fast
access and is often written to and read from,
such as system memory (RAM) in computers.
❖ Generally faster with higher data transfer rates,
making it suitable for tasks that require quick
access to data.
❖ Consumes power continuously to retain data,
leading to higher power consumption.
❖ Usually more expensive per bit of storage due
to higher performance.
❖ Data reliability is high as long as power is
supplied; however, data is lost on power
failure.
❖ Applications:
• DRAM: Used as the main memory in
computers, where the CPU stores data and
instructions for quick access.
• SRAM: Used in cache memory for faster
access speeds compared to DRAM.
❖ Volatile memory is essential for tasks requiring
rapid data access and temporary storage
DIGITAL INTERVIEW Q&A
Non-volatile Memory
❖ Memory that retains stored data even when
the power is turned off.
❖ ROM (Read-Only Memory), Flash memory,
EEPROM (Electrically Erasable Programmable
Read-Only Memory), SSDs (Solid State Drives),
and HDDs (Hard Disk Drives).
❖ Data is retained even after the device is
powered off.
❖ Used for permanent storage where data
persistence is important, such as firmware
storage (ROM), file storage (SSDs, HDDs), and
removable storage (USB drives).
❖ Typically, slower compared to volatile memory,
but advancements like NVMe (Non-Volatile
Memory Express) SSDs are bridging the speed
gap.
❖ Does not require power to retain data, thus
consuming less power when idle.
❖ Generally cheaper per bit of storage, making it
cost-effective for larger storage capacities.
❖ More reliable for long-term storage as it does
not depend on a continuous power supply.
❖ Applications:
• ROM: Stores firmware, such as the BIOS in
computers.
• Flash Memory: Used in USB drives, memory
cards, and SSDs for persistent data
storage.
• EEPROM: Used in small amounts for
storing configuration settings that need to
be updated infrequently.
❖ non-volatile memory is crucial for long-term
data retention and storage without the need
for continuous power.
 HANUMANTH REDDY day-20
SRAM
{Static Random-Access Memory}
 Composed of flip-flop circuits using 4 to
6 transistors per memory cell. It doesn't
require refreshing.
 Faster access times (typically in the
range of a few nanoseconds) due to the
absence of a need for refreshing and
simpler control logic.
 Consumes more power because it uses
multiple transistors per cell and
maintains the state as long as power is
supplied.
 Lower density as it requires more
transistors per memory cell.
 More expensive to produce due to the
higher number of transistors and lower
density.
 Used for cache memory (CPU cache),
register files, and small memory banks
where speed is critical.
 Volatile memory, meaning they lose
their stored data when power is turned
off.
 Simpler interface and control circuitry
since it doesn’t require refreshing.
 Often integrated directly on the same
chip as the CPU (e.g., L1/L2 cache).
 SRAM offers superior speed but at the
cost of being expensive and having
lower density.
 Used in applications where speed is
critical, such as CPU cache memory and
high-performance networking
equipment.
DIGITAL INTERVIEW Q&A
DRAM
{Dynamic Random-Access Memory }
 Composed of a single transistor and a
capacitor per memory cell. The
capacitor stores the bit of data and
requires periodic refreshing.
 Slower access times (typically in the
range of tens of nanoseconds) because
of the need to refresh the capacitors
periodically.
 Consumes less power in standby mode
but more power overall due to the
constant refreshing of memory cells.
 Higher density because it uses fewer
transistors per cell, allowing more
memory cells to fit in the same silicon
area.
 Less expensive due to higher density
and fewer transistors per cell.
 Used for main system memory (RAM) in
computers, where larger capacity is
needed at a lower cost.
 Volatile memory, meaning they lose
their stored data when power is turned
off.
 More complex control circuitry to
handle the refresh cycles.
 Typically found on separate
chips/modules (e.g., DIMMs) and
connected via the memory bus.
 DRAM is slower but cheaper, more
compact, and consumes less power,
making it ideal for main memory
applications.
 Used as the main memory (RAM) in
most computers due to its lower cost
and higher density.
 HANUMANTH REDDY day-21
Clock Domain Crossing
• Deals with the movement of data between
different clock domains in a digital circuit. A
clock domain refers to a group of flip-flops or
latches that share a common clock signal.
• When data needs to be transferred from a
register controlled by one clock to a register
controlled by another clock. This can happen
because of design choices or the inherent
nature of the system.
• In itself, CDC isn't inherently bad. However, if
not handled properly, it can lead to
metastability and other issues like data loss or
glitches in the receiving clock domain.
• Requires techniques like synchronizers
(special circuits) to ensure the data is stable
before it's captured by the receiving flip-flop
in the different clock domain.
• Imagine two teams working independently
(different clock domains). When they need to
exchange information (data transfer), a
designated person (synchronizer) ensures a
smooth handover to avoid confusion.
• Specialized EDA tools are often used to
analyze and verify CDC issues during the
design phase.
DIGITAL INTERVIEW Q&A
Metastability
• Focuses on a specific issue that can arise
during CDC - the possibility of a signal being in
an unstable state for an unpredictable amount
of time.
• Occurs when a signal transition on the data
line happens too close to the clock edge of the
receiving flip-flop. This violates the setup and
hold time requirements of the flip-flop,
leaving it in an indeterminate state (neither a
clear 0 nor 1).
• Can cause the receiving flip-flop to output an
unpredictable value (0 or 1) or take an
abnormally long time to settle. This can lead
to malfunctions in the circuit.
• By itself, metastability can't be entirely
prevented. However, CDC techniques like
synchronizers help to reduce the probability
of its occurrence and its impact on the circuit.
• The designated person might momentarily
fumble with the information (unstable state)
due to bad timing, but they eventually deliver
it correctly (resolves to a stable state).
• Metastability is typically analyzed using timing
analysis tools and simulation to ensure that
the probability of occurrence is minimized.
 HANUMANTH REDDY day-22
Static Hazard
• A static hazard occurs when the output
is supposed to remain at a constant value
(either 0 or 1) but temporarily glitches to the
opposite value before stabilizing back to the
intended value.
o Static1 hazard output is supposed to
stay at 1.
o Static0 hazard output is supposed to
stay at 0.
• Occurs for specific combinations of
inputs due to the presence of redundant terms
in the logic expression. These redundant terms
can cause a momentary change in the output
even when the overall logic function doesn't
require it.
• Behavior: The output incorrectly
transitions from 0 to 1 (static-1 hazard) or 1 to
0 (static-0 hazard) for a short duration before
settling to the correct value.
• Adding redundant logic to ensure all
paths provide the correct output despite
input changes.
• Careful design and optimization of the
circuit to minimize propagation delay
differences.
• Occur when the output is intended to
remain constant but temporarily glitches to
the opposite value (either 0 or 1). They can
be static-1 or static-0 hazards based on
whether the glitch is a brief drop from 1 to 0
or a brief rise from 0 to 1.
DIGITAL INTERVIEW Q&A
Dynamic Hazard
• A dynamic hazard occurs when the
output is supposed to change from one
value to another (e.g., from 0 to 1 or from 1
to 0), but it oscillates (glitches multiple
times) before settling to the final correct
value.
• Dynamic hazards are caused by the
presence of multiple paths with different
delays that affect the output during a
transition. When an input change leads to a
condition where different paths propagate
signals at different times, the output can
oscillate before reaching its final stable
state.
• Behavior: The output exhibits multiple
unintended transitions (0->1->0 or 1->0->1)
during the settling time. This can be
visualized as a series of spikes or dips in the
output voltage.
• Ensuring minimal delay differences
among all paths that influence the output
transition.
• Using faster logic gates and better
synchronization techniques.
• Occur when the output is intended to
change from one value to another but
oscillates multiple times before settling to
the correct value.
 HANUMANTH REDDY
Clock Skew
• Clock skew refers to the difference in timing
between the arrival of clock signals at different
components or locations within a synchronous
system.
• Clock skew is a spatial variation, affecting
different parts of a system at different times.
• Skew typically affects the relative timing
between different clocked components.
• Skew arises mainly due to physical layout and
design issues within the clock distribution
network.
• Causes:
o Variations in the length of the clock
distribution paths.
o Differences in the loading of the clock signal.
o Variations in the propagation delay through
the clock distribution network.
o Process variations and temperature
differences across the chip.
• Mitigation Techniques:-
o Designing balanced clock tree structures.
o Using clock buffers and repeaters to equalize
path delays.
o Employing skew compensation techniques
such as delay lines.
o Implementing synchronous circuits with
skew-tolerant design methodologies.
day-23 DIGITAL INTERVIEW Q&A
Clock Jitter
• Clock jitter refers to the short-term variations in
the timing of clock edges from their ideal
positions. It is essentially a measure of the
instability of the clock signal.
• Clock jitter is a temporal variation, affecting the
consistency of clock edges over time.
• Jitter affects the timing accuracy of the clock
signal itself at a single point.
• Jitter is caused by noise and instability in the
clock generation and propagation process.
• Causes:
o Power supply noise and variations.
o Electromagnetic interference (EMI).
o Thermal noise and other forms of electronic
noise.
o Imperfections in the clock generation
circuitry (e.g., phase-locked loops (PLLs)).
• Mitigation Techniques:-
o Improving power supply filtering and
regulation.
o Shielding sensitive circuits from EMI.
o Using low-jitter clock generation circuits
(e.g., high-quality PLLs).
o Implementing jitter cleaning techniques
such as phase-locked loops or delay-locked
loops (DLLs).
 HANUMANTH REDDY day-24
Synthesis
• Synthesis is the process of transforming a high-level
hardware description (written in an HDL) into a gate-
level representation that can be implemented on a
physical hardware platform, such as an FPGA or an
ASIC.
• The primary purpose of synthesis is to create a
hardware implementation of a design that can be
fabricated or programmed into a physical device.
• Process:
o Parsing: The HDL code is parsed to create an
intermediate representation.
o Optimization: The intermediate representation is
optimized for area, speed, or power consumption.
o Mapping: The optimized design is mapped to the target
technology (e.g., specific FPGA architecture or ASIC
standard cells).
o Place and Route: For FPGA designs, the mapped design
is placed and routed on the target device.
• The output of synthesis is typically a netlist, which is a
description of the logical elements and their
connections in the circuit.
• Optimizes the design for factors like size and speed.
• Examples of synthesis tools include Synopsys Design
Compiler, Xilinx Vivado, and Intel Quartus Prime.
DIGITAL INTERVIEW Q&A
Simulation
• Simulation is the process of verifying the functionality
and timing of a digital design by executing its HDL
description in a software environment.
• The primary purpose of simulation is to validate that
the design behaves as intended before it is synthesized
and implemented in hardware. This includes checking
for logical correctness and timing issues.
• Process:
o Compilation: The HDL code is compiled into a format
that the simulator can execute.
o Execution: The compiled code is executed, and the
design’s behavior is observed over time.
o Verification: The output of the simulation is compared
against expected results to verify correct functionality.
• Types:
o Functional Simulation: Focuses on verifying the logical
correctness of the design without considering timing
constraints.
o Timing Simulation: Includes timing information to
check for issues related to signal propagation delays
and setup/hold times.
• The output of a simulation is typically a waveform or
log file that shows how signals change over time in
response to test inputs.
• It can also include reports that highlight any
mismatches between expected and actual behavior.
• Examples of simulation tools include ModelSim,
Cadence Xcelium, and Synopsys VCS.
 HANUMANTH REDDY day-25
Cache Memory
▪ Cache memory is used to temporarily
store frequently accessed data and
instructions to speed up processing. It
acts as a buffer between the CPU and the
main memory (RAM).
▪ Cache memory is extremely fast, much
faster than both RAM and flash memory.
This high speed is essential for keeping up
with the CPU.
▪ Cache memory is volatile, meaning it loses
its data when the power is turned off.
▪ Cache memory is typically located very
close to the CPU, often on the same chip
or die. This proximity helps in reducing
access time.
▪ Cache memory is relatively small in size
compared to RAM and flash memory,
usually ranging from a few kilobytes (KB)
to several megabytes (MB).
▪ Cache memory is more expensive per
byte compared to both RAM and flash
memory due to its high speed and low
latency characteristics.
▪ cache memory is highly durable in terms
of operational write cycles and longevity
under normal operating conditions but
requires effective thermal management
to ensure longevity.
▪ There are different levels of cache
memory (L1, L2, L3) with L1 being the
smallest and fastest, and L3 being larger
and slower compared to L1 and L2 but still
faster than main memory.
DIGITAL INTERVIEW Q&A
Flash Memory
▪ Flash memory is used for long-term data
storage. It is non-volatile, meaning it
retains data even when the power is
turned off. Common uses include solid-
state drives (SSDs), USB flash drives, and
memory cards.
▪ Flash memory is slower than cache
memory and RAM but faster than
traditional mechanical hard drives
(HDDs).
▪ Flash memory is non-volatile, meaning it
retains data without needing a constant
power supply.
▪ Flash memory is typically used in storage
devices that can be internal or external
to the computer. It is not directly
connected to the CPU.
▪ Flash memory can store large amounts of
data, ranging from gigabytes (GB) to
terabytes (TB).
▪ Flash memory is cheaper per byte than
cache memory but more expensive than
traditional HDDs.
▪ Flash memory has a limited number of
write/erase cycles, meaning it can wear
out after a certain amount of use.
However, modern flash memory devices
use wear-leveling algorithms to extend
their lifespan.
▪ Flash memory comes in various forms
such as NAND and NOR. NAND flash is
commonly used in SSDs and memory
cards, while NOR flash is used in devices
requiring fast read operations and
reliability.