1290 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 50, NO.

6, DECEMBER 2003

A Simple AC–DC PWM Full-Bridge Converter With

Integrated Power-Factor Correction
Gerry Moschopoulos, Member, IEEE

Abstract—A simple ac–dc pulsewidth-modulation (PWM)

converter that can perform isolated dc–dc conversion while
shaping the input current to improve power factor is proposed in
this paper. The converter is almost the same as a standard PWM
full-bridge converter with a diode rectifier/LC low-pass filter
input except for some slight modifications. The converter topology
is, therefore, very simple, as is the method of control used to
achieve both power-factor correction and dc–dc conversion. In the
paper, the operation of the converter is explained and analyzed,
and the converter’s steady-state characteristics are discussed. A
design procedure for the selection of components is presented,
and then demonstrated with an example. The feasibility of the
converter, and its ability to meet EN61000-3-2 Class D standards
for electrical equipment is shown with results obtained from an
experimental prototype.
Index Terms—AC–DC converter, EN 61000-3-2 specification,
power-factor correction, rectifier, single-stage converter.
Fig. 1. Two-stage ac–dc PWM converter with diode rectifier/LC filter front
end.

I. INTRODUCTION
stage converter are increased because an additional switching
W ITH THE rapid rise in the use of electrical equipment
in recent years (i.e., computers, telecommunications
systems, consumer electronics, etc.), power converter manufac-
converter must be implemented.
Converters that integrate the PFC and dc–dc conversion
functions in a single switching converter have, therefore, been
turers are being pressured by regulatory agencies to implement
proposed [2]–[13]. This results in cost savings due to the
some form of power-factor correction (PFC) in their products.
elimination of the boost converter switch and the controller
High power factor and low input current harmonics are more
used to control its operation. Most of these converters are
and more becoming mandatory performance criteria for power
low-power single-switch forward converters where the switch
converters so that agency standards such as EN61000-3-2
is simultaneously used as a boost converter and as a forward
[1] can be satisfied. Although it is possible to satisfy these
converter switch, and the input current is made discontinuous so
standards by adding passive filter elements to the traditional
that it takes the shape of the sinusoidal input voltage, ensuring a
passive diode rectifier/LC filter input combination (Fig. 1), the
high power factor. There has been much less research performed
resulting converter would be very bulky and heavy due to the
on higher power integrated or single-stage full-bridge-type
size of the low-frequency inductors and capacitors. The passive
converters ( 500 W) and most of it has focused on the
filter approach to PFC is limited to applications where the size
topology shown in Fig. 2, which has the regular four-switch
and weight of the converter are not major concerns.
structure of a full-bridge converter but with an input boost section
For conventional two-stage ac–dc converters with output iso-
directly connected to it. The input current in this converter rises
lation where an ac–dc conversion (rectifying) stage and an iso-
whenever the switches in one or both converter legs are on,
lated dc–dc conversion stage are used, the traditional passive
and falls whenever a pair of diagonally opposed switches is on
diode rectifier/LC filter input combination has been replaced
as energy is transferred from the primary input to the output
with a boost converter in the rectifying stage for most applica-
load. The input current can be shaped so that the input section
tions. The boost converter shapes the input line current so that
operates with a high power factor and dc–dc conversion can be
it is almost sinusoidal, with a harmonic content compliant with
simultaneously performed by turning the converter switches
agency standards, but the cost and complexity of the overall two-
on and off in an appropriate manner.
The topology in Fig. 2, however, has several drawbacks,
Manuscript received February 18, 2002; revised March 28, 2003. Abstract one of these being the lack of an energy storage capacitor
published on the Internet September 17, 2003. This paper was presented in part
at the IEEE International Telecommunications and Energy Conference (INT- across the primary-side dc bus. Such a capacitor cannot be
ELEC 2001), Edinburgh, U.K., Oct. 14–18, 2001. placed in this position since the converter legs are regularly
The author is with the Department of Electrical and Computer Engineering, shorted during normal steady-state converter operation. This
University of Western Ontario, London, ON N6G 1H1 Canada (e-mail:
gmoschopoulos@eng.uwo.ca). results in the appearance of high voltage overshoots and
Digital Object Identifier 10.1109/TIE.2003.819575 ringing across the dc bus whenever a converter switch is turned
0278-0046/03$17.00 © 2003 IEEE
MOSCHOPOULOS: SIMPLE AC–DC PWM FULL-BRIDGE CONVERTER WITH INTEGRATED PFC
Fig. 2. Boost-based current-fed ac–dc PWM integrated full-bridge converter.
off, requiring that higher voltage rated and more expensive
devices be used for the converter switches. It is the transformer
leakage inductance that prevents the primary voltage from
being clamped to the reflected voltage across the secondary
capacitor; reducing this inductance is difficult, especially for
lower output voltages where larger turns ratios are needed.
The voltage overshoots and ringing can be damped by a
lossy snubber, which would reduce converter efficiency, or by
adding resonant components to the converter as was done in
[9] and [11] so that the converter operates as a soft-switched
variable-switching-frequency-controlled resonant converter.
The use of variable-switching-frequency control, however,
makes the design of the magnetic components difficult.
Another drawback with the converter topology shown in
Fig. 2 is that the output voltage has a large low-frequency
120-Hz ripple that restricts the use of this converter to applica-
tions where a tightly regulated output voltage is not required.
This large output voltage ripple is due to the fact that the
converter’s output filter must be purely capacitive since the
topology is a current-fed one based on the boost converter. The
amount of ripple can be reduced by implementing a second
converter in parallel that can be used for ripple cancellation as
was proposed in [10], but adding a second converter makes the
overall converter system just as costly as the standard two-stage
ac–dc converter system and a more complicated method of
control must be used.
The problems of primary dc bus voltage overshoots and
ringing, and large low-frequency output voltage ripple can be
eliminated if a voltage-fed full-bridge converter with output
LC filter is used. Such a converter has an energy-storage
capacitor across its dc bus that can clamp voltage overshoots
and ringing, but the steady-state voltage across this capacitor
becomes excessive ( 600 V) under high-line low-output load
conditions—especially if the input current has been made dis-
continuous to ensure a high input power factor. This is because
the energy-storage capacitor voltage is not solely regulated by
the ac–dc boost PFC stage as it is for a conventional two-stage
converter and therefore cannot purposefully be kept constant.
Auxiliary transformers or auxiliary windings from the main
power transformer can be used to reduce the energy fed into
the capacitor by diverting some of it to the output, as was done
1291
Fig. 3. Proposed voltage-fed PWM full-bridge converter.
for the integrated full-bridge converter proposed in [13], but
the cost and the complexity of the converter was increased and
the dc bus voltage remained excessive.
A pulsewidth-modulation (PWM) full-bridge converter with
integrated PFC that can operate with an input current harmonic
content that meets EN61000-3-2 Class D standards for electrical
equipment without the above-mentioned disadvantages is pro-
posed in this paper. This converter has a very simple topology
and can operate without a large 120-Hz output voltage ripple,
without any dc bus voltage overshoots or ringing, with simple
PWM control, and with a dc bus voltage less than 450 V at a
high input line voltage of 265 V. The dc bus voltage is reduced
without using any additional or auxiliary components, but by
simply designing the converter so that its input current is “semi-
continuous” instead of discontinuous, and by taking advantage
of certain properties inherent to full-bridge converters, but not
to forward converters. Although the input current is semicontin-
uous, its harmonic content still satisfies EN61000-3-2 standards
because the standards are fairly benign requirements that allow
for simpler, less costly approaches to PFC to be used. The Class
D standard is a specified harmonic ratio for converters operating
with input power of 75 W–600 W, while the Class A standard
is an absolute maximum harmonic level requirement even less
strict than Class D.
In the paper, the converter’s operation is explained and an-
alyzed, and its steady-state characteristics are discussed. A de-
sign procedure for the selection of components is presented, and
then demonstrated with an example. The feasibility of the con-
verter, and its ability to meet EN61000-3-2 Class D standards
for electrical equipment is shown with results obtained from an
experimental prototype.
II. CONVERTER OPERATION
The proposed converter (Fig. 3) is almost the same as the con-
ventional PWM full-bridge converter with a diode rectifier, L–C
filter front-end, except that input inductor is connected to
switch instead of energy-storage capacitor . This modi-
fication allows switch to perform the same current-shaping
function as the switch in a boost converter so that there is no
need to add an additional boost converter for PFC; otherwise,
the converter operates in a manner similar to a standard PWM
1292 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 50, NO. 6, DECEMBER 2003

Fig. 4. Equivalent circuits for operating intervals in a half-switching cycle.

full-bridge converter. Energy is transferred from capacitor to

the load whenever a pair of diagonally opposed pair of switches
is on ( and or and ), and none is transferred when-
ever the voltage across the transformer primary is zero and the
converter is in a freewheeling mode of operation.
The converter can operate in any one of several possible
combinations of operating modes. The output section of the
converter can operate in either the discontinuous conduction
mode (DCM) or the continuous conduction mode (CCM). The
input section can operate in the DCM, the CCM, or a semi-
continuous conduction mode (SCM), which is a combination
of DCM and CCM. Regardless of the combination of input
and output section modes, the converter passes through sev-
eral distinct intervals of operation during a single steady-state
switching cycle. These intervals, which can be seen from the
circuit diagrams and waveforms shown in Figs. 4 and 5, are
as follows.
1) Interval 1 : At , switches and are on
and energy is being transferred from capacitor to the
load. While this is happening, input current is rising
as the full rectified input voltage is placed across inductor
.
2) Interval 2 : At , switch is turned off and
capacitors and begin to discharge and charge,
respectively. Both the input current and the transformer
Fig. 5. Typical converter waveforms.
primary current do the charging and discharging of these
capacitors.
3) Interval 3 : At , the converter enters a transfer to the load. The input current flows through the
freewheeling mode of operation and there is no energy body diode of into capacitor while the transformer
MOSCHOPOULOS: SIMPLE AC–DC PWM FULL-BRIDGE CONVERTER WITH INTEGRATED PFC 1293

III. STEADY-STATE ANALYSIS

The key parameter that must be derived from an analysis of
any integrated converter is the storage-capacitor voltage ,
because it is only then that other parameters such as input
current can be determined. Unlike a conventional two-stage
converter, is not solely regulated by the ac–dc boost PFC
stage and cannot be purposefully kept constant. This voltage
can be derived by noting that an energy equilibrium must exist
for storage-capacitor when the converter is in steady-state
operation. The energy pumped into the capacitor from the
input section must be equal to the energy that provides to
the output, so that the net dc current flowing in and out of
must be zero during a half-line cycle. , however, cannot be
determined by an equation with a closed-form solution, due to
the various possible combinations of input and output modes
of operation, but must instead be determined using a computer
program.
Fig. 6. Gating signals. If it is assumed that the converter has ideal semiconductors,
and an ideal transformer with no leakage inductance and negli-
gible magnetizing current, then for an operating point with given
primary current is circulating through switch . This in- input voltage , output voltage , switching frequency ,
terval is bypassed if capacitors and cannot be input inductor , output inductor , transformer turns ratio
fully discharged and charged, respectively. , and output current can be determined
4) Interval 4 : At , switch is turned on and as follows:
the converter continues to operate as it did during Interval 1) Assume a duty cycle as an initial “guess” (i.e.,
3. ).
5) Interval 5 : At , switch is turned off 2) Assume that the output current is continuous; then, use
and capacitors and are charged and discharged, (1) to find
respectively, by the transformer primary current.
6) Interval 6 : Current will begin to flow through (1)
the body diode of at . This interval is bypassed 3) With this value of , verify that the output current is
if capacitors and cannot be fully charged and continuous by seeing that the peak output current ripple
discharged, respectively. does not exceed the average current
7) Interval 7 ): At , switch is turned on.
Both the input and transformer primary currents continue (2)
to flow through switch in the direction indicated in
Fig. 4(g). If this relation is satisfied, then is equal to the value
8) Interval 8 : At , the transformer primary determined in (1). If not, then the output current is dis-
current reverses direction. The direction of the current continuous and must be determined using (3), which
through depends on whether the input current is greater has been derived for DCM
or less than the transformer primary current. If the input
current is discontinuous, then it becomes zero sometime (3)
after . If this is the case, then the equivalent circuit
4) With known, find the average current that flows out
during Interval 7 is the one shown in Fig. 4(i) where the
of capacitor during a half-line cycle using either (4)
converter is shown to act exactly like a standard PWM for CCM or (5) for DCM
full-bridge converter, with no interaction from the input.
If the input current is continuous, then there will be a (4)
net current flow into while and are on.
(5)
The gating signals used for the switches in the proposed con-
verter are different from the phase-shift control technique typ- 5) Determine the average current that is fed from the input
ically used in a PWM full-bridge converter. As can be seen in to during a half-line cycle using (6)
Fig. 6, the gating signals of the switches in a leg of the pro-
posed converter are asymmetrical with the top switch having
a pulse width of (with duty cycle and
switching period) and the bottom switch having a pulse (6)
width of . The gating signals of the switches in a leg where is the peak input current value during a
are complementary with some “dead time” added to avoid the switching cycle cycle k, just before is turned off at
possibility of cross conduction. time .
1294 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 50, NO. 6, DECEMBER 2003

6) If (6) is equal to (4) or (5), then the converter is con-

firmed to be operating under steady-state conditions and
the value of that has been calculated is valid. If not,
then the operating point for which is to be determined
is not a valid operating point, and the procedure must
be repeated for a different value of . If
, then repeat with a smaller value of ; if
then repeat with a larger value
of .

IV. CONVERTER CHARACTERISTICS

The procedure discussed in Section III can be repeated to de-
termine (or any other parameter) for other operating points,
in order for curves to be generated for analysis and design pur-
poses. If this is done, then the following steady-state character-
istics can be determined.
1) When output current and input current are both
discontinuous, remains constant regardless of what
the load is. It is dependent on the ratio of , and on Fig. 7. Graph of dc bus voltage versus output power for V = 100 Vrms and
the transformer turns ratio . V = 48 V.
2) When and are both continuous, again remains
constant regardless of what the load is. It is dependent
mainly on the transformer turns ratio , and slightly on
the ratio of . This is particularly true if and
are deep in CCM.
3) When the output current is continuous, then the voltage
across capacitor will increase when the load de-
creases if is discontinuous.
4) decreases as is increased and the other com-
ponent values are kept constant. This property is most
apparent when has considerable ripple so that a change
in has a greater effect on .
5) decreases as is decreased and the other component
values are kept constant. This property is most apparent Fig. 8. Typical semicontinuous input current waveform with energy-storage/
when has a considerable ripple so that a change in energy-transfer ratio indicated.
has a greater effect on .
6) decreases as transformer turns ratio energy-storage to energy-transfer ratio across the line cycle for
is decreased and the other component values are kept a typical input waveform is shown in Fig. 8. This ratio cannot
constant. exist in a single-switch forward converter unless an additional
Several of these properties can be seen in the graph shown in switch is added to the main converter structure as was proposed
Fig. 7, which is a graph of dc bus or energy-storage voltage in [5]. The auxiliary switch in this case would be used to change
versus output power for various combinations of N, , and . the energy-storage to energy-transfer ratio from a 1 : 1 ratio. No
The dc bus voltage can be reduced by increasing the such switch needs to be added to the proposed converter, there-
value of according to property 4) listed above. Doing so fore minimizing cost and complexity.
can result in the input current being semicontinuous as shown in It should be noted that a reduction in the dc bus voltage means
Fig. 8. is also reduced by taking advantage of an inherent that other measures needed to reduce this voltage can be relaxed.
property in the full-bridge converter structure. It can be seen For example, the dc bus voltage can be reduced by decreasing
from Fig. 3 that input inductor is connected to , which is the value of output inductor , thus making the output current
on once every switching cycle. When is turned off, the energy more discontinuous. The proposed converter can be operated
stored in is transferred to ; this again occurs once every with a higher value of output inductance and its output section
switching cycle. Meanwhile, the full-bridge converter can enter deeper in CCM because of the improvement in the ratio of en-
an energy-transfer mode twice during a switching cycle—once ergy storage to energy transfer intervals in a switching cycle.
when and are on, the other when and are on. It
can be seen from Fig. 4(h) that there is a net current flow out
V. DESIGN PROCEDURE
of capacitor when (transformer primary current)
and and are on, and a net current flow into when A design procedure for the selection of converter components
. This means that it is possible for the ratio of energy based on the analysis and characteristics described in Sections III
storage to energy transfer intervals in a switching cycle to be and IV is presented here. The objectives of the procedure are
1 : 2 instead of always being 1 : 1, as is the case for other inte- to avoid having energy-storage capacitor voltage exceed
grated converters; the result is a lower dc bus voltage . The 450 V when the input voltage is 265 Vrms, to avoid (if possible)
MOSCHOPOULOS: SIMPLE AC–DC PWM FULL-BRIDGE CONVERTER WITH INTEGRATED PFC 1295

having excessive peak input and output currents, and to satisfy

the EN61000-3-2 harmonic current requirements for Class D
electrical equipment. With these criteria in mind, the following
procedure can be used.
1) Find a value for . This can be done with a computer
program to determine , as described in Section III,
for various values of and with fixed values of
. should be the highest value for which valid oper-
ating points exist for the two most extreme line and load
conditions: high line, light load and low line, full load.
should be high enough to reduce the primary current
circulating in the full bridge (and, thus, lower conduc-
tion losses), but low enough to prevent from being
excessive.
2) Once has been determined, generate a graph of
versus for various values of with fixed at Fig. 9. Design curves of dc bus voltage versus input inductance for V =
265 Vrms. For each combination, the highest 265 Vrms.
value of that is encountered across the desired load
range should be plotted. From this graph, potential valid
combinations of (i.e., ones whose highest pos-
sible value of across the load range does not exceed
450 V) can be identified.
3) Examine whether the possible valid combi-
nations identified in the previous step can satisfy the
EN6100-3-2 requirements for Class D equipment by
generating graphs of third, fifth, and seventh input cur-
rent harmonic versus for various values of with
Vrms and maximum load value. The
standard can be satisfied for the higher order harmonics
if it can be satisfied for these harmonics. The individual
harmonics can be determined through computer analysis
of the input line current using a Fourier series. The
graphs should be derived for Vrms to satisfy (a)
the requirements of the EN61000-3-2 specification and
for maximum load value since this is when the
worst-case input current harmonics occur.
4) Repeat step 3) with Vrms as a representative
low-line voltage.
5) Select a combination that will allow the design
criteria to be satisfied.

VI. DESIGN EXAMPLE

In order to illustrate the design procedure presented in Sec-
tion V, an example is given here, where the converter is to be
designed with the following:
input voltage Vrms;
output voltage V; (b)
maximum output power W; Fig. 10. Design curves of 3rd, 5th, and 7th input current harmonics versus
maximum capacitor voltage V; input inductance for (a) V = 230 Vrms and (b) V = 100 Vrms.
switching frequency kHz.
1) It can be determined that a transformer ratio of is exceeding 450 V. Likewise, if is reduced, then so too
a satisfactory value for which valid operating points exist can .
for the two most extreme line and load conditions of high 3) A graph of low-order input current harmonics versus
line, light load and low line, full load. for various values of has been plotted in Fig. 10(a) with
2) A graph of “highest possible” versus for various fixed at 230 Vrms. It can be seen that the individual
values of has been plotted in Fig. 9 with fixed current harmonics increase as is increased, and that
at 265 Vrms. From this graph, it can be seen that as the seventh harmonic can exceed the Class D limits for
is increased, so too must in order to keep from higher values of .
1296
(a)
(b)
Fig. 11. Input voltage and current waveforms operating at P = 500 W.
(a) V = 230 Vrms, scale: V : 200 V/div, I : 4 A/div, t: 5 ms/div. (b) V =
100 Vrms, scale: I : 10 A/div, V : 40 V/div, t: 5 ms/div.
4) A graph of low-order input current harmonics versus
for H has been plotted in Fig. 10(b) with
fixed at 100 Vrms. It can be seen that the individual har-
monics can easily satisfy the Class D limits at this voltage,
and that the value of the output inductance has little effect
on the input current harmonics (and have been approxi-
mated as constant). This is because the input current is
very continuous at low line and full load.
5) H and H have been selected based
on the graphs of Figs. 9 and 10(a). It can be seen that for
these inductances, is approximately 430 V, and that
the EN61000-3-2 Class D limits can be satisfied. Once
values for N, , and , have been determined,
then the remaining components can be designed using
standard procedures and are, therefore, not shown here.
VII. EXPERIMENTAL RESULTS
The feasibility of the converter was verified with results ob-
tained from an experimental prototype with H,
H, and transformer turns ratio . be seen from Fig. 13(c) that a maximum converter efficiency
Fig. 11(a) and (b) shows the input current waveforms when
the converter is operating with W and with
230 and 100 Vrms, respectively. Fig. 12(a) and (b) shows the
worst case input current harmonic content for 100 and
230 Vrms at W. It can be seen that, in both cases,
the EN61000-3-2 standard for Class D electrical equipment is
satisfied.
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 50, NO. 6, DECEMBER 2003
(a)
(b)
Fig. 12. Input current harmonic content at output power P = 500 W for
(a) V = 230 Vrms and (b) V = 100 Vrms.
Fig. 13(a)–(c) shows graphs of dc bus voltage , input
power factor, and converter efficiency versus load for various
values of , ranging from 100 to 230 Vrms (which was the
maximum available input voltage). From Fig. 13(a), it can be
seen that the dc bus voltage can be kept below 450 V when the
input line is high and that the voltage will vary with varying
input voltage. It can also be seen that the voltage is relatively
constant with varying load for a fixed input voltage, which
is a property not commonly seen in many integrated forward
converters since these converters are normally operated with
both input and output sections in DCM, whereas the proposed
converter operates with various input–output combinations of
DCM, CCM, and SCM. It can be seen from Fig. 13(b) that the
input power factor can range from 0.85 to 0.95, and that the
input power factor for light load tends to be greater for low-line
conditions when the input current is very discontinuous and the
ratio of to is high and worse for heavy-load low-line
conditions when the input current is the most continuous. It can
of approximately 85% can be achieved, that efficiency for
light loads is greatest at low-line conditions when there is little
current (therefore, few current-related losses) and the dc bus
voltage is relatively low (therefore, fewer switching losses),
and that efficiency for heavy loads is greatest at high-line
conditions where there are relatively fewer current-related
losses as compared to lower line conditions.
MOSCHOPOULOS: SIMPLE AC–DC PWM FULL-BRIDGE CONVERTER WITH INTEGRATED PFC
(a)
(b)
(c)
Fig. 13. (a) Experimental dc bus voltage versus output power. (b)
Experimental input power factor versus output power. (c) Experimental
efficiency versus output power.
VIII. CONCLUSION
A PWM full-bridge converter that simultaneously performs
input PFC and dc–dc conversion was presented in this paper.
The converter has a very simple topology as it is almost the
same as a standard PWM full bridge with a diode rectifier/LC
filter front end. In the paper, the operation of the converter was
1297
explained, and a method of analysis by which characteristic
and design curves could be derived by means of a computer
program was shown. The converter’s steady-state characteris-
tics were discussed, and a design procedure for the selection of
components was presented, and then demonstrated with an ex-
ample. The feasibility of the converter, and its ability to meet
EN61000-3-2 Class D standards for electrical equipment while
maintaining a dc bus voltage of less than 450 V, an input power
factor ranging from 0.85 to 0.95, and a maximum efficiency of
approximately 85% was shown with results obtained from an
experimental prototype. The converter was able to achieve these
results with its input section operating in a semicontinuous cur-
rent conduction mode of operation while its output section was
operating in a continuous current conduction mode at heavier
loads.
REFERENCES
[1] Electromagnetic Compatibility—Part 3: Limits—Section 2: Limits for
Harmonic Current Emissions (Equipment Input Current  16 A per
Phase), IEC/EN 61000-3-2, 1995.
[2] R. Redl and L. Balogh, “Design considerations for single-stage isolated
power-factor-corrected power supplies with fast regulation of the output
voltage,” in Proc. IEEE APEC’95, 1995, pp. 454–458.
[3] F.-S. Tsai, P. Markowski, and E. Whitcomb, “Off-line flyback converter
with input harmonic current correction,” in Proc. IEEE INTELEC’96,
1996, pp. 120–124.
[4] M. Daniele, P. Jain, and G. Joos, “A single stage power factor corrected
ac/dc converter,” in Proc. IEEE INTELEC’96, 1996, pp. 256–262.
[5] Z. Jindong, F. C. Lee, and M. M. Jovanovic, “An improved CCM single-
stage PFC converter with a low-frequency auxiliary switch,” in Proc.
IEEE APEC’99, 1999, pp. 77–83.
[6] S. Korotov, R. Miftakhutdinov, A. Nemchinov, and S. Fraidlin, “Asym-
metrical half-bridge in a single stage PFC AC/DC converter,” in Proc.
IEEE APEC’97, 1997, pp. 484–488.
[7] L. Huber and M. M. Jovanovic, “Single-stage, single-switch input-cur-
rent-shaping technique with fast-output-voltage regulation,” IEEE
Trans. Power Electron., vol. 13, pp. 476–486, May 1998.
[8] C. Qiao and K. M. Smedley, “A topology survey of single-stage power
factor corrector with a boost type input-current shaper,” in Proc. IEEE
APEC’00, 2000, pp. 460–467.
[9] R. Liu, C. Q. Lee, and I. Bataresh, “A unified approach to the design
of resonant power factor correction circuits,” in Proc. IEEE PESC’92,
1992, pp. 181–188.
[10] Y. Jiang and F. C. Lee, “Single-stage single-phase parallel power factor
correction scheme,” in Proc. IEEE PESC’94, 1994, pp. 1145–1151.
[11] H. Benqassmi, J.-P. Ferrieux, and J. Barbaroux, “Current source resonant
converter in power factor correction,” in Proc. IEEE PESC’97, 1997, pp.
378–384.
[12] J.-G. Cho, J.-W. Baek, D. I. Song, and G.-H. Rim, “A single stage zero-
voltage switched PWM full-bridge converter with power factor correc-
tion,” in Proc. IEEE APEC’97, 1997, pp. 471–476.
[13] P. K. Jain, J. R. Espinoza, and N. A. Ismail, “A single-stage zero-voltage
zero-current-switched full-bridge DC power supply with extended load
power range,” IEEE Trans. Ind. Electron., vol. 46, pp. 261–270, Apr.
1999.
Gerry Moschopoulos (S’89–M’98) received the
B.Eng., M.A.Sc., and Ph.D. degrees from Concordia
University, Montreal, QC, Canada, in 1989, 1992,
and 1997, respectively, all in electrical engineering.
From 1996 to 1998, he was a Design Engineer in
the Advanced Power Systems Division, Nortel Net-
works, Lachine, QC, Canada. From 1998 to 2000, he
was a Postdoctoral Fellow at Concordia University,
where he performed research in the area of power
electronics for telecommunications applications. He
is presently an Assistant Professor at the University
of Western Ontario, London, ON, Canada. His research interests include input
power-factor-correction techniques, high-frequency soft-switching power con-
verters, and power converters for telecommunications applications.
Dr. Moschopoulos is a Member of the Professional Engineers of Ontario,
Canada.