Professional Documents
Culture Documents
vlsi funda all
vlsi funda all
Evolution of logic
complexity in Integrated
Circuit for information
technology services
By Prof. Hitesh Dholakiya
Engineering Funda
Outlines
❖ Evolution in logic complexity in Integrated circuits
❖ Evolution of size in Integrated services
❖ Prominent Information Technology services
❖ Features of Integrated circuits
Evolution in logic complexity in IC’s
• Medium Scale Integration
• Introduced in 1967
MSI • Logic Block per chip 20-200
3.5 –
3.0 –
2.5 –
2.0 –
1.5 –
1.0 –
0.5 –
0.1
0.0 –
1975 1980 1985 1990 1995 2000
Year
Prominent Information Technology services
Video on Demand
Speech Processing
More Opportunities
Less Opportunities for performance
Shorter design for performance improvement
time until improvement
“maturity”
Design Time
Technology Window
Circuit Performance
Time
Technology Window 1 Technology Window 2
VLSI Lecture series
Semi Custom and Full
Custom design
By Prof. Hitesh Dholakiya
Engineering Funda
Full Custom Design Semi Custom Design
1. Complete design, layout, geometry, orientation and 1. Some commonly used design, layout, geometry and
placement of transistor is done designer placement of transistor is interfaced with given demand.
2. Entire design is made without use of any library. 2. Design is completed with the use of multiple library.
3. Development time for design before maturity is more. 3. Development time for design before maturity is less.
4. It has more opportunity for performance improvement 4. It has less opportunity for performance improvement
More Opportunities
Less Opportunities for performance
Shorter design for performance improvement
time until improvement
“maturity”
Design Time
VLSI Lecture series
Semi Custom
By Prof. Hitesh Dholakiya
Engineering Funda
Outlines
❖ Basics of Semicustom design
❖ Classification of Semicustom design
❖ Working of Different Semicustom design
Basics of Semicustom design
❖ This method is used to reduce time to market.
❖ Here, we reduce cost of designing of product.
❖ Performance of semicustom design is lower then full custom design.
❖ Here, in semicustom design, we use readily available block, design,
library or modules.
Classification of Semicustom design
Semicustom Design
HDL Coding
Architecture design
Simulation
Gate level design
Verification
Circuit level design
Meets
No
Yes
Fabrication
Domains of VLSI Design Flow
❖ The design description for a VLSI circuit may be described in forms of
three domains:
1. Behavioral Domain
2. Structural Domain
3. Physical Domain
Y Chart of VLSI Design
Structural Behavior
Domain Domain
System Algorithm
Mask
Cell placement
Modules
placement
Chip Floor plan
Physical Domain
VLSI Lecture series
Importance CAD tool
in VLSI design
By Prof. Hitesh Dholakiya
Engineering Funda
Outlines
❖ Basics of CAD tool in VLSI design
❖ IC design process
❖ IC fabrication process
❖ Important feature of CAD tools in VLSI design
Basics of CAD tools in VLSI design flow
❖ As per Moore’s Law, complexity of IC’s is increasing over the years.
❖ Designing of VLSI circuit with millions of transistor in single IC is
beyond humans brain.
❖ To design VLSI circuit, Computer is required to check layout, circuit
performance, process etc.
❖ Computer are used to aid in the design and optimization process.
❖ VLSI designers are normally given a set of design rules based on
given technology.
IC design process and IC fabrication process
Pattern file
Design Entry
Produce mask
Pattern Generator
Package
Test
Feature of VLSI CAD tools
❖VLSI CAD tools have following tools to meet design features:
1. Physical design (Layout, editor, circuit schematics)
2. Physical verification (DRC (design Rule Check), circuit extractor, plot output,
visual checking)
3. Behavioral verification.
VLSI Lecture series
Comparison of FPGA
and CPLD
By Prof. Hitesh Dholakiya
Engineering Funda
Comparison of FPGA and CPLD
Parameters FPGA CPLD
1. Full Form 1. Field Programable Gate Array 1. Complex Programable Logic Design
2. Architecture 2. Based on “Look up table” 2. Based on “Logic Function”
3. Blocks in Architecture 3. Around 100000 3. Few blocks
4. Architecture tuning 4. Fine Grain Devices 4. Course Grain Devices
5. Architectural Memory 5. SRAM 5. EPROM
6. Complexity 6. High 6. Less
7. Cost 7. High 7. Less
8. Time to ON 8. It takes time to load program 8. Instant ON
9. Volatility of Program 9. Program lost once power is OFF 9. Program stays in CPLD
10. Power Consumption 10. Ideal Power Consumption 10. Weaker Power Consumption
11. Timing Analysis 11. Complex to determine 11. Easier to determine
VLSI Lecture series
On Chip Clock Generation
and Distribution
By Prof. Hitesh Dholakiya
Engineering Funda
Outlines
❖ Basics of Clock in Digital Integrated circuits
❖ Pierce Crystal oscillator
❖ Generation of two non overlapping clocks
❖ Y chart of VLSI Design flow
Basics of Clock in Digital Integrated Circuits
❖ Clock signals are the heartbeats of digital systems. So, stability of
clock signal is highly important.
❖ Ideally, clock signal should have minimum rise time & fall time, it
should have specified duty cycles and zero skew.
Skew
Basics of Clock in Digital Integrated Circuits
❖ Practically, there is noticeable rise time and fall time, Duty cycles can
also vary.
❖ In fact, as much as 10% of a machine cycle time us expanded to
allow realistic clock skews in large computer system.
❖ On chip generated clock can be process dependent and unstable.
❖ As a result, usually separate clock chip which use crystal oscillators
have been used for high performance VLSI chip.
Pierce Crystal Oscillator
❖ In this crystal, series resonant exists.
❖ But internal series resonant
determines the oscillation frequency.
❖ External load at the terminals has
considerable effect on its frequency
and frequency stability.
❖ Higher the series resistance, lower
the resonant frequency.
Generation of two non overlapping clock
❖ Product of two non overlapping clock is zero at all times.
Ck
Ck-1
Ck-2
VLSI Lecture series
Comparison of FPGA,
CPLD, PLC,
Microprocessor,
Microcontroller & DSP
By Prof. Hitesh Dholakiya
Engineering Funda
Parameters FPGA CPLD PLC MP MC DSP
Field Complex
Programmable Digital Signal
1. Full Form Programmable Programmable Microprocessor Microcontroller
Logic Control Processor
Gate Array Logic Device
CPU, IO port, Von Neumann Harvard
2. Architecture Look up table Logical Blocks CPU, IO Port
Memory Mostly architecture
Consumer
Real Time In Industries, at Real Time
Course Tuning Computer Electronics like
3. Applications Applications high power & Applications
Applications Applications Camera,
(Fine Tuning) high Temp. Automobile
(Fine Tuning)
Needs
5. Immunity with noise Very Good Moderate Highest Low Good
additional setup
Less Time (In Less Time (In Less Time (In Less Time (In
It takes time to It takes time to
7. Turn ON time terms of mili terms of Mili terms of Micro terms of Neno
get ON get ON
Sec) Sec) Sec) Sec)
SiO2 Layer
n – Type Substrate
SiO2 Layer
P+ diffusion
Photoresist mask
SiO2 Layer
P well ❖ 1st window is covered by photoresist mask.
❖ Then p type impurities diffused to form p
Epitaxial Layer well.
n – Type Substrate
N+ diffusion
Photoresist mask
SiO2 Layer
❖ 2nd window is covered by photoresist mask.
n well p well
❖ Then n type impurities diffused to form n
well.
Epitaxial Layer
n – Type Substrate
SiO2 Layer
❖ Grow Thin SiO2 layer by thermal oxidation
n well p well for Gate terminal
❖ Grow Polysilicon layer for photolithography
Epitaxial Layer and pattern making.
n – Type Substrate
SiO2 Layer
n well p well
❖ Each SiO2 and Polysilicon to implant Drain
and Source.
Epitaxial Layer
n – Type Substrate
p+ diffusion
Photoresist mask
n – Type Substrate
n+ diffusion
Photoresist mask
n – Type Substrate
S G D S G D
𝒒𝝌 = 𝟎. 𝟗𝟓𝐞𝐕
𝑬𝒄 Conduction Band 𝒒𝝌 = 𝟒. 𝟏𝟓𝐞𝐕
𝒒𝝓𝑴 = 𝟒. 𝟏𝒆𝑽
𝑬𝑭 Fermi Level
𝑬𝒗 valance Band
Energy band Diagram of combined MOS structure
❖ When we combined the three MOS material, fermi level must lined up in
single line and Free space must be continuous.
❖ Because of work function difference in between semiconductor and metal,
there is voltage drop across MOS and banding of bands.
Metal Al Oxide Semiconductor Si
𝑬𝒄 Conduction Band
𝑬𝒊 Intrinsic Level
𝑬𝑭 Fermi Level
𝑬𝑽 Valance Band
VLSI Lecture series
Flat Band Voltage
and Example on Flat
Band Voltage
By Prof. Hitesh Dholakiya
Engineering Funda
Basics of Flat Band Voltage
❖ Individually there is a different work function with Metal, SiO2 and
Substrate.
❖ When we combine three layers, Because of work function difference
between metal and semiconductor, voltage drop occurs across the
MOS structure.
❖ Part of this voltage appears across SiO2 layer and rest across the
silicon surface.
❖ This results into banding of energy bands.
❖ So, to get energy band without any banding, voltage required is
referred as flat band voltage
Consider the MOS structure that consists of a p type doped Si substrate, a SiO2 layer and a metal (Al)
gate. The equilibrium Fermi potential of the doped Si substrate is 𝒒𝝓𝑭𝒑 = 𝟎. 𝟐𝒆𝑽. Using electron
affinity for Si & work function for Al given in figure, Calculate the built in potential difference across
MOS system.
❖ So if voltage corresponding to this is applied externally between gate and substrate then the banding of energy bands
can be compensated and energy bands become flat. So flat band voltage is given by
∴ 𝑽𝑭𝑩 = 𝝓𝒎 − 𝝓𝒔
VLSI Lecture series
MOS under External
Bias
By Prof. Hitesh Dholakiya
Engineering Funda
Basics of External biasing to MOS
❖ Here, we apply external bias to MOS by Gate voltage 𝑉𝐺 and
substrate voltage 𝑉𝐵 .
❖ Here we keep, 𝑉𝐵 = 0 (constant) and 𝑉𝐺 as controlling voltage.
❖ Depending on the polarity and magnitude of 𝑉𝐺 , MOS functions in
three different regions.
❑ Accumulation
❑ Depletion
❑ Inversion
Condition 1 : 𝑽𝑮 < 𝟎 and 𝑽𝑩 = 𝟎 Accumulation
Gate G Terminal Metal Al Oxide Semiconductor Si
𝑽𝑮 < 𝟎
𝑽𝑮 Gate Voltage
Metal
𝑬𝒄 Conduction
𝑬𝒐𝒙 Oxide SiO2 𝑬𝒐𝒙 Band
Metal 𝑬𝒄 Conduction
Band
𝑬𝒐𝒙 Oxide SiO2 𝑬𝒐𝒙
Metal 𝑬𝒄 Conduction
Band
𝑬𝒐𝒙 Oxide SiO2 𝑬𝒐𝒙
❖ For Large gate voltage, electrons will make layer at surface of oxide, which is
𝑽𝑩 = 𝟎 opposite to p type substrate, that is called surface inversion.
Substrate Terminal
𝑽𝑩 Substrate Voltage ❖ Below electrons, there will depletion layer.
❖ After some voltage, depletion layer will not increase and electrons will
increase.
VLSI Lecture series
Thickness of depletion
region, Depletion region
charge density and Surface
Inversion in MOS structure
By Prof. Hitesh Dholakiya
Engineering Funda
𝑽𝑮 > 𝟎 (small) and 𝑽𝑩 = 𝟎 Depletion region
❖ Here we will calculate depletion 𝝓𝑺 𝒙𝒅
𝒒𝑵𝑨 𝒙𝒅𝒙
Gate G Terminal width 𝒙𝒅 as a function of surface ∴ න 𝒅𝝓 = න
𝑽𝑮 > 𝟎 𝝓𝑭 𝟎 𝜺𝑺𝒊
𝑽𝑮 Gate Voltage potential 𝝓𝑺 .
❖ Mobile hole charge in a thin 𝒒𝑵𝑨 𝒙𝒅 𝟐
∴ 𝝓𝑺 − 𝝓𝑭 =
Metal horizontal layer parallel to the 𝟐𝜺𝑺𝒊
surface is ❖ So depth of depletion region is
𝑬𝒐𝒙 Oxide SiO2 𝑬𝒐𝒙 𝒅𝑸 = −𝒒𝑵𝑨 𝒅𝒙
𝟐𝜺𝑺𝒊 (𝝓𝑺 − 𝝓𝑭 )
❖ The change in surface potential ∴ 𝒙𝒅 =
Depletion Region 𝒙𝒅 required to displace thin charge 𝒒𝑵𝑨
X dQ by distance 𝒙𝒅 can be ❖ So depletion region charge density
P Type Si Substrate calculated by Poisson equation. is given by
𝒅𝑸 ∴ 𝑸 = −𝒒𝑵𝑨 𝒙𝒅
𝒅𝝓 = −𝒙 .
𝜺𝑺𝒊
∴ 𝑸 = − 𝟐𝒒𝑵𝑨 𝜺𝑺𝒊 (𝝓𝑺 − 𝝓𝑭 )
𝒒𝑵𝑨 𝒙𝒅𝒙
𝑽𝑩 = 𝟎 𝒅𝝓 = ❖ Now if we further increase the
Substrate Terminal 𝜺𝑺𝒊 gate voltage then it will start to
𝑽𝑩 Substrate Voltage ❖ In integration, dx varies from 0 to create surface inversion by
𝒙𝒅 and potential varies from attracting electrons.
Fermi potential 𝝓𝑭 to surface
potential 𝝓𝑺 .
𝑽𝑮 > 𝟎 (Large) and 𝑽𝑩 = 𝟎 Inversion Region
Source S Drain D
Metal
Oxide SiO2
Source n+ Channel Length L Drain n+
P Type Si Substrate
Substrate
Working of n Channel MOSFET in cut off region
Depletion Region
Working of n Channel MOSFET cut off region
Depletion Region
Working of n Channel MOSFET in Linear region
𝑽𝑫 small
Depletion Region
Working of n Channel MOSFET threshold of
linear region
𝑽𝑮𝑺 > 𝑽𝑻𝟎
𝑽𝑫 = 𝑽𝑫𝑺𝑨𝑻
𝑽𝑫 > 𝑽𝑫𝑺𝑨𝑻
𝑽𝑫𝑺 small
Y=0 Y=L
X
Depletion Region
❖ 𝑽𝑮𝑺 > 𝑽𝑻𝑶 and 𝑽𝑮𝑫 > 𝑽𝑻𝑶 , to form a channel.
𝒅𝒚
❖ Threshold voltage 𝑽𝑻𝑶 is assumed to be constant. 𝒅𝑹 = −
𝑾. 𝝁𝒏 . 𝑸𝑰 (𝒀)
❖ Channel Voltage 𝑽𝑪 (𝒚) will change with respect to Y. ❖ Channel current density is assumed to be constant, 𝑰𝑫
𝑽𝑪 𝒀 = 𝟎 = 𝑽𝑺 = 𝟎 current flows from source to drain. So as per Ohm’s law
𝑽𝑪 𝒀 = 𝑳 = 𝑽𝑫𝑺 𝑰𝑫
𝒅𝑽𝑪 = 𝑰𝑫 . 𝒅𝑹 = − . 𝒅𝒚
𝑾. 𝝁𝒏 . 𝑸𝑰 𝒀
❖ Electric field component in Y direction is dominant
compared to X direction, so current flow only confined in ❖ Here, y changes from 0 to L and 𝑽𝑪 changes from 0 to 𝑽𝑫𝑪
Y direction. 𝑳 𝑽𝑫𝑺
∴ න 𝑰𝑫 . 𝒅𝒚 = −𝑾. 𝝁𝒏 න 𝑸𝑰 𝒀 . 𝒅𝑽𝑪
❖ Let 𝑸𝑰 (𝒀) is the charge density in channel, 𝟎 𝟎
𝑽𝑫𝑺
𝑸𝑰 (𝒀) = −𝑪𝑶𝑿 𝑽𝑮𝑺 − 𝑽𝑪 𝒀 − 𝑽𝑻𝑶
∴ 𝑰𝑫 . 𝑳 = 𝑾. 𝝁𝒏 . 𝑪𝑶𝑿 න [𝑽𝑮𝑺 −𝑽𝑪 − 𝑽𝑻𝑶 ] . 𝒅𝑽𝑪
❖ Net voltage at source is (𝑽𝑮𝑺 − 𝑽𝑻𝑶 ) maximum and Net 𝟎
voltage at drain is (𝑽𝑮𝑺 − 𝑽𝑫𝑺 − 𝑽𝑻𝑶 ) minimum. So, for dy 𝝁𝒏 . 𝑪𝑶𝑿 𝑾
∴ 𝑰𝑫 = . 𝟐 𝑽𝑮𝑺 − 𝑽𝑻𝑶 𝑽𝑫𝑺 − 𝑽𝑫𝑺 𝟐
thickness, we will calculation incremental resistance dR. 𝟐 𝑳
❖ Here, if consider, 𝒌′ = 𝝁𝒏 . 𝑪𝑶𝑿 , then drain current will be ❖ So for saturation region drain current 𝑰𝑫 will be
𝒌′ 𝑾 𝒌
∴ 𝑰𝑫 = . 𝟐 𝑽𝑮𝑺 − 𝑽𝑻𝑶 𝑽𝑫𝑺 − 𝑽𝑫𝑺 𝟐 ∴ 𝑰𝑫𝑺𝑨𝑻 = 𝟐 𝑽𝑮𝑺 − 𝑽𝑻𝑶 (𝑽𝑮𝑺 − 𝑽𝑻𝑶 ) − (𝑽𝑮𝑺 − 𝑽𝑻𝑶 )𝟐
𝟐 𝑳 𝟐
𝑾
❖ Here, if consider, 𝐤 = 𝒌′ , then drain current will be 𝒌
𝑳 ∴ 𝑰𝑫𝑺𝑨𝑻 = . (𝑽𝑮𝑺 − 𝑽𝑻𝑶 )𝟐
𝒌 𝟐
∴ 𝑰𝑫 = 𝟐 𝑽𝑮𝑺 − 𝑽𝑻𝑶 𝑽𝑫𝑺 − 𝑽𝑫𝑺 𝟐
𝟐 𝝁𝒏 . 𝑪𝑶𝑿 𝑾
∴ 𝑰𝑫𝑺𝑨𝑻 = . . (𝑽𝑮𝑺 − 𝑽𝑻𝑶 )𝟐
❖ This equation of drain current 𝑰𝑫 is valid in linear region of 𝟐 𝑳
MOSFET.
❖ In saturation region of MOSFET,
∴ 𝑽𝑫𝑺 ≥ 𝑽𝑫𝑺𝑨𝑻 = 𝑽𝑮𝑺 − 𝑽𝑻𝑶
VLSI Lecture series
Channel Length
Modulation of MOSFET
By Prof. Hitesh Dholakiya
Engineering Funda
Outlines
❖ Basics of Channel Length Modulation
❖ Channel length Modulation in MOSFET
❖ Derivation of drain current for channel length modulation
❖ Characteristics of MOSFET with channel length modulation
Basics of Channel length Modulation
❖ In saturation region of working with MOSFET, there is channel length
Modulation with MOSFET.
❖ In that channel length will change with respect to drain voltage of
MOSFET.
❖ Channel length will decrease with respect to increase in drain
voltage in saturation region.
Channel Length Modulation in MOSFET
𝑽𝑫 >
= 𝑽𝑫𝑺𝑨𝑻
small
L’ ∆L L
Inversion Layer (Channel)
Drain Current
with λ ≠ 0
𝑽𝑮𝑺𝟐 with λ=0
with λ ≠ 0
𝑽𝑮𝑺𝟏 with λ=0
Drain Voltage
VLSI Lecture series
Examples on Drain
Current Calculation
By Prof. Hitesh Dholakiya
Engineering Funda
Drain current 𝑰𝑫 is given by
𝝁𝒏 . 𝑪𝑶𝑿 𝑾
∴ 𝑰𝑫 = . 𝟐 𝑽𝑮𝑺 − 𝑽𝑻𝑶 𝑽𝑫𝑺 − 𝑽𝑫𝑺 𝟐
𝟐 𝑳
𝟒𝟎𝟎 × 𝟏𝟎−𝟒 × 𝟖𝟎𝟎 × 𝟏𝟎−𝟔
∴ 𝑰𝑫 = × 𝟏. 𝟓 × 𝟐 𝟏. 𝟖 − 𝟏 𝟏 − 𝟏𝟐
𝟐
∴ 𝑰𝑫 = 𝟏𝟒. 𝟒 × 𝟏𝟎−𝟔 𝑨
∴ 𝑰𝑫 = 𝟏𝟒. 𝟒 𝝁𝑨
Example 2 : For an n channel MOS transistor with 𝝁𝒏 = 𝟔𝟎𝟎 𝒄𝒎𝟐 /𝑽𝑺𝒆𝒄, 𝑪𝑶𝑿 =
𝟕 × 𝟏𝟎−𝟖 𝑭/𝒄𝒎𝟐 , 𝑾 = 𝟐𝟎𝝁𝒎, 𝐋 = 𝟐𝝁𝒎 and 𝑽𝑻𝑶 = 𝟏𝑽.
Here biasing voltages for drain, Source and substrate are given by 3V, 0V and 0V,
respectively. For drain current to be 1mA, what should be gate bias voltage?
Drain current 𝑰𝑫 is given by
𝝁𝒏 . 𝑪𝑶𝑿 𝑾 𝒌
∴ 𝑰𝑫 = . 𝟐 𝑽𝑮𝑺 − 𝑽𝑻𝑶 𝑽𝑫𝑺 − 𝑽𝑫𝑺 = . 𝟐 𝑽𝑮𝑺 − 𝑽𝑻𝑶 𝑽𝑫𝑺 − 𝑽𝑫𝑺 𝟐
𝟐
𝟐 𝑳 𝟐
k is given by Drain current 𝑰𝑫 is given by
𝑾 𝒌
∴ 𝒌 = 𝝁𝒏 . 𝑪𝑶𝑿 . ∴ 𝑰𝑫 = . 𝟐 𝑽𝑮 − 𝑽𝑻𝑶 𝑽𝑫 − 𝑽𝑫 𝟐
𝑳 𝟐
−𝟖 −𝟔
𝟕 × 𝟏𝟎 𝟐𝟎 × 𝟏𝟎
∴ 𝒌 = 𝟔𝟎𝟎 × 𝟏𝟎−𝟒 × × 𝟎. 𝟒𝟐
𝟏𝟎 −𝟒 𝟐 × 𝟏𝟎−𝟔 ∴𝟏 = . 𝟐 𝑽𝑮 − 𝟏 𝟑 − 𝟑𝟐
𝟐
∴ 𝒌 = 𝟒. 𝟐 × 𝟏𝟎−𝟒 𝑨/𝑽𝟐
∴ 𝑽𝑮 = 𝟑. 𝟐𝟗 𝑽𝒐𝒍𝒕
∴ 𝒌 = 𝟎. 𝟒𝟐 𝒎𝑨/𝑽𝟐
For pMOSFET to be in Saturation region Part -1 for pMOSFET
∴ 𝑽𝑫𝑺 ≤ 𝑽𝑮𝑺 − 𝑽𝑻𝑶 ∴ (𝟑 − 𝟓) ↔ (𝟎 − 𝟓) − (−𝟏. 𝟓)
∴ −𝟐 ↔ −(𝟑. 𝟓)
∴ −𝟐 > − 𝟑. 𝟓 (so Linear region)
For nMOSFET to be in Saturation region Part -2 for nMOSFET
∴ 𝑽𝑫𝑺 ≥ 𝑽𝑮𝑺 − 𝑽𝑻𝑶 ∴ (𝟑 − 𝟎) ↔ (𝟓 − 𝟎) − (𝟏. 𝟓)
∴ 𝟑 ↔ (𝟑. 𝟓)
∴ 𝟑 < 𝟑. 𝟓 (so Linear region)
VLSI Lecture series
Substrate Bias Effect
in MOSFET
By Prof. Hitesh Dholakiya
Engineering Funda
Outlines
❖ Basics of Substrate Bias Effect in MOSFET
❖ Substrate Bias Effect with MOSFET characteristics
❖ Threshold voltage under substrate bias voltage
❖ Drain Current under substrate bias voltage
Basics of Substrate Bias Effect
❖ We have studied MOSFET characteristics with substrate bias
voltage 𝑽𝑺𝑩 = 𝟎.
❖ For zero substrate bias voltage, threshold voltage is referred as
𝑽𝑻𝑶 .
❖ In many digital circuit applications, the source potential of nMOS
transistor can be larger values, which results into 𝑽𝑺𝑩 > 𝟎.
❖ In that cases, Threshold voltage will change with respect to 𝑽𝑺𝑩
and that leads to change in drain current, it means drain current is a
function of 𝑽𝑺𝑩 , 𝑽𝑮𝑺 and 𝑽𝑫𝑺 .
𝑰𝑫 = 𝒇(𝑽𝑮𝑺 , 𝑽𝑫𝑺 , 𝑽𝑺𝑩 )
Substrate Bias Effect
Threshold Voltage under substrate bias voltage
❖ Threshold voltage under substrate bias voltage is given by
Linear region
𝑪𝑮𝑩 = 𝟎
𝟏
𝑪𝑮𝑫 = 𝑪𝑶𝑿 𝑾𝑳 + 𝑪𝑶𝑿 𝑾𝑳𝑫
𝟐
𝟏
𝑪𝑮𝑺 = 𝑪𝑶𝑿 𝑾𝑳 + 𝑪𝑶𝑿 𝑾𝑳𝑫
𝟐
Saturation region
𝑪𝑮𝑩 = 𝟎
𝑪𝑮𝑫 = 𝑪𝑶𝑿 𝑾𝑳𝑫
𝟐
𝑪𝑮𝑺 = 𝑪𝑶𝑿 𝑾𝑳 + 𝑪𝑶𝑿 𝑾𝑳𝑫
𝟑
VLSI Lecture series
BIST
(Built In Self Test)
By Prof. Hitesh Dholakiya
Engineering Funda
Outlines
❖ Basics of BIST
❖ Types of BIST
❖ Architecture of BIST
❖ Working of BIST
❖ Issues of designing BIST
❖ Advantages of BIST
❖ Disadvantages of BIST
Basics of BIST
❖ It is technique of designing additional hardware and software into
integrated circuits to allow them to perform self testing.
❖ Aim of BIST technique is to avoid costly use of ATE (Automated Test
Equipment) testing.
❖ As IC’s are getting complex, many blocks are interfaced in IC with
analog and digital ports, in that ATE testing is difficult and costly
service.
❖ BIST is also useful to those blocks of IC which has no direct
connection with external pins.
❖ As IC’s are upgrading, in future conventional testers will no longer be
adequate for the latest and fastest chip.
Types of BIST
❖ Here, I will give basic explanation about two different BIST
1. Logic BIST (LBIST)
2. Memory BIST (MBIST)
Logic BIST (LBIST)
❖ It is designed for testing random logic.
❖ Here we use pseudo random pattern generator to generate random
input pattern.
❖ Multiple Input signature register (MISR) gives response of input
pattern and MISR output indicates defect in the device.
Memory BIST (MBIST)
❖ It is used for testing memories.
❖ It has a circuit that apply, read and compare test patterns.
❖ There are some industry standard for MBIST
❑ The March Algorithm
❑ The checkerboard Algorithm
❑ The varied pattern background Algorithm
Basic Architecture of BIST
Test
Reference
Normal Signature
Input
Output
MUX
CUT
Response Comparator
Hardware (Circuit Under Test) Signature
Compactor
Pattern
generator
Good/Faulty
Issues of BIST designing
❖ how many faults to be covered
❖ how much chip area occupied by BIST
❖ Test Time
❖ Flexibility by software and hardware
Advantages of BIST
❖ It lowers testing cost
❖ Testing is independent on future technology
❖ better fault coverage
❖ shorter test time
❖ Easier customer support
Disadvantages of BIST
❖ Additional circuit (Silicon area) for BIST testing in IC
❖ Additional Pin required for BIST testing in IC
❖ On chip testing may get failed then how to test it.
VLSI Lecture series
Resistive Load
Inverter
By Prof. Hitesh Dholakiya
Engineering Funda
Outlines
❖ Circuit of resistive load inverter
❖ Working of resistive load inverter
❖ Voltage transfer characteristics of resistive load inverter
❖ Parameters of resistive load inverter
Circuit of Resistive load Inverter
𝑽𝑫𝑫
𝑽𝑶𝑼𝑻 = 𝑽𝑫𝑺
𝑽𝑰𝑵 = 𝑽𝑮𝑺
Working of Resistive load Inverter
❖ Due to capacitance of gate oxide layer, gate
current is zero.
❖ So, 𝑰𝑹 = 𝑰𝑫
𝑰𝑹 ❖ So, Output voltage 𝑽𝑶𝑼𝑻 equation will be
∴ 𝑽𝑶𝑼𝑻 = 𝑽𝑫𝑫 − 𝑰𝑹 𝑹
𝑰𝑫 ∴ 𝑽𝑶𝑼𝑻 = 𝑽𝑫𝑫 − 𝑰𝑫 𝑹
❖ If input is lower voltage (logic 0), then
inversion layer will not get formed, So Drain
current will be zero
∴ 𝑽𝑶𝑼𝑻 = 𝑽𝑫𝑫 (logic 1)
❖ If input is higher voltage (Logic 1), then
inversion layer will get formed, So drain
current will increase, which will decrease
output to logic 0.
Working of Resistive load Inverter
❖ So, drain current equation will be
𝑽𝑫𝑫 − 𝑽𝑶𝑼𝑻
∴ 𝑰𝑫 =
𝑹
❖ Here, If MOSFET is there in linear region then 𝑽𝒊𝒏 − 𝑽𝑻𝑶 > 𝑽𝑶𝑼𝑻
❖ Drain current 𝑰𝑫 in linear region will be
𝒌
∴ 𝑰𝑫 = 𝟐 𝑽𝑮𝑺 − 𝑽𝑻𝑶 𝑽𝑫𝑺 − 𝑽𝑫𝑺 𝟐
𝟐
𝒌
∴ 𝑰𝑫 = 𝟐 𝑽𝑰𝑵 − 𝑽𝑻𝑶 𝑽𝑶𝑼𝑻 − 𝑽𝑶𝑼𝑻 𝟐
𝟐
❖ Here, If MOSFET is there in saturation region then 𝑽𝒊𝒏 − 𝑽𝑻𝑶 < 𝑽𝑶𝑼𝑻
𝒌
∴ 𝑰𝑫 = . (𝑽𝑮𝑺 − 𝑽𝑻𝑶 )𝟐
𝟐
𝒌
∴ 𝑰𝑫 = . (𝑽𝑰𝑵 − 𝑽𝑻𝑶 )𝟐
𝟐
Voltage Transfer Characteristics of Resistive load Inverter
𝑽𝑶𝑼𝑻
𝑽𝑶𝑯 𝒅𝑽𝑶𝑼𝑻
= −𝟏
𝒅𝑽𝑰𝑵
𝒅𝑽𝑶𝑼𝑻
= −𝟏
𝒅𝑽𝑰𝑵
𝑽𝑶𝑳
𝑽𝑰𝑵
𝑽𝑰𝑳 𝑽𝑰𝑯 𝑽𝑶𝑯
Calculation of 𝑽𝑶𝑯
❖ Input voltage is less, so drain current is zero,
so per
∴ 𝑽𝑶𝑼𝑻 = 𝑽𝑫𝑫 − 𝑰𝑫 𝑹
∴ 𝑽𝑶𝑼𝑻 = 𝑽𝑫𝑫
Calculation of 𝑽𝑶𝑳
❖ Here, 𝑽𝒊𝒏 − 𝑽𝑻𝑶 > 𝑽𝑶𝑼𝑻 , so MOSFET is there in
linear region, so drain current will be
𝒌
∴ 𝑰𝑫 = 𝟐 𝑽𝑰𝑵 − 𝑽𝑻𝑶 𝑽𝑶𝑼𝑻 − 𝑽𝑶𝑼𝑻 𝟐
𝟐
❖ Drain current is already derived
𝑽𝑫𝑫 − 𝑽𝑶𝑼𝑻
∴ 𝑰𝑫 =
𝑹
❖ From above equation
𝑽𝑫𝑫 − 𝑽𝑶𝑳 𝒌
∴ = 𝟐 𝑽𝑫𝑫 − 𝑽𝑻𝑶 𝑽𝑶𝑳 − 𝑽𝑶𝑳 𝟐
𝑹 𝟐
𝟏 𝟐
∴ 𝑽𝑶𝑳 𝟐 − 𝟐 𝑽𝑫𝑫 − 𝑽𝑻𝑶 + 𝑽𝑶𝑳 + 𝑽 =𝟎
𝒌𝑹 𝒌𝑹 𝑫𝑫
❖ Solution of this equation is
𝟐
𝟏 𝟏 𝟐𝑽𝑫𝑫
∴ 𝑽𝑶𝑳 = 𝑽𝑫𝑫 − 𝑽𝑻𝑶 + − 𝑽𝑫𝑫 − 𝑽𝑻𝑶 + −
𝒌𝑹 𝒌𝑹 𝒌𝑹
Calculation of 𝑽𝑰𝑳
❖ Here, 𝑽𝒊𝒏 − 𝑽𝑻𝑶 < 𝑽𝑶𝑼𝑻 , so MOSFET is there in
saturation region, so drain current will be
𝒌
∴ 𝑰𝑫 = . (𝑽𝑰𝑵 − 𝑽𝑻𝑶 )𝟐
𝟐
❖ Drain current is already derived
𝑽𝑫𝑫 − 𝑽𝑶𝑼𝑻
∴ 𝑰𝑫 =
𝑹
❖ From above equation
𝑽𝑫𝑫 − 𝑽𝑶𝑼𝑻 𝒌
∴ = . (𝑽𝑰𝑵 − 𝑽𝑻𝑶 )𝟐
𝑹 𝟐
❖ If differentiate given equation with respect to 𝑽𝒊𝒏
𝟏 𝒅𝑽𝑶𝑼𝑻
∴− . = 𝒌. 𝑽𝑰𝑵 − 𝑽𝑻𝑶
𝑹 𝒅𝑽𝑰𝑵
𝟏
∴ − . (−𝟏) = 𝒌. 𝑽𝑰𝑳 − 𝑽𝑻𝑶
𝑹
𝟏
∴ 𝑽𝑰𝑳 = 𝑽𝑻𝑶 +
𝒌𝑹
Calculation of 𝑽𝑰𝑯
❖ Here, 𝑽𝒊𝒏 − 𝑽𝑻𝑶 > 𝑽𝑶𝑼𝑻 , so MOSFET is there in
linear region, so drain current will be
𝒌
∴ 𝑰𝑫 = 𝟐 𝑽𝑰𝑵 − 𝑽𝑻𝑶 𝑽𝑶𝑼𝑻 − 𝑽𝑶𝑼𝑻 𝟐
𝟐
❖ Drain current is already derived
𝑽𝑫𝑫 − 𝑽𝑶𝑼𝑻
∴ 𝑰𝑫 =
𝑹
❖ From above equation
𝑽𝑫𝑫 − 𝑽𝑶𝑼𝑻 𝒌
∴ = 𝟐 𝑽𝑰𝑵 − 𝑽𝑻𝑶 𝑽𝑶𝑼𝑻 − 𝑽𝑶𝑼𝑻 𝟐
𝑹 𝟐
❖ If differentiate given equation with respect to 𝑽𝒊𝒏
𝟏 𝒅𝑽𝑶𝑼𝑻 𝒌 𝒅𝑽𝑶𝑼𝑻 𝒅𝑽𝑶𝑼𝑻
∴− . = 𝟐 𝑽𝑰𝑵 − 𝑽𝑻𝑶 − 𝟐𝑽𝑶𝑼𝑻
𝑹 𝒅𝑽𝑰𝑵 𝟐 𝒅𝑽𝑰𝑵 𝒅𝑽𝑰𝑵
𝟏
∴ 𝑽𝑰𝑳 = 𝑽𝑻𝑶 + 𝟐𝑽𝑶𝑼𝑻 −
𝒌𝑹
𝟖 𝑽𝑫𝑫 𝟏
∴ 𝑽𝑰𝑳 = 𝑽𝑻𝑶 + −
𝟑 𝒌𝑹 𝒌𝑹
Average DC Power consumption
❖ Power consumption is voltage into current.
❖ Here duty cycle is 50%, so voltage = 𝑉𝐷𝐷ൗ2
𝑉𝐷𝐷 −𝑉𝑂𝐿
❖ Here current =
𝑅
❖ So average DC power dissipation is given by
𝑽𝑫𝑫 𝑽𝑫𝑫 − 𝑽𝑶𝑳
∴ 𝑷𝑫𝑪 (𝑨𝒗𝒆𝒓𝒂𝒈𝒆) = ×
𝟐 𝑹
VLSI Lecture series
Ion Implantation
and it’s Advantage
over Diffusion
By Prof. Hitesh Dholakiya
Engineering Funda
Ion Implantation
❖ It is alternative to diffusion process in IC fabrication.
❖ Diffusion Process is done at high temperature, but Ion implantation
is done at low temperature.
❖ In Ion Implantation, high energy dopant ions are accelerated, so that
ions can easily penetrate the Si wafer.
❖ The depth of penetration can be increased by increasing accelerating
voltage.
VLSI Lecture series
Faults in Integrated
Circuit
By Prof. Hitesh Dholakiya
Engineering Funda
Outlines
❖ Basics of Faults
❖ Types of Faults
❑ Permanent fault
❑ Non Permanent fault
Basics of Faults in IC
❖ It leads to improper output of IC.
❖ It may give false output in IC or It may reduce speed of IC.
❖ There are basically two types of faults in IC
❑ Permanent Fault
❑ Non Permanent Fault
Permanent Fault
❖ It changes functional behavior permanently.
❖ Mostly it happens due to physical fault.
❖ Examples
❑ Incorrect IC Mask
❑ Wrong Connections in IC’s
❑ PCB heating
Non Permanent Fault
❖ It happens at random moments
❖ It effects system behavior for random time period
❖ It is comparatively difficult to detect.
❖ There are two types
❑ Transient Faults : It is caused by environmental conditions such as humidity,
Pressure, vibrations, α particles etc.
❑ Intermittent Faults : It is caused by non environmental conditions such as
loose connections, Ageing of components etc.
VLSI Lecture series
Photolithography
By Prof. Hitesh Dholakiya
Engineering Funda
Photolithography
❖ It is a process to produce circuit/pattern on the Si Layer.
❖ UV light exposure is used.
❖ Two important steps are there in photolithography
1. Photographic Masking : It contains information which we want to project on
Si wafer.
2. Photographic Etching : It contains pattern information which we wants to
remove from layer.
❑ There are two types of photographic etching
➢ Wet Etching (By Chemical)
➢ Dry Etching (By UV light exposure)
VLSI Lecture series
Stuck at Fault
By Prof. Hitesh Dholakiya
Engineering Funda
Stuck at fault
❖ Any terminal may stuck at logic ‘0’ or Logic ‘1’ is referred as stuck at
fault.
❖ At that terminal, it has no dependency on I/P and O/P.
A B Correct Y Actual Y
❖ Examples
Stuck at ‘1’ 0 0 0 0
❑ Stuck at logic ‘1’
0 1 0 1
A 1 0 0 0
Y
B 1 1 1 1
A B Correct Y Actual Y
❑ Stuck at logic ‘0’ Stuck at ‘0’ 0 0 0 0
A 0 1 0 0
Y 1 0 0 0
B 1 1 1 0