library IEEE;

use IEEE.STD_LOGIC_1164.all;

use IEEE.numeric_std.all;

use IEEE.std_logic_unsigned.all

entity Alto_nivel is

Port ( infrarrojo2 : in STD_LOGIC;

inicio2 : in STD_LOGIC;

reinicio2 : in STD_LOGIC;

data_out2: out STD_LOGIC_VECTOR (5 downto 0);

);

end Alto_nivel;

architecture Behavioral of Alto_nivel is

component RAM

Port ( clk : in STD_LOGIC;

infrarrojo : in STD_LOGIC;

reinicio : in STD_LOGIC;

data_out: out STD_LOGIC_VECTOR (5 downto 0);

data_in: in STD_LOGIC_VECTOR (5 downto 0);

);

end component;

component cronometro

Port ( clk : in STD_LOGIC;

reinicio : in STD_LOGIC;

inicio : in STD_LOGIC;

salida: out STD_LOGIC_VECTOR (5 downto 0);

);

end component;

-- Señales RAM

signal clk_s : STD_LOGIC:= '0';

signal infrarrojo_s : STD_LOGIC:= '0';

signal reinicio_s : STD_LOGIC:= '0';

signal data_out_s : STD_LOGIC_VECTOR (5 downto 0):= (others=> '0');

signal data_in_s : STD_LOGIC_VECTOR (5 downto 0):= (others=> '0');

-- Señales Cronometro

signal inicio_s : STD_LOGIC:= '0';

begin

UO: RAM Port map (

clk => clk_s,

infrarrojo => infrarrojo_s,

reinicio=> reinicio_s,

data_out => data_out_s,

data_in => data_in_s,

);

UO: cronometro Port map (

clk => clk_s,

reinicio=> reinicio_s,

inicio => inicio_s,

salida_in => data_in_s,

);
process begin

wait for 100 ns;

clk_s <= '0';

reinicio_s <= '1';

inicio_s <= '0';

infrarrojo_s <= '0';

wait for 100 ns;

clk_s <= '1';

reinicio_s <= '1';

inicio_s <= '0';

infrarrojo_s <= '0';

wait for 100 ns;

clk_s <= '0';

reinicio_s <= '0';

inicio_s <= '1';

infrarrojo_s <= '0';

wait for 100 ns;

clk_s <= '1';

reinicio_s <= '0';

inicio_s <= '1';

infrarrojo_s <= '0';

wait for 100 ns;

clk_s <= '0';

reinicio_s <= '0';

inicio_s <= '0';

infrarrojo_s <= '0';

wait for 100 ns;

clk_s <= '1';

reinicio_s <= '0';

inicio_s <= '0';

infrarrojo_s <= '0';

wait for 100 ns;

clk_s <= '0';

reinicio_s <= '0';

inicio_s <= '0';

infrarrojo_s <= '1';

wait for 100 ns;

clk_s <= '1';

reinicio_s <= '0';

inicio_s <= '0';

infrarrojo_s <= '1';

wait for 100 ns;

clk_s <= '0';

reinicio_s <= '0';

inicio_s <= '0';

infrarrojo_s <= '0';

wait for 100 ns;

clk_s <= '1';

reinicio_s <= '0';

inicio_s <= '0';

infrarrojo_s <= '0';

wait for 100 ns;

clk_s <= '0';

reinicio_s <= '0';

inicio_s <= '0';

infrarrojo_s <= '0';

wait for 100 ns;

clk_s <= '1';

reinicio_s <= '0';

inicio_s <= '0';

infrarrojo_s <= '1';

wait for 100 ns;

clk_s <= '0';

reinicio_s <= '0';

inicio_s <= '0';

infrarrojo_s <= '1';

wait for 100 ns;

clk_s <= '1';

reinicio_s <= '0';

inicio_s <= '0';

infrarrojo_s <= '0';

wait for 100 ns;

clk_s <= '0';

reinicio_s <= '0';

inicio_s <= '0';

infrarrojo_s <= '0';

wait for 100 ns;

clk_s <= '1';

reinicio_s <= '0';

inicio_s <= '0';

infrarrojo_s <= '1';

wait for 100 ns;

clk_s <= '1';

reinicio_s <= '0';

inicio_s <= '0';

infrarrojo_s <= '1';

wait for 100 ns;

clk_s <= '1';

reinicio_s <= '0';

inicio_s <= '0';

infrarrojo_s <= '0';

wait for 100 ns;

clk_s <= '0';

reinicio_s <= '0';

inicio_s <= '0';

infrarrojo_s <= '0';

wait for 100 ns;

wait;

end process;

end behavioral;