MICROPROCESSOR SYSTEMS

Lesson 4: Fetch–Decode–Execute Cycle

FETCH–DECODE–EXECUTE CYCLE
 a fundamental process that a microprocessor repeatedly performs each time it
runs a program

a.) FETCH
 gets the instruction from memory and brings it to the instruction register

b.) DECODE
 interprets the fetched instruction in the instruction register

c.) EXECUTE
 implements the instruction and processes the data

Figure 3. Fetch–Decode–Execute Diagram

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FETCH–DECODE–EXECUTE PROCESS:
1.) Fetches the instruction byte from the address pointed to by the program counter
(PC) and places it in the instruction register (IR).
2.) Increments the PC by 1.
3.) Interprets the instruction byte in the IR and executes it accordingly.
4.) Repeats the process until it is instructed to stop.

Figure 4. Bog Standard Microprocessor Architecture

DIFFERENT CPU REGISTERS:

1.) Memory Address Register (MAR)
 stores the address being accessed from the memory

2.) Memory Buffer Register (MBR)

 stores the information that is being sent to, or received from, the memory
along the bidirectional data bus

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3.) Memory Data Register (MDR)

 stores the data fetched from the memory

4.) Accumulator (AC)

 stores the data that is being worked on by the ALU
 the key register in the data section of the CPU

5.) Program Counter (PC)

 keeps track of the memory address of the next instruction to be fetched
 holds the address in memory of the next program instruction
 increments after each instruction fetch

6.) Instruction Register (IR)

 holds the current instruction being processed
 facilitates the separation of the operation code (opcode) and operand

 OpCode
 specifies the operation to be performed
 the most significant bits of the instruction
 the genuine instruction part of the instruction that tells the CPU what
to do

 Operand
 data on which the operation is performed
 the least significant bits of the instruction
 specifies the address or register where the data is fetched

7.) Stack Pointer (SP)

 holds the address of a special chunk of main memory used for temporary
storage during program execution

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CPU UNITS:
1.) Arithmetic-Logic Unit (ALU)
 for bit operations on data held in the AC and MBR
 for storing the results of operations
 contains arithmetic adders, logical AND-ers and OR-ers, etc.

2.) Control Unit (CU)

 responsible for the timing and execution of the various register transfers
required to fulfill an instruction held in the IR

3.) Status Register (SR)

 also called flag register
 contains information about the state of the microprocessor

5 DIFFERENT DATA STATUS OR FLAGS IN 8085:

a.) Carry (CY) Flag
b.) Zero (Z) Flag
c.) Sign (S) Flag
d.) Parity (P) Flag
e.) Auxiliary Carry (AC) Flag

D7 D6 D5 D4 D3 D2 D1 D0

S Z X AC X P X CY

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Lesson 5: Computer Language and Computer Architecture

COMPUTER LANGUAGE
 a structured form of communication between a programmer and the
microprocessor

COMPUTER LANGUAGE HIERARCHY:

1.) HIGH-LEVEL LANGUAGE
 made up of English like terms more suitable for human understanding

2.) LOW-LEVEL LANGUAGE

a.) ASSEMBLY LEVEL
 made up of alphanumeric characters called mnemonics

b.) MACHINE LEVEL

 made up of binary codes usually expressed in its shorthand hexadecimal
form

LANGUAGE TRANSLATORS:
1.) ASSEMBLER
 a process or a program designed to convert assembly level language programs
down to machine level

HAND ASSEMBLY
 the manual process of assembly making use of a look up table of one-to-one
correspondence between a mnemonic and its equivalent machine level
equivalent

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2.) COMPILER
 a process or a program designed to convert high-level language programs down
to machine level

COMPUTER ARCHITECTURE
 defines the physical structure by which a microprocessor is built

2 TYPES OF COMPUTER ARCHITECTURES:

1.) VON NEUMAN ARCHITECTURE
 a three-bus architecture that makes use of an address bus, data bus, and
control bus to interconnect the three main parts of a computer

Figure 5. Von Neuman Architecture

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2.) HARVARD ARCHITECTURE

 a four-bus architecture that makes use of an address bus, data bus, control
bus, and a separate bus for instructions to interconnect the three main parts
of a computer

Figure 6. Harvard Architecture

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Lesson 6: Z-80 Microprocessor

FEATURES OF Z-80 MICROPROCESSOR:

 a 40-pin DIP chip developed by Zilog in 1974
 Von-Neuman Architecture
 16/8-bit address bus
 8-bit data bus
 4-pin control bus
 maximum clock frequency of 8 MHz

Figure 7. Z-80 Pin Description

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Z-80 INTERNAL REGISTERS:

 B-L General Purpose Registers
 B’-L’ Alternate Registers
 AC Accumulator
 FR Flag Register
 PC Program Counter
 IR Instruction Register
 SP Stack Pointer
 IX-IY Index Registers

Z-80 CONTROL SIGNALS:

1.) ̅̅̅̅̅̅̅̅̅̅
𝑴𝑬𝑴𝑹 (Memory Read)
 reads data from the memory

2.) ̅̅̅̅̅̅̅̅̅̅̅
𝑴𝑬𝑴𝑾 (Memory Write)
 writes data into the memory

3.) ̅̅̅̅̅̅
𝑰𝑶𝑹 (Input Read)
 accepts data from input devices

̅̅̅̅̅̅̅ (Output Write)

4.) 𝑰𝑶𝑾
 sends data to output devices

*** Z-80 control signals are not directly generated by the microprocessor.

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Z-80 INSTRUCTION GROUPS:

Every microprocessor has its own instruction set for programming. The following are
the instruction groups under which instructions in the Z-80 instruction set are grouped:
 Data Transfer
 Arithmetic
 Logical and Rotate
 Branch
 Stack, I/O, Machine Control
 Exchange, Block Transfer, and Search
 Bit Manipulation

Z-80 ADDRESSING MODE

 define the manner by which data is transferred from one location of the
microcomputer system to another

6 ADDRESSING MODES:

ADDRESSING MODE EXAMPLE OPERATION

a.) DIRECT LDA (1800) 𝐴𝐶 ← (1800)

b.) REGISTER STA B 𝐴𝐶 ← 𝐵

LDA (HL)
c.) REGISTER INDIRECT 𝐴𝐶 ← (1800)
HL = 1800

d.) IMMEDIATE LDA 18 𝐴𝐶 ← 18

e.) RELATIVE JP (PC + 10) 𝑃𝐶 = 𝑃𝐶 + 10

LDA (IX)
f.) INDEXED 𝐴𝐶 ← (1800)
IX = 1800

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Example:
Determine the contents of accumulator, register B, address (1800), and the data bus
after the execution of the following program. Note that all values and addresses are in
hexadecimal form.
Initial Values:
(1800) = 13
B = 14

ADDRESS MNEMONICS MACHINE CODES

8000 LDA (1800) 3A 00 18

8003 STA B 32

8004 ADD B 80

8005 OUT (06) D3 06

8007 RST 7 FF

LDA (1800) STA B ADD B OUT (06) RST 7

PC

IR

AC

Data Bus

Address
Bus

(06)

(1800)

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