`timescale 1ns/1ps

module tb_tea_ctr;

//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
localparam CLK_PERIOD = 10;
localparam NUM_ROUNDS = 32;

//----------------------------------------------------------------
// Register and Wire declarations.
//----------------------------------------------------------------
reg clk;
reg reset_n;
reg encdec;
reg next;
reg [127:0] key;
reg [63:0] nonce;
reg [63:0] block;
wire ready;
wire [63:0] result;

//----------------------------------------------------------------
// Device Under Test.
//----------------------------------------------------------------
tea_ctr dut (
.clk(clk),
.reset_n(reset_n),
.encdec(encdec),
.next(next),
.ready(ready),
.key(key),
.nonce(nonce),
.block(block),
.result(result)
);

//----------------------------------------------------------------
// Clock generation.
//----------------------------------------------------------------
always begin
# (CLK_PERIOD / 2) clk = ~clk;
end

//----------------------------------------------------------------
// Testbench logic.
//----------------------------------------------------------------
initial begin
// Initialize signals.
clk = 0;
reset_n = 0;
encdec = 1; // 1 for encryption
next = 0;
key = 128'h0123456789abcdef0123456789abcdef;
nonce = 64'h0011223344556677;
block = 64'h0123456789abcdef;

// Apply reset.
 # (2 * CLK_PERIOD);
reset_n = 1;

// Wait for reset release.

# (2 * CLK_PERIOD);

// Start encryption
next = 1;
# (CLK_PERIOD);
next = 0;

// Wait for encryption to complete

wait (ready);

// Display the result

$display("Ciphertext: %h", result);

// Start decryption
encdec = 0;
next = 1;
# (CLK_PERIOD);
next = 0;

// Wait for decryption to complete

wait (ready);

// Display the result

$display("Decrypted: %h", result);

// End simulation
$stop;
end

endmodule