EE 5325 – Hardware

Modeling with VHDL

Lecture 1
Class Info. & Introduction

Shankar Balachandran
Center for Integrated Circuits and Systems
Department of Electrical Engineering
University of Texas at Dallas

Goals
ƒ To learn syntax and semantics of VHDL
ƒ To model digital systems at various abstraction
levels using VHDL
ƒ To learn synthesizable subset of VHDL
ƒ To learn tools that support VHDL Simulation and
Synthesis
ƒ To introduce students to ASIC and FPGA design
process

9/15/2003 2

1
 Personnel
ƒ Instructor
Shankar Balachandran
Email : shankars at utdallas dot edu
Office : TBD
Off. Hrs : TBD
ƒ TA
TBD

9/15/2003 3

Reference Text Books

ƒ “VHDL Design Representation and Synthesis”,
J.R. Armstrong and F.G. Gray
ƒ “Advanced ASIC Chip Synthesis: Using Synopsys Design
Compiler, Physical Compiler, and Primetime”,
Himanshu Bhatnagar
ƒ “Digital Systems Design with VHDL and Synthesis - An
Integrated Approach”, Chang
ƒ “The Student’s Guide to VHDL”, P.J. Ashenden
ƒ Class notes and class webpage
http://www.utdallas.edu/~shankars/teaching/ee5325
ƒ Consult the class outline

9/15/2003 4

2
 Requisites
ƒ EE 4320 or equivalent
ƒ Knowledge of some high level programming
language like C or C++
ƒ Debugging experience with some high level
programming language
ƒ Unix platform

9/15/2003 5

Class Policies
ƒ Check UTD rules and regulations.
ƒ All students must have Unix computer accounts
in UTD.
ƒ Synopsys CAD tools will be used for simulation
and synthesis.
ƒ Homework assignments will be given every 3-4
classes.
ƒ Students can discuss problems but copying is
prohibited. Cheating will result in automatic F

9/15/2003 6

3
 Class Policies (contd.)
ƒ Assignments are due in the first 30 minutes of the
class. Late submissions within 1 day get 75%
credit. 0 credit after that.
ƒ Graded assignments can be contested within 10
days.
ƒ Special requests should be made well ahead of
time.
ƒ Regular attendance is recommended and
important for quizzes etc.
ƒ Check the class webpage frequently for
announcements.
9/15/2003 7

Grading Policy
Tentative Policy :

Homework : 30%
Quizzes : 10%
Project : 25%
Exam : 35%

9/15/2003 8

4
 Important Dates
ƒ Exam – Wednesday, Oct 29 2003, 8:30-9:45 p.m.
ƒ Project – Due on Monday, Dec 1 2003, 5:00 p.m.

9/15/2003 9

Design Flow
ƒ The process of converting an “idea” to a “chip” is
called the VLSI Design Process.
ƒ VLSI Design Process involves a sequence of
steps – Flow.
ƒ Tools that enable the design process are called
CAD (Computer Aided Design) tools for VLSI.

9/15/2003 10

5
 Steps in a Typical Design Process
Chip Idea and
Specifications

Create Logical
Design

Verify Logical
Design
(Simulation)

Generate &
Verify Physical
Design

Generate
Manufacturing
Tests

CHIP

9/15/2003 11

Abstraction Hierarchy
ƒ Designers use different abstraction domains for
VLSI design.
ƒ Structural Domain
ƒ Set of primitive components.
ƒ Primitive components are interconnected to form larger
components.
ƒ Behavioral Domain
ƒ Components are defined by their input/output
response.
ƒ The components can themselves be implemented in
many ways.

9/15/2003 12

6
 Gajski’s Chart

9/15/2003 13

Abstraction Levels

SYSTEM
CHIP
REGISTER
GATE
CIRCUIT

SILICON

9/15/2003 14

7
 Gajski Kuhn Chart
System Level
Behavioral Algorithmic Structural
Communicating RT Level
Processes Logic Level Processor
Algorithms CPU
Circuit ALU, Register, Mux
Transformations
Gate, Flip Flop
Boolean Expressions Transistor
Differential Equations

Rectangles

SSI component Standard Cell

Macro Cell

Board, VLSI Component, SOC

Bus, rack
Physical

9/15/2003 15

Silicon Level

9/15/2003 16

8
 Circuit Level
V+
S
G
P
D

Inverter Vin Vout

D
G
N

9/15/2003 17

Gate Level
S
Q

Q
SR Flip Flop R

S Q

R Q

9/15/2003 18

9
 Register Level

REG

MUX REG

CLK A

CLK B

INC

9/15/2003 19

Chip Level

RAM
8
µP 8
Par.
Port
8

USART

Int.
Con.

9/15/2003 20

10
 System Level

IMU

A/B
RADAR
Computer

C/D

9/15/2003 21

Typical Design Track

Behavioral Structural
System English

Chip Algorithmic

Register Data Flow

Logic
Gate

Circuit
Circuit

Layout
Geometrical
Layout
9/15/2003 22

11
 Typical Design Track
Requirements
logic design refinement functional design circuit design synthesis

Structural
Behavioral

circuit design

Fabrication and
Testing

physical design
generation

Final System
physical design

Physical

9/15/2003 23

Representation
ƒ Notice that the typical design track is represented
in two forms.
ƒ Similarly designs themselves can be represented
in multiple ways.
ƒ Pictures
ƒ Text
ƒ Is picture worth a thousand words?

9/15/2003 24

12
 Design Representation Using
Pictures
Specification: Detect inputs
that are identical and in
sequence S0 R

R 0/0 1/0
0/0
X
Z
TWO_CON
CLK S1 S2
1/0

0/1

Block diagram State diagram

9/15/2003 25

As a Timing Diagram …

CLK

9/15/2003 26

13
 As a State Table …
STATE
STATE TABLE ASSIGNMENT

X Code

State 0 1 State y1y0

S0 S1/0 S2/0 S0 00

S1 S1/1 S2/0 S1 01

S2 S1/0 S2/1 S2 11

9/15/2003 27

As a Circuit …
X
Y1
D Q

Q
CLK R
Z
R

I D Q
Y0
R Q

9/15/2003 28

14
 And in VHDL
architecture DATAFLOW of TWO_CON is
signal Y1, Y0: BIT;
begin
STATE: block(( CLK = ‘1’ and not CLK’ STABLE) or R = ‘0’)
begin
Y1 <= guarded ‘0’ when R = ‘0’ else X;
Y0 <= guarded ‘0’ when R = ‘0’ else ‘1’;
end block STATE;
Z <= Y0 and ((not Y1 and not X) or (Y1 and X));
end DATAFLOW;

9/15/2003 29

HDL
ƒ HDL stands for Hardware Description
Language
ƒ Definition : A high level programming language
used to model hardware.
ƒ Hardware Description Languages
ƒ have special hardware related constructs.
ƒ currently model digital systems, and in future can
model analog systems also.
ƒ can be used to build models for simulation, synthesis
and test.
ƒ have been extended to the system design level.

9/15/2003 30

15
 What is VHDL?
ƒ VHSIC Hardware Description Language
ƒ VHSIC – Very High Speed Integrated Circuit Program
ƒ Started by Department of Defense in 1983
ƒ Used as an exchange medium between different contractors.
ƒ Consensus of opinion of many hardware designers.
ƒ Completed in 1985.
ƒ IEEE standardization
ƒ Done in Dec. 1987
ƒ Many changes were incorporated and was released as VHDL 93

9/15/2003 31

Why Use VHDL?

ƒ Allows textual representation of a design.
ƒ High level language similar to C,C++.
ƒ Can be used for Modeling at the
ƒ Gate Level
ƒ Register Level
ƒ Chip Level
ƒ Can be used for many applications at the
ƒ Systems Level
ƒ Circuit Level
ƒ Switch Level
ƒ Design decomposition is simple with VHDL and hence
can manage complexity
ƒ Early validation of designs.
9/15/2003 32

16