fe_fs9000a

Faraday Technology Corp.
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FS9000A 0.25 m Standard Cell Data Book
1.1 General Description

1.1.1 Technology and Features
The FS9000A is a 0.25µm (drawn) standard cell l brary. It is manufactured on the state-of-the-art
0.25µm single Polysilicon and 5 layer metal, p substrate, twin-well CMOS process.
• 0.25µm (drawn) single POLY, 4 or 5-layer metal CMOS process
• 2.5V operating voltage
• Very high density and porosity
• High speed: Tpd = 40 ps/stage (Typ. 2.5V, measured from 101 stages inverter ring)
• Low power: 0.12 µW/Gate/MHz (ND2, Typ. 2.5V, 25oC, fanout=2 standard load)
• All I/O are Programmable
• Programmable input characteristics for pull up, pull down, and Schmitt trigger
• Programmable drive strength outputs from 2mA to 24mA
• Mixed 2.5V, 3.3V I/O interface
• True 3.3V I/O(or 3.3V with 5V tolerant I/O) available in dual(thick) oxide process
• Programmable oscillator pads
• All-layer high density and low power SRAM/ROM blocks available
• Byte write SRAM available
• Megacells available for integration
1.1.2 Targeted Applications

The FS9000A standard cell family is especially tailored for high performance, low power and high
integration user-specific design applications in the high speed Electronic Data Processing,
Computing, Graphics, Telecommunications and portable markets. Complex and rich cells of
FS90A_A library also makes nowadays synthesize tools easier to meet the smaller, faster design
goal. These cells include:
• Various driver strength cell supported
• Rich set of AOI / AO / OAI / OA complex cells
• AND / OR with inverted inputs
• Single output for Flip-Flops and Latches
1.2 Cell Library

The FS9000A standard cell library includes the primitive cell library, the I/O cell library, RAM/ROM
blocks, and Megacell functional blocks.
1.2.1 Fundamental Core Cell Library

The FS9000A standard cell family is supported by an extensive family of internal SSI and MSI
macrocells.
AN/AnxBy ..................................... AND / inverted input
AOI/AO ...……………................. AND into NOR/OR complex gates
BUF/BUFT/BUFB ...................................... Buffers / 3-State
DEC/DEH ...................................... Decoders
DEL ...................................... Delay cells
HA/FA ...................................... Half and Full Adders
INV/INVT/INVB ...................................... Inverting buffers / 3-State
MAO/MOA ...................................... Complex gates
1-1
Faraday Technology Corp. ô
MUX/MXL ...................................... Multiplexers

ND ...................................... NAND gates
NR ...................................... NOR gates
OAI/OA ...................................... OR into NAND/AND complex gates
OR/ORxBy ...................................... OR / inverted input
PAR/CMPE ...................................... Parity Generators / Equal Comparator
PUI/PDI ...................................... Pull Up/Down internal tristate
XNR/XOR ...................................... Exclusive NOR and OR gates
DFF/DBF/DFZ/QDF ...................................... D-type Flip Flops/scan/single output
JKF/JKZ/QJK ...................................... JK Flip Flops/scan/single output
T/QT ...................................... Toggle Flip Flops/single output
DL/DBH/ QDL/QDBH ...................................... Latches/single output
NDL/NRL ...................................... SR Latches
RAM ...................................... RAM bit
Most logic functions are available in more than one drive version. For instance, the 2-input NAND
gate is available as ND2L, ND2, ND2A, ND2P, ND2B, ND2T, and ND2F. The driving capability is
ND2L < ND2 < ND2A < ND2P < ND2B < ND2T < ND2F. The higher drives makes use of the larger
transistor sizes and therefore has shorter delays for high fan-out nets. The lower drives, on the
other hand, will always occupy lower silicon space and lower power consumption.
1.2.2 Megacells
The following megacells are available in softmacro format for user integration, For detail please
consult your local AEs (Application Engineer).
Cell Name Function Description
F8031 8-bit ROMless Micro controller
F8031 Turbo 8-bit ROMless Micro controller
F8042 Keyboard Controller
F8051 8-bit Micro controller with ROM
F82365 PCMCIA Card Interface Controller
F8237 Direct Memory Access Controller
F8254 Programmable Interval Timer
F8255 Programmable Peripheral Interface
F8259 Programmable Interrupt Controller
F8530 HDLC Serial Communication Controller
F1394 IEEE 1394 High Speed Serial Bus function core
F146818 Real Time Clock with 128X8 RAM
F16450/16550 Universal Asynchronous Receiver Transmitter
FAX51 16-bit Micro Controller
FPCI PCI Master/Slave Function Core
FR3000 MIPS R3000 compatible RISC
FUSB Universal Serial Bus Device function core
Table 1-1
1.2.3 Embedded Functional Block Design Considerations

For embedded functional blocks, the user should design the application logic such that the Chip
Select input is normally at the Standby state. The Chip Select input should be asserted prior to the
activation of the embedded blocks.
1-2
Testing embedded functional blocks can be easily accomplished if the user includes parallel
access logic around the blocks. This logic is in the form of simple multiplexers. The inputs to the
blocks can be directly accessed through properly selecting the multiplexers. Likewise, outputs
from the blocks can be directly monitored through properly selecting another set of multiplexers.
The control signals for the multiplexers are most simply done by dedicating one input pin as the
Test pin.
8VHU 8VHU
/RJLF /RJLF
08;
5$0 08; Figure 1-1

08;
7HVW (QDEOH
To minimize timing constraints, it is also recommended that latches be added to the SRAM
outputs. After the necessary parallel direct access logic is included into the design, RAM or ROM
test patterns can be inserted very easily. The user should create a test pattern where the direct
access logic is enabled. RAM and ROM vectors will then be implemented at the factory level.
1.2.4 The Definition of Cell Unit

In the datasheet, "cell unit" is used to represent the complexity of the cells. Actually, it is
proportional to the physical cell size. Another kinds of unit is the "gate count" or "gate equivalent",
which is a structure from which a 2-input NAND gate or a 2-input NOR gate can be built. The
relationship between "cell unit and "gate equivalent" is
“gate equivalent” = “cell unit” / 2.85
The "gate equivalent" is just for design reference.
1.3 I/O Cells

FS9000A library provides several groups of I/O cells, Including :
PAD
&Group A: True 2.5V programmable I/O
&Group B: True 3.3V programmable I/O
&Group C: 3.3V programmable I/O, with 5V tolerance PAD
&Group D: 3.3V PCI I/O(66MHz)
&Group E: 3.3V AGP1X I/O(66MHz) and APG2X I/O(133 MHz) ô
44.1
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&Group F: True 2.5V programmable oscillator 80.1
Note: 1. All of the above I/O cells have two structure for Pad limited Design
Pad Limited Core Limited
(Version A) and Core limited Design (Version B), respectively.
2. I/O cells of group C(5V tolerant) are forbidden if any cells of Group B, D, E are
Figure 1-2
used, for process consideration. The detailed is listed in the following table:
1-3
Group Name
of I/O Cells A B C D E F
Process
2.5V 2.5/3.3V 2.5/5V 2.5/3.3V 2.5/3.3V 2.5V
Name
Forbidden B or
Groups in the D or
Same Chip C C C
E
UAA XAA XFAA XPCIAA XAGP1AA USCIOALA
VA2OTA YA2OTA YFA28TA YPCITA YAPG1TA USCIOAHA
VA2OAA YA2OAA YFA28AA ZPCIATA ZAGP1ATA
Version A
WAA2OTA ZAA2OTA YFA4CTA XAGP2AA
I/O List
WAA2OAA ZAA2OAA YFA4CAA YAGP2TA
ZFA28TA ZAGP2ATA
ZFA28AA ZAGPBIA
ZFA4CTA
ZFA4CAA
UAB XAB XFAB XPCIAB XAGP1AB USCIOALB

VA2OTB YA2OTB YFA28TB YPCITB YAPG1TB USCIOAHB
VA2OAB YA2OAB YFA28AB ZPCIATB ZAGP1ATB
Version B
WAA2OTB ZAA2OTB YFA4CTB XAGP2AB
I/O List
WAA2OAB ZAA2OAB YFA4CAB YAGP2TB
ZFA28TB ZAGP2ATB
ZFA28AB ZAGPBIB
ZFA4CTB
ZFA4CAB
Table 1-2
Note: 2.5V/3.3V and 2.5V/5V processes are dual oxide processes. More mask layers and process steps are needed in dual
oxide process than single oxide process.
1-4
1.3.1 PIOS
1.3.1.1 What is PIOS ?

PIOS(Programmable I/O on Silicon) is a new strategy I/O that allows users to program the I/O
functions even after Silicon. PIOS is programmable such that it can fit various systems. It solves
the problems of variable loading, system variation, inconsistent between vendors, pull up/pull
down, and Schmitt trigger for noise immunity, etc.
1.3.1.2 Why PIOS ?

Benefits for Users
z Program I/O on silicon
z Reduce risk on I/O mismatch
z Time to market
z Optimal configuration for variable systems
1.3.1.3 PIOS in FS9000A Library

z Group A, B, and C I/O cells are PIOS structure with driving capability control in output buffers,
pull up/pull down control and Schmitt trigger control in the input buffers.
z Group D and E I/O cells are PIOS structure with pull up/pull down control in the input buffers.
z Group F I/O cells are PIOS cells for crystal oscillators.
1.3.2 I/O Cell Naming Conventions
1.3.2.1 Naming Rules of Group A, B, and C I/O Cells
Name of Input Cells:
Operating Voltage + Input Function + Conserved Word
where
Operating Conserved
Input Function
Voltage Word
U: 2.5V A : PIOS Input A: Version A

FA : PIOS Input,
X: 3.3V 5V Tolerant B: Version B
1-5
Name of Output Cells:
Operating Min. Max. Slew Conserved

+ Output Function + + + +
Voltage Driving Driving Control Word
where
Operating Min. Max. Conserved
Output Function Slew Control
Voltage Driving Driving Word
V: 2.5V A : 3-State PIOS Output 2: 2mA 8: 8mA A: Slew A: Version A
FA: 3-State PIOS Output, C: 12mA
Y: 3.3V 5V Tolerant
4: 4mA T: Non-slew B: Version B
O: 24mA
Name of Bidirection Cells:
Operating Output Min. Max. Slew Conserved

+ I/O Function + + + + +
Voltage Function Driving Driving Control Word
where
Operating Output Min. Max. Slew Conserved
I/O Function Control Word
Voltage Function Driving Driving
W: 2.5V A : PIOS I/O 2: 2mA 8: 8mA A: Slew A: Version A

A: 3-State
C: 12mA
Z: 3.3V FA:
PIOS I/O, PIOS I/O 4: 4mA T: Non-slew B: Version B
5V Tolerant
O: 24mA
Examples:
UAA : Programmable CMOS input buffer, 2.5V, version A (pad limited).
XAB : Programmable CMOS input buffer, 3.3V, version B (core limited).
XFAB: Programmable CMOS input buffer, 5V tolerant, 3.3V, version B (core limited)
VA2OTB: Programmable 2~24 mA CMOS 3-state output buffer, 2.5V, version B
(core limited).
YA2OAA: Programmable 2~24 mA CMOS output buffer, Slew rate, 3.3V, version A
(pad limited).
YFA28AA: Programmable 2~8 mA CMOS output buffer, Slew rate, 5V tolerant, 3.3V,
version A (pad limited)
ZAA2OAA: Programmable 2~24 mA CMOS bidirection buffer, Slew rate, 3.3V, version A
(pad limited).
WAA2OTB:Programmable 2~24 mA CMOS bidirection buffer, 2.5V, version B (core limited)
ZFA4CTA: Programmable 4~12 mA CMOS bidirection buffer, 5V tolerant, 3.3V, version A
(pad limited).
1-6
1.3.2.2 Naming Rules of Group D (PCI) I/O Cells
where
Operating Voltage Input Function Conserved Word
PCIA:PCI PIOS A: Version A

X: 3.3V
Input B: Version B
Operating Voltage + Output Function + Conserved Word
where
Operating Output
Conserved Word
Voltage Function
PCIT:PCI 3-State A: Version A

Y: 3.3V
Output B: Version B
Operating Voltage + I/O Function + Conserved Word
where
Operating Voltage I/O Function Conserved Word
PCIAT: A: Version A
Z: 3.3V
PCI PIOS I/O B: Version B
Examples:
XPCIAA : Programmable PCI input buffer, 3.3V, version A (pad limited).
XPCIAB : Programmable PCI input buffer, 3.3V, version B (core limited).
YPCITA : PCI 3-state output buffer, 3.3V, version A (pad limited).
YPCITB : PCI 3-state output buffer, 3.3V, version B (core limited).
ZPCIATA: Programmable PCI bidirection buffer, 3.3V, version A (pad limited).
ZPCIATB: Programmable PCI bidirection buffer, 3.3V, version B (core limited).
1-7
1.3.2.3 Naming Rules of Group E (AGP) I/O Cells
where
Operating Voltage Input Function Conserved Word
AGP1:AGP1X PIOS Input A: Version A
X: 3.3V
AGP2:AGP2X PIOS Input B: Version B
Operating Voltage + Output Function + Conserved Word
where
Operating Voltage Output Function Conserved Word
AGP1T:AGP1X 3-State output A: Version A

Y: 3.3V
AGP2T:AGP2X 3-State output B: Version B
Operating Voltage + I/O Function + Conserved Word
where
Operating Voltage I/O Function Conserved Word

AGP1AT:AGP1X PIOS I/O A: Version A
Z: 3.3V
AGP2AT:AGP2X PIOS I/O B: Version B
Name of Bias Cells:
Operating Voltage + Function + Conserved Word
where
Operating Voltage Function Conserved Word
A: Version A
Z: 3.3V AGPBI:AGP 2X Bias Circuit
B: Version B
1-8
Examples:
XAGP1AA : Programmable AGP 1X input buffer, 3.3V, version A (pad limited).

XAGP2AB : Programmable AGP 2X input buffer, 3.3V, version B (core limited).
YAGP1TB : AGP 1X output buffer, 3.3V, version B (core limited).
YAGP2TA : AGP 2X output buffer, 3.3V, version A (pad limited).
ZAGP1ATA: Programmable AGP 1X bidirection buffer, 3.3V, version A (pad limited).
ZAGP2ATB: Programmable AGP 2X bidirection buffer, 3.3V, version B (core limited).
ZAGPBIB: AGP 2X Bias Circuit, 3.3V, version B (core limited)
1.3.2.4 Naming Rules of Group F (Crystal Oscillator) I/O Cells
Name of Crystal Oscillator Cells:
Operating Voltage + Crystal Oscillator Function + Conserved Word
where
Operating
Crystal Oscillator Function Conserved Word
Voltage
SCIOAL: Low Frequency Crystal
Oscillator PIOS with Enable and A: Version A
Internal Feedback Control
U: 2.5V
SCIOAH: High Frequency Crystal Oscillator
PIOS With Enable and Internal Feedback B: Version B
Control
The Low frequency ones are for crystal oscillators with frequency of 32KHz, and the high frequency
ones are for crystal oscillators with frequency from 3MHz to 50MHz, or higher.
Examples:
USCIOAHA : Programmable high frequency crystal oscillator with enable and

internal feedback control, 2.5V, version A (pad limited).
USCIOAHB : Programmable high frequency crystal oscillator with enable and
internal feedback control, 2.5V, version B (core limited).
USCIOALA : Programmable high frequency crystal oscillator with enable and
USCIOALB : Programmable high frequency crystal oscillator with enable and
1-9
1.3.3 True 2.5V Programmable I/O Cells
UAA Programmable CMOS Input Buffer, 2.5V, Version A;

VA2OAA Programmable 2~24mA CMOS 3-State Output Buffer, Slew Rate, 2.5V, Version A;
VA2OTA Programmable 2~24mA CMOS 3-State Output Buffer, 2.5V, Version A;
WAA2OAA Programmable 2~24mA CMOS Bidirect Buffer, Slew Rate, 2.5V, Version A;
WAA2OTA Programmable 2~24mA CMOS Bidirect Buffer, 2.5V, Version A;
UAB Programmable CMOS Input Buffer, 2.5V, Version B;
VA2OAB Programmable 2~24mA CMOS 3-State Output Buffer, Slew Rate, 2.5V, Version B;
VA2OTB Programmable 2~24mA CMOS 3-State Output Buffer, 2.5V, Version B;
WAA2OAB Programmable 2~24mA CMOS Bidirect Buffer, Slew Rate, 2.5V, Version B;
WAA2OTB Programmable 2~24mA CMOS Bidirect Buffer, 2.5V, Version B;
Programmable Features:
Input Characteristics
Schmitt Trigger / None
Pull Up / Pull Down / None (75K Ohms)
Output Characteristics:
2/4/6/8/10/12/14/16/18/20/22/24 mA
1.3.3.1. Power Supply of True 2.5V programmable I/O Cells
The power bussing structure over the I/O cell is illustrated here
VCC2I
VCC2I VCCK VCC2O
VCCK VCC2I
2.5V CORE
GNDIK
GNDK GNDIK
GNDK GNDO
GNDO
FS9000A
Figure 1-3
where
VCC2I : VCC for 2.5V input buffer
VCC2O : VCC for 2.5V output buffer
VCCK : VCC for 2.5V internal circuit
GNDO : GND for 2.5V output buffer
GNDIK : GND for 2.5V input buffer
and internal circuit
1 - 10
1.3.3.2 Application Usage of True 2.5V programmable I/O Cells
VCC
E2 E4 E6 E10 SMT PU PD
E2 E4 E6 E10 E2 E4 E6 E10
I/O Configuration Register
E E IO Programming Tables :
IO E 2~24mA
2~24mA IO I 2.5V E2 E4 E6 E10 Driving
I 2.5V 4mA 0 0 0 0 2mA
2.5V
E2E4E6E10 = I
O
E2E4E6E10
PU
1
:
:
0
:
:
0
:
:
0
:
:
4mA
:
:
O PU C SMT Input
C O PD
0 Normal
PD C SMT 1 Schmitt Trigger
SMT
SMT PU PD PU PD Pull Up/Pull Down
SMT PU PD VCC 1 0 75K Pull Up
0 1 75K Pull Down
Others None
Level 1 Level 2
Figure 1-4
The above figure shows example of application circuit of true 2.5V programmable I/O cells. The
Programming pins can be hard-wired for level 1 users. Level 2 users can program using the
programming table after silicon. Both level 1 and level 2 users should refer programming table
for application. Please refer datasheets for detailed programming table.
1.3.3.3. DC Characteristics of True 2.5V programmable I/O Cells
(Under Recommended Operating Conditions, Tj = 0°C to + 115°C )
SYMBO L PARAMETER CONDITIONS MIN TYP MAX UNITS

VCCK Power Supply 2.3 2.5 2.7 V
VCC2I Power Supply 2.3 2.5 2.7 V
VCC2O Power Supply 2.3 2.5 2.7 V
VIL Input Low Voltage CMOS 0.3*Vcc V
VIH Input High Voltage CMOS 0.7*Vcc V
Schmitt trigger negative going
Vt- CMOS 0.8 1.0 V
threshold voltage
Schmitt trigger positive going
Vt+ CMOS 1.5 1.75 V
threshold voltage
VOL Output low voltage IOL=2,4,...,24mA 0.3 V
VOH Output high voltage IOH=2,4,...,24mA 1.9 V
Rpu/Rpd Input Pull-up/down resistance Vin=0 ; Vin=VCC2I 45 75 150 KΩ
Table 1-3
1 - 11
25oC, Vcc=2.5V, typ.

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Figure 1-5 Vol-Iol Characteristics (2.5V Buffer)

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Figure 1-6 Voh-Ioh Characteristics (2.5V Buffer)
1 - 12

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Figure 1-7 CMOS Threshold Characteristics (2.5V Buffer)

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Schmitt Trigger
Level
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Figure 1-8 Schmitt Trigger Threshold Characteristics (2.5V Buffer)
1 - 13

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Figure 1-9 Pull Up Transistor DC Characteristics (2.5 V Buffer)

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Figure 1-10 Pull down Transistor DC Characteristics (2.5 V Buffer)
1 - 14
1.3.4 True 3.3V Programmable I/O Cells
XAA Programmable CMOS Input Buffer, 3.3V, Version A;

YA2OAA Programmable 2~24mA CMOS 3-State Output Buffer, Slew Rate, 3.3V, Version A;
YA2OTA Programmable 2~24mA CMOS 3-State Output Buffer, 3.3V, Version A;
ZAA2OAA Programmable 2~24mA CMOS Bidirect Buffer, Slew Rate, 3.3V, Version A;
ZAA2OTA Programmable 2~24mA CMOS Bidirect Buffer, 3.3V, Version A;
XAB Programmable CMOS Input Buffer, 3.3V, Version B;
YA2OAB Programmable 2~24mA CMOS 3-State Output Buffer, Slew Rate, 3.3V, Version B;
YA2OTB Programmable 2~24mA CMOS 3-State Output Buffer, 3.3V, Version B;
ZAA2OAB Programmable 2~24mA CMOS Bidirect Buffer, Slew Rate, 3.3V, Version B;
ZAA2OTB Programmable 2~24mA CMOS Bidirect Buffer, 3.3V, Version B;
2/4/6/8/10/12/14/16/18/20/22/24 mA
1.3.4.1. Power Supply of True 3.3V programmable I/O Cells

VCC3I VCCK VCC3I

VCC2I VCC3O
VCC2I
L.S.
2.5V CORE
GNDIK GNDIK GNDIK GNDO
FS9000A L.S. Level Shifter
Figure1-11
where
and 2.5V internal circuit
1 - 15
1.3.4.2. Application Usage of True 3.3V programmable I/O Cells
Please refer section 1.3.3.2 for application usage
1.3.4.3. DC Characteristics of True 3.3V programmable I/O Cells
(Under Recommended Operating Conditions , Tj = 0°C to + 115°C )

VIL Input Low Voltage * CMOS/LVTTL 0.3*Vcc V
VIH Input High Voltage * CMOS/LVTTL 2 V
Vt- CMOS/LVTTL 0.9 1.1 V
threshold voltage
Vt+ CMOS/LVTTL 1.6 1.9 V
threshold voltage
Rpu/Rpd Input Pull-up/ down resistance Vin=0 ; Vin=VCC3I 45 75 150 KΩ
Table 1-4
* The input level is CMOS and LVTTL compatible. The Vil(max)=0.3VCC of CMOS also complied with the
Vil(max) =0.8 for LVTTL spec. The Vih(min)=2V of LVTTL also complied with the Vih(min) = 0.7*VCC
for CMOS spec.
1 - 16

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Figure 1-12 Vol-Iol Characteristics (3.3V Buffer)

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Figure 1-13 Voh-Ioh Characteristics ( 3.3V Buffer)
1 - 17
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Figure 1-14 CMOS/LVTTL Threshold Characteristics (3.3V Buffer)
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Figure 1-15 Schmitt Trigger Threshold Characteristics (3.3V Buffer)
1 - 18

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Figure 1-16 Pull Up Transistor DC Characteristics (3.3 V Buffer)

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µ ± öÂ
´ ¶ öÂ
´ ± öÂ
Êêï ³ ¶ öÂ
³ ± öÂ
² ¶ öÂ
² ± öÂ
¶öÂ
±öÂ
± ¯±× ± ¯¶× ² ¯±× ² ¯¶× ³ ¯±× ³ ¯¶× ´ ¯±×
× êï
Figure 1-17 Pull Down Transistor DC Characteristics (3.3 V Buffer)
1 - 19
1.3.5 3.3V Programmable I/O Cells with 5V Tolerance
XFAA Programmable CMOS Input Buffer, 3.3V, Version A;

YFA28AA Programmable 2~8mA CMOS 3-State Output Buffer, Slew Rate, 3.3V, Version A;
YFA28TA Programmable 2~8mA CMOS 3-State Output Buffer, 3.3V, Version A;
ZFA28AA Programmable 2~8mA CMOS Bidirect Buffer, Slew Rate, 3.3V, Version A;
ZFA28TA Programmable 2~8mA CMOS Bidirect Buffer, 3.3V, Version A;
YFA4CAA Programmable 4~12mA CMOS 3-State Output Buffer, Slew Rate, 3.3V, Version A;
YFA4CTA Programmable 4~12mA CMOS 3-State Output Buffer, 3.3V, Version A;
ZFA4CAA Programmable 4~12mA CMOS Bidirect Buffer, Slew Rate, 3.3V, Version A;
ZFA4CTA Programmable 4~12mA CMOS Bidirect Buffer, 3.3V, Version A;
XFAB Programmable CMOS Input Buffer, 3.3V, Version B;
YFA28AB Programmable 2~8mA CMOS 3-State Output Buffer, Slew Rate, 3.3V, Version B;
YFA28TB Programmable 2~8mA CMOS 3-State Output Buffer, 3.3V, Version B;
ZFA28AB Programmable 2~8mA CMOS Bidirect Buffer, Slew Rate, 3.3V, Version B;
ZFA28TB Programmable 2~8mA CMOS Bidirect Buffer, 3.3V, Version B;
YFA4CAB Programmable 4~12mA CMOS 3-State Output Buffer, Slew Rate, 3.3V, Version B;
YFA4CTB Programmable 4~12mA CMOS 3-State Output Buffer, 3.3V, Version B;
ZFA4CAB Programmable 4~12mA CMOS Bidirect Buffer, Slew Rate, 3.3V, Version B;
ZFA4CTB Programmable 4~12mA CMOS Bidirect Buffer, 3.3V, Version B;
5V tolerant I/O cells are necessary if the input voltage of the buses connected to the I/O may be 5V.
2/4/6/8 mA or 4/8/12 mA
1.3.5.1. Power Supply of 5V Tolerant 3.3V Programmable I/O Cells
VCC3I VCCK VCC3I

VCC2 VCC3O
VCC2 The power bussing structure over the
I/O cell is illustrated here:
where
L.S
2.5V CORE VCC3I : VCC for 3.3V input buffer
GNDIK GNDIK GNDIK GNDO GNDIK : GND for 3.3V input buffer
FS9000A L.S Level Shifter
Figure1-18
1 - 20
1.3.5.2. Application Usage of 5V Tolerant 3.3V Programmable I/O Cells
Please refer section 1.3.3.2 for application usage
1.3.5.3. DC Characteristics of 5V Tolerant 3.3V Programmable I/O Cells

VIL Input Low Voltage * CMOS/LVTTL 0.3*Vcc V
VIH Input High Voltage * CMOS/LVTTL 2 V
Vt- CMOS/LVTTL 0.9 1.1 V
threshold voltage
Vt+ CMOS/LVTTL 1.6 1.9 V
threshold voltage
Table 1-5
* The input level is CMOS and LVTTL compatible. The Vil(max)=0.3VCC of CMOS also complied with the
Vil(max) = 0.8 for LVTTL spec. The Vih(min)=2V of LVTTL also complied with the Vih(min) = 0.7*VCC
for CMOS spec.
1 - 21

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³±¯±îÂ 4îÂ Ãöççæó
²±¯±îÂ ³îÂ Ãöççæó
±¯±îÂ
±¯±× ±¯¶× ²¯±× ²¯¶× ³¯±× ³¯¶× ´¯±×
×ðí
Figure 1-19 Vol-Iol Characteristics (5V tolerant 3.3V Buffer)

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®²±¯±îÂ
³îÂ Ãöççæó
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®´±¯±îÂ 6îÂ Ãöççæó

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±¯±× ±¯¶× ²¯±× ²¯¶× ³¯±× ³¯¶× ´¯±×
×ðé
Figure 1-20 Voh-Ioh Characteristics (5V tolerant 3.3V Buffer)
1 - 22
´ ¯± ×
³ ¯¶ ×
³ ¯± ×
CM O S /LV TTL
Level ² ¯¶ ×
² ¯± ×
± ¯¶ ×
± ¯± ×
± ¯± × ± ¯¶ × ² ¯± × ² ¯¶ × ³ ¯± × ³ ¯¶ × ´ ¯± ×
×êï
Figure 1-21 CMOS/LVTTL Threshold Characteristics (5V Tolerant 3.3V Buffer)
´¯± ×
³¯¶ ×
³¯± ×
Schmitt Trigger
Level ²¯¶ ×
²¯± ×
±¯¶ ×
±¯± ×
±¯± × ±¯¶ × ²¯± × ²¯¶ × ³¯± × ³¯¶ × ´¯± ×
×êï
Figure 1-22 Schmitt Trigger Threshold Characteristics(5V Tolerant 3.3V Buffer)
1 - 23

±öÂ
®¶ ö Â
®² ± ö Â
®² ¶ ö Â
®³ ± ö Â
Ê êï
®³ ¶ ö Â
®´ ± ö Â
®´ ¶ ö Â
®µ ± ö Â
®µ ¶ ö Â
± ¯± × ± ¯¶ × ² ¯± × ² ¯¶ × ³ ¯± × ³ ¯¶ × ´ ¯± ×
×êï
Figure1-23 Pull Up Transistor DC Characteristics (5V tolerant 3.3V Buffer)

µ¶öÂ
µ±öÂ
´¶öÂ
´±öÂ
³¶öÂ
Êêï
³±öÂ
²¶öÂ
²±öÂ
¶öÂ
±öÂ
± ¯± × ± ¯¶ × ² ¯± × ² ¯¶ × ³ ¯± × ³ ¯¶ × ´ ¯± ×
×êï
Figure 1-24 Pull down Transistor DC Characteristics (5V tolerant 3.3V Buffer)
1 - 24
1.3.6 PCI 3.3V I/O Cells
XPCIAA Programmable PCI Input Buffer, 3.3V, Version A;

YPCITA PCI 3-State Output Buffer, 3.3V, Version A;
ZPCIATA Programmable PCI Bidirect Buffer, 3.3V, Version A;
XPCIAB Programmable PCI Input Buffer, 3.3V, Version B;

YPCITB PCI 3-State Output Buffer, 3.3V, Version B;
ZPCIATB Programmable PCI Bidirect Buffer, 3.3V, Version B;
For more detail of PCI , please refer to the PCI Specification.
Pull Up /Pull Down / None (75K Ohms)
1.3.6.1. Power Supply of PCI 3.3V I/O Cells
VCC3I VCCK
VCCK VCC3I VCC3O
VCC2I VCC2I
L.S.
2.5V CORE
FS9000A L.S. Level Shifter
Figure 1-25
where
1 - 25
1.3.6.2. DC Characteristics of PCI 3.3V I/O Cells
(Under Recommended Operating Conditions , Tj = 0°C to + 115°C )

VIL Input Low Voltage -0.5 0.3*Vcc V
VIH Input High Voltage 0.5*Vcc Vcc+0.5 V
VOL Output low voltage ô
Iout=1500 A 0.1*Vcc V
VOH Output high voltage ô
Iout=-500 A 0.9*Vcc V
Table 1-6
For the detailed, please refer PCI Local Bus Specification Revision 2.1
1.3.7 AGP 3.3V I/O Cells
XAGP1AA Programmable AGP 1X Input Buffer, 3.3V, Version A;

YAGP1TA AGP 1X 3-State Output Buffer, 3.3V, Version A;
ZAGP1ATA Programmable AGP 1X Bidirect Buffer, 3.3V, Version A;
XAGP2AA Programmable AGP 2X Input Buffer, 3.3V, Version A;
YAGP2TA AGP 2X 3-State Output Buffer, 3.3V, Version A;
ZAGP2ATA Programmable AGP 2X Bidirect Buffer, 3.3V, Version A;
ZAGPBIA AGP 2X Bias Circuit, 3.3V, Version A;
XAGP1AB Programmable AGP 1X Input Buffer, 3.3V, Version B;

YAGP1TB AGP 1X 3-State Output Buffer, 3.3V, Version B;
ZAGP1ATB Programmable AGP 1X Bidirect Buffer, 3.3V, Version B;
XAGP2AB Programmable AGP 2X Input Buffer, 3.3V, Version B;
YAGP2TB AGP 2X 3-State Output Buffer, 3.3V, Version B;
ZAGP2ATB Programmable AGP 2X Bidirect Buffer, 3.3V, Version B;
ZAGPBIB AGP 2X Bias Circuit, 3.3V, Version B;
Pull Up /Pull Down / None (75K ohms)

Power Down
1 - 26
1.3.7.1. Power Supply of Programmable AGP 3.3V I/O Cells
VCC3I
VCC2I VCCK VCC3I VCC3O
VCCK VCC2I VCC2I
L.S.
2.5V CORE
FS9000A Level Shifter

L.S.
Figure 1-26
where
1.3.7.2. DC Characteristics of AGP 3.3V I/O Cells
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VIL Input Low Voltage -0.5 0.3*Vcc V
VIH Input High Voltage 0.5*Vcc Vcc+0.5 V
VOL Output low voltage ô
Iout=1500 A 0.1*Vcc V
VOH Output high voltage ô
Iout=-500 A 0.9*Vcc V
Vref Input reference voltage for 2x mode 0.39*VCC3I 0.41*VCC3I V
Rpu/Rpd Input Pull-up/down resistance Vin=0; Vin=VCC3I 45 75 150 KΩ
Table 1-7
Note: Designers should choose proper package type, PGA recommended, and proper package pins for the I/O pins
to minimize bounding wire inductance in order to get good slew rate. For the detailed, please refer
AGP Local Bus Specification Revision 2.1
1 - 27
1.3.8 True 2.5V Programmable Oscillator Cells
USCIOAHA Programmable high frequency crystal oscillator with enable and

USCIOALA Programmable low frequency crystal oscillator with enable and
USCIOAHB Programmable high frequency crystal oscillator with enable and
USCIOALB Programmable low frequency crystal oscillator with enable and
Internal Feedback Resistor Control / None
Stop Control / None
Tri-state
Parallel (low/high freq. oscillator pad can be connected in parallel)
Variable Operating Mode
1.3.8.1. Power Supply of True 2.5V programmable Oscillator Cells
VCC2I
VCC2I VCCK VCC2O
VCCK VCC2I
2.5V CORE
GNDIK GNDIK
GNDK GNDO
GNDO
GNDK
FS9000A
Figure 1-27
where
1 - 28
1.3.8.2. Application Usage of True 2.5V Programmable Oscillator Cells
Figure 1-28 shows example of application circuit of crystal oscillator cells-USCIOALA &
USCIOAHA. All the configuration pins can be hard-wired for level1 users. Level2 users can use
the IO configuration file for programmable usage after silicon. Both level1 and level2 users should
refer "Programmable Oscillator Configuration Table"(see data sheet) for application. The oscillator
circuit contains one cell with two pads I & IO, crystal and external capacitors C1&C2. The circuit
constraints and electrical characteristics greatly depend on crystal and package conditions on
printed circuit board. Consult crystal supplier for more information.
USCIOALA and USCIOAHA can be connected in parallel only for level2 users. The application
circuit is also shown in Figure.1. It is capable of operating with 32KHz crystal or with 3M~50MHz
crystal. When low frequency application is needed, USCIOAHA has to be set to "Parallel" mode
to save power; when mid/high frequency is needed, USCIOALA has to be set to "Parallel" mode.
So do USCIOALB and USCIOAHB similarly.
Please contact your local AEs for detail information.
VCC VCC
FEBH FEBM USCIOAHA FEBL USCIOALA
I I
IO IO
E E
S0
S1 EB O EB O
Inside ASIC Inside ASIC
Outside ASIC Outside ASIC

Level 1 Level 1
C1 C2 C1 Crystal C2
Crystal
Figure 1-28-a
1 - 29
FEBH FEBM USCIOAHA
I
IO
IO Configuration File: E
S0 S1 E EB FEBM FEBH S0
S1 EB O
0 0 1 1 1 1
0 1 1 1 1 1
MUX O
Level 2
IO Configuration File:
E EB FEBL
FEBL USCIOALA
1 1 1
1 0 1 I
IO
E
EB O
Level 2
Inside ASIC
Outside ASIC
Crystal
C1 C2
Figure 1-28-b
1 - 30
1.4 General DC Characteristics
1.4.1 Absolute Maximum Ratings(1)

SYMBOL PARAMETER RATING UNITS
Vcc Power Supply -0.2 to 3.0 V
VIN Input Voltage -0.6 to Vcc+0.3 V
VOUT Output Voltage -0.6 to Vcc+0.3 V
Vcc3 Power Supply for Dual Oxide Cells -0.2 to 3.9V V
Input Voltage for non-5v-tolerant
VIN3 -0.6 to Vcc3+0.3 V
Dual Oxide Cells
Output Voltage for non-5v-tolerant
VOUT3 -0.6 to Vcc3+0.3 V
Dual Oxide Cells
Input Voltage for 5V tolerant
VIN5 -0.6 to 6.0 V
Dual Oxide Cells
Output Voltage for 5V tolerant
VOUT5 -0.6 to Vcc3+0.3 V
Dual Oxide Cells
TSTG Storage Temperature -55 to 150 oC
Table 1-8
1.4.2 Recommended Operating Conditions

SYMBOL PARAMETER MIN TYP MAX UNITS
Vcc Power Supply 2.3 2.5 2.7 V
VIN Input Voltage 0 Vcc V
Vcc3 Power Supply for Dual Oxide Cells(2) 3.0 3.3 3.6 V
VIN3 Input Voltage for Dual Oxide Cells 0 Vcc3 V
Input Voltage for 5V tolerant Dual
VIN5 0 VIN3 5.25 V
Oxide Cells
Junction Operating Commercial 0 25 115 O
Tj C
Temperature Industry -40 25 125
Table 1-9
1.4.3 Leakage Current and Capacitance(3)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
IIL Input leakage current(4) no pull-up or pull-down -1 1 µA
IOZ Tri-state leakage current -1 1 µA
CIN2 2.5V Input capacitance 3.1 pF
COUT2 2.5V Output capacitance 3.1 pF
CBID2 2.5V Bi-directional buffer capacitance 3.1 pF
CIN3 3.3V Input capacitance 3.1 pF
COUT3 3.3V Output capacitance 3.1 pF
CBID3 3.3V Bi-directional buffer capacitance 3.1 pF
Table 1-10
(1). Permanent device damage may occur if Absolute Maximum Ratings are exceeded.
(2). The max value of VCC for APG is 3.45V, the min one is 3.15V. For the detailed, please refer AGP spec V.2.0
(3). The capacitance's listed above do not include PAD capacitance and package capacitance. One can estimate pin capacitance
by adding pad capacitance's which is about 0.1pF and the package capacitance.
(4). The pull up/pull down input leakage current can be derived from the pull up/pull down resistance (Rpu/Rpd) in the DC
characteristics table for each type I/O buffer.
1 - 31
1.5 AC Characteristics
1.5.1 Derating Factors
The speed of a MOS device is dependent on voltage and temperature factors. In addition to these
2 factors, there is also process variation. Performance prediction is done based on a combination
of these three factors. The central operating condition is characterized at 2.5V, 25oC and typical
process parameters. The other conditions are normalized from the central operating conditions.
The most commonly operating points are listed as below.
LU Temperature Derating Factor

2/36
2/2: 2/32
2/31
2/26 2/26
2/21 2/217
2/16 2/16
2/11 2/11
1/:6 1/:6
1/:1 1/9:3
1/96 1/97
.51 226 236 o
.61 .36 1 36 61 86 211 C
Figure 1-29
LW Voltage Derating Factor

2/51
2/3:
2/31
2/19
2/11
2/11
1/:3
1/96
1/91
3/1 3/4 3/6 3/8 4/1 V
Figure 1-30
1 - 32
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−4 σ −3 σ −2 σ −1 σ 0σ 1σ 2σ 3σ 4σ
Cftu dbtf Uzqjdbm dbtf Xpstu dbtf
Lq 1/91 2/11 2/35
Figure 1-31
Note : @2.5V : Best case 0 oC,2.7V ; Typical case 25 oC, 2.5V ; Worst case 115 oC, 2.3V
@3.3V : Best case 0 oC,3.6V ; Typical case 25 oC, 3.3V ; Worst case 115 oC, 3.0V
The following equation shows how the overall derating factor is determined :
Κ tot = ΚT × ΚV × ΚP
where :
Κ tot = Total derating factor
ΚT = Factor due to junction temperature
ΚV = Factor due to operating voltage
ΚP = Factor due to process variation
To predict the real world performance of the design, the propagation delay of the macrocell is
evaluated under three cases:
1. Typical case: At 2.5V, 25oC, and typical processing, the derating factor is:
Κtot = ΚT × ΚV × ΚP = 1 × 1 × 1 =1
2. Best case: At 2.7V,0oC, and best processing, the derating factor is:
Κtot = ΚT × ΚV × ΚP
= 0.95 × 0.92 × 0.8
= 0.70
and the propagation delay will be
Κtot × Ttyp = 0.70×Ttyp
2. Worst case : At 2.3V,115oC and worst processing, the derating factor is:
Κtot = ΚT × ΚV × ΚP
= 1.19 × 1.08 × 1.24
= 1.59
and the propagation delay will be
Κtot × Ttyp = 1.59 × Ttyp
1 - 33
1.5.2 Propagation Delay Calculation

The precision of the propagation delay is ensured by a well-defined characterization process. The
complete delay equation incorporate the non-linear slope and loading effects with adjustment
parameters for process, temperature and voltage variation. The rise and fall time is characterized
respectively. A simplified version of delay equation is as follows:
Tpd = Κ tot * ( T0 + K * CL + Q * SW )
where Κtot = process, temperature and voltage variation factor

T0 = Intrinsic delay of the macrocell
K = Marginal delay per pico farad (pf)
CL = Fanout and interconnect capacitance
Q = Marginal delay per Unit slope
SW = Unit slope representing fanout and interconnect capacitance
For pre-route and post-route simulations, more accurate and complex delay calculation is applied
by the Central Delay Calculator software. For pre-route simulation, the Central Delay Calculator
takes the output fanout, chip dimension, routing area and grouping information into consideration
from the empirical statistics. For post-route simulation, the actual wire delay is extracted by the
layout extraction tool and is accompanied with the macro cell delay to reflect the physical timing
behavior of the design.
1.5.3 Timing Definitions

The timing definitions for both internal core macrocells and Input/Output buffers are listed in this
section.
1.5.3.1 Internal Core Macrocells
All timing delays for internal macrocells are characterized at the 50% point to 50% point. This
includes propagation delay times through combinatorial functions as well as setup, hold time and
release time definitions for sequential elements.
1. Propagation delay : time between an input signal transition and the resultant output signal
transition.
Input
Figure 1-32
Output
Tplh Tphl
2. Setup time : The minimum time that input data must remain unchanged prior to an active
clock transition.
Data Input
Figure 1-33
Clock
Setup
1 - 34
3. Hold time : The minimum time that input data must remain unchanged subsequent to an
active clock transition.
Data Input
Figure 1-34
Clock
Hold
4. Recovery time : The minimum time that the Set or Reset input must remain un-activated prior
to an active clock transition.
Set or Reset
(Active High)
Figure 1-35
Clock
Recovery
5. Removal time : The minimum time that the Set or Reset input must remain activated
subsequent to an active clock transition.
Set or Reset
(Active High)
Figure 1-36
Clock
Removal
6. Minimum Pulse Width: The minimum length of time between the leading and trailing edges of a
pulse.
MPW_H
Clock Figure 1-37
MPW_L
Note : 1.The timing of (L>>Z) are characterized with output terminated through a resistor to VDD
2.The timing of (H>>Z) are characterized with output terminated through a resistor to GND
1.5.3.2 Primary Input Buffers
Timing delays are measured at input trip points that are defined by the type of function being
characterized. Output trip points are always measured at the 50% trip point.
Function type Vcc Input trip point (VI) Output trip point
CMOS 2.3V-2.7V / 3.0v~3.6v 50% of Vcc 50% of Vcc
Input Pad 50% 50%
Figure 1-38
Output pin
Tplh
Tphl
CMOS
1 - 35
1.5.3.3 Primary Output Buffers
Timing delays are measured at the 50% input trip point. Output trip points are defined by the type
of function being characterized.
Function type Vcc Input trip point Output trip point (VO)
CMOS 2.3-2.7V / 3.0v~3.6v 50% of Vcc 50% of Vcc
Input Pin
Figure 1-39
Output Pad 50% 50%
Tplh
Tphl
CMOS
Note : 1.The timing of (L>>Z) are characterized with output terminated through a resistor to VDD
2.The timing of (H>>Z) are characterized with output terminated through a resistor to GND
1.5.4 AC Power Consumption and Power Model
The AC power consumption includes power consumption within the cell and power consumption
by external load. The power consumption within the cell is the power required to charge and
discharge inside the cell. It can be modeled by a well-defined characterization process. The
precise power model incorporates the non-linear slope and loading effects with adjustment
parameters for process, temperature and voltage variation. The rise and fall toggle power
consumption is characterized individually and modeled on an average base. The power (energy)
consumption by external load can be simply expressed as: CV2/2
where C = external load

V = supply voltage
1 - 36

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Faraday Technology Corp.

1.1 General Description

1.1.2 Targeted Applications

1.2 Cell Library

1.2.1 Fundamental Core Cell Library

MUX/MXL ...................................... Multiplexers

1.2.3 Embedded Functional Block Design Considerations

5$0 08; Figure 1-1

1.2.4 The Definition of Cell Unit

1.3 I/O Cells

UAB XAB XFAB XPCIAB XAGP1AB USCIOALB

1.3.1.1 What is PIOS ?

1.3.1.2 Why PIOS ?

1.3.1.3 PIOS in FS9000A Library

1.3.2 I/O Cell Naming Conventions

1.3.2.1 Naming Rules of Group A, B, and C I/O Cells

Name of Input Cells:

Operating Voltage + Input Function + Conserved Word

U: 2.5V A : PIOS Input A: Version A

Name of Output Cells:

Operating Min. Max. Slew Conserved

Name of Bidirection Cells:

Operating Output Min. Max. Slew Conserved

W: 2.5V A : PIOS I/O 2: 2mA 8: 8mA A: Slew A: Version A

1.3.2.2 Naming Rules of Group D (PCI) I/O Cells

Name of Input Cells:

Operating Voltage + Input Function + Conserved Word

Operating Voltage Input Function Conserved Word

PCIA:PCI PIOS A: Version A

Name of Output Cells:

Operating Voltage + Output Function + Conserved Word

PCIT:PCI 3-State A: Version A

Name of Bidirection Cells:

Operating Voltage + I/O Function + Conserved Word

Operating Voltage I/O Function Conserved Word

1.3.2.3 Naming Rules of Group E (AGP) I/O Cells

Name of Input Cells:

Operating Voltage + Input Function + Conserved Word

Name of Output Cells:

Operating Voltage + Output Function + Conserved Word

AGP1T:AGP1X 3-State output A: Version A

Name of Bidirection Cells:

Operating Voltage + I/O Function + Conserved Word

Operating Voltage I/O Function Conserved Word

Name of Bias Cells:

Operating Voltage + Function + Conserved Word

Operating Voltage Function Conserved Word

XAGP1AA : Programmable AGP 1X input buffer, 3.3V, version A (pad limited).

1.3.2.4 Naming Rules of Group F (Crystal Oscillator) I/O Cells

Name of Crystal Oscillator Cells:

Operating Voltage + Crystal Oscillator Function + Conserved Word

USCIOAHA : Programmable high frequency crystal oscillator with enable and

1.3.3 True 2.5V Programmable I/O Cells

UAA Programmable CMOS Input Buffer, 2.5V, Version A;

1.3.3.1. Power Supply of True 2.5V programmable I/O Cells

1.3.3.2 Application Usage of True 2.5V programmable I/O Cells

1.3.3.3. DC Characteristics of True 2.5V programmable I/O Cells

(Under Recommended Operating Conditions, Tj = 0°C to + 115°C )

SYMBO L PARAMETER CONDITIONS MIN TYP MAX UNITS

25oC, Vcc=2.5V, typ.

²³±¯±î Â ³µîÂ Ãöççæó

¹±¯±î Â ²·îÂ Ãöççæó

±¯±× ±¯¶× ²¯±× ²¯¶× ³¯±× ³¯¶×

Figure 1-5 Vol-Iol Characteristics (2.5V Buffer)