Unit-II

Intel 8086 Micro Processor

 Intel 8086 was launched in 1978.
 It was the first 16-bit microprocessor.
 This microprocessor had major improvement over the execution speed of 8085.
 It is available as 40-pin Dual-Inline-Package (DIP).
 It is available in three versions:
 8086 (5 MHz)
 8086-2 (8 MHz)
 8086-1 (10 MHz)
 It consists of 29,000 transistors.
 It has a 16 line data bus.
 And 20 line address bus.
 It could address up to 1 MB of memory.
 It has more than 20,000 instructions.
 It supports multiplication and division.

Pin Diagram of Intel 8086

1
Power supply and frequency signals

It uses 5V DC supply at VCC pin 40, and uses ground at VSS pin 1 and 20 for its operation.

Clock signal

Clock signal is provided through Pin-19. It provides timing to the processor for operations. Its
frequency is different for different versions, i.e. 5MHz, 8MHz and 10MHz.

Address/data bus

AD0-AD15. These are 16 address/data bus. AD0-AD7 carries low order byte data and
AD8AD15 carries higher order byte data. During the first clock cycle, it carries 16-bit address
and after that it carries 16-bit data.

Address/status bus

A16-A19/S3-S6. These are the 4 address/status buses. During the first clock cycle, it carries 4-
bit address and later it carries status signals.

S7/BHE

BHE stands for Bus High Enable. It is available at pin 34 and used to indicate the transfer of
data using data bus D8-D15. This signal is low during the first clock cycle, thereafter it is
active.

Read($\overline{RD}$)

It is available at pin 32 and is used to read signal for Read operation.

Ready

It is available at pin 32. It is an acknowledgement signal from I/O devices that data is
transferred. It is an active high signal. When it is high, it indicates that the device is ready to
transfer data. When it is low, it indicates wait state.

RESET

It is available at pin 21 and is used to restart the execution. It causes the processor to
immediately terminate its present activity. This signal is active high for the first 4 clock cycles
to RESET the microprocessor.

INTR

It is available at pin 18. It is an interrupt request signal, which is sampled during the last clock
cycle of each instruction to determine if the processor considered this as an interrupt or not.

2
NMI

It stands for non-maskable interrupt and is available at pin 17. It is an edge triggered input,
which causes an interrupt request to the microprocessor.

$\overline{TEST}$

This signal is like wait state and is available at pin 23. When this signal is high, then the
processor has to wait for IDLE state, else the execution continues.

MN/$\overline{MX}$

It stands for Minimum/Maximum and is available at pin 33. It indicates what mode the
processor is to operate in; when it is high, it works in the minimum mode and vice-aversa.

INTA

It is an interrupt acknowledgement signal and id available at pin 24. When the microprocessor
receives this signal, it acknowledges the interrupt.

ALE

It stands for address enable latch and is available at pin 25. A positive pulse is generated each
time the processor begins any operation. This signal indicates the availability of a valid address
on the address/data lines.

DEN

It stands for Data Enable and is available at pin 26. It is used to enable Transreceiver 8286. The
transreceiver is a device used to separate data from the address/data bus.

DT/R

It stands for Data Transmit/Receive signal and is available at pin 27. It decides the direction of
data flow through the transreceiver. When it is high, data is transmitted out and vice-a-versa.

M/IO

This signal is used to distinguish between memory and I/O operations. When it is high, it
indicates I/O operation and when it is low indicates the memory operation. It is available at pin
28.

WR

It stands for write signal and is available at pin 29. It is used to write the data into the memory
or the output device depending on the status of M/IO signal.

3
HLDA

It stands for Hold Acknowledgement signal and is available at pin 30. This signal acknowledges
the HOLD signal.

HOLD

This signal indicates to the processor that external devices are requesting to access the
address/data buses. It is available at pin 31.

QS1 and QS0

These are queue status signals and are available at pin 24 and 25. These signals provide the
status of instruction queue. Their conditions are shown in the following table −

QS0 QS1 Status

0 0 No operation

0 1 First byte of opcode from the queue

1 0 Empty the queue

1 1 Subsequent byte from the queue

S0, S1, S2

These are the status signals that provide the status of operation, which is used by the Bus
Controller 8288 to generate memory & I/O control signals. These are available at pin 26, 27,

and 28.

Following is the table showing their status −

S2 S1 S0 Status

4
0 0 0 Interrupt acknowledgement

0 0 1 I/O Read

0 1 0 I/O Write

0 1 1 Halt

1 0 0 Opcode fetch

1 0 1 Memory read

1 1 0 Memory write

1 1 1 Passive

LOCK

When this signal is active, it indicates to the other processors not to ask the CPU to leave the
system bus. It is activated using the LOCK prefix on any instruction and is available at pin 29.

RQ/GT1 and RQ/GT0

These are the Request/Grant signals used by the other processors requesting the CPU to release
the system bus. When the signal is received by CPU, then it sends acknowledgment.
RQ/GT0 has a higher priority than RQ/GT1.

8086 CPU ARCHITECTURE AND BLOCK DIAGRAM

5
The microprocessors functions as the CPU in the stored program model of the digital computer.
Its job is to generate all system timing signals and synchronize the transfer of data between
memory, I/O, and itself. It accomplishes this task via the three-bus system architecture
previously discussed.

The microprocessor also has a S/W function. It must recognize, decode, and execute program
instructions fetched from the memory unit. This requires an Arithmetic-Logic Unit (ALU) within
the CPU to perform arithmetic and logical (AND, OR, NOT, compare, etc) functions.

The 8086 CPU is organized as two separate processors, called the Bus Interface Unit (BIU) and
the Execution Unit (EU). The BIU provides H/W functions, including generation of the memory
and I/O addresses for the transfer of data between the outside world -outside the CPU, that is-
and the EU.

The EU receives program instruction codes and data from the BIU, executes these instructions,
and store the results in the general registers. By passing the data back to the BIU, data can also
be stored in a memory location or written to an output device. Note that the EU has no
connection to the system buses. It receives and outputs all its data thru the BIU.

The only difference between an 8088 microprocessor and an 8086 microprocessor is the BIU. In the
8088, the BIU data bus path is 8 bits wide versus the 8086's 16-bit data bus. Another difference is that
the 8088 instruction queue is four bytes long instead of six.

6
The important point to note, however, is that because the EU is the same for each processor, the
programming instructions are exactly the same for each. Programs written for the 8086 can be run on the
8088 without any changes.

FETCH AND EXECUTE

Although the 8086/88 still functions as a stored program computer, organization of the CPU into a
separate BIU and EU allows the fetch and execute cycles to overlap. To see this, consider what happens
when the 8086 or 8088 is first started.

1. The BIU outputs the contents of the instruction pointer register (IP) onto the address bus, causing the
selected byte or word to be read into the BIU.

2. Register IP is incremented by 1 to prepare for the next instruction fetch.

3. Once inside the BIU, the instruction is passed to the queue. This is a first-in, first-out storage register
sometimes likened to a "pipeline".

4. Assuming that the queue is initially empty, the EU immediately draws this instruction from the queue
and begins execution.

5. While the EU is executing this instruction, the BIU proceeds to fetch a new instruction. Depending on
the execution time of the first instruction, the BIU may fill the queue with several new instructions
before the EU is ready to draw its next instruction.

The BIU is programmed to fetch a new instruction whenever the queue has room for one (with the 8088)
or two (with the 8086) additional bytes. The advantage of this pipelined architecture is that the EU can
execute instructions almost continually instead of having to wait for the BIU to fetch a new instruction.

There are three conditions that will cause the EU to enter a "wait" mode. The first occurs when an

7
instruction requires access to a memory location not in the queue. The BIU must suspend fetching
instructions and output the address of this memory location. After waiting for the memory access, the
EU can resume executing instruction codes from the queue (and the BIU can resume filling the queue).

The second condition occurs when the instruction to be executed is a "jump" instruction. In this case
control is to be transferred to a new (nonsequential) address. The queue, however, assumes that
instructions will always be executed in sequence and thus will be holding the "wrong" instruction codes.
The EU must wait while the instruction at the jump address is fetched. Note that any bytes presently in
the queue must be discarded (they are overwritten).

One other condition can cause the BIU to suspend fetching instructions. This occurs during execution of
instructions that are slow to execute. For example, the instruction AAM (ASCII Adjust for
Multiplication) requires 83 clock cycles to complete. At four cycles per instruction fetch, the queue will
be completely filled during the execution of this single instruction. The BIU will thus have to wait for
the EU to pull over one or two bytes from the queue before resuming the fetch cycle.

A subtle advantage to the pipelined architecture should be mentioned. Because the next several
instructions are usually in the queue, the BIU can access memory at a somewhat "leisurely" pace. This
means that slow-mem parts can be used without affecting overall system performance.

PROGRAMING MODEL

As a programmer of the 8086 or 8088 you must become familiar with the various registers in the EU and
BIU.

The data group consists of the accumulator and the BX, CX, and DX registers. Note that each can be
accessed as a byte or a word. Thus BX refers to the 16-bit base register but BH refers only to the higher
8 bits of this register. The data registers are normally used for storing temporary results that will be acted
on by subsequent instructions.

The pointer and index group are all 16-bit registers (you cannot access the low or high bytes alone).
These registers are used as memory pointers. Sometimes a pointer reg will be interpreted as pointing to a
memory byte and at other times a memory word. As you will see, the 8086/88 always stores words with
the high-order byte in the high-order word address.

8
Register IP could be considered in the previous group, but this register has only one function -to point to
the next instruction to be fetched to the BIU. Register IP is physically part of the BIU and not under
direct control of the programmer as are the other pointer registers.

Six of the flags are status indicators, reflecting properties of the result of the last arithmetic or logical
instructions. The 8086/88 has several instructions that can be used to transfer program control to a new
memory location based on the state of the flags.

Three of the flags can be set or reset directly by the programmer and are used to control the operation of
the processor. These are TF, IF, and DF.

The final group of registers is called the segment group. These registers are used by the BIU to
determine the memory address output by the CPU when it is reading or writing from the memory unit.
To fully understand these registers, we must first study the way the 8086/88 divides its memory into
segments.

SEGMENTED MEMORY

Even though the 8086 is considered a 16-bit processor, (it has a 16-bit data bus width) its memory is still
thought of in bytes. At first this might seem a disadvantage:

Why saddle a 16-bit microprocessor with an 8-bit memory?

Actually, there are a couple of good reasons. First, it allows the processor to work on bytes as well as
words. This is especially important with I/O devices such as printers, terminals, and modems, all of
which are designed to transfer ASCII-encoded (7- or 8-bit) data.

Second, many of the 8086's (and 8088's) operation codes are single bytes. Other instructions may require
anywhere from two to seven bytes. By being able to access individual bytes, these odd-length
instructions can be handled.

We have already seen that the 8086/88 has a 20-bit address bus, allowing it to output 210, or 1'048.576,
different memory addresses. As you can see, 524.288 words can also be visualized.

As mentioned, the 8086 reads 16 bits from memory by simultaneously reading an odd-addressed byte
and an even-addressed byte. For this reason the 8086 organizes its memory into an even-addressed bank
and an odd-addressed bank.

With regard to this, you might wonder if all words must begin at an even address. Well, the answer is
yes. However, there is a penalty to be paid. The CPU must perform two memory read cycles: one to
fetch the low-order byte and a second to fetch the high-order byte. This slows down the processor but is
transparent to the programmer.

The last few paragraphs apply only to the 8086. The 8088 with its 8-bit data bus interfaces to the 1 MB
of memory as a single bank. When it is necessary to access a word (whether on an even- or an odd-
addressed boundary) two memory read (or write) cycles are performed. In effect, the 8088 pays a

9
performance penalty with every word access. Fortunately for the programmer, except for the slightly
slower performance of the 8088, there is no difference between the two processors.

MEMORY MAP

Still another view of the 8086/88 memory space could be as 16 64K-byte blocks beginning at hex
address 000000h and ending at address 0FFFFFh. This division into 64K-byte blocks is an arbitrary but
convenient choice. This is because the most significant hex digit increments by 1 with each additional
block. That is, address 20000h is 65.536 bytes higher in memory than address 10000h. Be sure to note
that five hex digits are required to represent a memory address.

The diagram is called a memory map. This is because, like a road map, it is a guide showing how the
system memory is allocated. This type of information is vital to the programmer, who must know exactly
where his or her programs can be safely loaded.

Note that some memory locations are marked reserved and others dedicated. The dedicated locations are
used for processing specific system interrupts and the reset function. Intel has also reserved several
locations for future H/W and S/W products. If you make use of these memory locations, you risk
incompatibility with these future products.

SEGMENT REGISTERS

Within the 1 MB of memory space the 8086/88 defines four 64K-byte memory blocks called the code
segment, stack segment, data segment, and extra segment. Each of these blocks of memory is used
differently by the processor.

The code segment holds the program instruction codes. The data segment stores data for the program.
The extra segment is an extra data segment (often used for shared data). The stack segment is used to
10
store interrupt and subroutine return addresses.

You should realize that the concept of the segmented memory is a unique one. Older-generation
microprocessors such as the 8-bit 8086 or Z-80 could access only one 64K-byte segment. This mean that
the programs instruction, data and subroutine stack all had to share the same memory. This limited the
amount of memory available for the program itself and led to disaster if the stack should happen to
overwrite the data or program areas.

The four segment registers (CS, DS, ES, and SS) are used to "point" at location 0 (the base address) of
each segment. This is a little "tricky" because the segment registers are only 16 bits wide, but the
memory address is 20 bits wide. The BIU takes care of this problem by appending four 0's to the low-
order bits of the segment register. In effect, this multiplies the segment register contents by 16.

The point to note is that the beginning segment address is not arbitrary -it must begin at an address
divisible by 16. Another way if saying this is that the low-order hex digit must be 0.

Also note that the four segments need not be defined separately. Indeed, it is allowable for all four
segments to completely overlap (CS = DS = ES = SS).

Memory locations not defined to be within one of the current segments cannot be accessed by the
8086/88 without first redefining one of the segment registers to include that location. Thus at any given
instant a maximum of 256 K (64K * 4) bytes of memory can be utilized. As we will see, the contents of
the segment registers can only be specified via S/W. As you might imagine, instructions to load these
registers should be among the first given in any 8086/88 program.

LOGICAL AND PHYSICAL ADDRESS

Addresses within a segment can range from address 00000h to address 0FFFFh. This corresponds to the
64K-byte length of the segment. An address within a segment is called an offset or logical address. A
logical address gives the displacement from the address base of the segment to the desired location
within it, as opposed to its "real" address, which maps directly anywhere into the 1 MB memory space.
This "real" address is called the physical address.

What is the difference between the physical and the logical address?

The physical address is 20 bits long and corresponds to the actual binary code output by the BIU on the
address bus lines. The logical address is an offset from location 0 of a given segment.

11
When two segments overlap it is certainly possible for two different logical addresses to map to the same
physical address. This can have disastrous results when the data begins to overwrite the subroutine stack
area, or vice versa. For this reason you must be very careful when segments are allowed to overlap.

ADVANTAGES OF SEGMENTED MEMORY

Segmented memory can seem confusing at first. What you must remember is that the program op-codes
will be fetched from the code segment, while program data variables will be stored in the data and extra
segments. Stack operations use registers BP or SP and the stack segment. As we begin writing programs
the consequences of these definitions will become clearer.

An immediate advantage of having separate data and code segments is that one program can work on
several different sets of data. This is done by reloading register DS to point to the new data. Perhaps the
greatest advantage of segmented memory is that programs that reference logical addresses only can be
loaded and run anywhere in memory. This is because the logical addresses always range from 00000h to
0FFFFh, independent of the code segment base. Such programs are said to be relocatable, meaning that
they will run at any location in memory. The requirements for writing relocatable programs are that no
references be made to physical addresses, and no changes to the segment registers are allowed.

General Purpose Registers of 8086

These registers can be used as 8-bit registers individually or can be used as 16-bit in pair to have
AX, BX, CX, and DX.

1. AX Register: AX register is also known as accumulator register that stores operands for
arithmetic operation like divided, rotate.
2. BX Register: This register is mainly used as a base register. It holds the starting base
location of a memory region within a data segment.

12
 3. CX Register: It is defined as a counter. It is primarily used in loop instruction to store
loop counter.
4. DX Register: DX register is used to contain I/O port address for I/O instruction.

Segment Registers
Additional registers called segment registers generate memory address when combined with
other in the microprocessor. In 8086 microprocessor, memory is divided into 4 segments as
follow:

Fig. 2: Memory Segments of 8086

1. Code Segment (CS): The CS register is used for addressing a memory location in the
Code Segment of the memory, where the executable program is stored.
2. Data Segment (DS): The DS contains most data used by program. Data are accessed in
the Data Segment by an offset address or the content of other register that holds the offset
address.
3. Stack Segment (SS): SS defined the area of memory used for the stack.
4. Extra Segment (ES): ES is additional data segment that is used by some of the string to
hold the destination data.

Flag Registers of 8086

Flag register in Execution Unit is of 16-bit and is shown in the following figure.

Fig. 3: Flag Register of 8086

Flags Register determines the current state of the processor. They are modified automatically by
CPU after mathematical operations, this allows to determine the type of the result, and to

13
determine conditions to transfer control to other parts of the program. 8086 has 9 flags and they
are divided into two categories:

1. Conditional Flags
2. Control Flags

Conditional Flags
Conditional flags represent result of last arithmetic or logical instruction executed. Conditional
flags are as follows:

Carry Flag (CF): This flag indicates an overflow condition for unsigned integer arithmetic. It is
also used in multiple-precision arithmetic.

• Auxiliary Flag (AF): If an operation performed in ALU generates a carry/barrow from

lower nibble (i.e. D0 – D3) to upper nibble (i.e. D4 – D7), the AF flag is set i.e. carry
given by D3 bit to D4 is AF flag. This is not a general-purpose flag, it is used internally
by the processor to perform Binary to BCD conversion.
• Parity Flag (PF): This flag is used to indicate the parity of result. If lower order 8-bits of
the result contains even number of 1’s, the Parity Flag is set and for odd number of 1’s,
the Parity Flag is reset.
• Zero Flag (ZF): It is set; if the result of arithmetic or logical operation is zero else it is
reset.
• Sign Flag (SF): In sign magnitude format the sign of number is indicated by MSB bit. If
the result of operation is negative, sign flag is set.
• Overflow Flag (OF): It occurs when signed numbers are added or subtracted. An OF
indicates that the result has exceeded the capacity of machine.

Control Flags
Control flags are set or reset deliberately to control the operations of the execution unit. Control
flags are as follows:

1. Trap Flag (TP):

a. It is used for single step control.
b. It allows user to execute one instruction of a program at a time for debugging.
c. When trap flag is set, program can be run in single step mode.
2. Interrupt Flag (IF):

a. It is an interrupt enable/disable flag.

b. If it is set, the maskable interrupt of 8086 is enabled and if it is reset, the interrupt
is disabled.
c. It can be set by executing instruction sit and can be cleared by executing CLI
instruction.
3. Direction Flag (DF):

a. It is used in string operation.

14
 b. If it is set, string bytes are accessed from higher memory address to lower
memory address.
c. When it is reset, the string bytes are accessed from lower memory address to
higher memory address.

Concept of pipelining

o A technique used in advanced microprocessors where the microprocessor begins

executing a second instruction before the first has been completed.
o A Pipeline is a series of stages, where some work is done at each stage. The work is not
finished until it has passed through all stages.
o With pipelining, the computer architecture allows the next instructions to be fetched
while the processor is performing arithmetic operations, holding them in a buffer close to
the processor until each instruction operation can perform.

◼The instruction Fetch (IF) stage is responsible for obtaining the requested instruction
from memory. The instruction and the program counter (which is incremented to the

15
 next instruction) are stored in the IF/ID pipeline register as temporary storage so that
may be used in the next stage at the start of the next clock cycle.

◼ The Instruction Decode (ID) stage is responsible for decoding the instruction and sending
out the various control lines to the other parts of the processor. The instruction is sent to the
control unit where it is decoded and the registers are fetched from the register file.

◼The Execution (EX) stage is where any calculations are performed. The main component
in this stage is the ALU. The ALU is made up of arithmetic, logic and capabilities.

◼The Write (W)stage is responsible for writing the result of a calculation, memory access
or input into the register file.

Address, Data and Control buses.

➢ A bus, in computing, is a set of physical connections (cables, printed circuits, etc.) which
can be shared by multiple hardware components in order to communicate with one
another.

➢ The bus contains multiple wires (signal lines) that contain addressing information that
describes the memory location of where the data is being sent or where it is being
retrieved. Each wire in the bus carries a single bit of information, which means the more
wires a bus has the more information it can address.
➢ For example, a computer with a 32-bit address bus can address 4 GB of memory, and a
computer with a 36-bit bus can address 64 GB of memory.

➢ A bus is capable of being a parallel or serial bus and today all computers utilize two bus
types, an internal bus or local bus and an external bus, also called the expansion bus.
An internal bus enables communication between internal components such as a video
card and memory. An external bus is capable of communicating with external
components such as a USB or SCSI device.

16
 The following diagram shows different types of buses of a computer.

❖ The address bus (sometimes called the memory bus) transports memory addresses which
the processor wants to access in order to read or write data. It is a unidirectional bus.
❖ The data bus transfers instructions coming from or going to the processor. It is a
bidirectional bus.
❖ The control bus (or command bus) transports orders and synchronization signals coming
from the control unit and travelling to all other hardware components. It is a bidirectional
bus, as it also transmits response signals from the hardware.
System Bus

A system bus is a single computer bus that connects the major components of a computer
system, combining the functions of a data bus to carry information, an address bus to determine
where it should be sent, and a control bus to determine its operation. The technique was
developed to reduce costs and improve modularity.

17
 The following diagram shows System bus.

In the above diagram CPU exchanges data with memory. For this purpose, it typically makes use
of two internal (to the CPU) registers: a memory address register (MAR), which specifies the
address in memory for the next read or write, and a memory buffer register (MBR), which
contains the data to be written into memory or receives the data read from memory. Similarly, an
I/O address register (I/OAR) specifies a particular I/O device. An I/O buffer register (I/OBR) is
used for the exchange of data between an I/O module and the CPU.
A memory module consists of a set of locations, defined by sequentially numbered addresses.
Each location contains a binary number that can be interpreted as either an instruction or data.
An I/O module transfers data from external devices to CPU and memory, and vice versa. It
contains internal buffers for temporarily holding these data until they can be sent on.

18
19