ADE

CAMBRIDGE INSTITUTE OF TECHNOLOGY

K.R. PURAM, BENGALURU-560036

Department of Computer Science & Engineering

III Sem Analog and Digital Electronics (21CS33)
Question Bank

Module-1

1. Explain the operation of a 4 bit R – 2R ladder type DAC for the input 0001.
2. Determine the following for an 8 bit resistive divider network:
i) Weight of first LSB
ii) Weight of MSB
iii) Output voltage for the inputs 10101111 and 11110001
iv) Full scale output voltage if logic 0 = 0V and logic 1 = 5V.
3. .Explain the operation of Flash type ADC.
4. Design an astable multivibrator for output frequency of 1KHz and duty cycle of 45%. Draw
the circuit diagram and output waveform.
5. Explain base bias circuit using an NPN transistor.
6. Design a collector to base bias circuit to fix the operation point (7V, 1.2mA). Draw the circuit
diagram and DC load line of the circuit. Given Vcc = 15V, β = 100.
7. Explain the operation of successive approximation ADC.

8. Explain collector to base bias circuit using an NPN transistor.

9. Explain the working of relaxation oscillator using opamp.
10. Describe the operation of first order low pass and high pass filters using opamp.
11. Explain the operation of peak detector and absolute value circuits using opamp.
12. Determine IB, Ic, VCE, VB, VE and VC for a VDB circuit. Draw the circuit diagram and DC
load line. Consider Vcc = 12V, Rc=1K, β = 100, RE=0.76K, R1=6.6K and R2=1.2K.
13. Explain Voltage divider Bias circuit.
14. Explain the operation of schimitt trigger using opamp.
15. Explain current to voltage and voltage to current converters with a neat circuit diagram.
16. What is band-pass filter? Explain wide band-pass filter with neat sketch
17. Explain narrow band-pass filter with neat sketch.
18. Explain wide band-reject filter with neat sketch.
19. With a neat sketch explain the working of a non-linear amplifier.
20. Write a brief note on voltage regulation. List and explain the factors affecting the load
voltage in a power supply.
21. Write a brief note on – (a) Three terminal regulators, and (b) Adjustable voltage regulators.
22. With a neat block diagram, explain a typical A/D and D/A converter.

Module-2

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1. What is a K - map? Explain K - Map with an example. State the limitations of K -

Map.
2. Show the minimum sum of products expression for the function f(R, S, T) =
(R’T’+RS’+RS) using K – map.

3. Determine the minimum product of sums expression for the function

f(A,B,C,D) = Σm (0,2,4,5,8,12)+ d(1,10) using K – map. Give the implementation of
the simplified expression using NOR gates.

4. Show the minimum product of sums expression for the function f(R,S,T) =
(R’+S+T)(R+S’+T)(R’+S’+T)(R+S+T)(R+S+T’) using
K – map.

5. Determine the minimum sum of products expression for the function

F(A,B,C,D) = πM (3,6,7,9,11,13,14,15).d(1,10) using K – map. Give the
implementation of the simplified expression using NAND gates.

6. Determine the minimum sum of products expression for the function f(A,B,C,D) =
Σm (0,2,3,4,8,10,12,13,14) using Quine-McCluskey method.

7. Determine the minimum sum of products expression for the function f(A,B,C,D) =
πM (8,11,14).D(2,9,15) using Quine-McCluskey method.

8. What is a K - map? Show how a truth table is converted into K - map with an
example.
9. Show the minimum sum of products expression for the function f(w,x,y,z) = Σm
(1,2,3,9,10) + d (0,4,15) using K – map.

10. A Digital system of four inputs is to be designed in which the month of a year is given
as input in 4 bit form. The month Jan is represented as 0000, Feb – 0001 and so on.
The output of the system should be 1 corresponding to the input of the month
containing 30 days or otherwise it is 0. Consider the excess numbers beyond 1011 as
don’t care for the system of 4 variables ABCD. Construct the truth table, give the
Boolean expression in πM form, simplify using K – map and implement the
simplified equation using NOR gates.

11. Show the minimum product of sums expression for the function f(P,Q,R,S) =
M1.M4.M5.M11.M12.M14.M15 using K – map.

12. The system has four inputs. The output will be high only for the decimal equivalent of
the inputs is divisible by 3 or 7. Construct the truth table, give the Boolean expression
in Σm form, simplify using K – map and implement the simplified equation using
NAND gates.

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13. . Determine the minimum sum of products expression for the function f(A,B,C,D) =
Σm (0,1,5,6,8,9,11,13) +Σd(7,10,12) using Quine-McCluskey method.

14. Determine the minimum sum of products expression for the function f(A,B,C,D) =
πM (1,10,12).D(2,5,15) using Quine-McCluskey method.

15. What is a K - map? Show the pair, quad, octet, rolling and overlapping in K – map.

16. Show the minimum sum of products expression for the function f(p,q,r,s)) = Σm
(1,3,4,5,6,7,10,12,13) + Σd (2,9) using K – map.

17. A switching circuit has two control inputs (C1 and C2), two data inputs (X1 and X2)
and one output (Z). The circuit performs logic operations on the two data inputs as
shown in the table:

C1 C2 Function performed by
the circuit
0 0 X1 . X2
0 1 X1  X2
1 0 X1’ + X2
1 1 X1  X2

Develop a truth table for Z and use K – map to find minimum AND-OR gate circuit to
realize Z.

18. Show the minimum product of sums expression for the function f(P,Q,R,S) = πM
(5,7,13,14,15) .πD (1,2,3,9) using K – map.

19. The system has four inputs.The output will be high only when majority of the inputs
are low. Construct the truth table, give the Boolean expression in Σm form, simplify
using K – map and implement the simplified equation using NAND gates.

20. Determine the minimum sum of products expression for the function f(A,B,C,D) =
Σm (5,6,8,9,11,13,14) +Σd (1,4,15) using Quine-McCluskey method.

21. Determine the minimum sum of products expression for the function f(A,B,C,D) =
πM(2,4,11,12,15).D(3,5,14) using Quine-McCluskey method.

22. .Determine the minimum product-of-sums expression the function f(A,B,C,D) = Σm

(0,2,4,5,8,12) + d(1,10) using Entered Variable Map.

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23. Determine the minimum sum-of-products expression for the the function F(A,B,C,D)
= πM (3,6,7,9,11,13,14,15) . D(1,10) using Entered variable Map.

Module-3
1. What is a multiplexer? Show the design of 4:1 MUX
2. Show the implementation of the following:
i) 8-to-1 MUX with three control inputs using four 2-to1 and one 4-to-1
multiplexers.
ii) 16-to-1 MUX with four control inputs using four 4-to-1 and three 2-to-1
multiplexers.
iii) 32:1 mux using 8:1 mux and 4:1 Mux.

3. Implement f(A,B,C,D) = Σm (0,2,3,4,8,10,12,13,14) using an 8:1 Mux.

4. Implement f(p,q,r,s)) = Σm (1,3,4,5,6,7,10,12,13) + Σd (2,9)using an 8:1 Mux.

5. What is a De- multiplexer? Show the design of 1:4 DE-MUX.

6. Design 1: 32 demux using 1:4 demux and 1: 2 demux.

7. What is a decoder? Show the working of 3 to 8 decoder.

8. Show the design of Decimal to BCD decoder.

9. Show the implementation of full subtractor using 3 to 8 decoder and OR gates.

10. Show the implementation of full adder using 3 to 8 decoder and OR gates.

11. Show the implementation of functions f1(a,b,c) = Σm(1,4,5), f2(a,b,c) = Σm(2,4,6,7)

using 3-to-8 decoder and OR gates.

12. What is an encoder? Explain octal to binary ( 8 to 3) encoder.

13. Implement the following equations using PLA. F1(A, B, C) = ∑ m(1, 3, 7) F2(A,
B, C) = ∑m(2, 3, 5).

14. Implement a full subtractor/full adders using a PAL.

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15. Implement a full subtractor/full adders using a PLA.

16. Show he implementation of BCD to Seven segment decoder using PLA

17. Design a logic diagram for the functions f1(A,B,C) = A’B+BC’+C and f2(A,B,C) =
AB+B+CA’ using PLA/PAL.
18. Explain the design of circuits with limited gate fan in with an example.

19. Explain Propagation delay in logic gates with an example and timing diagram.

20. What is a static-0 hazard? Show with an example, how to detect and eliminate static -
0 hazard.

21. What is a static-1 hazard? Show with an example, how to detect and eliminate static -
1 hazard.
22. Consider the following logic function.f(A,B,C,D)= Σm (0,4,5,10,11,13,14,15)
i) Identify static-1 hazards in the circuit.
ii) Write AND-OR circuit for F which has no hazard.
iii) Identify static-0 hazards in the circuit.
iii) Write OR-AND circuit for F which has no hazard.

23. Explain four kinds of three state buffers along with the truth table and circuit diagram.

Module-4

1. Explain Gate level, data flow and behavioral models with an example.
2. Explain VHDL description of combinational circuits with an example.
3. Explain VHDL model for multiplexers.
4. Develop a VHDL module for 4:1 mux using conditional statements.
5. Develop a VHDL module for 8:1 mux using conditional statements.
6. Explain the structure (entity and architecture declarations )of VHDL program with an
example.
7. Write VHDL code for 4 bit parallel adder using full adder as component.
8. Explain the working of SR latch with a neat logic diagram and truth table.
9. Explain the working of D-FF with a neat logic diagram and truth table.
10. Explain the working of gated RS-FF with a neat logic diagram and truth table.

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11. Explain the working of gated D-FF with a neat logic diagram and truth table.
12. Explain the working of positive edge triggered (Clocked) RS- flip - flop with neat
diagrams
13. Explain the working of Negative edge triggered (Clocked) RS- flip - flop with neat
diagrams
14. Explain the working of Positive edge triggered (Clocked) D- flip - flop with neat
diagrams
15. Explain the working of Negative edge triggered (Clocked) D- flip - flop with neat
diagrams
16. Explain the working of Positive edge triggered (Clocked) JK- flip - flop with neat
diagrams.
17. Explain the working of Master- Slave JK FF with a neat diagram and truth table.
18. Explain the working of T flip - flop with a neat diagram and truth table.
19. Show the various representations of RS FF.
20. Show the various representations of D FF.
21. Show the various representations of JK FF.
22. Show the various representations of T FF.

Module-5
1. Explain Register transfer with an example using D-FF
2. With neat diagram, explain how data can be transferred from the output of one of two
registers into a third register using tri-state buffers.
3. Explain the working of 4 – bit parallel adder with accumulator.
4. Explain the working of SISO shift register using D/JK/SR flip – flop with a neat timing
diagram.
5. Explain the working of SIpO shift register using D/JK/SR flip – flop with a neat timing
diagram.
6. Explain the working of PISO shift register using D/JK/SR flip – flop with a neat timing
diagram.
7. Explain the working of PIPO shift register using D/JK/SR flip – flop with a neat timing
diagram.
8. Explain the working of ring counter with a neat timing diagram.

9. Explain the working of Johnson counter using JK flip – flops with a neat timing diagram.
10. Design a mod-5 synchronous up counter using JK flip – flop.
11. Design a synchronous counter using SR flip – flop for the following counting sequence: 001,
101, 000, 100, 111, and 011.

12. Design a mod-4 synchronous up counter using SR/JK flip – flop.

13. Design a decade counter using gray code for decimal digits. Use JK/SR flips – flops.

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14. Design a mod-6 synchronous self-correcting up counter using JK/SR flip – flop.
15. Design a synchronous counter using SR flip – flop for the following counting sequence: 01,
10, 00, and 11.
16. Design a mod-9 synchronous up counter using D/SR/ JK flip – flop.
17. Design a synchronous counter using SR flip – flop for the following counting sequence: 001,
000, 100, 011, 010, 101 and110.
18. Design a synchronous counter using JK flip – flop for the following counting sequence: 111,
100, 000, 101, 110, and 001.
19. Design a synchronous counter using SR/JK/ D flip – flop for the following counting
sequence: 001, 000, 100, 011, 010, 101, and 110.

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