Microelectronics Journal 139 (2023) 105883

Contents lists available at ScienceDirect

Microelectronics Journal
journal homepage: www.elsevier.com/locate/mejo

Ultra-low voltage start-up clock generators for micro-scale energy

harvesting: New variants of body-biased stacked inverter based ring
oscillators
Ankur Mukherjee, Ashik C. Jayamon, Sai Chandra Teja R. ∗, Ashudeb Dutta
Green PMU Semi Private Limited, Hyderabad, India

ARTICLE INFO ABSTRACT

Index terms: This work aims to discuss the challenges of implementing an integrated ultra low voltage start-up clock/oscillator,
Energy harvesting the state of the art and propose four new variants of a body-biased stacked inverter based ring oscillator and
Ultra-low voltage analyse the same. The proposed delay cells designed in 180-nm BCD CMOS process are connected to form a
Ring oscillator
13-staged ring oscillator (RO) with regular 𝑉𝑡 transistors.
Body-bias
All four proposed variants’ performance is compared against the former works (implemented in the same
process) with respect to the lowest supply voltage required for sustained oscillations (𝑉DDmin ), oscillation
frequency and peak-to-peak voltage swing (𝑉pp ). For a supply voltage of 50 mV, over 90% 𝑉DD is obtained
from post layout simulations for all four proposed architectures consuming around 24 pW of average power,
out of which the variant that has the maximum swing of 92% (an improvement of 9.2% compared to that of
stacked inverter based RO), is able to start and sustain an oscillation at 32.5 mV supply voltage. The fastest
architecture proposed has a frequency (post layout) of 131.5 Hz at 50 mV 𝑉DD , which is 62% more than that
of the stacked inverter based RO with body bias. Monte Carlo analysis reveals that the proposed RO variants’
𝑉pp have lesser interquartile range (IQR) and relatively higher median values.

1. Introduction transducers, photo-voltaic cells; due to the stochastic nature of the

In recent years, sensor network systems called Machine to Machine
(M2M) and Internet of Things (IoT) have attracted a lot of attention. In
such a sensor network system, communication is performed between
a terminal that collects sensor data called an individual sensor node
terminal and a server that collects the data. This sensor node terminal
uses wireless communication in consideration of the mobile environ-
ment, and is mainly composed of a sensor, microprocessor, power
supply circuit, and wireless system. However, unlike traditional wire-
less technologies, autonomous sensor networks need to operate in an
environment without power. To realize an autonomous sensor network
by using a power source that uses energy harvesting in place of batter-
ies has attracted attention. As commercialization of energy-harvesting
technology is progressing, the demand for the ultra-low-voltage circuits
has become higher.
Micro-scale energy harvesting [1–4], just as the name suggests,
turns out to be a subset of that, to power wireless sensor network
systems.
There are many challenges when it comes to extracting energy
from transducers viz., thermo-electric generators (TEGs), piezoelectric
maximum power that could be extracted from these, which could be
attributed to the inconsistent physical phenomena they are interfaced
with. Moreover, transducers like TEGs, that produce sub-100 mV open-
circuit voltage (𝑉oc ) add on to the challenge; to address which there are
many literary works as in [2,3,5], that deal with sub-100 mV startup
conditions.
One of the blocks that a transducer sees is an oscillator as shown in
Fig. 1, which then drives a switched capacitor DC–DC converter/charge
pump and other blocks that follow [6–9]. An oscillator with no external
inductors or other associated start-up circuitry which can start and
sustain an oscillation at sub 100 mV supply voltages aids in realizing a
fully integrated system.
There have been works which use fully integrated LC based os-
cillators, being described in [6] capable of starting an oscillation for
voltages in the order of tens of millivolts, the drawback being the
requirement of large energy storage elements which are often difficult
to realize and implement on-chip. Hence, many works revolve around
the ring oscillator primarily because of its structural simplicity and
relative ease of design. Realization and implementation of the design on

∗ Corresponding author.
E-mail addresses: ankur.mkjee@greenpmusemi.com (A. Mukherjee), saichandrateja@greenpmusemi.com (Sai Chandra Teja R.).

https://doi.org/10.1016/j.mejo.2023.105883
Received 5 April 2023; Received in revised form 26 June 2023; Accepted 26 June 2023
Available online 3 July 2023
0026-2692/© 2023 Elsevier Ltd. All rights reserved.
A. Mukherjee et al. Microelectronics Journal 139 (2023) 105883

Table 1
Body connection for each RO configuration.
Body bias scheme BpST𝑖 BnST𝑖 BpM𝑖 BnM𝑖 BpSB𝑖 BnSB𝑖
NN-NN-NN IN𝑖+2 IN𝑖+2 IN𝑖+2 IN𝑖+2 IN𝑖+2 IN𝑖+2
XX-NN-YY X𝑖+1 X𝑖+1 IN𝑖+2 IN𝑖+2 Y𝑖+1 Y𝑖+1
SBBIRO VDD VSS IN𝑖+2 IN𝑖+2 VDD VSS
XX-XY-YY X𝑖+1 X𝑖+1 X𝑖+1 Y𝑖+1 Y𝑖+1 Y𝑖+1
SIRO VDD VSS VDD VSS VDD VSS
XX-GS-YY X𝑖+1 X𝑖+1 VSS VDD Y𝑖+1 Y𝑖+1

sub-threshold currents of a CMOS inverter devices at ultra low voltage

Fig. 1. Generic energy harvesting system. supplies and solving, one can arrive at (1) after differentiating output
𝜕𝑣
voltage (𝑣out ) with respect to input voltage (𝑣in ) (i.e., 𝜕𝑣out ).
in
{ ( ) }
|𝐴INV | 1 𝑉 DD
| |max = 𝜂 exp 2𝑉 −1 (1)
T
where 𝜂 is the sub-threshold slope factor and 𝑉T is the thermal voltage
(=26 mV at 300 K).
The limit as to how low 𝑉DD could drop to and still not lose its binary
switching ability, as reported in [12,13] is often called the Meindl limit
(2), which can be obtained by equating (1) to unity and then solving
for 𝑉DD .
Fig. 2. Ring oscillator (RO).
𝑉DD = 𝑉DDmin = 2𝑉T ln(1 + 𝜂) (2)

For a process with a sub-threshold slope factor 𝜂 of unity or equiv-

chip for an RO is straight forward. However, MOSFETs operate in deep
sub-threshold at ultra low voltage supplies as opposed to the strong
inversion region. For the design of CMOS delay cell in an RO with
regular CMOS devices, it is necessary to take appropriate measures to
enhance the gain and swing.
Alternatives to the conventional CMOS inverter were proposed,
where the basic CMOS inverter delay cell was replaced by a 6-transistor
Schmitt Trigger structure [3,10] or by a stacked inverter (SI) struc-
ture [7], both of which trying to address the low-gain at ultra-low
voltage supplies.
Forward body biasing the devices, as demonstrated in [8,9], can
aid in enhancing the gain and swing. These works have used delay
cells that were forward body biased and had implemented a ring
oscillator (SBBIRO or stacked body biased inverter based RO in [9])
with sustained oscillations at as low as 34 mV supply voltage.
This work aims to explore some variants of the stacked inverter
delay cell based RO in which stage 𝑖 uses nodes from the successive
stage 𝑖 + 1 to bias the body terminals of its devices to enhance the
benefits of using a stacked inverter based delay cell [7].
This paper is structured as follows; Section 2 discusses the conven-
tional CMOS based ring oscillators, challenges when trying to realize
such an RO and modifications that were made to address them. Sec-
tion 3 introduces the design and implementation of the proposed
architectures along with the SIRO (stacked inverter based RO as in [7])
and SBBIRO, post-layout simulation results are presented in Section 4
followed by conclusion in Section 5.
2. CMOS ring oscillators
A CMOS inverter based RO (Fig. 2) comprises of an odd number of
inverters connected in a loop/ring, hence the name. Such a structure
can sustain an oscillation with a frequency of 2𝑛𝑇1 [11], where 𝑛
𝐷
being the number of inverters connected in the loop, and 𝑇𝐷 being the
propagation delay of one inverter; provided that the gain is greater than
the required value as described by the Barkhausen criterion, i.e., the
small signal loop gain being at least unity, which is generally the
case with conventional CMOS inverters operating at strong inversion
regions.
However, a conventional CMOS inverter’s gain magnitude, ||𝐴INV ||,
decreases when the supply voltage (𝑉DD ) goes down. Upon equating the
alently, a sub-threshold swing 𝑆𝑆 (= 𝜂𝑉T ln(10)) of 60 mV/decade, the
value of the minimum supply voltage (𝑉DDmin ) turns out to be 36 mV
at 300 K. As mentioned in [14], for a 180-nm bulk CMOS process, the
value of sub-threshold swing could be typically (90 mV/decade) which
makes 𝑉DDmin rise up to about 48 mV at 300 K.
As mentioned in Section 1, the main challenge when a CMOS
inverter tries to operate in deep sub-threshold (sub 100 mV) is the
reduced gain and the 𝑖on to 𝑖off ratio moving closer to unity. This is
when the leakage current from the off block (𝑖off ) becomes comparable
to the on current from the active block (𝑖on ) resulting in a deteriorated
voltage swing. To combat such issues, the ST [3,10] structure and more
recently, the SI structure [7] were proposed in place of the conventional
CMOS inverter.
To go further down in supply, the bulk or body terminal was
appropriately biased for gain enhancement, as in works [8,9], the
latter work reconciling the stacked architecture and body biasing. This
work aims to explore more such body biasing techniques using the SI
structure which is elaborated in the succeeding sections.
3. Proposed body-bias RO
The delay cell has three inverters as in Fig. 3 referred to as ST,
M and SB which stands for stacked-top, Middle and stacked-bottom
respectively connected in a configuration similar to [7].
MpST, MnST; MpM, MnM; MpSB, MnSB represent the pmos-nmos
transistor pairs of the top, middle and bottom inverters; Mp (Mn)
being the pmos (nmos). Using this unit, the body terminals of the
𝑖th stage (which are BpST𝑖 , BnST𝑖 , BpM𝑖 , BnM𝑖 , BpSB𝑖 , BnSB𝑖 ) are biased
using one or a combination of VDD, VSS, Y𝑖+1 , X𝑖+1 or IN𝑖+2 terminals
as summarized in Table 1 which are elaborated in Fig. 4. Fig. 3 depicts
two adjacent delay cells in the ring oscillator (𝑖th and 𝑖 + 1th stages)
showing the nomenclature of the devices and the body terminals. ‘B’
refers to the bulk/body terminal of a MOSFET; ‘p’ (‘n’) following ‘B’
refers to the type of MOSFET, ‘p’ for pmos and ‘n’ for nmos. The next
two letters refer to the location of the device in the delay cell; ‘ST’ or
‘‘Stacked Top’’, ‘SB’ or ‘‘Stacked Bottom’’ and ‘M’ referring to the FETs
in the Middle inverter or the main inverter; 𝑖 is just the index, referring
to the delay cell in the chain. ‘M’ in MpST𝑖 for instance, stands for
MOSFET or the device. This convention will be followed throughout
the rest of the paper.

2
A. Mukherjee et al. Microelectronics Journal 139 (2023) 105883

Fig. 3. Two adjacent delay cells (𝑖th and 𝑖 + 1th stages) in the RO from Fig. 2 showing
the nomenclature of the devices and the body terminals.

Table 2
Delay cell device dimensions.
Device Width Length
MpST 13 μm 0.18 μm
MnST 1.3 μm 0.4 μm
MpM 5 μm 0.18 μm
MnM 0.9 μm 0.4 μm
MpSB 8 μm 0.18 μm
MnSB 4 μm 0.4 μm

Table 3
Layout area comparison.
RO type Dimensions in μm Area in μm2
NN-NN-NN 125 × 47 5875
XX-NN-YY 192 × 60 11 520
SBBIRO 210 × 60 12 600
XX-XY-YY 210 × 60 12 600
SIRO 192 × 60 11 520
XX-GS-YY 210 × 60 12 600

3.1. Design and implementation

The cells are designed and optimized in the 180-nm tech node using
regular 𝑉𝑡 devices (of approximately 500 mV), although low or medium
𝑉𝑡 devices could be used to obtain higher sub-threshold currents. The
device dimensions are tabulated in Table 2. The middle inverter was
sized first to obtain a decent gain and symmetric voltage transfer
characteristic (VTC).
MpST (MnSB) are sized much wider than MpM (MnM) so that the
overall pull-up (pull-down) strength of MpM (MnM) is not affected by
the stacked top (bottom) inverters (also mentioned in [7]).
Having lesser pull-down (pull-up) strengths for MnST (MpSB) com-
pared to the pull-up (pull-down) strengths MpST (MnSB) is necessary so
that these devices do not interfere with the pull-up (pull-down) action
of MpST (MnSB), however, weakening them too much would elevate
the leakage current. With increase in leakage current, the 𝑖on /𝑖off ratio
drops thereby bringing down the overall swing at ultra-low voltages.
Fig. 4. Schematics of two adjacent delay cells (𝑖th and 𝑖 + 1th stages) in the RO from
Also, to fix the number of stages 𝑛, the time period of oscillation needs
Fig. 2 of all the proposed variants.
to be sufficiently greater than the rise and fall time of the delay cell.
This is to ensure that the nodes in the RO chain are able to reach and
settle at their minimum/maximum value so as to obtain a rail-to-rail
square pulse with maximum 𝑉pp . The layouts of four 13-staged ring Fig. 5. The layout area is the least for the NN-NN-NN variant, roughly
oscillators using the proposed four variants of delay cells are shown in half the area compared to the other variants (Table 3), as all the body

3
A. Mukherjee et al.
Fig. 5. Layout of all the proposed 13-staged RO architecture in 180-nm CMOS process.
terminals in each delay stage share a common connection i.e., the
bodies of all the devices of the 𝑖th delay cell are connected to the output
4
Microelectronics Journal 139 (2023) 105883
Fig. 6. Output voltage (IN𝑖+1 ) and gain versus input voltage (IN𝑖 ) applied to all the
delay cell variants.
of the succeeding stage or IN𝑖+2 ; referring to Table 1 which helped in
reducing the distances between the cells in the layout.
3.2. Qualitative analysis of various derivatives of the proposed delay cell
Considering the NN-NN-NN biasing scheme (from Table 1); without
the loss of generality, when the input IN𝑖 to a stage 𝑖 transitions from
high to low, the output IN𝑖+1 transitions from low to high, the ON
current (𝑖𝑜𝑛 ) charging IN𝑖+1 is being provided by MpST𝑖 via MpM𝑖 and
the output of 𝑖 + 1th stage (i.e., IN𝑖+2 ) also starts transitioning from
high to low, similar to IN𝑖 with a delay. IN𝑖+2 is fed back to the body
terminals (which are BpST𝑖 , BnST𝑖 , BpM𝑖 , BnM𝑖 , BpSB𝑖 , BnSB𝑖 ) of the
transistors in the 𝑖th stage . The gain (or swing) boosting is initiated
when IN𝑖+2 starts transitioning from high to low which dynamically
lowers the 𝑉𝑡 of the PMOS devices MpST𝑖 , MpM𝑖 , MpSB𝑖 and raises the
𝑉𝑡 of MnST𝑖 , MnM𝑖 , MnSB𝑖 .
This positive feedback (giving rise to two peaks in Fig. 6) thus
changes the effective threshold voltages by forward body biasing of the
pmos devices, hence boosting them; an effect qualitatively similar to
A. Mukherjee et al. Microelectronics Journal 139 (2023) 105883

Fig. 7. Post-layout comparison of different RO Architectures.

the three inverter Schmitt trigger structure as discussed in [15]. The

rise in 𝑉𝑡 of the nmos counterparts (MnST𝑖 , MnM𝑖 , MnSB𝑖 ) adds on to
the advantage by lessening the off current (𝑖off ) thereby enhancing the
swing.
However, this structure is slower compared the SBBIRO [9] as
gain/swing are being traded with speed/frequency, due to the manifes-
tation of hysteresis (as in Fig. 6, similar to a Schmitt trigger- [15,16])
in the VTC and also by the increased capacitance of each delay cell
due to the added load from the bulk connections. The other proposed
Fig. 8. Post-layout transient plots for different RO Architectures.
variants (excluding SBBIRO and SIRO) in Table 1 attempt to inspect
possibilities of biasing the body using any other node (instead of IN𝑖+2 )
so as to achieve better speeds than NN-NN-NN. With each modification
Table 4
a better speed (higher frequency) was achieved by a reduction in the
Schematic versus post-layout frequency comparison.
voltage swing (or gain) (Fig. 6).
RO type Schematic frequency Post-layout frequency
To begin with, the body terminals BpST𝑖 (BnSB𝑖 ) and BnST𝑖 (BpSB𝑖 )
NN-NN-NN 46.7 Hz 42.2 Hz
connected to X𝑖+1 (Y𝑖+1 ), leaving BpM𝑖 (BnM𝑖 ) connected to IN𝑖+2 as in
XX-NN-YY 97 Hz 70.2 Hz
XX-NN-YY. SBBIRO 115.6 Hz 81.1 Hz
In XX-XY-YY, the body terminals BpM𝑖 (BnM𝑖 ) are connected to X𝑖+1 XX-XY-YY 136.1 Hz 108.2 Hz
(Y𝑖+1 ). SIRO 164.8 Hz 131.1 Hz
In the above variants, the speed is improved as X𝑖+1 and Y𝑖+1 nodes XX-GS-YY 167.5 Hz 131.5 Hz

are quicker to respond as compared to IN𝑖+2 . It must be noted however

that X and Y nodes, though quicker to respond than IN, do not swing in
the same domain as IN does. X (Y) nodes does not reach the maximum
(minimum) value that the IN nodes reach since MnSB (MpST) are sized
much wider than MpSB (MnST) as explained in 3.1.
To increase the frequency further, the body terminals BpM𝑖 and
BnM𝑖 are connected to VSS and VDD respectively. This reduces the
𝑉𝑡 of both the devices in the middle inverter and this reduction is
independent of any other node voltage, making it faster than both the
variants above.
4. Simulation results and discussion
Figs. 7 and 8 summarizes the transient post-layout simulation results
for the different kinds of delay cell body connections (as mentioned in
the Table 1) and a 13-staged ring oscillator built out of each of these
connections. The proposed delay cell structures (NN-NN-NN, XX-NN-
YY, XX-XY-YY and XX-GS-YY) were compared against the structures in
works [7,9] which are referred to as SIRO and SBBIRO respectively
with all the unit delay cells’ devices having the same dimensions as
mentioned in Table 2.
Referring to Fig. 7, NN-NN-NN has the maximum voltage swing
(𝑉pp ) followed by XX-NN-YY, XX-XY-YY, XX-GS-YY, SBBIRO and SIRO
with 𝑉pp of 46 mV, 45.45 mV, 45.23 mV, 45.02 mV, 42.56 mV and
41.41 mV respectively for 50 mV supply voltage. Table 4 compares
the frequencies obtained in schematic and post-layout transient sim-
ulations.
Monte Carlo (MC) simulations are performed on all the RO schemat-
ics to investigate the effect on voltage swing due to global or process
variations and mismatch. 1000 runs at 50 mV supply voltage for
each of the ROs are analysed through schematic transient simulations.
From Fig. 9, the median voltage swings in descending order are as
follows: NN-NN-NN, XX-NN-YY, XX-XY-YY, XX-GS-YY, SBBIRO and
SIRO; however, the reverse order holds for the interquartile range
(IQR), i.e., NN-NN-NN has the least variation in its voltage swing
across process and mismatch followed by XX-NN-YY, XX-XY-YY, XX-GS-
YY, SBBIRO and SIRO. Median and IQR are preferred over mean and
standard deviation as the MC histograms are not symmetric/normally
distributed and is skewed to the side of higher voltage swings.
Referring to Table 5, the 𝑉DDmin for which the oscillations started
and sustained (for post-layout) were 32.5 mV, 34 mV, 35 mV, 36 mV,
37 mV and 38 mV for NN-NN-NN, XX-NN-YY, XX-XY-YY, XX-GS-YY,

5
A. Mukherjee et al. Microelectronics Journal 139 (2023) 105883

Table 5
Peak-to-peak voltage swing and minimum supply voltage required for sustained
oscillations for all types.
RO type 𝑉pp at 𝑉DD = 50 mV 𝑉DDmin
NN-NN-NN 46 mV 32.5 mV
XX-NN-YY 45.45 mV 34 mV
SBBIRO 42.56 mV 37 mV
XX-XY-YY 45.23 mV 35 mV
SIRO 41.41 mV 38 mV
XX-GS-YY 45.02 mV 36 mV

Fig. 9. Monte-Carlo plots for different RO Architectures.

Fig. 11. Frequency versus supply voltage for different RO Architectures showing
variation across the fast and slow corners.

oscillators across the fast–fast (FF) corner at 85 ◦ C and slow–slow (SS)

Fig. 10. Normalized peak to peak voltage swing versus supply voltage.
SBBIRO and SIRO respectively. This trend is in-line with the gain of the
respective delay cells. More gain per delay cell results in a lower supply
voltage at which the oscillator (made out of the respective delay cell)
can start and sustain the oscillations. Fig. 10 shows the dependence of
𝑉pp with respect to 𝑉DD . With rise in 𝑉DD , the voltage swing improves
eventually reaching full swing for higher supplies. Fig. 11 illustrates
the trend of frequency with respect to 𝑉DD for all the types of ring
corner at −40 ◦ C for all the variants mentioned in Table 1, the y-axis
being in logarithmic scale. The frequency increases exponentially with
increase in 𝑉DD . Both Figs. 10 and 11 are obtained from post layout
transient simulations of the ROs.
Fig. 12 shows the variation in frequency with different number of
delay cells in the RO chain at a 𝑉DD of 100 mV (transient simulation us-
ing the schematic). For cases where 𝑉DD is not expected to drop below a
certain value, the number of delay cells in the RO chain can be brought
down (from 13) to achieve higher oscillation frequencies. Fig. 13 shows
the phase noise characteristics of the different RO variants when the
schematics are operated at a supply of 100 mV.
Fig. 14 shows the average current sourced (sinked) by the
pmos (nmos) body/bulk terminals in one delay cell when the ROs are
made to operate during a transient simulation at the typical corner
condition. The proposed RO variants are intended to be operated for
𝑉DD values of less than 400 mV to avoid the body diode leakage current
which becomes prominent at higher supplies (beyond 500 mV).

6
A. Mukherjee et al.
Fig. 12. Number of delay cells in the RO chain versus frequency for different RO
Architectures at a supply voltage of 100 mV.
Fig. 13. Phase noise comparison of different RO Architectures at a supply voltage of
100 mV.
5. Conclusion
Four new variants of a body biased stacked inverter based delay cell
are proposed using which 13-staged ring oscillators (for each variant)
are implemented in 180-nm BCD CMOS process, for which post layout
simulations are carried out. The variants are compared with the pre-
vious works, SI and SBBI based RO, both of which being implemented
using the same unit delay cell (by appropriately connecting the body
terminals as mentioned in the works as discussed above) in the same
process along with the other four. All the architectures implemented
consume around 24 pW of average power at 𝑉DD of 50 mV. Over 90%
𝑉pp at 50 mV 𝑉DD is achieved in all the proposed RO types the highest
being 92% for NN-NN-NN which is 6.9% and 9.2% more than that of
SBBIRO and SIRO respectively. The same variant (NN-NN-NN) has the
maximum gain per unit cell and is able to start and sustain oscillation
for a supply voltage as low as 32.5 mV; which is lower than the SBBIRO
7
Microelectronics Journal 139 (2023) 105883
Fig. 14. Average current taken by the body terminals in a single delay cell for different
supply voltages.
and SIRO types with a 𝑉DDmin of 37 mV and 38 mV respectively. Monte
Carlo simulations indicate that the proposed ROs have higher median
values and comparatively lesser IQR, lesser than 4 mV, in their voltage
swings when compared to SIRO (5.97 mV) and SBBIRO (4.77 mV). The
fastest variant proposed (XX-GS-YY) is able to oscillate at a frequency
of 131.5 Hz which is 62% more than that of SBBIRO.
CRediT authorship contribution statement
Ankur Mukherjee: Methodology, Investigation, Writing – original
draft, Visualization. Ashik C. Jayamon: Writing – review & editing, Vi-
sualization. Sai Chandra Teja R.: Conceptualization, Writing – review
& editing, Project administration, Supervision, Funding acquisition.
Ashudeb Dutta: Writing – review & editing, Funding acquisition.
Declaration of competing interest
The authors declare the following financial interests/personal rela-
tionships which may be considered as potential competing interests:
Prof Ashudeb Dutta reports financial support was provided by WxBunka
Foundation.
Data availability
No data was used for the research described in the article.
Acknowledgement
This research was supported by WNI WxBunka Foundation, Japan.
The authors acknowledge Prakash Goriparthi and Raviteja Sanampudi
for the layout design.
A. Mukherjee et al.
References
[1] G. Chowdary, A. Singh, S. Chatterjee, An 18 nA, 87% efficient solar, vibration
and RF energy-harvesting power management system with a single shared
inductor, IEEE J. Solid-State Circuits 51 (10) (2016) 2501–2513.
[2] S. Bose, T. Anand, M.L. Johnston, A 3.5 mV input, 82% peak efficiency
boost converter with loss-optimized MPPT and 50 mV integrated cold-start
for thermoelectric energy harvesting, in: 2019 IEEE Custom Integrated Circuits
Conference, CICC, IEEE, 2019, pp. 1–4.
[3] J. Goeppert, Y. Manoli, Fully integrated startup at 70 mV of boost converters
for thermoelectric energy harvesting, IEEE J. Solid-State Circuits 51 (7) (2016)
1716–1726.
[4] S. Bandyopadhyay, P.P. Mercier, A.C. Lysaght, K.M. Stankovic, A.P. Chan-
drakasan, A 1.1 nW energy-harvesting system with 544 pW quiescent power for
next-generation implants, IEEE J. Solid-State Circuits 49 (12) (2014) 2812–2824.
[5] R.L. Radin, M. Sawan, C. Galup-Montoro, M.C. Schneider, A 7.5-mV-Input boost
converter for thermal energy harvesting with 11-mV self-startup, IEEE Trans.
Circuits Syst. II 67 (8) (2020) 1379–1383.
[6] R.L. Radin, M.B. Machado, M. Sawan, C. Galup-Montoro, M.C. Schneider, Ultra-
low-voltage oscillators, in: Ultra-Low Voltage Circuit Techniques for Energy
Harvesting, Springer, 2022, pp. 25–52.
[7] S. Bose, M.L. Johnston, A stacked-inverter ring oscillator for 50 mV fully-
integrated cold-start of energy harvesters, in: 2018 IEEE International Symposium
on Circuits and Systems, ISCAS, IEEE, 2018, pp. 1–5.
[8] R. Matsuzuka, T. Terada, K. Matsumoto, M. Kitamura, T. Hirose, A 42 mV startup
ring oscillator using gain-enhanced self-bias inverters for extremely low voltage
energy harvesting, Japan. J. Appl. Phys. 59 (SG) (2020) SGGL01.
Microelectronics Journal 139 (2023) 105883
[9] M. Nishi, K. Matsumoto, N. Kuroki, M. Numa, H. Sebe, R. Matsuzuka, O. Maida,
D. Kanemoto, T. Hirose, A 34-mV startup ring oscillator using stacked body bias
inverters for extremely low-voltage thermoelectric energy harvesting, in: 2020
18th IEEE International New Circuits and Systems Conference, NEWCAS, IEEE,
2020, pp. 38–41.
[10] N. Lotze, Y. Manoli, Ultra-sub-threshold operation of always-on digital circuits
for IoT applications by use of schmitt trigger gates, IEEE Trans. Circuits Syst. I.
Regul. Pap. 64 (11) (2017) 2920–2933.
[11] B. Razavi, Design of Analog CMOS integrated circuits the McGraw-Hill
Companies, Inc.., United States, 2001.
[12] R.M. Swanson, J.D. Meindl, Ion-implanted complementary MOS transistors in
low-voltage circuits, IEEE J. Solid-State Circuits 7 (2) (1972) 146–153.
[13] J.D. Meindl, J.A. Davis, The fundamental limit on binary switching energy
for terascale integration (TSI), IEEE J. Solid-State Circuits 35 (10) (2000)
1515–1516.
[14] B. Zhai, D. Blaauw, D. Sylvester, K. Flautner, The limit of dynamic voltage scaling
and insomniac dynamic voltage scaling, IEEE Trans. Very Large Scale Integr.
(VLSI) Syst. 13 (11) (2005) 1239–1252.
[15] T.D. Fernandes, C. Galup-Montoro, M.C. Schneider, Analysis and design of the
three-inverter schmitt trigger for supply voltages down to 50 mv, IEEE Trans.
Circuits Syst. II 68 (7) (2021) 2302–2306.
[16] L.A.P. Melek, A.L. da Silva, M.C. Schneider, C. Galup-Montoro, Analysis and
design of the classical CMOS schmitt trigger in subthreshold operation, IEEE
Trans. Circuits Syst. I. Regul. Pap. 64 (4) (2016) 869–878.