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be_computer-engineering_semester-3_2023_october_digital-electronics-and-logic-design-deld-pattern-2019
be_computer-engineering_semester-3_2023_october_digital-electronics-and-logic-design-deld-pattern-2019
be_computer-engineering_semester-3_2023_october_digital-electronics-and-logic-design-deld-pattern-2019
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P-5397 [Total No. of Pages : 2
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S.E. (Computer Engineering) (Insem.)
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DIGITAL ELECTRONICS AND LOGIC DESIGN
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(2019 Pattern) (Semester - III) (210245)
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Time : 1 Hour] [Max. Marks : 30
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2) Neat diagrams must be drawn wherever necessary.
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Q1) a) Simplify the following function F(A, B, C, D) = å m(0, 2, 4, 5, 6, 7, 8,
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b) Simplify the following function [5]
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b) Simplify the following function [5]
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F(w, x, y, z) = å m(4, 5, 7, 12, 14, 15) +d(3, 8, 10)
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Q3) a) Draw and explain 4-bit BCD adder using IC 7483. Explain any two BCD
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Q4) a) Design a 4 bit BCD to Excess-3 code converter circuit using logic gates.[5]
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[5]
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Q5) a) What do you mean by half adder and full adder? How will you implement
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full adder using half adder? Draw the circuit diagram. [5]
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b) Convert the following expressions into their standard SOP form [5]
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i) Y = AB + AC + BC
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ii) Y = A + BC + ABC
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OR
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Q6) a) 3/1 13
Minimize the function using K-map and implement Using NAND gates,
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F(A, B, C, D) = å m(4, 5, 6, 7, 8, 12) +d(1, 2, 3, 9, 11, 14).
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[5]
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