COA Assignment

AND GATE
An AND gate is an electrical circuit that combines two signal and
gives one output signal. The output of the AND gate is connected to
a base driver which is coupled to the bases of transistors, and
alternately switches the transistors at opposite corners of the
inverter.

 Code for DataFlow:

entity and_df is:

port ( a : in STD_LOGIC;

b : in STD_LOGIC;

c : out STD_LOGIC );

end and_df;

architecture dataflow of and_df is

begin

c <= a and b;

end dataflow;

 Code for TestBench:

entity and_tb is

end and_tb;

architecture Behavioral of and_tb is

component and_df is

port ( a : in STD_LOGIC;

b : in STD_LOGIC;

c : out STD_LOGIC );

end component;
signal a1:std _logic:=’0’;

signal b1:std _logic:=’0’;

signal c1:std _logic;

begin

uut:and_df port map (a=>a1,b=>b1,c=>c1);

stim_proc:process

begin

wait for 100ns;

a<=’0’;

b<=’1’;

wait for 100ns;

a<=’1’;

b<=’0’;

wait for 100ns;

a<=’1’;

b<=’1’;

wait;

end process;

end behavioral;

Circuit Diagram:
OR GATE
OR gate is the type of Logic Gate which combines two input and
gives one output. When at least one of the provided inputs is high
then the output is high otherwise it’s low.

 Code for DataFlow:

entity or_df is:

port ( a : in STD_LOGIC;

b : in STD_LOGIC;

c : out STD_LOGIC );

end or_df;

architecture dataflow of or_df is

begin

c <= a or b;

end dataflow;

 Code for TestBench:

entity or_tb is

end or_tb;

architecture Behavioral of or_tb is

component or_df is

port ( a : in STD_LOGIC;

b : in STD_LOGIC;
 c : out STD_LOGIC );

end component;

signal a1:std _logic:=’0’;

signal b1:std _logic:=’0’;

signal c1:std _logic;

begin

uut:or_df port map (a=>a1,b=>b1,c=>c1);

stim_proc:process

begin

wait for 100ns;

a<=’0’;

b<=’1’;

wait for 100ns;

a<=’1’;

b<=’0’;

wait for 100ns;

a<=’1’;

b<=’1’;

wait;

end process;

end behavioral;

Circuit Diagram:
NAND GATE
The NAND gate is the combination of two basic logic gates, the AND

gate and the NOT gate connected in series.It combines two input
and gives one output.

 Code for DataFlow:

entity nand_df is:

port ( a : in STD_LOGIC;

b : in STD_LOGIC;

c : out STD_LOGIC );

end nand_df;

architecture dataflow of nand_df is

begin

c <= a nand b;

end dataflow;

 Code for TestBench:

entity nand_tb is
end nand_tb;

architecture Behavioral of nand_tb is

component nand_df is

port ( a : in STD_LOGIC;

b : in STD_LOGIC;

c : out STD_LOGIC );

end component;

signal a1:std _logic:=’0’;

signal b1:std _logic:=’0’;

signal c1:std _logic;

begin

uut:nand_df port map (a=>a1,b=>b1,c=>c1);

stim_proc:process

begin

wait for 100ns;

a<=’0’;

b<=’1’;

wait for 100ns;

a<=’1’;

b<=’0’;

wait for 100ns;

a<=’1’;

b<=’1’;

wait;

end process;

end behavioral;
Circuit Diagram:

NOR GATE
The NOR gate is the combination of two basic logic gates, the OR

gate and the NOT gate connected in series. It combines two input
and gives one output.

 Code for DataFlow:

entity nor_df is:

port ( a : in STD_LOGIC;

b : in STD_LOGIC;

c : out STD_LOGIC );

end nor _df;

architecture dataflow of nor_df is

begin

c <= a nor b;

end dataflow;

 Code for TestBench:

entity nor_tb is

end nor_tb;

architecture Behavioral of nor_tb is

component nor_df is

port ( a : in STD_LOGIC;

b : in STD_LOGIC;

c : out STD_LOGIC );

end component;

signal a1:std _logic:=’0’;

signal b1:std _logic:=’0’;

signal c1:std _logic;

begin

uut:and_df port map (a=>a1,b=>b1,c=>c1);

stim_proc:process

begin

wait for 100ns;

a<=’0’;

b<=’1’;

wait for 100ns;

a<=’1’;

b<=’0’;

wait for 100ns;

a<=’1’;

b<=’1’;

wait;

end process;
end behavioral;

Circuit Diagram:

XOR GATE
It is a logical “exclusive OR” function. For two given logical statements, the
XOR function would return TRUE if one of the statements is true and FALSE if
both statements are true. If neither of the statements is true, it also returns
FALSE.

 Code for DataFlow:

entity xor_df is:

port ( a : in STD_LOGIC;

b : in STD_LOGIC;

c : out STD_LOGIC );

end xor_df;

architecture dataflow of xor_df is

begin

c <= a xor b;

end dataflow;
  Code for TestBench:
entity xor_tb is

end xor_tb;

architecture Behavioral of xor_tb is

component xor_df is

port ( a : in STD_LOGIC;

b : in STD_LOGIC;

c : out STD_LOGIC );

end component;

signal a1:std _logic:=’0’;

signal b1:std _logic:=’0’;

signal c1:std _logic;

begin

uut:xor_df port map (a=>a1,b=>b1,c=>c1);

stim_proc:process

begin

wait for 100ns;

a<=’0’;

b<=’1’;

wait for 100ns;

a<=’1’;

b<=’0’;

wait for 100ns;

a<=’1’;

b<=’1’;

wait;
end process;

end behavioral;

Circuit Diagram:

XNOR GATE
An XNOR gate (Exclusive NOR gate) is a digital logic gate with two input and
one output that performs logical equality. The output of an XNOR gate is true
when both inputs are true or when both inputs are false.

 Code for DataFlow:

entity xnor_df is:

port ( a : in STD_LOGIC;

b : in STD_LOGIC;

c : out STD_LOGIC );

end xnor_df;

architecture dataflow of xnor_df is

begin

c <= a xnor b;
end dataflow;

 Code for TestBench:

entity xnor_tb is

end xnor_tb;

architecture Behavioral of xnor_tb is

component xnor_df is

port ( a : in STD_LOGIC;

b : in STD_LOGIC;

c : out STD_LOGIC );

end component;

signal a1:std _logic:=’0’;

signal b1:std _logic:=’0’;

signal c1:std _logic;

begin

uut:xnor_df port map (a=>a1,b=>b1,c=>c1);

stim_proc:process

begin

wait for 100ns;

a<=’0’;

b<=’1’;

wait for 100ns;

a<=’1’;

b<=’0’;

wait for 100ns;

a<=’1’;

b<=’1’;
wait;

end process;

end behavioral;

Circuit Diagram:

NOT GATE
A NOT gate (Inverter Gate) is a logic gate. Each NOT gate has only one input
signal and one output signal.

 Code for DataFlow:

entity not_df is:

port ( a : in STD_LOGIC;

c : out STD_LOGIC );

end not_df;

architecture dataflow of not_df is

begin

c <= not a;

end dataflow;
  Code for TestBench:
entity not_tb is

end not_tb;

architecture Behavioral of not_tb is

component not_df is

port ( a : in STD_LOGIC;

c : out STD_LOGIC );

end component;

signal a1:std _logic:=’0’;

signal c1:std _logic;

begin

uut:not_df port map (a=>a1,c=>c1);

stim_proc:process

begin

wait for 100ns;

a<=’1’;

wait;

end process;

end behavioral;

Circuit Diagram: