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Lecture 12- Memory Technologies
Lecture 12- Memory Technologies
Rose Gomar
Department of Systems and Computer Engineering
Textbook/Copyright
• Hennessy, John L., and David A. Patterson. Computer architecture: a
quantitative approach. Elsevier, 6th edition, 2017, Chapter 2.
• Hennessy, John L., and David A. Patterson. Computer architecture: a
quantitative approach. Elsevier, 6th edition, Appendix B.
• Hennessy, John L., and David A. Patterson, Computer Organization and
Design: RISC-V edition, Chapter 5.
• Part of the slides are provided by Elsevier (Copyright © 2019, Elsevier
Inc. All rights reserved)
2
What we learn in this lecture?
• Memory technologies
• Memory Hierarchy
• Motivation for cache
• Caches
3
The Three Main Memory Categories
• Generally, there are three categories of
memory inside a computer system:
➢ CPU memory
➢ Main memory
➢ Secondary memory
5
The Three Main Memory Categories
• Generally, there are three categories
of memory inside a computer system:
➢ CPU memory
➢ Main memory
➢ Secondary memory
6
The Three Main Memory Categories
• Generally, there are three categories
of memory inside a computer system:
➢ CPU memory
➢ Main memory
➢ Secondary memory
8
Memory Technologies
• Random Access Memory (RAM)
• SRAM (Static RAM)
• DRAM (Dynamic RAM)
• Read Only Memory (ROM)
• Flash Storage
• A type of EEPROM
• Magnetic Disk
• Why do we need different memory technologies?
• Designers always want unlimited fastest memory!
• SRAM is the fastest but the most expensive one!
• DRAM is slower but less expensive
• Flash and magnetic will provide even more capacity
9
A Simple Memory Model
• Not a good model for big capacities
• Very slow (why?)
Write
data
Read
Write
Read data
Memory
Address
clk CLK
Read
address
Decoder
Write address
10
Main Memory Arrays
• Efficiently store large amounts of data
N
• 3 common types: Address Array
– Dynamic random-access memory
(DRAM)
– Static random-access memory (SRAM)
M
– Read only memory (ROM)
Data
• M-bit data value read/written at each unique N-bit
address
11
Main Memory Arrays
• Efficiently store large amounts of data
N
• 3 common types: Address Array
– Dynamic random-access memory (DRAM)
– Static random-access memory (SRAM)
– Read only memory (ROM) M
• M-bit data value read/written at each unique N-bit
address Data
• 2-dimensional array of bit cells Address Data
• Each bit cell stores one bit 11 0 1 0
2
• N address bits and M data bits: Address Array 10 1 0 0
depth
– 2N rows and M columns 01 1 1 0
– Depth: number of rows (number of words) 3 00 0 1 1
– Width: number of columns (size of word)
Data width
– Array size: depth × width = 2N × M
12
Memory Cell Access
• Cells are accessed using wordline and bitline
bitline
wordline
stored
bit
bitline = bitline =
wordline = 1 wordline = 0
stored stored
bit = 0 bit = 0
bitline = bitline =
wordline = 1 wordline = 0
stored stored
bit = 1 bit = 1
(a) (b)
15
Memory Cell Access
• Cells are accessed using wordline and bitline
bitline
wordline
stored
bit
bitline = 1 bitline = Z
wordline = 1 wordline = 0
stored stored
bit = 1 bit = 1
(a) (b)
16
Memory Array Layout
• Memory Array with Address Decoder
2:4
Decoder bitline2 bitline1 bitline0
wordline3
11
2 stored stored stored
Address bit = 0 bit = 1 bit = 0
wordline 2
10
stored stored stored
wordline1 bit = 1 bit = 0 bit = 0
01
stored stored stored
bit = 1 bit = 1 bit = 0
wordline0
00
stored stored stored
bit = 0 bit = 1 bit = 1
17
Memory Arrays
One Memory cell
Row Decoder
Column
Decoder
18
Main Memory: Static RAM
• Main Memory: Static RAM. This is the
type of RAM in which data is held until
power is removed from it. One memory
cell (bit) of SRAM consists of at least 6
transistors (6 T memory cell).
19
Main Memory: Static RAM
• Main Memory: Static RAM. This is the type of
RAM in which data is held until power is
removed from it. One memory cell (bit) of
SRAM consists of at least 6 transistors (6 T
memory cell).
• SRAM data is organized into cells.
One SRAM Cell
• Cells are organized into arrays where
address decoders determines the row and
column of the desired information.
22
Static RAM Write Cycles
• The steps of a write cycle of SRAM:
➢ Place the address to be written to on the address
bus.
➢ Ensure that the chip is activated by making CS low.
➢ Place the data to be written on the data bus.
➢ Activate the WR line. Only then the data is valid.
23
DRAM Technology
• Data stored as a charge in a capacitor
• Single transistor used to access the charge
• Must periodically be refreshed
• Read contents and write back A DRAM cell. Very economic compared to
• Performed on a DRAM “row” SRAM that has 6 or more Transistors per cell
26
Main Memory: Dynamic RAM
• Read Cycle of DRAM : a processor when
addressing memory sends the complete
address on its address pins
• Between the processor and a DRAM chip,
there is a memory controller whose function
is to split the address into two, as columns
and rows. Memory controller for a DRAM
27
DRAM Read Cycle
6) The CAS pin also serves as the Output Enable; so, once the
CAS signal has stabilized, the sense amps place the data
from the selected row and column on the data bus.
29
DRAM Refreshing
• DRAM Refreshing Hints:
• Rate: It varies, but typically manufacturers specify
that each row should be refreshed every 64 ms.
• How is refreshing done: by activating each
31
Advanced DRAM Organization
• Bits in a DRAM are organized as a rectangular array
• DRAM accesses an entire row
• Synchronous DRAM
• Allows for consecutive accesses in bursts without needing to send
each address
• Improves bandwidth
• Double data rate (DDR) DRAM
• Transfer on rising and falling clock edges
• Quad data rate (QDR) DRAM
• Separate DDR inputs and outputs
33
ROM (Read Only Memory)
• Main Memory: ROM (Read Only Memory): This
is ‘Read Only Memory’. A ROM does not lose its
contents when power is switched off. ROM is a
type of ‘programmable’ memory. It has internal
fuses which when blown create a bit pattern
which is permanent and hence can be read
whenever needed. However, if it is an OTP (one
time programmable) ROM, its contents can
never be changed again.
Categorization of main memory types
• EPROMs are ‘Erasable and Programmable’
exposing them to ultraviolet radiation. EEPROM technology is used for BIOS ROMs
• EEPROM: This is ‘Electrically Erasable’ PROM, in personal computers.
and erasure can be done while on circuit board.
• Flash ROM: This is a special type of EEPROM Flash ROM technology is used in
that can be erased and reprogrammed in blocks microcontrollers and embedded computer
instead of one byte at a time. This feature gave systems
flash memory the advantage of speed over
EEPROM.
34
Flash Storage
• Nonvolatile semiconductor storage
• 100× – 1000× faster than disk
• Smaller, lower power, more robust
• But more $/GB (between disk and DRAM)
• Popular in personal mobile devices
Flash Types
• NOR flash: bit cell like a NOR gate
• Random read/write access
• Used for instruction memory in embedded systems
• NAND flash: bit cell like a NAND gate
• Denser (bits/area), but block-at-a-time access
• Cheaper per GB
• Used for USB keys, media storage, …
More information on :
https://www.youtube.com/watch?v=NtPc0jI21i0
A bit on SSD: https://www.youtube.com/watch?v=5Mh3o886qpg
Summary
• Memory technologies
• RAM
SRAM
DRAM
• ROM
• Secondary storages
Future lecture
• Principles of locality
• Caches