Lecture 10_ARM Interrupt

Department of Systems and Engineering
Design, Carleton University
SYSC 3320 Computer Systems Design
Interrupt Concept and ARM Interrupt

Handling Process
What we learn in lecture 10
• Interrupt concept
• Interrupt types
• Interrupt handling mechanism
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Copyright
• Credit for lecture notes: Dr. Mohamed Atia
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Motivation for Interrupt
• How does a calculator handle unexpected events such as an accidental division
by zero or a button press?
― Division by zero: The programmer could forcefully check the operation performed
each time
― Button press on Keyboard: The programmer could poll the buttons, constantly
checking to see if they are pressed (e.g. in a while loop)
• Neither solution is effective and wastes a substantial amount of time to check
for specific scenarios
• Processors use a mechanism called interrupts to deal with these unexpected
events
• The idea is that the processor is interrupted from executing its code
― The processor finishes executing the current instruction then proceeds to deal with
the interrupt
Interrupt Concept
• The Keyboard Example:
• Using interrupts, a program waiting for a key-press from the user will not
prevent the processor from doing other tasks such as refreshing monitor,
responding to mouse clicks, writing in a word editor, …etc.
Polling I/O: Processor repeats the “Was a key pressed?” until a response is received
Interrupt I/O: keyboard will notify the processor when “a key is pressed”
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Interrupt: An Analogy
• Assume you are watching TV,
• You expect to receive an important phone call
• What is the best approach?
• Constantly watching your phone to see if you receive the call
• Continue watching TV, you are notified by your phone ring when you
receive the call
• The phone ring is an analogy for interrupt signal
• Now assume you receive a call, but its not the one you expect, and it is not
that important and you can ignore it for now and call to that person later
• This is an analogy for maskable interrupt
• Assume you receive the important call, in this case you stop watching TV and
take this really important call, and after the call, you continue watching TV
• This is an analogy for non-maskable interrupt
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Types of Interrupts
• Interrupts can be generated by external hardware units (i.e. peripherals ) and also
from within the system (i.e.. internal).
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Types of Interrupts
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Types of Interrupts
• Peripherals interrupts are commonly called hardware interrupts. In hardware
interrupts, an interrupt signal is an asynchronous signal that is generated by a
hardware unit to indicate the need for the processor attention.
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Types of Interrupts
• Internal interrupts some times come from internal components (e.g. DMA controller)
or software interrupts where an interrupt is also an asynchronous event which
indicates to the processor that a change in normal execution is needed (e.g. division by
zero or unauthorized access to a protected memory region).
• Question: How the processor handles multiple interrupts at the same time?
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Types of Interrupts
• Internal interrupts some times come from internal components (e.g. DMA controller)
or software interrupts where an interrupt is also an asynchronous event which
indicates to the processor that a change in normal execution is needed (e.g. division by
zero or unauthorized access to a protected memory region).
• Example: ARM A9 Interrupt Systems
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Interrupt-based I/O
• Interrupt-based I/O: To avoid wasting CPU time in just waiting for a device, a better
mechanism is to offload the CPU from waiting and let the I/O device notify the CPU
when it is ready.
• Instead of waiting, the CPU will switch to another useful task until the device sends
a notification.
• This notification is called an interrupt request to the CPU. When the CPU receives an
interrupt request, it will switch to the I/O operation.
• In this way, a program waiting for a key-press from the user for example will not
prevent the CPU from doing other tasks such as refreshing monitor, responding to
mouse clicks, writing in a word editor, …etc.
• This “switch” between tasks, is the key for multi-tasking. Therefore, multitasking and
interrupts are closely related concepts.
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ARM Interrupts Handling Mechanism
• ARM Cortex-A9 Dual Core Interrupt handling
➢ Internal Interrupts
o Some are coming from software (i.e., programs that trigger an error)
o Others are coming from system sub-components such as
• Memory management unit “MMU”
• Timers (will be used in Lab 5)
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Sources of Interrupts
• ARM Cortex-A9 Dual Core Interrupt handling
➢ Internal Interrupts
o Some are coming from software (i.e., programs that trigger an error)
o Others are coming from system sub-components such as
• Memory management unit “MMU”
• Timers (will be used in Lab 5)
➢ External Interrupts (coming from I/O device):

o GPIO
o Bush-buttons/Switches
o USB or UART Ports
o SPI or I2C Ports
o Camera Sensor
o Temperature Sensor
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Types of Hardware Interrupts
• Hardware interrupts can be further categorised into the following types
➢Maskable Interrupts (IRQs) — The trigger event of a masked interrupt is not always
important. It is up to the programmer to decide whether the event should cause the
program to jump to the requested execution or not. Examples of devices which may
use maskable interrupts include timers, comparators and ADCs.
➢Non-Maskable Interrupts (NMIs) — These are interrupts which should never be
ignored, and are therefore deemed much more important than maskable interrupts.
Events which require NMIs include power-on, external reset (from a physical button)
and serious device faults.
➢Inter-Processor Interrupts (IPIs) — In multiple processor systems, one processor
may need to interrupt the operation of another processor. In this situation, an IPI will
be generated
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• ARM Interrupt Handling has the following general basic components
➢ Vector Table: Saves Interrupt Service Routine “ISR” Addresses
➢ Interrupt Service Routine (ISR): The program that will run when the interrupt occurs
➢ Interrupt Controller: The unit that will manage and prioritize multiple interrupts
➢ Processor Interrupt Registers: Registers used to store interrupt request information
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• ARM Interrupt Handling has the following general basic components
➢ Vector Table: Saves Interrupt Service Routine “ISR” Addresses
➢ Interrupt Service Routine (ISR): The program that will run when the interrupt occurs
➢ Interrupt Controller: The unit that will manage and prioritize multiple interrupts
➢ Processor Interrupt Registers: Registers used to store interrupt request information
• These basic components are shown in the following figure

Memory
Peripheral or
I/O Device
Interrupt Signal
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• ARM Interrupt Handling Basic Components
Vector table and service routine are stored in

the memory.
Peripheral or I/O
Device
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ARM modes of operation
• The ARM processor must work under a
specific mode to handle interrupts
• The ARM Cortex-A9 has several main
modes of operation, listed below:
➢ User mode
➢ System mode
➢ Supervisor mode
➢ Abort mode
➢ Undefined mode
➢ IRQ mode (Interrupt Mode)
➢ FIQ mode (Fast Interrupt Mode)
• The operating mode of the processor

is indicated in the Current Processor
Status Register CPSR
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• Depending on the processor mode, registers
available to the software running on the
microprocessor will differ.
The ARM Cortex-A9 Registers in different modes
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• The figure shows the general-purpose registers
in a Cortex-A9 processor, and illustrates how
the registers are related to the processor
mode.
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mode.
• In User mode, there are 16 registers, R0-R15,
plus the CPSR.
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mode.
plus the CPSR.
• Supervisor mode has additional (banked copies
of) stack pointer and link register that are used
only when the processor is in this mode.
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mode.
plus the CPSR.
• Supervisor mode has additional (banked copies
of) stack pointer and link register that are used
only when the processor is in this mode.
• Different modes have different banked copies
of other registers
• The CPSR register is common for all modes, but
when the processor is switched from one
mode into another, the current content of the The ARM Cortex-A9 Registers in different modes
CPSR is copied into the new mode’s saved
processor status register (SPSR)
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• The Cortex-A9 processor enters IRQ mode in response to receiving an
IRQ signal from the GIC (Generic Interrupt Controller). In the
system booting, the following configuration steps are performed:
1) Disable interrupts by setting the IRQ disable bit in the
CPSR to 1.
2) Configure the GIC by assigning for each I/O device a unique
interrupt ID.
3) Configure each I/O peripheral device to send IRQ interrupt
requests to the GIC.
4) Enable interrupts by setting the IRQ disable bit in the CPSR
to 0.
• In complex processor systems like the ARM A9, the code that
implements these steps is given to the programmer as a library that
comes with the hardware to facilitate interrupts handling. This is the
initialization code generated by Vivado IDE in Lab 5 to initialize GIC.
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• Cortex-A9 Interrupt handling
➢Vector Table tells the processor where to find the interrupt service routine (ISR) of
an IRQ signal of a specific interrupt ID . The Vector Table is part of the processor
memory that can be accessed by the software that initializes the GIC.
Memory
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• Cortex-A9 Interrupt handling
➢ Interface between HW and SW.
Vector Table
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• Cortex-A9
Interrupt handling
• ARM IRQ Handler Notice here we
are using the
is given by the link register
System Code (LR_irq) twice
• C Subroutine is the
User’s Code for this
Interrupt
• Both System code
and User code are
blended together
to have a working
software on the
system
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Steps of ARM Interrupts Handling Mechanism
• 1) Acceptance of Interrupt : The processor
accepts an Interrupt/exception if the
following conditions are met: Reset
➢ The processor is running
➢ The interrupt/exception is enabled
User Mode
(NMI is always enabled)
➢The interrupt/exception has higher

priority than the currently ISR priority Exception Starting
(if any) Processing Exception
Completed Processing
➢ The interrupt/exception is enabled
• The normal user application model of the
processor is called “user” mode. When the IRQ Mode
processor accepts a “system” exception, it
switches to a privileged mode called “IRQ”
mode.
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Stack pointer before Stacking
• 2) Interrupt (or Exception) Entrance Sequence

➢Stacking of a number of registers, including
return address to the currently selected
stack. This enables an interrupt/exception
handler to be written as a normal C
function.
Stack pointer after stacking
➢Fetching the interrupt/exception vector
(starting address of the exception
handler/ISR) from the IVT (Vector Table).
➢Fetching instructions of
interrupt/exception handler to be executed.
After the starting address of the handler is
determined, the instructions can be
fetched.
➢Update of various status and control
registers like Program Status Register (PSR),
Link Register (LR), Program Counter (PC),
and Stack Pointer (SP).
IVT (Vector Table)
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Stack pointer before Stacking
• 2) Interrupt (or Exception) Entrance Sequence

➢Stacking of a number of registers, including
return address to the currently selected
stack. This enables an interrupt/exception
handler to be written as a normal C
function.
Stack pointer after stacking
➢Fetching the interrupt/exception vector
(starting address of the exception
handler/ISR) from the IVT (Vector Table).
➢Fetching instructions of
interrupt/exception handler to be executed.
After the starting address of the handler is
determined, the instructions can be
fetched.
➢Update of various status and control
registers like Program Status Register (PSR),
Link Register (LR), Program Counter (PC),
and Stack Pointer (SP).
IVT (Vector Table)
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• 3) Interrupt (or Exception) Handler Execution
➢Within the handler, you can carry out
services for the peripheral that requires
service
➢If a higher-priority exception arrives during
this stage, the new interrupt will be
accepted, and the currently executing
handler will be suspended and pre-empted
by the higher-priority handler. This is called
a nested interrupt.
➢If another exception with the same or
lower priority arrives during this stage, the Snapshot of Keil IDE that shows stacked
newly arrived exception will stay in the registers in exception handling
pending state and will be serviced when the
current exception handler is completed.
ISR (or handler) may save additional
➢At the end of the ISR, it executes a return registers on stack. For example, if ISR calls
that causes the EXC_RETURN (Exception or a subroutine, LR must be stacked.
ISR Return)
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• 3) Interrupt (or Exception) Handler Execution
➢Within the handler, you can carry out
services for the peripheral that requires
service
➢If a higher-priority exception arrives during
this stage, the new interrupt will be
accepted, and the currently executing
handler will be suspended and pre-empted
by the higher-priority handler. This is called
a nested interrupt.
➢If another exception with the same or
lower priority arrives during this stage, the Snapshot of Keil IDE that shows stacked
newly arrived exception will stay in the registers in exception handling
pending state and will be serviced when the
current exception handler is completed.
ISR (or handler) may save additional
➢At the end of the ISR, it executes a return registers on stack. For example, if ISR calls
that causes the EXC_RETURN (Exception or a subroutine, LR must be stacked.
ISR Return)
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• 4) Interrupt/Exception Return
➢The interrupt/exception return mechanism is triggered
using a special return address called EXC_RETURN.
➢Return address is generated at interrupt/exception entrance
and is stored in the Link Register (LR). When this value is
written to the PC with one of the allowed exception return
instructions, it triggers the interrupt/exception return
sequence.
➢When the interrupt/exception return mechanism is
triggered, the processor accesses the previously stacked
register values in the stack memory during exception
entrance and restores them back to the register bank. This is
called unstacking. In addition, a number of GIC registers
(e.g., active status) and registers in the processor core will be
updated
➢In addition to the unstacking operation, the processor start
fetching the instructions of the previously interrupted
program to allow the program to resume operation. Snapshot of Keil IDE that
shows the effect of returning
from exception handling
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• Interrupt Handling State Machine
➢ Initially all interrupts are inactive
➢ Once an interrupt is received, it will
be initially “pending” until the GIC
checks the following:
o The interrupt is enabled
o The interrupt is of higher priority
➢ If the interrupt was not previously
active, it will go to active
➢ If an interrupt was active when a new

higher priority interrupt came, it will
go to active and pending
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• Summary of interrupt handling scenario. Conventionally, note that when an
interrupt is active, you cannot accept the same interrupt request again until it
has completed and terminated with an exception return (sometimes called an
exception exit).
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Input/output and Peripherals Interfacing on Zynq
• Any computer system (conventional or SoC)
needs a communication mechanism to exchange
information between different components.
• Information exchange can happen between
➢ The system and the outside world (e.g. Peripherals)
➢ The PS and the PL parts of the system (e.g. Accelerators)
➢ Within the PS or PL internal components (e.g.
Processor/Memory)
• In the figures, solid dark lines show the general
Input/output interfacing within the computer
system
• Regardless of the technology (SoC or others),
Input/output design has common concepts. We
will go through them broadly and then we will
study some specific I/O techniques designed for
SoC computer systems
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Generic Interrupt Controller (GIC)
• ARM Generic Interrupt Controller (GIC): If more than one processor

cores exist, the GIC has a Dispatcher component to CPU Interface
component as shown in the figures
➢ Dispatcher: distribute incoming interrupts to different CPUs
➢ CPU Interface: handle interrupt interface for each individual CPU
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Details of the GIC (Generic Interrupt Controller)
• Shared vs. Private Interrupts: In SoCs with more than one processor core (like
the Zynq device used in the lab that uses two Cortex-A9 cores), GIC distributes
different interrupts among processor cores (CPU interface 1 and CPU interface
0). Three categories of interrupts are distributed
➢ Private Peripheral Interrupts (PPIs)
o This is a peripheral interrupt that is
specific to a single processor
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oThis is a peripheral interrupt that is
➢ Shared Peripheral Interrupts (SPIs)

oThis is a peripheral interrupt that
the Distributor can route to any of a
specified combination of processor
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oThis is a peripheral interrupt that is
➢ Shared Peripheral Interrupts (SPIs)

oThis is a peripheral interrupt that
the Distributor can route to any of a
specified combination of processor
➢ Software Generated Interrupts (SGIs)

o Used also for interprocessor communication
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• Nested Interrupts: GIC Management of Multiple Interrupts

➢ GIC handles the masking of interrupts (checking if the interrupt is enabled or not)
➢GIC handles the prioritization of interrupts (highest priority interrupt can
interrupt a currently served interrupt. This is known as “nested interrupts”)
➢ GIC will decide which final interrupt request signal to be sent to the processor
GICD_CTLR:
GIC Distributor Control Register
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In a multiprocessor implementation, for PPIs and SGIs, the GIC can have
multiple interrupts with the same interrupt ID. Such an interrupt is called a
banked interrupt, and is identified uniquely by the combination of its
interrupt ID and its associated CPU who is handling this interrupt.
•Banked interrupt IDs:
• ID0-ID15 are used for SGIs
• ID16-ID31 are used for PPIs
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• GIC CPU Interface: The CPU Interface in the GIC is used to send IRQ
signals to the processor cores. There is one CPU Interface for each
processor core in the multicore SoC.
• The following registers are used in the CPU Interface component:
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Details of the CPU Interface
• The Interrupt Acknowledge Register (ICCIAR) contains the Interrupt ID

of the I/O peripheral that has caused an interrupt.
• When a processor core receives an IRQ signal from the GIC, software
code (i.e., the interrupt handler) running on the processor must read
the ICCIAR to determine which I/O peripheral has caused the interrupt
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• The CPU Interface Control Register (ICCICR) is used to enable
forwarding of interrupts from the CPU Interface to the
corresponding processor core. Setting bit E = 1 in this register enables
the sending of interrupts to the processor core, and setting E = 0 disables
these interrupts
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• End of Interrupt Register (ICCEOIR): After the processor core
has completed the handling of an IRQ interrupt generated by the GIC,
the processor core must then clear this interrupt from the CPU
Interface. This action is accomplished by writing the appropriate
Interrupt ID into the Interrupt ID field in the End of Interrupt Register
(ICCEOIR). After writing into the ICCEOIR, the interrupt handler
software can then return control to the previously-interrupted main
program.
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• The Interrupt Priority Mask Register (ICCPMR) is used to set a
threshold for the priority-level of interrupts that will be forwarded
by a CPU Interface to a processor core. Only interrupts that have a
priority level greater than the Priority field in ICCPMR will be sent to a
processor core by its CPU Interface.
• The lower the value of this field the greater the priority is. So, level 0 is
the highest priority and level 255 is the lowest. Setting the Priority field
in ICCPMR to the value 0 will prevent any interrupts from being
generated by the CPU Interface.
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• GIC Distributor for private
peripherals interrupts (PPIs):
• The Interrupt Set Enable Registers
(ICDISERn) are used to enable the
forwarding of each supported
interrupt from the Distributor to the
CPU Interface.
• In the same way, each interrupt can
be disabled by using the Interrupt
Clear Enable Registers (ICDICERn).
• The Interrupt Priority Registers
(ICDIPRn) are used to associate a
priority level with each individual
interrupt.
• The Interrupt Processor Targets
Registers (ICDIPTRn) are used to
specify the CPU interfaces to which
each interrupt should be forwarded.
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Thank You ☺
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Department of Systems and Engineering

Design, Carleton University

SYSC 3320 Computer Systems Design

Interrupt Concept and ARM Interrupt

• Timers (will be used in Lab 5)

• Timers (will be used in Lab 5)

➢ External Interrupts (coming from I/O device):

• These basic components are shown in the following figure

Vector table and service routine are stored in

• The operating mode of the processor

The ARM Cortex-A9 Registers in different modes

The ARM Cortex-A9 Registers in different modes

The ARM Cortex-A9 Registers in different modes

The ARM Cortex-A9 Registers in different modes

➢The interrupt/exception has higher

• 2) Interrupt (or Exception) Entrance Sequence

• 2) Interrupt (or Exception) Entrance Sequence

➢ If an interrupt was active when a new

• ARM Generic Interrupt Controller (GIC): If more than one processor

➢ Shared Peripheral Interrupts (SPIs)

➢ Shared Peripheral Interrupts (SPIs)

➢ Software Generated Interrupts (SGIs)

• Nested Interrupts: GIC Management of Multiple Interrupts

• The Interrupt Acknowledge Register (ICCIAR) contains the Interrupt ID

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