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Mm Solvedn
Mm Solvedn
PART A
3. Explain the procedure for generating physical address and generate the physical
address corresponds to the segment address 1055H and offset address 5555H
4. Explain the indexed addressing and based index addressing modes of 8086 with
examples
PART B
Answer any Two questions. Each carries 9 marks
5.
6.
PART C
Answer all questions. Each carries 3 marks
PART D
Answer any Two questions. Each carries 9 marks
12. What do you meant by an interrupt and how an interrupt is handled in 8086
13.
a. Write about memory mapped i/o and isolated i/o.
b. Interface Two 16X8 ROM and Two 32X8 RAM with 8086. Select the starting
address of EPROM suitably. The RAM address must start at 00000H.
14. Briefly explain the architecture of programmable input-output (8255)
PART E
15.
a. Write about Microcontrollers and its types. (4 marks)
b. Discuss the factors to be considered while selecting microcontrollers.
c. Mention the applications of Microcontrollers.
A macro call is an instruction to replace the macro name with its body, whereas
subroutine call is an instruction to transfer the program’s control to the subroutine’s
definition with all parameters, if required.
A macro call results in macro expansion, whereas subroutine call results in execution.
Macro expansion increases the size of the program but subroutine execution doesn’t
affect the size of the program
Macro expansion doesn’t affect the execution speed of the program much in comparison
to subroutines affect the execution speed of the program
2.
a. HOLD: Input signal to the processor form the bus masters as a request to grant the
control of the bus. Usually used by the DMA controller to get the control of the bus.
HLDA: Is an Acknowledgment signal from the processor for HOLD (1.5marks)
b. DEN (Data Enable): Output signal from the processor used as out put enable for the
transceivers and
BHE (Bus High Enable): It is used to enable data onto the most significant half of data
bus, D8-D15. 8-bit device connected to upper half of the data bus use BHE (Active Low)
signal. It is multiplexed with status signal S7. (1.5 mark)
4. Steps
1. Segment address shifted by 4 bit positions
2. Add shifted segment address with offset address (1 mark)
Problem (2 marks)
4 bit left shift segment address 0001 0000 0101 0101 0000 +
Offset address 0101 0101 0101 0101
PART C
8. NON-MASKABLE INTERRUPT (1.5 marks)
The processor has non-maskable interrupt pin (NMI) having higher priority than
the maskable interrupt request pin (INTR) and it is of type 2 interrupt.
Example TRAP
The NMI is activated on positive transition
MASKABLE INTERRUPT (1.5 marks)
A maskable interrupt is one that can be ignored by setting (or clearing) a bit in an
interrupt control register.
Example INTR
The INTR is a maskable interrupt because the microprocessor will be interrupted
only if interrupts are enabled using set interrupt flag instruction. It should not be
enabled using clear interrupt Flag instruction.
Fixed port addressing is of 8-bit. In this case, only the lower AX, that is, AL is
used. Here the address of the port is directly mentioned in the instruction
Example IN AL, 45H Move 8-bit data from an input port with the
address 45H
Variable Port Addressing (1.5 marks)
Each DMA channel has one DMA address register. The function of this register is to
store the address of the starting memory location, which will be accessed by the DMA
channel.
The mode set register is used for programming the 8257 as per the requirements of the
system. The function of the mode set register is to enable the DMA channels individually
and also to set the various modes of operation.
Status Register
The status register of 8257 is shown in figure. The lower order 4-bits of this register
contain the terminal count status for the four individual channels. If any of these bits is set,
it indicates that the specific channel has reached the terminal count condition.
1.ScannedKeyboardMode:
This mode allows a key matrix to be interfaced using either encoded or decoded
scans. In the encoded scan, an 8 x 8 keyboard or in decoded scan , a 4 x 8
Keyboard can be interfaced. The code of key pressed with SHIFT and CONTROL
status is stored into the FIFO RAM.
In this mode, a sensor array can be interfaced with 8279 using either encoder or
decoder scans. With encoder scan 8 x 8 sensor matrix or with decoder scan 4 x 8
sensor matrix can be interfaced .
3. Strobed Input :
In this mode, if the control line goes low, the data on return lines, is stored in the
FIFO byte by byte.
1. Display Scan:
In this mode, 8279 provides 8 or 16 character multiplexed displays those can be
organized as dual 4-bit or single 8-bit display units
2. Display Entry:
The Display data is entered for display either from the right side or from the left
side.
8086 Interrupts
We are aware of the fact that the interrupt can be either hardware or software.
If the interrupts are generated by the inbuilt devices, like timers or by the
interfaced devices, they are called as hardware interrupts.
NMI
It is a single non-maskable interrupt pin (NMI) having higher priority than the
maskable interrupt request pin (INTR)and it is of type 2 interrupt.
INTR
The INTR is a maskable interrupt because the microprocessor will be interrupted
only if interrupts are enabled using set interrupt flag instruction. It should not be
enabled using clear interrupt Flag instruction.
If the interrupts are generated by the software code, they are called as software
interrupts.
Whenever an interrupt occurs the processor completes the execution of the current
instruction and starts the execution of an Interrupt Service Routine (ISR) or
Interrupt Handler. ISR is a program that tells the processor what to do when the
interrupt occurs. After the execution of ISR, control returns back to the main
routine where it was interrupted.
The starting address of an ISP is often called the Interrupt Vector or Interrupt
Pointer. Therefore the table is referred as Interrupt Vector Table. In this table, IP
value is put in as low word of the vector & CS is put in high vector.
1.Isolated i/o(2.5marks)
b) explaining details(4.5marks)
This three-state bi-directional 8-bit buffer is used to interface the 8255 to the system
data bus. Data is transmitted or received by the buffer upon execution of input or output
instructions by the CPU. Control words and status informa-tion are also transferred
through the data bus buffer.
The function of this block is to manage all of the internal and external transfers of
both Data and Control or Status words. It accepts inputs from the CPU Address and
Control busses and in turn, issues commands to both of the Control Groups.
(CS) Chip Select. A "low" on this input pin enables the communcation between the 8255
and the CPU.
(RD) Read. A "low" on this input pin enables 8255 to send the data or status information
to the CPU on the data bus. In essence, it allows the CPU to "read from" the 8255.
(WR) Write. A "low" on this input pin enables the CPU to write data or control words
into the 8255.
(A0 and A1) Port Select 0 and Port Select 1. These input signals, in conjunction with the
RD and WR inputs, control the selection of one of the three ports or the control word
register. They are normally connected to the least significant bits of the address bus (A0
and A1).
(RESET) Reset. A "high" on this input initializes the control register to 9Bh and all ports
(A, B, C) are set to the input mode.
A1 A0 SELECTION
0 0 PORT A
0 1 PORT B
1 0 PORT C
1 1 CONTROL
Ports A, B, and C
The 8255 contains three 8-bit ports (A, B, and C). All can be configured to a wide variety
of functional characteristics by the system software but each has its own special features
or "personality" to further enhance the power and flexibility of the 8255.
Port A One 8-bit data output latch/buffer and one 8-bit data input latch. Both "pull-up"
and "pull-down" bus-hold devices are present on Port A.
Port B One 8-bit data input/output latch/buffer and one 8-bit data input buffer.
Port C One 8-bit data output latch/buffer and one 8-bit data input buffer (no latch for
input). This port can be divided into two 4-bit ports under the mode control. Each 4-bit
port contains a 4-bit latch and it can be used for the control signal output and status signal
inputs in conjunction with ports A and B.
PART E
15. Explain
a)
Microcontroller- A microcontroller (μC or uC) is a solitary chip microcomputer
fabricated from VLSI fabrication. A micro controller is also known as embedded
controller(.5marks)
functional unit(1.5marks)( CPUMemoryInput/output portsSerial Ports TimersADC
(Analog to digital converter)DAC (digital to analog converter) Interpret Control-Special
Functioning Block)
Microcontrollers are divided into categories according to their memory,
architecture, bits and instruction sets. So types of microcontrollers(2marks)
Bits:
1. 8 bits microcontroller executes logic & arithmetic operations. Intel
8031/8051.
2. 16 bits microcontroller executes with greater accuracy and performance in
contrast to 8-bit. Example Intel 8096.
3. 32 bits microcontroller is employed mainly in automatically controlled
appliances such as office machines, implantable medical appliances, etc.
Memory:
1.External Memory Microcontroller – When an embedded structure is built with
a microcontroller which does not comprise of all the functioning blocks
existing on a chip it is named as external memory microcontroller.
2.Embedded Memory Microcontroller – When an embedded structure is built
with a microcontroller which comprise of all the functioning blocks existing on
a chip it is named as embedded memory microcontroller.
Instruction Set:
1. CISC- CISC means complex instruction set computer.
2. RISC- RISC means Reduced Instruction Set Computers
Memory Architecture:
1. Harvard Memory Architecture Microcontroller
2. Princeton Memory Architecture Microcontroller
b)criteria
17. a)
explain five interrupts. They are maskable and vectored interrupts. Out of these five,
two are external interrupt and three are internal interrupts.
This is an 8 bit register used for setting the priority of the interrupts
b) writing program effectively(5 marks)
…………………………………………………………………….
Prepared By
MUMTHAS T.K, JINSHA K