Combinational Logic Circuits

DIGITAL AND ANALOG ELECTRONICS

Combinational logic circuits are one type of logic circuits, in which, the sequence of input does
not affect the output. The output is the same for a given combination of inputs regardless of
the order of application.
e.g.: Design XOR and XNOR gates using basic gate types.

1. XOR gate

2. XNOR gate

Converting truth tables into Boolean expressions

The process of designing a digital circuit starts with the requirement criteria. Normally, the
conditions will be given in the form of truth table, where, the designer should analyze it to
produce the circuit diagram. There are two methods to obtain Boolean expressions from truth
tables. This is the first step in converting the requirements of a digital circuit into design. The
two methods are,

1. Sum Of Products (SOP) / min-term

2. Product Of Sums (POS) / max-term
Sum of Products
Sum of products considers the combination of inputs for output ‘1’ and a Boolean product
term for that combination is written such that the output will equal to 1. After getting all the
expressions, they will be joined using Boolean addition.
e.g.: Three judges’ problem
There are three judges who are manipulating the performance of the participants in a reality
show. They will individually give their votes whether to select or reject a candidate. Each judge
has a switch to give his/her response. The decision of two or more judges (the majority) will
be taken as final decision. Design a logic circuit to fulfill the requirement.

X = A̅ BC + AB̅ C + ABC ̅ + ABC

Product of Sums
Product of sum considers the combination of inputs for output ‘0’ and a Boolean sum term
for that combination is written such that the output will equal to ‘0’. After getting all
expressions, they will be joined using Boolean multiplication.
e.g.: Three judges’ problem

X = (A+B+C). (A+B+C)̅ . (A+B̅ +C). (A̅ +B+C)

Circuit Minimization
The design process of digital circuits should be efficient and effective in the following aspects.

1. Propagation Delay
Every gate is made up of electronic devices. These devices need some time to stabilize
its output to the corresponding input. This time duration (or) the delay for the
propagation of result through the gate is called propagation delay. If more gates are
implemented, the propagation delay will be increased as every gate poses delay on
the propagation of the signal.

2. Cost
Gates are associated with its manufacturing cost. Hence, more gates would create
more expense for the design of the circuit.

3. Size
The final device should be compact in size. Reduction of gates would eliminate
unnecessary space.

4. Power consumption
If the number of gates were reduced, the power consumed by redundant gates can be
eliminated.
Circuit Minimization Techniques Boolean axioms
The Boolean identities can be applied to the expressions for the simplification process. e.g.:
Three judges’ problem

X = A̅ BC + AB̅ C + ABC ̅ + ABC

X = A̅ BC + AB̅ C + ABC ̅ + ABC + ABC + ABC (∵ A + A = A)
X = A̅ BC + ABC + AB̅ C + ABC + ABC ̅ + ABC
X = BC (A + A̅ ) + AC (B + B̅ ) + AB(C + C)̅ (∵ A + A̅ = 1)
X = BC + AC + AB
Karnaugh Map
Karnaugh map is a graphical technique used to simplify logic circuits.
Hamming distance and gray coding
Hamming distance is the number of bits which are different in between two binary strings
with same length.
e.g.:
11010110
01010100 H.D. = 2
Gray coding is the arrangement of the given binary strings in a sequence in which the hamming
distance in between successive strings are 1.
e.g.: Arrange all the binary strings created using 3 bits in Gray coding.
000 001 011 010 110 100 101 111
2-Variable karnaugh map

A B X
0 0 0
0 1 1
1 0 1
1 1 0

X = AB̅ + A̅ B
3-Variable karnaugh map
Consider the three judges’ problem

X = AB + AC + BC
Rules for the karnaugh map

• The square contain ‘1’ should be taken in simplifying, at least once.

• The square that contains ‘1’can be considered as many times as the grouping is
possible with it.
• Group shouldn’t include any zeros (0).
• A group should be as large as possible.
• Groups can be horizontal or vertical. Grouping of variables in diagonal manner is not
allowed.
• If the square containing ‘1’ has no possibility to be placed in a group, then it should be
added to the final expression.
• Groups can overlap.
• The number of squares in a group must be equal to powers of 2, such as 1, 2, 4, 8 etc.
• Groups can wrap around. As the K-map is considered as spherical or folded, the
squares at the corners (which are at the end of the column or row) should be
considered as the adjacent squares.
• The grouping of K-map variables can be done in many ways, so the obtained simplified
equation need not to be unique always.
• The Boolean equation must be in canonical form, in order to draw a K-map.
Large Karnaugh maps
Karnaugh map becomes difficult to solve if the number of variables increased. Therefore, the
karnaugh map is split for easy manipulation.
Don’t care combination
In digital logic, for some combinations of inputs the outputs are not expected. Similarly, some
input combinations will never happen. These conditions are generally stated as don’t care
combinations. This condition is denoted by ‘×’ symbol. The designer can choose the output
condition such that it will result in a minimized circuit.
e.g.: BCD to SSD example
Universal property of NAND and NOR gates
Even though there are different types of gates, some gates can be realized through other gates
as well. This phenomenon has led to consider logic circuit design using a single type of gate.
There are two different gates which could be used for this purpose because they are easier to
fabricate.

• NAND gate
• NOR gate
Circuit realization using only one type of gate can be greatly benefitted in circuit designing
procedure as only one type of gate is needed to be manufactured. This could reduce the cost
associated with the circuit designing.
NAND only implementation
Every gate will have a circuit representation with NAND gates only.
e.g.: Implement the logic circuit for three judges’ problem using NAND gates only.
X = AB + AC + BC
X = AB + AC + BC
X = AB. AC. BC

NOR only implementation

Every gate will have a circuit representation with NOR gates only.
e.g.: Implement the logic circuit for three judges’ problem using NOR gates only.
X = (A + B).(A + C).(B + C)
X = (A + B).(A + C).(B + C)
X = (A + B) + (A + C) + (B + C)

Implicants in K-map
Implicant is a product/minterm term in Sum of Products (SOP) or sum/maxterm term in
Product of Sums (POS) of a Boolean function.
E.g.: Consider a boolean function, F = AB + ABC + BC. Implicants are AB, ABC and BC.
Prime Implicants
A group of square or rectangle made up of bunch of adjacent minterms which is allowed by
definition of K-Map are called prime implicants (PI) i.e. all possible groups formed in K-Map.
Example:
Essential Prime Implicants
These are those subcubes (groups) which cover atleast one minterm that can’t be covered by
any other prime implicant. Essential prime implicants (EPI) are those prime implicants which
always appear in final solution.
Example:

Redundant Prime Implicants

The prime implicants for which each of its minterm is covered by some essential prime
implicant are redundant prime implicants (RPI). This prime implicant never appears in final
solution.
Example:
Selective Prime Implicants
The prime implicants for which are neither essential nor redundant prime implicants are called
selective prime implicants(SPI). These are also known as non-essential prime implicants. They
may appear in some solution or may not appear in some solution.
Example:

Example-1: Given F = ∑ (1, 5, 6, 7, 11, 12, 13, 15), find number of implicant, PI, EPI, RPI and
SPI.
No. of Implicants = 8
No. of Prime Implicants(PI) = 5
No. of Essential Prime Implicants(EPI) = 4
No. of Redundant Prime Implicants(RPI) = 1
No. of Selective Prime Implicants(SPI) = 0
Example-2: Given F = ∑(0, 1, 5, 8, 12, 13), find number of implicant, PI, EPI, RPI and SPI.
No. of Implicants = 6
No. of Prime Implicants(PI) = 6
No. of Essential Prime Implicants(EPI) = 0
No. of Redundant Prime Implicants(RPI) = 0
No. of Selective Prime Implicants(SPI) = 6
Example-3: Given F = ∑(0, 1, 5, 7, 15, 14, 10), find number of implicant, PI, EPI, RPI and SPI.
No. of Implicants = 7
No. of Prime Implicants(PI) = 6
No. of Essential Prime Implicants(EPI) = 2
No. of Redundant Prime Implicants(RPI) = 0
No. of Selective Prime Implicants(SPI) = 4
Quine-McCluskey Minimization Method
The Quine–McCluskey algorithm (or the method of prime implicants) is a method used for
minimization of Boolean functions. It is functionally identical to Karnaugh mapping, but the
tabular form makes it more efficient for use in computer algorithms, and it also gives a
deterministic way to check that the minimal form of a Boolean function has been reached. It
is sometimes referred to as the tabulation method.
Solving for optimized expression using Q-M method

𝑓(𝐴, 𝐵, 𝐶, 𝐷) = ∑ 𝑚(4,8,10,11,12,15) + 𝑑(9,14)

Step 1: finding prime implicants

To optimize, all minterms that evaluate to one are first placed in a minterm table. Don't-care
terms are also added into this table, so they can be combined with minterms.
Number Binary
Minterm
of 1s Representation

m4 0100
1
m8 1000

m9 1001

2 m10 1010

m12 1100

m11 1011
3
m14 1110

4 m15 1111
At this point, one can start combining minterms with other minterms. If two terms vary
by only a single digit changing, that digit can be replaced with a dash indicating that the
digit doesn't matter. Terms that can't be combined any more are marked with an asterisk
(*). When going from Size 2 to Size 4, treat '-' as a third bit value. For instance, -110 and
100 can be combined, as well as -110 and -11-, but -110 and 011- cannot. (Trick: Match
up the '-' first.)
Number
Minterm 0-Cube Size 2 Implicants Size 4 Implicants
of 1s
m4 0100 m(4,12) -100* m(8,9,10,11) 10--*

1 m8 1000 m(8,9) 100- m(8,10,12,14) 1--0*

— — m(8,10) 10-0 —
 — — m(8,12) 1-00 —

m9 1001 m(9,11) 10-1 m(10,11,14,15) 1-1-*

2
m10 1010 m(10,11) 101- —

— — m(10,14) 1-10 —

m12 1100 m(12,14) 11-0 —

m11 1011 m(11,15) 1-11 —

3
m14 1110 m(14,15) 111- —

4 m15 1111 — —
Note: In this example, none of the terms in the size 4 implicants table can be combined
any further. Be aware that this processing should be continued otherwise
(size 8 etc.).
Step 2: prime implicant chart
None of the terms can be combined any further than this, so at this point we construct an
essential prime implicant table. Along the side goes the prime implicants that have just been
generated, and along the top go the minterms specified earlier. The don't care terms are not
placed on top—they are omitted from this section because they are not necessary inputs.

4 8 10 11 12 15 ⇒ A B C D

m(4,12)* ⇒ — 1 0 0

m(8,9,10,11) ⇒ 1 0 — —

m(8,10,12,14) ⇒ 1 — — 0

m(10,11,14,15)* ⇒ 1 — 1 —

To find the essential prime implicants, we run along the top row. We have to look for
columns with only 1 "✓". If a column has only 1 "✓", this means that the minterm can
only be covered by 1 prime implicant. This prime implicant is essential.
For example, in the first column, with minterm 4, there is only 1 "✓". This means that
m(4,12) is essential. So we place a star next to it. Minterm 15 also has only 1 "✓", so
m(10,11,14,15) is also essential. Now all columns with 1 "✓" are covered.
 The second prime implicant can be 'covered' by the third and fourth, and the third prime
implicant can be 'covered' by the second and first, and neither is thus essential. If a prime
implicant is essential then, as would be expected, it is necessary to include it in the
minimized boolean equation. In some cases, the essential prime implicants do not cover
all minterms. In the current example, the essential prime implicants do not handle all of
the minterms, so, in this case, one can combine the essential implicants with one of the
two non-essential ones to yield one equation:
𝑓(𝐴, 𝐵, 𝐶, 𝐷) = BC′D′ + AB′ + AC
or
𝑓(𝐴, 𝐵, 𝐶, 𝐷) = BC′D′ + AD′ + AC

Gate Propagation Delay

Logic gates are implemented using electronic components (essentially transistors) which have
a finite switching speed. Consequently, there will be a finite delay before the output of a gate
responds to a change in its inputs, which is called propagation delay. The cumulative delay
owing to a number of gates in cascade can increase the time before the output of a
combinational logic circuit becomes valid. For example, in the Ripple Carry Adder, the sum at
its output will not be valid until any carry has ‘rippled’ through possibly every full adder in the
chain – clearly the MSB will experience the greatest potential delay. As well as slowing down
the operation of combinational logic circuits, gate delay can also give rise to so called
‘Hazards’ at the output These Hazards manifest themselves as unwanted brief logic level
changes (or glitches) at the output in response to changing inputs.
Timing Diagrams
To visually represent Delays we will use the so called ‘timing diagram’. This shows the logical
value of a signal as a function of time. For example, the following timing diagram shows the

variation of output of the specified circuit for the given input variation without any delay.
Example: Timing Diagram of OR gate with delay
Circuit Hazards
Logic hazards are manifestations of a problem in which changes in the input variables do not
change the output correctly due to some form of delay caused by logic elements (NOT, AND, OR
gates, etc.) This results in the logic not performing its function properly.
Example:

𝑌 = 𝐴𝐵 + 𝐵𝐶

Hazard Removal
To remove a 1 hazard, draw the K-map of the output concerned. Add another term which
overlaps the essential terms. To remove a 0 hazard, draw the K-map of the complement of
the output concerned. Add another term which overlaps the essential terms (representing
the complement).
Special combinational logic circuits
The techniques of combinational logic functions are widely applied in many branches of digital
circuits. There are some popular applications which can be seen in major digital systems such
as computers, calculators, etc.
Half – Adder
As the name suggests this circuit will do some addition process, but not a complete process.
It takes two bits and produce the sum and carry of both through the addition. The truth table
and the logic circuit for the Half Adder are shown in the Table and Figure respectively.

Full Adder
A Full adder consists of two half adders. The full adder is capable of doing complete addition
process of two bits, because, apart from the two input bits, it accepts the carry bit which is
brought from the addition of bits in the previous place value. Figure and Table depicts the
circuit diagram and the corresponding truth table for the full adder.
 x y Cin S Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

Fig. Complete circuit diagram of a Full Adder

Parallel Binary Adders
Several full adders can be connected together to form parallel binary adders. This array of
adder circuits is used to add two strings of binary numbers. Adders are the building blocks for
many digital circuits such as ALUs and calculators.
e.g.: A 4-bit parallel adder

Comparator
Comparator is used to compare whether two binary strings are equal. An XNOR gate can be
used for this purpose. Comparators are widely used in memory address comparison in cache
memory.
e.g.: A 4-bit comparator

Encoder
An Encoder is a combinational circuit which accepts an input from one of its many input pins
and converts it to a coded output. A familiar example is a decimal-to-BCD encoder.
e.g.: Calculators, where each keypad stroke is converted into BCD form.
Computer key boards, where each key stroke is converted into ASCII code.
Decoder
A Decoder does the opposite operation of an encoder. It accepts a string of binary code and
produces a unique output corresponding to the code. An n bit decoder can decode 2 n outputs.
e.g.: BCD to 7-Seg. Display
Multiplexer
A multiplexer (or) data selector allows digital information from several sources to be sent
through a single line by selecting only one source at a time for the transmission of data. It
consists of several data input lines and data select lines and only one output line. The bit
pattern on data select line determines which input line to be connected to the output line.
Demultiplexer
A demultiplexer does the opposite operation of a multiplexer. It gets the data from the input
line and distributes it to several output lines, which are specified by the data distributor bits.