PROGRAM OUTCOMES(POs)

Program Outcomes as defined by NBA (PO) Engineering Graduates will be able to:

1. Engineering knowledge: Apply the knowledge of mathematics, science, engineering fundamentals, and an
engineering specialization to the solution of complex engineering problems.
2. Problem analysis: Identify, formulate, review research literature, and analyze complex engineering problems
reaching substantiated conclusions using first principles of mathematics, natural sciences, and engineering
sciences.
3. Design/development of solutions: Design solutions for complex engineering problems and design system
components or processes that meet the specified needs with appropriate consideration for the public health and
safety, and the cultural, societal, and environmental considerations.
4. Conduct investigations of complex problems: Use research-based knowledge and research methods including
design of experiments, analysis and interpretation of data, and synthesis of the information to provide valid
conclusions.
5. Modern tool usage: Create, select, and apply appropriate techniques, resources, and modern engineering and
IT tools including prediction and modeling to complex engineering activities with an understanding of the
limitations.
6. The engineer and society: Apply reasoning informed by the contextual knowledge to assess societal, health,
safety, legal and cultural issues and the consequent responsibilities relevant to the professional engineering
practice.
7. Environment and sustainability: Understand the impact of the professional engineering solutions in societal
and environmental contexts, and demonstrate the knowledge of, and need for sustainable development.
8. Ethics: Apply ethical principles and commit to professional ethics and responsibilities and norms of the
engineering practice.
9. Individual and team work: Function effectively as an individual, and as a member or leader in diverse teams,
and in multidisciplinary settings.
10. Communication: Communicate effectively on complex engineering activities with the engineering
community and with society at large, such as, being able to comprehend and write effective reports and design
documentation, make effective presentations, and give and receive clear instructions.
11. Project management and finance: Demonstrate knowledge and understanding of the engineering and
management principles and apply these to one’s own work, as a member and leader in a team, to manage
projects and in multidisciplinary environments.
12. Life-long learning: Recognize the need for, and have the preparation and ability to engage in independent
and life-long learning in the broadest context of technological change.
 Vision (College)
To nurture talent & enrich society through excellence in technical education, research &
innovation.
Mission (College)
1. To augment innovative Pedagogy & kindle quest for interdisciplinary learning & to
enhance conceptual understanding.
2. To build competence, professional ethics & develop entrepreneurial thinking.
3. To strengthen Industry Institute Partnership & explore global
Collaborations.
4. To inculcate culture of socially responsible citizenship.
5. To focus on Holistic & Sustainable development
Vision (Dept)

To achieve excellence in technical education, research, innovation in computer science

and Engineering by emphasizing on global trending technologies.
Mission (Dept)
1. To train students with conceptual understanding through innovative pedagogies.
2. To imbibe professional, research and entrepreneurial Skills with commitment to the
nation development at large.
3. To strengthen the industry institute Interaction.
4. To promote life–long learning with a sense of societal & ethical responsibilities.
Program Educational Objectives (PEO)
To develop abilities to identify and groom the skills required in
PEO1 the field of Computer Science & Engineering in analysing,
designing and providing problem solving capabilities.
To develop abilities to work in a team on multidisciplinary
PEO2 projects with effective communication skills, ethical qualities
and leadership roles.
To develop abilities to become successful Computer Science
PEO3
Engineer with the goal of lifelong learning.
Program Specific Outcomes (PSO)
To develop abilities to model real world problems using
PSO 1
appropriate algorithms, computational theories and
programming languages in the area of Computer Science and
Engineering.
To develop an ability to inculcate innovation,
PSO 2
entrepreneurial and leadership skills.
 Mapping of Experiments with CO, PO and PSO

S.No. Experiment Details CO PO PSO

PART A

Given a 4-variable logic expression, simplify it using appropriate

1 CO1 PO1
technique and simulate the same using basic gates.

Design a 4 bit full adder and subtractor and simulate the same
2 CO2 PO3
using basic gates.

Design Verilog HDL to implement simple circuits using structural,

3 CO2 PO3
Data flow and Behavioral model.

Design Verilog HDL to implement Binary Adder-Subtractor – Half CO2

4 PO3
and Full Adder, Half and Full Subtractor.

5 Design Verilog HDL to implement Decimal adder CO2 PO3

Design Verilog program to implement Different types of

6 CO2 PO3
multiplexer like 2:1, 4:1 and 8:1.

7 Design Verilog program to implement types of De-Multiplexer CO2 PO3

Design Verilog program for implementing various types of Flip- CO2

8 PO3
Flops such as SR, JK and D
Date: Expt. STUDY OF LOGIC GATES
No.:

AIM:
To study about logic gates and verify their truth tables.

APPARATUS REQUIRED:

SL No. COMPONENT SPECIFICATION QTY

1. AND GATE IC 7408 1
2. OR GATE IC 7432 1
3. NOT GATE IC 7404 1
4. NAND GATE 2 I/P IC 7400 1
5. NOR GATE IC 7402 1
6. X-OR GATE IC 7486 1
7. NAND GATE 3 I/P IC 7410 1
8. IC TRAINER KIT - 1
9. PATCH CORD - 14
THEORY:
Circuit that takes the logical decision and the process are called logic gates. Each
gate has one or more input and only one output.
OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as universal
gates. Basic gates form these gates.
AND GATE:
The AND gate performs a logical multiplication commonly known as AND function.
The output is high when both the inputs are high. The output is low level when any one
of the inputs is low.
OR GATE:
The OR gate performs a logical addition commonly known as OR function. The
output is high when any one of the inputs is high. The output is low level when both the
inputs are low.
NOT GATE:
The NOT gate is called an inverter. The output is high when the input is low.
The output is low when the input is high.
NAND GATE:
 The NAND gate is a contraction of AND-NOT. The output is high when both inputs are low
and any one of the input is low .The output is low level when both inputs are high.
NOR GATE:
The NOR gate is a contraction of OR-NOT. The output is high when both inputs
are low. The output is low when one or both inputs are high.
X- OR GATE:
The output is high when any one of the inputs is high. The output is low when both
the inputs are low and both the inputs are high.
PROCEDURE:
(i) Connections are given as per circuit diagram.
(ii) Logical inputs are given as per circuit diagram.
(iii) Observe the output and verify the truth table

AND GATE:
SYMBOL: PIN DIAGRAM:
OR GATE:

NOT GATE:
SYMBOL: PIN DIAGRAM:
X-OR GATE :
SYMBOL : PIN DIAGRAM :

2- INPUT NAND GATE:

SYMBOL: PIN DIAGRAM:
NOR GATE:

RESULT:
Date: Expt. Given a 4-variable logic expression, simplify it using appropriate
No.: technique and simulate the same
using basic gates
Assume a simple Boolean Expression

The values for the Y with the inputs P, Q, R are tabulated below.
P Q R
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 1
 DESIGN A 4 BIT FULL ADDER AND SUBTRACTOR AND SIMULATE THE
Date: SAME USING BASIC GATES.
Expt. No.:

AIM:
To design and construct full adder and full subtractor circuits and verify the truth table using logic gates.

FULL ADDER:
Full adder is a combinational circuit which consists of three binary input variables called augends and
addends and two binary output variables called sum and carry out. In the addition result, the lower
significant bit is called as sum and the higher significant bit is called as carry out. The truth table of the full
adder describes all the eight possible input variations. The full adder results the outputs are equal to logic
‘0’ when all the applied inputs are equal to logic ‘0’ and the outputs are equal to logic ‘1’ when all the inputs
are equal to logic ‘1’. The sum is equal to 1 when odd numbers of inputs are equal to 1 from the applied
three inputs. The carry out is equal to 1 if more than one applied inputs are equal to 1.

TRUTH TABLE:
Inputs Outputs

A B Cin Cout S

0 0 0 0 0

0 0 1 0 1

0 1 0 0 1

0 1 1 1 0
 1 0 0 0 1

1 0 1 1 0

1 1 0 1 0

1 1 1 1 1

FULL SUBTRACTOR:
Full subtractor is a combinational circuit which consists of three binary input
variables called minuend and subtrahend, and two binary output variables called
difference and borrow out. In the subtraction result, the lower significant bit is called as
difference and the higher significant bit is called as barrow out. The truth table of the full
subtractor describes all the eight possible input variations. The full subtractor results the
outputs are equal to logic ‘0’ when all the applied inputs are equal to logic ‘0’.

TRUTH TABLE

Inputs Outputs

A B Bin Bout D

0 0 0 0 0

0 0 1 1 1

0 1 0 1 1

0 1 1 1 0

1 0 0 0 1

1 0 1 0 0

1 1 0 0 0

1 1 1 1 1
 4-Bit Full Adder

4-Bit Full Subtractor

 Date: Expt. Design Verilog HDL to implement Decimal adder.
No.:

//module declaration with inputs and outputs

module bcd_adder(a,b,carry_in,sum,carry);

//declare the inputs and outputs of the module with their sizes.
input [3:0] a,b;
input carry_in;
output [3:0] sum;
output carry;
//Internal variables
reg [4:0] sum_temp;
reg [3:0] sum;
reg carry;

//always block for doing the addition

always @(a,b,carry_in)
begin
sum_temp = a+b+carry_in; //add all the inputs
if(sum_temp > 9) begin
sum_temp = sum_temp+6; //add 6, if result is more than 9.
carry = 1; //set the carry output
sum = sum_temp[3:0]; end
else begin
carry = 0;
sum = sum_temp[3:0];
end
end

endmodule
 Date: Design Verilog HDL to implement Binary Adder-Subtractor – Half and Full
Adder, Half and Full Subtractor.
Expt. No.:

//Half Subtractor
module xor_gate(a1, b1, c1);
input a1, b1;
output c1;
assign c1 = a1 ^ b1;
endmodule

module and_gate(a2, b2, c2);

input a2, b2;
output c2;
assign c2 = a2 & b2;
endmodule

module not_gate(a3, b3);

input a3;
output b3;
assign b3 = ~ a3;
endmodule

module half_subtractor(a, b, difference, borrow);

input a, b;
output difference, borrow;
wire x;
xor_gate u1(a, b, difference);
and_gate u2(x, b, borrow);
not_gate u3(a, x);
endmodule
//half_adder
module half_adder_structural (
input a, // Input 'a'
input b, // Input 'b'
output s, // Output 's' (Sum)
output c // Output 'c' (Carry)
);
xor gate_xor (s, a, b); // XOR gate for sum
and gate_and (c, a, b); // AND gate for carry
endmodule

//Full Adder
module full_adder_s (
input a,b,cin,
output sum,carry
);
wire w1,w2,w3,w4; //Internal connections
xor(w1,a,b);
xor(sum,w1,cin); //Sum output
and(w2,a,b);
and(w3,b,cin);
and(w4,cin,a);
or(carry,w2,w3,w4); //carry output
endmodule
//Full Subtractor
module full_subtractor ( a ,b ,c ,diff ,borrow );
output diff ;
output borrow ;
input a ;
input b ;
input c ;
assign diff = a ^ b ^ c;
assign borrow = ((~a) & b) | (b & c) | (c & (~a));
endmodule
Digital Design and Computer Organization BCS302

Date: Expt. Design Verilog HDL to implement simple circuits using structural,
No.: Data flow and Behavioral model.

Structural Model:
// StructuralCircuit.v
module StructuralCircuit (
input A,
input B,
input C,
output Y
);
// Components
AND_gate u1 (.A(A), .B(B), .Y(Y_and));
OR_gate u2 (.A(Y_and), .B(C), .Y(Y));
Endmodule

Data Flow Model:

// DataFlowCircuit.v
module DataFlowCircuit (
input A,
input B,
input C,
output Y
);
// Data flow assignment
assign Y = A & B | C;
endmodule

Behavioral Model:
// BehavioralCircuit.v

module BehavioralCircuit (
input A,
input B,
input C,
output Y
);

// Declare internal variables

Dept. Computer Science and Engineering, KLS’s VDIT, Haliyal 1

Digital Design and Computer Organization BCS302

reg YInternal;

// Behavioral assignment
always_comb begin
YInternal = A & B | C;
end

// Assign output
assign Y = YInternal;

endmodule

Dept. Computer Science and Engineering, KLS’s VDIT, Haliyal 2

Digital Design and Computer Organization BCS302

Date: Expt. Design Verilog program to implement Different types of multiplexer

No.: like 2:1, 4:1 and 8:1.

2:1 Multiplexer

// 2to1Mux.v

module TwoToOneMux (
input wire A, B,
input wire Sel,
output reg Y
);

always @* begin
Y = (Sel == 1'b0) ? A : B;
end
endmodule

//4:1 Multiplexer:

Dept. Computer Science and Engineering, KLS’s VDIT, Haliyal 3

Digital Design and Computer Organization BCS302

module FourToOneMux (
input wire [3:0] D,
input wire [1:0] Sel,
output reg Y
);
always @* begin
case (Sel)
2'b00: Y = D[0];
2'b01: Y = D[1];
2'b10: Y = D[2];
2'b11: Y = D[3];
default: Y = 1'b0; // Default case for safety
endcase
end
endmodule

8:1 Multiplexer:

Dept. Computer Science and Engineering, KLS’s VDIT, Haliyal 4

Digital Design and Computer Organization BCS302

// 8to1Mux.v
module EightToOneMux (
input wire [7:0] D,
input wire [2:0] Sel,
output reg Y
);

always @* begin
case (Sel)
3'b000: Y = D[0];
3'b001: Y = D[1];
3'b010: Y = D[2];
3'b011: Y = D[3];
3'b100: Y = D[4];
3'b101: Y = D[5];
3'b110: Y = D[6];
3'b111: Y = D[7];
default: Y = 1'b0; // Default case for safety
endcase
end
endmodule

Dept. Computer Science and Engineering, KLS’s VDIT, Haliyal 5

Digital Design and Computer Organization BCS302

Date: Expt. Design Verilog program to implement types of De-Multiplexer.

No.:

1:2 De-Multiplexer:

// 1to2Demux.v

module OneToTwoDemux (
input wire D,
input wire Sel,
output reg Y0,
output reg Y1
);

always @* begin
Y0 = (Sel == 1'b0) ? D : 1'b0;
Y1 = (Sel == 1'b1) ? D : 1'b0;
end
endmodule

Dept. Computer Science and Engineering, KLS’s VDIT, Haliyal 6

Digital Design and Computer Organization BCS302

Date: Expt. Design Verilog program for implementing various types of Flip-Flops
No.: such as SR, JK and D.

//SR Flip-Flop:
// SRFlipFlop.v

module SRFlipFlop (
input S, R, CLK,
output reg Q, Qn
);

always @(posedge CLK or posedge S or posedge R) begin

if (S && ~R)
Q <= 1'b1;
else if (~S && R)
Q <= 1'b0;
end

always @(posedge CLK or posedge S or posedge R) begin

if (S && ~R)
Qn <= 1'b0;
else if (~S && R)
Qn <= 1'b1;
end

endmodule

Dept. Computer Science and Engineering, KLS’s VDIT, Haliyal 7

Digital Design and Computer Organization BCS302

//JK Flip-Flop:
// JKFlipFlop.v

module JKFlipFlop (
input J, K, CLK,
output reg Q, Qn
);

always @(posedge CLK or posedge J or posedge K) begin

if (J && ~K)
Q <= 1'b1;
else if (~J && K)
Q <= 1'b0;
else if (J && K)
Q <= ~Q;
end

always @(posedge CLK or posedge J or posedge K) begin

if (J && ~K)
Qn <= 1'b0;
else if (~J && K)
Qn <= 1'b1;
else if (J && K)
Qn <= Q;
end

endmodule

Dept. Computer Science and Engineering, KLS’s VDIT, Haliyal 8

Digital Design and Computer Organization BCS302

D Flip-Flop:
// DFlipFlop.v
module DFlipFlop (
input D, CLK,
output reg Q, Qn
);

always @(posedge CLK or posedge D) begin

Q <= D;
end

always @(posedge CLK or posedge D) begin

Qn <= ~D;
end

endmodule

Dept. Computer Science and Engineering, KLS’s VDIT, Haliyal 9