Order Number: MCUK990801G8

Technical Guide
GD90 Personal Cellular Telephone
Handheld Portable
EB-GD90

Specification
900 MHz 1800 MHz

Frequency range Tx: 890 - 915 MHz Tx: 1710 - 1785 MHz
Rx: 935 - 960 MHz Rx: 1805 - 1880 MHz
Tx/Rx frequency separation 45 MHz 95 MHz
RF channel bandwidth 200 kHz
Number of RF channels 124 374
Speech coding Full rate/Half rate/Enhanced Full rate/Half rate
Full rate
Operating temperature -10°C to +55°C
Type Class 4 Handheld Class 1 Handheld
RF Output Power 2 W maximum 1 W maximum
Modulation GMSK (BT = 0.3)
Connection 8 ch/TDMA
Voice digitizing 13 kbps RPE-LTP / 13 kps ACLEP / 5.6 kps CELP / VSLEP
Transmission speed 270.3 kbps
Diversity Frequency hopping
Signal Reception Double superheterodyne
Intermediate Frequency 282MHz and 45MHz
Antenna Terminal Impedance 50 Ω
Antenna VSWR <2.1 : 1
Dimensions Height: 118 mm
Width: 42 mm
Depth: 16.5 mm
Volume 84.5 cc
Weight 88 g
Display Graphical chip on glass liquid crystal, Alphanumeric 16 x 3
characters, 5 icons and 6 x 1 characters
Illumination Green:
4 LEDs for the LCD
8 LEDs for the keyboards
1 LED Incoming call
Red:
1 LED Charging indicator
Keypad 17 keys, Navigation key
SIM Plug-in type only
External DC Supply Voltage 3.6 V
Battery 3.6 V
Standby Battery Life 95 hrs maximum
DRX 9
Conversation Battery Life 200 minutes
PL 7, DTX 50%

Unless stated these specifications are with Battery Pack (EB-BSD90) fitted.

Battery life figures are dependent on network conditions.

WARNING
This service information is designed for experienced repair technicians only and is not designed for use by the general public. It does not contain warnings or
cautions to advise non-technical individuals of potential dangers in attempting to service a product.
Products powered by electricity should be serviced or repaired only by experienced professional technicians. Any attempt to service or repair the product or
products dealt with in this service manual by anyone else could result in serious injury or death.

Issue 1
Revision 0
This Technical Guide is copyright and issued on the strict understanding that it is not to be reproduced, copied, or disclosed to
any third party, either in whole or part, without the prior written consent of Matsushita Communication Industrial UK Ltd.
Every care has been taken to ensure that the contents of this publication give an accurate representation of the equipment.
However, Matsushita Communication Industrial UK Ltd. accepts no responsibility for inaccuracies which may occur and
reserves the right to make changes to the specification or design without prior notice.
The information contained in this manual and all rights in any designs disclosed therein, are and remain the exclusive property
of Matsushita Communication Industrial UK Ltd.
Other patents applying to material contained in this publication:
BULL CP8 PATENTS
Comments or correspondence concerning this manual should be addressed to:
Customer Support Department,
Matsushita Communication Industrial UK Ltd.,
Colthrop,Thatcham,
Berkshire. RG19 4ZD.
ENGLAND
© 1999 Matsushita Communication Industrial UK Ltd.

Issue 1 – ii – MCUK990801G8
Revision 0 Technical Guide
CONTENTS
1 INTRODUCTION
1.1 Purpose of this Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Structure of the Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

2 INTERFACES AND TEST POINTS

2.1 Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

3 RF OVERVIEW
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.3 RF & Accessory Connector . . . . . . . . . . . . . . . . . . . . . . 10

4 TRANSMITTER
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . 12

5 RECEIVER
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . 16

6 BASEBAND OVERVIEW
6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.2 Functional Description of the PCB . . . . . . . . . . . . . . . . 19

7 GEMINI
7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . 25

8 VEGA
8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
8.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . 29

9 POWER SUPPLIES
9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
9.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
9.3 Power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
9.4 Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
9.5 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

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Issue 1 Section MCUK990801G8

Revision 0 – iv – Technical Guide
 INTRODUCTION

1 INTRODUCTION
1.1 Purpose of this Guide
This guide contains technical information for the Panasonic GD90 personal cellular telephone system operating on the GSM
network. Procedures for installing, operating and servicing (e.g. disassembly and testing) the telephone system are provided
in the associated Service Manual.

1.2 Structure of the Guide

The guide is structured to provide service-engineering personnel with the following technical information on the GSM mobile
telephone:
1. Interface details and relevant test points.
2. Functional description of each section of the mobile telephone.
3. Detailed description of each section of the mobile telephone.

MCUK990801G8 Section 1 Issue 1

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INTRODUCTION

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Issue 1 Section 1 MCUK990801G8

Revision 0 –2– Technical Guide
 INTERFACES AND TEST POINTS

2 INTERFACES AND TEST POINTS

2.1 Interfaces
2.1.1 Main and Keypad PCBs
The interface between Main and Keypad PCBs is made via a 34-way connector as follows:

GND 1 18 GND
D28V 2 19 D28V
KEYBKLT 3 20 nPOWKEY
LCD_GRN 4 21 PAGING_LED
LCD_RED 5 22 CHARGING_LED
A(1) 6 23 nRESET
RnV 7 24 CS_LCD
KBC(4) 8 25 KBR(3)
KBC(3) 9 26 KBR(2)
KBC(2) 10 27 KBR(4)
KBC(0) 11 28 KBR(1)
KBC(1) 12 29 KBR(0)
D(4) 13 30 D(5)
D(3) 14 31 D(6)
D(2) 15 32 D(7)
D(1) 16 33 REC_P
D(0) 17 34 REC_N

10075-1

Figure 2.1: GD90 Interboard Connector

No. Signal Name MAIN <=> KEYPAD Function Connection

1 GROUND -
2 D28V - Power Source for LCD Module
3 KEYBKLT ==> Key Backlight Power Source Charge IC pin 16
4 LCD_GRN ==> LCD Green Backlight Power Charge IC pin 18
5 LCD_RED ==> LCD Red Backlight Power Charge IC pin 17
6 A(1) ==> MPU Address bus (1) GEMINI pin 25
7 RnW ==> MPU Read/nWrite signal GEMINI pin 20
8 KBC(4) ==> Key Column 4 signal for Key scan GEMINI pin 128
9 KBC(3) ==> Key Column 3 signal for Key scan GEMINI pin 129
10 KBC(2) ==> Key Column 2 signal for Key scan GEMINI pin 130
11 KBC(0) ==> Key Column 0 signal for Key scan GEMINI pin 132
12 KBC(1) ==> Key Column 1signal for Key scan GEMINI pin 133
13 D(4) <==> MPU Data bus (4)
14 D(3) <==> MPU Data bus (3)
15 D(2) <==> MPU Data bus (2)
16 D(1) <==> MPU Data bus (1)
17 D(0) <==> MPU Data bus (0)
18 GROUND - l
19 D28V - Power Source for LCD Module
20 nPOWKEY <== Power Key sense signal
21 PAGING_LED ==> Paging LED control signal SIM_PWR IC pin 22
22 CHARGE_LED ==> Charge LED control signal GEMINI pin 105
23 nRESET ==> MPU nRESET signal
24 CS_LCD ==> LCD chip select signal GEMINI pin 55
25 KBR(3) <== Key Row 3 signal for Key scan GEMINI pin 123
26 KBR(2) <== Key Row 2 signal for Key scan GEMINI pin 124
27 KBR(4) <== Key Row 4 signal for Key scan GEMINI pin 122
28 KBR(1) <== Key Row 1 signal for Key scan GEMINI pin 125
29 KBR(0) <== Key Row 0 signal for Key scan GEMINI pin 126

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INTERFACES AND TEST POINTS

No. Signal Name MAIN <=> KEYPAD Function Connection

30 D(5) <==> MPU Data bus (5)
31 D(6) <==> MPU Data bus (6)
32 D(7) <==> MPU Data bus (7)
33 REC_P ==> Receiver Positive Output
34 REC_N ==> Receiver Negative Output

GD90 has two external connectors:

1. a multi-way connector for use with a handsfree data;
2. additional contacts for charging the battery pack while in the desktop charger;
All interfaces are electrically and mechanically compatible with GD90.

Main Unit <==> External I/O

No. Name H/H <=> EXT Total Function H/H Circuit
1 GND ==> 6 Ground
10095-1

2 PA_ON ==> 1 Gating of spectrum analyser for Transmitter

performance testing 10k
330p
L: Off, Hi - Z: On)
10096-1

3 nLOGIC_PWR ==> 1 Accessory Power Control signal.

In the handsfree this is logical OR’ed with
IGNITION in order that the software can 330

maintain the Handsfree power-on state if the

4 IGNITION
10097-1
user is in a call and that the IGNITION is
switched off. L: Power-on, Hi-Z: Power-off
<== 1 IGNITION is used in two cases.
1) Determine the mode of operation of the H/H
when the Handsfree accessory is attached.
L: At a suitable time enter dummy sleep mode
50k
and therefore minimise the drain on the car
330
battery (nLOGIC_POWER = Hi - Z) 200k
H: Normal mode
2) Satisfy 2nd of 2 conditions for sending 10098-1

initialise Testset command and entering Testset

mode. (see nADP_SENSE for 1st condition)
L: Condition 2 satisfied
H: Enter Testset mode not satisfied
5 VBAT <=> 1 The pin is either an input or an output
depending upon the battery connection.
1) Battery/Dummy battery connected: Output
supply terminal for attached accessories.
2) No connection: Low current input supply 10099-1
terminal for non-RF performance checking in
Testset Mode or Flash programming.

6 nH/F_SENSE <== 1 Handsfree sense line

L: connected
H (internal pull-up): disconnected 100k

10100-1
330

7 nRADIO_MUTE ==> 1 Radio Mute 50k

330
L: mute, Hi-Z: unmute)
200k

10101-1

8 RX_AUDIO ==> 1 Accessory Receiving Audio

560
-16 dBm0 = 76.7m Vrms
10102-1
1F

9 GND ==> Ground Refer to pin 1

Issue A Section 2 MCUK990801G8

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 INTERFACES AND TEST POINTS

No. Name H/H <=> EXT Total Function H/H Circuit

10 EXT-PWR <== 2 Power supply for battery charging, Power ON/
Off control and accessory control circuits. Trickle Charge Circuit
Voltage: 5.8 ± 0.2 V Power On/Off Control Circuit
Rapid Charge Circuit
Current: 650 ± 50 mA Accessory Control Circuit 10103-1

11 NON_HOOK <== 1 Indicates if the optional second handset is on or

off hook. In handsfree operation, if the optional
handset is not fitted this signal defaults to on 100k
hook. (Low.)
10100-1
330

12 SERIAL_OUT ==> 1 Downlink Serial Data

(Baud rate is same as SERIAL_IN)
2.2k
330

47k

10104-1

13 SERIAL_IN <== 1 Uplink Serial Data

The baud rate is dependant upon the attached
accessory, whether operating in Testset Mode
or Flash Downloading. 4.7 k
SMS cable: 9600 bps
RS232 Direct cable: 38.4 kbps 10105-1 330

Data adapter: 33.8 kbps

Testset: 9600 bps
Flash Download: 56 kbps
14 nADP_SENSE <== 1 NADP_SENSE has 5 possible states. The state
is determined by the value of the pull-down
resistor in the attached accessory / test set.
NADP_SENSE has 2 purposes as follows:
1) To identify an attached accessory.
Open (H): No attached accessory
82 kΩ=± 1% (MH): Headset Adapter
56 kΩ=± 1% (M): SMS Cable 100k
33 kΩ=± 1% (ML): RS232C Direct Cable
GND (L): Data Adapter 330
10100-1
2) Determine whether the 1st of 2 conditions
are satisfied for sending the initialise Testset
command on SERIAL_OUT, and entering
Testset mode (see IGNITION for 2nd condition).
H/MH: Condition 1 satisfied
M/ML/L: Enter Testset Mode not satisfied
15 NH/F_ON ==> 1 Accessory Sending & Receiving Audio paths 50k
330
unmute
200k
L: unmute, Hi-Z: mute
10101-1

16 GND ==> 6 Refer to pin 1 Refer to pin 1

17 TX_AUDIO <== 1 Accessory Sending Audio 1 10k 1
-16 dBm0 = 40.4 m Vrms
3k3

10106-1

18 GND ==> 6 Ground connection of Dual Charger Refer to pin 1

MCUK990801G8 Section 2 Issue A

Technical Guide – 11 – Revision 0
INTERFACES AND TEST POINTS

No. Name H/H <=> EXT Total Function H/H Circuit

19 GND ==> 6 Ground connection of Dual Charger Refer to pin 1
20 GND ==> 6 Ground connection of Dual Charger Refer to pin 1
21 GND ==> 6 Ground connection of Dual Charger Refer to pin 1
22 CHARGE_ON <=> 1 The Dual Charger shall hold CHARGE_ON to
the middle level unit a H/H is inserted into the
front slot. 330
CHARGE_ON
H: 2.0<=V<=3.0 volts; Dual Charger detects
10k 0.1µ
connection of H/H
M: 1.0<=V<2.0 volts; Unconnected 10107-1

L: 0.0<=V<1.0 volts; Dual Charger detects

connection of H/H
23 EXT_PWR <== 2 The Dual Charger shall control switching of the Refer to pin 8
power supply to the front slot (corresponds to
EXT_PWR) based on the state of the
CHARGE_ON signal.
H: EXT_PWR supplied
L: When the H/H can determine whether or not
to set CHARGE_ON. After the insertion of the
H/H, EXT_PWR shall be subsequently supplied
withinTBA hours

Battery Connector
No. Name H/H <=> EXT Total Function H/H Circuit
1 VBAT <== 1 Positive battery terminal.
Li+ (2 cells in parallel): 3.6 V nom.
NiMH (3 cells in series): 3.6 V nom.
10108-1

2 BAT_TEMP <== 1 BAT_TEMP has 2 purposes.

ChargerIC VREFOUT
1) Determine whether a battery is attached to
the H/H.
2) Monitor battery temperature for the purposes ESD
of charging. Vega_ADIN2

ESD
H: Abnormal battery Protection
M: Li+ or NiMH charging 10109-1

L: No battery or abnormal battery

3 GND <== 1 Negative battery terminal

10110-1

4 BAT_ID <== 1 BAT_ID is used to identify the type of attached

battery.
H: Li+ or no battery
L: NiMH

SIM Interface
Pin Signal
1 GND
2 5V
3 Not connected
4 Reset
5 Serial input/output
6 Clock
7 Not connected
8 Not connected

Issue A Section 2 MCUK990801G8

Revision 0 – 12 – Technical Guide
 RF OVERVIEW

3 RF OVERVIEW
3.1 Introduction
3.1.1 General Specifications
GD90 is a Dual Band product incorporating two switchable transceivers, one for the GSM900 band and another for the
GSM1800 (DCS1800) band. The transmit and receive bands for the mobile are given in the table below:

Tx Rx
GSM900 890-915 MHz 935-960 MHz
GSM1800 1710-1785 MHz 1805-1880 MHz

Other salient technical features are as follows:

GSM900 GSM1800 Units

Rx Bandwidth 25 75 MHz
Tx Bandwidth 25 75 MHz
Duplex Spacing 45 95 MHz
Number of Channels 124 374
ARFCN (Channel Numbers) 1-124 512-885
1st Tx Channel 890.2 1710.2 MHz
Last Tx Channel 914.8 1784.8 MHz
1st Rx Channel 935.2 1805.2 MHz
Last Rx Channel 959.8 1879.8 MHz
Maximum Tx Power 33.0 30.0 dBm
(Class 4) (PL5) (Class 1) (PL0)
Minimum Tx Power 5.0 0.0 dBm
(PL19) (PL15)

3.1.2 Description of Main PCB

All components required for the RF and Logic circuits, excluding the LCD module and backlight LEDs, are contained on the
Main PCB. The Main PCB has six layers made from FR4 material (Epoxide woven glass fabric copper-clad laminate as
specified in BS4584 Part 102 and prepeg as specified in BS4584 Part 103). Top and bottom layer tracks are gold-plated to
prevent oxidisation and enable better soldering. The board thickness is 0.9 mm (± 0.1 mm).
The RF components are located on both sides of the upper area of the Main PCB. To provide RF shielding, most of one side
of the Keypad PCB comprises a printed circuit groundplane. The Main board is connected to the Keypad PCB via a 34-way
dual in-line connector. A metallised plastic chassis is used to separate the Main and the Keypad PCB’s. When the chassis is
sandwiched between the Main and the Keypad PCB’s, the groundplane of the Main board together with the chassis forms an
effective shielded enclosure which prevents spurious emissions. The chassis has also been designed to provide smaller walled
sections which are used to isolate sensitive RF areas such as the VCTCXO and the VCO from high level interferers such as
the PA output.

3.2 Functional Description

3.2.1 Frequency Plan
The GD90 frequency plan is shown below

Tx Tx IF RFLO Tx IFLO Tx Unit

GSM900 890-915 270 1160-1185 540 MHz
GSM1800 1710-1785 130 1580-1655 520 MHz

Rx Rx 1st IF Rx 2nd IF RFLO Rx IFLO Rx Unit

GSM900 935-960 225 45 1160-1185 540 MHz
GSM1800 1805-1880 225 45 1580-1655 540 MHz

MCUK990801G8 Section 3 Issue 1

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Revision 0
Issue A

RF OVERVIEW
EFCH225MDQP2 45MHz
DUAL LNA IC (MACO)
PCNnGSM GN01073B
(MEC) DUAL RX SAW
Filter 3.8*3.8mm DCS IF SAW 2nd
Mixer (225MHz) Mixer PGC Demod I
(MACO)
(DCS)
DCS
LNA Q
DUAL RX SAW
3.8*3.8mm
(MACO)

(GSM) GSM
GSM DUAL LOCAL VCO Mixer TXON1
LNA UY76043A
(MACO)
GSM:1160~1185MHz RXON1
DCS:1580~1655MHz HITACHI
PCNnGSM BRIGHT-2
HD155123F RXON2
Figure 3.1: RF Block Diagram

LOOP PCNnGSM
ANT FILTER
CLOCK

DATA 1/2 CLOCK

V_PAON
Section 3

STROBE
– 14 –

PLL DATA
V_PAON GSM:540MHz 1/2 1/6
IC DCS TX:520MHz
PLL IC STROBE
MB15F03SL
RX:540MHz
[SSOP Package]
(Fujitsu) LOOP 3 wire bus control
Diplexer + 2 FILTER
1st, 2nd Mixer Gain
SW
LMC36-07A0503A 13MHz PGC Gain
(MURATA) PCNnGSM 13MHz VCXO
1/2 7.0*5.0mm
2nd LOCAL VCO
DUAL APC IC To (NDK)
HD155171T RAMP DATA (MACO) DC
MIXER PLL IC
(HITACHI) AFC

PCNnGSM
Ref.
LPF Coupler
Clock
(DCS)
LDC15H200J0897 PCNnGSM
(MURATA)
LOOP PHASE I&Q I
FILTER DETECTOR MODULATOR Q

Exciter
LPF Coupler MGA-81563
Dual PA (HP) DUAL TX SAW PCNnGSM
(GSM) Filter
PF08103B
MCUK990801G8

LDC15H200J0897 GSM:890~915MHz
Technical Guide

(HITACHI) 3.8*3.8mm
(MURATA) (MACO) DCS:1710~1785MHz
TX DUAL VCO
UY76044 10076-1
 RF OVERVIEW

Rx 1st IF Rx 2nd IF
935-960MHz
225MHz 45MHz
I

45MHz 90MHz
270MHz ÷2 ÷6
RF LO
1160-1185MHz
Fdiff ÷2
270MHz IF LO
VCO
540MHz
÷2

270MHz

Q
TX VCO Fcomparison
890-915MHz 270MHz 10077-1

Figure 3.2: GSM 900 Frequency Plan

Rx 1st IF Rx 2nd IF
1805-1880MHz
225MHz 45MHz
I

45MHz 90MHz
270MHz ÷2 ÷6
RF LO
1580-1655MHz
Fdiff ÷2
130MHz
IF LO VCO
260MHz Rx: 540MHz
÷2
Tx: 520MHz

Q
TX VCO Fcomparison
1710-1785MHz 130MHz
10078-1

Figure 3.3: GSM 1800 Frequency Plan

3.2.2 General
The major building blocks for the RF design are the Hitachi transmit (Tx) and receive (Rx) IC, Fujitsu RF-IF dual PLL and the
antenna subsystem.
In either receiver band, GSM900 or GSM1800, the Rx 1st IF is fixed at 225 MHz and 2nd IF at 45 MHz. Therefore, the 2nd
local oscillator is fixed at 540 MHz for receive mode.
In GSM900 transmit mode, the 2nd LO is reprogrammed to 540 MHz, the same for receive mode.
In GSM1800 mode, the 2nd local oscillator is re-programmed to 520 MHz. For this choice of IF, no transmitter in-band spurious
is believed to occur due to harmonics of the 1st LO.
The Tx VCO will be on-channel in either GSM900 or GSM1800 modes of operation.

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RF OVERVIEW

3.2.3 Antenna
The antenna is a fixed helical type.
A mechanical RF switch is used to route the RF signal from the external antenna for handsfree operation and test purposes.

3.2.4 Transmit and Receive

The transmit and receive paths of GD90 are covered in their own specific chapters later in this manual.

3.3 RF & Accessory Connector

In previous models the RF signal is routed to the accessory connector which contains a micro-switch. If the switch is open, the
RF signal is routed to the hands free unit. If it closed, the signal is routed back via the Main PCB to the antenna. This routing
of the RF signal up and down the Main PCB invariably has a finite power loss associated with it.
In addition, the GD90 has a limited PCB area and the routing of the RF signal in this way reduces further the available PCB
area required for the Dual Band circuit.
To alleviate these problems the RF connector is located close to the PA module. This reduces the loss and hence the PAs do
not have to be driven so hard. This allows the power supply voltage to be lower, thus improving battery performance.

Issue 1 Section 3 MCUK990801G8

Revision 0 – 10 – Technical Guide
 TRANSMITTER

4 TRANSMITTER
4.1 Introduction
This section provides a technical description of the transmitter circuit of the RF circuit. A circuit diagram of the whole system is
provided in the Service Manual.
The uplink frequencies for the GSM 900 and GSM 1800 can be calculated as follows:

4.1.1 Uplink Frequencies GSM 900

CHANNEL
UPLINK FREQUENCIES (MHz)
NUMBERS
1-5 890.200 890.400 890.600 890.800 891.000
6-10 891.200 891.400 891.600 891.800 892.000
11-15 892.200 892.400 892.600 892.800 893.000
16-20 893.200 893.400 893.600 893.800 894.000
21-25 894.200 894.400 894.600 894.800 895.000
26-30 895.200 895.400 895.600 895.800 896.000
31-35 896.200 896.400 896.600 896.800 897.000
36-40 897.200 897.400 897.600 897.800 898.000
41-45 898.200 898.400 898.600 898.800 899.000
46-50 899.200 899.400 899.600 899.800 900.000
51-55 900.200 900.400 900.600 900.800 901.000
56-60 901.200 901.400 901.600 901.800 902.000
61-65 902.200 902.400 902.600 902.800 903.000
66-70 903.200 903.400 903.600 903.800 904.000
71-75 904.200 904.400 904.600 904.800 905.000
76-80 905.200 905.400 905.600 905.800 906.000
81-85 906.200 906.400 906.600 906.800 907.000
86-90 907.200 907.400 907.600 907.800 908.000
91-95 908.200 908.400 908.600 908.800 909.000
96-100 909.200 909.400 909.600 909.800 910.000
101-105 910.200 910.400 910.600 910.800 911.000
106-110 911.200 911.400 911.600 911.800 912.000
111-115 912.200 912.400 912.600 912.800 913.000
116-120 913.200 913.400 913.600 913.800 914.000
121-124 914.200 914.400 914.600 914.800

Uplink frequency = 890 MHz + (ARFCN x 0.2 MHz)

e.g. for CH55
890 MHz + (55 x 0.2 MHz)
= 890 MHz + (11 MHz)
= 901 MHz

4.1.2 Uplink Frequencies GSM 1800

Uplink frequency = 1710 MHz + ((ARFCN - 511) x 0.2 MHz)
e.g. for CH512
1710 MHz + ((512 - 511) x 0.2 MHz)
= 1710 MHz + (0.2 MHz)
= 1710.2 MHz

MCUK990801G8 Section 4 Issue 1

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TRANSMITTER

4.2 Functional Description

I Q Dual Band Receiver (PART)

U101

Modulator

DC
Mixer

Antenna
Coupler Diplexer
Phase Dual Band PA + Sw.
E101 S101
Detector U104

Exciter
U103
900 900

Loop Dual Band

Filter Tx VCO
U102
1800 1800 Coupler
Dual Tx SAW E102
Filter
10086-1 FL101

Figure 4.1: Transmitter

The transmitter design is based on an IQ Modulator and operates at Class 4 (2W) in the GSM 900 band and at Class 1 (1W)
in the GSM 1800 band. The architecture has been carefully chosen to enable the GSM transmitter noise in receiver band
requirements to be met without the need for a duplexer.
The RF IC Bright2 provides the following transmitter functions:
I, Q Quadrature modulator
Down conversion mixer for modulated signal to intermediate frequency
Phase detector for the PLL modulation loop.
The IF LO signal generated by the IF VCO is modulated by the baseband I,Q signals in the quadrature modulator. Output from
the quadrature modulator is fed into the phase detector for the PLL modulation loop.
The output from the Tx VCO is fed into the down conversion mixer and is converted with the 1st LO signal which is generated
by the 1st VCO to IF frequency. The output signal from the down conversion mixer is fed into the phase detector for the PLL
modulation loop.
The charge pump output signal produced by the phase detector is fed back to the Tx VCO to generate modulated RF output.
The output from the Tx VCO is filtered before it is applied to the PA driver. This ensures that spurious emissions are well within
GSM specifications.
Output from the PA driver is amplified by the PA to any required level up to PL5 (33 dBm at the antenna) for GSM 900 and PL0
(30 dBm) for GSM 1800. PA output is applied to the antenna via a low-pass filter to remove unwanted harmonics.
A discrete diplexer is used after the PA buffer which provides low pass filtering for the 900 MHz band and high pass filtering
for the 1800 MHz band. The switching between the receiver and the transmitter for any band is achieved by means of pin diode
switches. The antenna ports of these switches are connected to the antenna or the handsfree RF connector. The hands free
connector incorporates a mechanical switch which enables the signal to be routed either to the antenna or to the hands free
connector depending on the operation required.
The RF LO is also a modular VCO which contains two VCOs, one for the 900 MHz band and the other for the 1800 MHz band.
The operation is similar to the Tx VCO in that the required RF VCO is switched by two control lines.
The IF VCO is a discrete design. Both the RF and IF LOs are designed around a dual PLL with the IF frequency range up to
600 MHz and the RF frequency range up to 2 GHz.

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 TRANSMITTER

4.2.1 GSM 900 Signal Levels

Typical case
Worst case

40
35
30
25
20
15
(dBm)

10
5
0
-5
-10
-15
Dual TX Power ATTN BPF Excitor ATT PA Coupler SW- ANT
VCO sprit Diplexer
10083-1

Figure 2.2: GSM 900 Transmitter Signal Levels

4.2.2 GSM 1800 Signal Levels

Typical case
Worst case

35
30
25
20
15
(dBm)

10
5
0
-5
-10
-15
Dual TX Power ATTN BPF Excitor ATT PA Coupler SW- ANT
VCO sprit Diplexer
10084-1

Figure 2.3: GSM 1800 Transmitter Signal Levels

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 RECEIVER

5 RECEIVER
5.1 Introduction
This Section provides a technical description of the receiver section of the RF circuit. A complete circuit diagram is provided in
the Service Manual.
The downlink frequencies for the GSM 900 and GSM 1800 bands can be calculated as follows:

5.1.1 Downlink Frequencies GSM 900

CHANNEL
DOWNLINK FREQUENCIES (MHz)
NUMBERS
1-5 935.200 935.400 935.600 935.800 936.000
6-10 936.200 936.400 936.600 936.800 937.000
11-15 937.200 937.400 937.600 937.800 938.000
16-20 938.200 938.400 938.600 938.800 939.000
21-25 939.200 939.400 939.600 939.800 940.000
26-30 940.200 940.400 940.600 940.800 941.000
31-35 941.200 941.400 941.600 941.800 942.000
36-40 942.200 942.400 942.600 942.800 943.000
41-45 943.200 943.400 943.600 943.800 944.000
46-50 944.200 944.400 944.600 944.800 945.000
51-55 945.200 945.400 945.600 945.800 946.000
56-60 946.200 946.400 946.600 946.800 947.000
61-65 947.200 947.400 947.600 947.800 948.000
66-70 948.200 948.400 948.600 948.800 949.000
71-75 949.200 949.400 949.600 949.800 950.000
76-80 950.200 950.400 950.600 950.800 951.000
81-85 951.200 951.400 951.600 951.800 952.000
86-90 952.200 952.400 952.600 952.800 953.000
91-95 953.200 953.400 953.600 953.800 954.000
96-100 954.200 954.400 954.600 954.800 955.000
101-105 955.200 955.400 955.600 955.800 956.000
106-110 956.200 956.400 956.600 956.800 957.000
111-115 957.200 957.400 957.600 957.800 958.000
116-120 958.200 958.400 958.600 958.800 959.000
121-124 959.200 959.400 959.600 959.800

Downlink frequency = 935 MHz + (ARFCN x 0.2 MHz)

e.g. for CH55
935 MHz + (55 x 0.2 MHz)
= 935 MHz + (11 MHz)
= 946 MHz

5.1.2 Downlink Frequencies GSM 1800

Downlink frequency = 1805 MHz + ((ARFCN - 511) x 0.2 MHz)
e.g. for CH512
1805 MHz + ((512 - 511) x 0.2 MHz)
= 1805 MHz + (0.2 MHz)
= 1805.2 MHz

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RECEIVER

5.2 Functional Description

The main building block for the Dual Band Receiver is the Hitachi Bright2 IC. The receiver is a double superhet type with the
1st IF at 225 MHz and 2nd IF at 45 MHz. The intermediate frequencies are common to both frequency bands.

The Rx IC contains the following stages:

1. Gain controlled 1st mixer for GSM 900 band.
2. Gain controlled 1st mixer for GSM 1800 band.
3. Gain controlled 2nd mixer.
4. Gain controlled IF amplifier
5. I,Q quadrature down converter.
6. Baseband Op Amps for further amplification and some filtering of the baseband I,Q signals.

5.2.1 Dual Band Receiver

DUAL Rx DUAL DUAL RX DUAL BAND RECEIVER (PART)

SAW LNA SAW U101
DIPLEXER FL201 U203 FL203
S101 IF
1st SAW 2nd Demodulator
PGC
Mixer Mixer
LPF I
Rx
Q
Tx GSM 900 900 900 FL200

HPF

Ext Rx
Ant.
Tx
GSM 1800 1800 1800

10085-1

Figure 5.1: Dual Band Receiver

RF input to the receiver is either via the antenna or via the H/F RF connector for test purposes. The input signal from the
antenna or the H/F RF connector is fed into the GSM 900/GSM 1800 dual band LNA MMIC via the Diplexer port, Tx/Rx
switches to the dual band Rx SAW filter. The diplexer band splits the two GSM frequency bands whilst the pin switches route
the signal flow from the receiver and the transmitter as required. The receiver 1st SAW filter provides the roofing filter for the
Rx front end.
The dual band LNA gain is constant, typically 18 dB for GSM 900 and 17dB for GSM 1800. Noise factor is typically 1.5dB for
both bands. Operation of the dual band LNA is controlled directly by the PCNnGSM band switch signal.
The output from the LNA passes through a dual BP SAW filter and is then fed into the 1st mixer for each band. Both mixers
are controlled by a 3-wire bus, typically providing between +9.5dB and -2dB gain for GSM900, and between +8.5dB and -3.5dB
for GSM 1800.
The IF output at 225 MHz from the 1st mixer is filtered by the differential IF SAW filter before it is fed into the 2nd mixer. The
use of differential filters eliminates the need for baluns and provides some cost and space advantage. The 2nd mixer is also
gain controlled from a 3-wire bus, typically between +13dB and -3.0dB. Gain switching is synchronised with the 1st mixer.
Output from the 2nd mixer at 45 MHz is filtered by an L-C network before it is fed to the gain controlled IF amplifiers.The IF
amplifier is gain controlled by a three-wire bus from -29 to +69 dB in 2 dB steps. This function is used for AGC purposes.
The output from IF amplifiers is fed into two quadrature mixers where it is converted down to baseband. The IF LO is generated
at 540 MHz by an external discrete VCO module. An on-chip divider on the Rx IC divides this six and then by two. It also
produces two outputs in quadrature to generate the baseband I and Q signals. The outputs from the mixers are connected to
external pins through a pair of buffers. Two on-chip Op Amps are used to amplify the AC signal from the mixers to meet the
overall signal performance requirements.
The DC level at the output of the Op Amps is 1.35 V with a 200 mV p-p single ended AC swing controlled by the AGC loop to
maintain optimum receiver performance.

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5.2.2 GSM 900 Signal Levels

The signal levels through the receiver IC for the GSM 900 band are given below.

Typical Case
Worst Case

10.0 Large Signal

0.0
-10.0

-20.0
-30.0
-40.0
-50.0
(dBm)

-60.0
-70.0

-80.0
-90.0

-100.0
-110.0

-120.0
ANT DIPLEX + RX LNA RX MIX IF 2nd 2nd IF I/Q
SW BPF BPF SAW MIX IF FL AGC Demod
10081-1

Figure 5.2: GSM 900 Nominal and Worst Case Signal Levels

5.2.3 GSM 1800 Signal Levels

The signal levels through the receiver IC for the GSM 1800 are given below.

Typical Case
DCS RX Level Diagram
Worst Case
10.0 Large Signal
0.0
-10.0

-20.0
-30.0
-40.0
(dBm)

-50.0
-60.0
-70.0
-80.0
-90.0

-100.0
-110.0

-120.0
ANT DIPLEX + RX LNA RX MIX IF 2nd 2nd IF I/Q
SW BPF BPF SAW MIX IF FL AGC Demod
10082-1

Figure 5.3: GSM 1800 Nominal and Worst Case Signal Levels

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 BASEBAND OVERVIEW

6 BASEBAND OVERVIEW
6.1 Introduction
The main Baseband circuitry is located with the RF circuits on the Main PCB, while the baseband sub-circuits, comprising keys
and LCD backlights, are located on the Keypad PCB.
A metallised plastic chassis is used to separate the Main and the Keypad PCBs. The continuous chassis design is important
for EMC purposes. When the chassis is sandwiched between the two PCB assemblies, the groundplane of the Keypad PCB
together with the chassis forms an effective shielded enclosure, preventing spurious emissions.

6.2 Functional Description of the PCB

The GD90 baseband is based around a two-chip GSM chipset developed by Texas Instruments. One chip (GEMINI) carries
out signal processing with DSP and CPU, and the other chip (VEGA3) contains the analogue interface chip. The highly
integrated nature of these components means each contain a large number of functions.

GEMINI VEGA
LEAD Megamodule
8-Bit LPF ULI
JTAG TEST & PLL & XIO BURST DIFF GMSK I DAC
EMULATION CLOCKS STORE ENCODE MOD 8-Bit ULQ
Q DAC LPF
TEST & ROM CPU XIO

INTER PCB CONNECTOR

DSP SERIAL I/F
EMULATION & ANTIALIASING DLI
RAM CORE FILTER SIGMA-DELTA FILTER
IRQ API SPI ANTIALIASING DLQ
FILTER SIGMA-DELTA FILTER
SYSTEM DAI RST APC PARAMP
SIMULATOR (D/A)
nLVA_INT INTERNAL REGISTERS AFC AFC
DATA INTH
ADAPTER (D/A)
SERIAL I/F
ACCESSORY
CONNECTOR

APIF
MCU

TESTSET SYSTEM
T DAI
TPU S SIMULATOR
TEST UART
MOBILE P
5V BPF SIGMA-DELTA LPF
DC/DC ARM TDM
VOICEBAND

SIM
SERIAL I/F

CONVERTER SIM CORE TIME-

CARD I/F A
INTER PCB CONNECTOR

+ LEVEL BASE C
SHIFTER T BPF SIGMA-DELTA
TIMER
VIBRATOR I/O
MICROWIRE MEMORY CLKM SLICER SLICER 5 INPUT AGC TEST
I/F I/F 10-BIT A/D (D/A)

BUZZER
BAT_VOLT
CURRENT

VSET

BACK- POWER ON/OFF

LIGHT CONTROL &
POWER SOURCE RAPID CHARGE
FAILURE CIRCUIT & BATTERY JTAG
KEYPAD MONITORING
CIRCUIT
VOICE EEPROM FLASH SRAM LCD EXTENDED
MEMO 2K*8 1M*16 256K*8 OUTPUT
TRICKLE
CHARGE
CIRCUIT
nLOGIC_PWR
nHF_SENSE

BAT_TEMP

RX_AUDIO
TX_AUDIO
EXT_PWR
IGNITION

BAT_ID
13MHz

VBAT

INTER PCB CONNECTOR ACCESSORY

CONNECTOR

BATTERY
10075-1

Figure 6.1: Baseband Block Diagram

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BASEBAND OVERVIEW

6.2.1 Keypad
The Keypad has a 5 x 5 matrix in rows and columns, allowing 25 keys to be scanned. Each row has a built-in pull-up resistor
and the column line outputs are selected low. On a key press, the row input is pulled low by the corresponding column
generating a keypad interrupt. To ascertain which key has been pressed, the software asserts all columns high then takes each
one low. While each column is held low the rows are polled to see which one has been pulled low.
As the END key doubles as ON / OFF key, it is allocated an entire row of the keyboard scan.
To eliminate false key presses, i.e. key bounce, the key has to remain pressed for a minimum of 20 ms.
Keyboard scanning is software controlled. Key pressed is indicated by an interrupt, but key release is controlled by software.

KBR(0:4)
4 3 2 1 0
TP762 TP763 TP764 TP765 TP766
KBC(0:4)
7 4 1
TP757 *
S701 S706 S711 S716
0

0 8 5 2
TP758
S702 S707 S712 S417
1

# 9 6 3
TP759
S703 S708 S413 S718
2

OK < v SND
TP760
S704 S709 S714 S719
3

CLR > v PB
TP761
S705 S710 S715 S720
4

TP767
D722
VOICE_MEMO
nPOWKEY

2
1
S721 3
D729

PWR/END
10067-1

Figure 6.2: Keypad Matrix

6.2.2 Subscriber Identity Module (SIM)

The SIM interface is designed to support 3 V and 5 V SIMs.
The GD90 GEMINI process is unable to support 5 V tolerant inputs. Therefore, in order to Interface GEMINI with a 2.8 V supply,
and the SIM with a 5 V supply, it is necessary to include a level shift. U505 is able to perform the required level shift. In addition
the device includes a switched capacitor charge pump DC/DC converter to generate the 5 V SIM supply from D2V8.
The SIM is initially activated by U505 with a 3 V supply and checks Status identification after receiving an ATR command. If
U505 detects a 3 V technology SIM, it operates it at 3 V. If a 5 V SIM, operation is switched to 5 V. If a faulty ATR is received
at 3 V, an error handling procedure is initiated. If the error handling does not result in an errorless ATR, the SIM is activated at
5 V. If no ATR is received at 3 V, the SIM will be deactivated and re-actived at 5 V.

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 BASEBAND OVERVIEW

6.2.3 Time Processing Unit (TPU)

The TPU provides the GSM TDMA timing requirements for the system, external timing signals are provided by an area of
Microcode within the GEMINI chip.

GEMINI Pin Description

65 VEGA BENA
66 VEGA BCAL
67 VEGA BULON
68 VEGA BDLON
69 RF PA_ON
70 RF PCNnGSM
118 RF signal RXON1
119 RF signal RXON2
58 VEGA_SEL
59 RF PLL_STRB
60 RF signal TXON
61 N.C.
62 RF IFAGCEN

6.2.4 CPU Memory

GD90 uses a Dual Operation (DL) Flash memory, comprising a 16 bit Flash ROM and 8 bit SRAM. DL Flash memory is able
to access one block of memory while writing another block of memory.

6.2.5 LCD
The LCD assembly is a sub-assembly comprising the LCD glass and driver chip on a flexible PCB with connection to the
Keypad PCB via zebra strip connectors.
A 96 x 58 pixel graphical display is used to give maximum information. It can also display Chinese characters and large
numbers. For example, 12 characters x 2 lines or 16 characters x 3 lines, both with two lines of icons.

View Area
Effective Area

0.018
18.02 23.2 min

0.293

0.018
0.245
25.23
29.4 min

Dimensions are in millimetres (mm)

10068-1

Figure 6.3: LCD Dimensions

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6.2.6 Real Time Clock

The Real Time Clock (RTC) and Alarm function is provided by U604 running at 32,768 MHz. It interfaces to the CPU via a four
serial lines: CE (chip enable), SCLK (serial clock), SI (serial input) and SO (serial output). To maintain power to the clock when
the main battery is removed, a small rechargeable back-up battery (VBACKUP) is used. This power source also provides power
back-up for data held in the SRAM.
The RTC can be calibrated using a high-precision oscillation adjustment function. This gives a maximum adjustment range of
±189.2 ppm in increments of 3 ppm. Addition functions of the RTC are date, alarm, periodic interrupt, 32 kHz output, supply
voltage monitoring and oscillation halt sensing.

6.2.7 Microphone
To provide improved speech pick-up, noise immunity and reduced echo, the microphone is a noise cancelling type. The GSM
standard requires that when in Handheld mode the sending audio frequency response must fit within the mask shown below.

5
dB

-5

-10

-15
100 1000 10000
Frequency (Hz)
10069-1

Figure 6.4: Handheld GSM Transmit Audio frequency response mask

When using the Handsfree feature GSM requires that the sending audio frequency response must fit within the mask shown
below.

5
dB

-5

-10

-15
100 1000 10000
Frequency (Hz)
10070-1

Figure 6.5: Handsfree GSM Transmit Audio frequency response mask

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 BASEBAND OVERVIEW

6.2.8 Speaker
Because Vega runs from a 2.7 V supply, a low impedance (dynamic) speaker must be used. The GSM standard requires that
the receive audio frequency response in Handheld use must fit within the mask shown below. GD90 is designed to meet
Handheld requirements with a type 1 artificial ear.

dB

-5

-10

-15
100 1000 10000
Frequency (Hz)
10071-1

Figure 6.6: Handheld GSM Receive Audio frequency response

Volume levels

Volume level PGA Volume Total Gain

1 3dB 0dB 3dB
2 0dB 0dB 0dB
3 -3dB 0dB -3dB
4 -3dB -6dB -9dB

When using the internal Handsfree feature, the receive audio frequency response must fit within the mask shown below.

0
dB

-5

-10

-15
100 1000 10000
Frequency (Hz)
10072-1

Figure 6.7: Handsfree GSM Transmit Audio frequency response mask

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6.2.9 Buzzer
The volume level of the buzzer is defined by the 6 bit PWM register setting in GEMINI I/O. The buzzer tone is then
superimposed on this level using software.
Timer 1 in GEMINI is used to time the period between switching the buzzer on and off to make the tone. For more complex
buzzer ringing tones, the buzzer volume level can also be altered after each time-out of Timer 1.

VBAT
BUZZER

BUZ_VOL0

BUZ_VOL1

BU from GEMINI

CHARGE IC
10074-1

Figure 6.8: Buzzer Control Circuit

6.2.10 Timers
Two 16 bit general purpose timers which can be used either as auto-reload or 1 shot timers to provide interrupts to the
ARM CPU. The timer clock duration is defined by a prescaler and 16 bit register. The Timer unit receives a 928 kHz clock from
the GEMINI clock module. A combination of prescaler and timer register gives a time range of 1.078 µsec to 9.039 sec.

Timer Function Setting

1 Buzzer Timer Tone frequency
2 Watch Dog Timer 40 ms

6.2.11 USART
The serial port is compatible with an Intel 8251 and has six pins.

USART Pin Assignments

Signal Name Pin No. Function I/O

TXD 113 USART serial data Tx O
RXD 111 USART serial data Rx I
DTR 114 Used as I/O pin O
DSR 110 Used as I/O pin I
TXE 115 Used as I/O pin O
RXE 116 Used as I/O pin O

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 GEMINI

7 GEMINI
7.1 Introduction
Gemini contains the DSP, CPU and GSM timing functions and many peripheral functions. The software for the DSP is
contained in masked ROM.

7.2 Functional Description

TIMERS

UART
BASEBAND SPEECH PWM
INTERFACE INTERFACE
GSM
TDMA

INTERFACE
TIMER
TPU DSP
CORE ARM

I/O

SERIAL I/F
DSP ROM

DSP RAM
JTAG

IRQ
SIM MEM
I/F I/F

10087-1

Figure 7.1: GEMINI Block Diagram

7.2.1 Digital Signal Processor

The Digital Signal Processor (DSP) core is compatible with the Texas Instruments TMS350C5xx family of DSPs. Included in
the DSP core is an interface to the CPU by a shared memory interface.
The DSP memory is also located within GEMINI. The ROM code size is determined by the size of the software.

7.2.2 CPU
The CPU is an ARM7 32 bit RISC CPU with 16 bit instruction set. The CPU is designed to access 32 bit memory and
peripherals; a further module within the GEMINI chip allows access to 8 or 16 bit memory.

Memory Access Times

Clock Speed Memory Access Time Additional Access time per wait state
19.5 MHz 41 ns 51 ns
13 MHz 67 ns 77 ns
9.75 MHz 91 ns 102 ns
6.5 MHz 144 ns 154 ns
4.875 MHz 194 ns 204 ns
3.75 MHz 298 ns 308 ns

For 120 ns access FLASH and RAM a 13 MHz clock gives 1 wait state access to both devices.

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7.2.3 Memory Interface

The memory interface allows the 32 bit CPU to access 16 and 8 bit devices, and allows the addition of wait states to memory
access. The memory interface allows between 0 and 7 wait states to be added. The ROM area is hardware write protected, a
FLASH write enable bit in the ROM wait state configuration register can be used to enable write access the ROM area.

CPU Memory MAP

Device Name Start address Size Use Bus width

ROM 0000:0000 2M FLASH 2 Mbytes 16 bits
RAM 0020:0000 2M RAM 256 kbytes 8 bits
BUS CNTRL 0040:0000 1M wait state registers 16 bits
API RAM 0050:0000 8k CPU/DSP shared ram 16 bits
APIC 0050:4000 1k CPU/DSP interface controller 16 bits
TPU RAM 0050:4400 1k GSM timer Microcode RAM 16 bits
SIM 0050:4800 1k SIM interface 16 bits
TSP 0050:4C00 1k Timed Serial port 16 bits
INTH 0050:5000 1k Interrupt controller 16 bits
TPU REG 0050:5400 1k GSM timer registers 16 bits
CLKM 0050:5800 1k Clock control module 16 bits
TIMER 0050:5C00 1k software timers 16 bits
APIF 0050:6000 1k ARM peripheral interface 16 bits
UWIRE 0050:6400 1k Synchronous Serial port 16 bits
ARMIO 0050:6800 1k Keypad, buzzer, LCD & I/O 16 bits
8251 0050:6C00 1k UART 16 bits
CS2 0060:0000 2M LCD driver 8 bits
nCS0 0080:0000 2M Extended I/O 8 bits
nCS1 00A0:0000 2M not used -

7.2.4 Interrupt Handler

The ARM CPU has two interrupts, FIQ is a Fast non-maskable interrupt and IRQ is a standard maskable interrupt.
Gemini has 11 interrupt sources. The Interrupt handler assigns priorities to these interrupts and routes them to either the FIQ
or IRQ inputs of the ARM CPU. Additionally, the interrupt handler controls waking up of the CPU on receiving an unmasked
interrupt, if the CPU is in sleep mode.
For GD90 the FIQ interrupt is reserved for the power supply fail priority interrupt.

Interrupt Level Assignments

Interrupt source Description Interrupt detection

IRQ_TIM1 Buzzer timer Edge sensitive
IRQ_TIM2 operating system timer Edge sensitive
IRQ_API DSP Interface interrupt Rising Edge sensitive
IRQ_EXT Power supply fail interrupt Low Level sensitive
IRQ_USART UART Interrupt Level sensitive
IRQ_ARMIO Keypad Interrupt Low for 1 clock period
IRQ_FRAME Frame Interrupt Edge sensitive
IRQ_PAGE Page Interrupt Edge sensitive
IRQ_TIM_GSM Edge sensitive
IRQ_TSP Timed serial port Interrupt Edge sensitive
IRQ_SIM SIM Interrupt Level sensitive
IRQ_F_USART Fast interrupt from USART Level sensitive
IRQ_RSS Radio subsystem interrupt Edge sensitive

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 GEMINI

7.2.5 General Purpose I/O

The general purpose I/O includes keypad scanning, two PWM ports and 16 general purpose I/O lines. The I/O lines are
multiplexed onto other functions, if I/O is selected the other function is unavailable.

I/O Pin Assignments

Signal Name Pin No. GD90 Function Description I/O

WDT_PULSE High Pulse _/ \_ 500 ns min.

I/O 1: RXE 116 LOGIC_PWR H = PSU kept on O
L = PSU off
I/O 2: TXE 112 nEXT_PWR L = External Power Supply 1
H = Battery Power Supply
I/O 3: DTR 114 HF_ON H = Handsfree On O
L = Handsfree Off
I/O 4: DSR 110 nIGNITION H = IGNITION Off I
L = IGNITION On
I/O 5: EXTINT 109 nLVA_INT Fast non-Maskable Interrupt N/A
I/O 6: nRESETOUT 106 SIM5Vn3V H = SIM PWR 5V O
L = SIM PWR 3V
I/O 7: SIM_RnW 105 ADC_ON ADC Sample control O
H = ADC read enable
L = ADC read disable
I/O 8: SIM_PWCTRL 104 SIM_PWRCNT H = SIM Power Enable O
L = SIM Power Disable
I/O 9: SIM_CD 95 nON_HOOK H = Off hook I
L = On hook
I/O 10: LT 134 BKLT (LED output) Backlight On O
Backlight Off
I/O 11: ARMCLK32 73 nHF_SENSE H = No Hands Free I
L = Hands Free connected
I/O 12: TSPACT(0) 65 TSPACT(0) BENA N/A
I/O 13: nPWRCS 56 VEGA_SLEEP H = VEGA SLEEP O
L = VEGA Active
I/O 14: nCS1 50 LO_EN H = RF Power ON (VCO etc.) N/A
L = RF Power OFF
I/O 15: nCS0 48 nCS0 To make Triggered signal with R/nW N/A
signal.

Specific I/O are reserved for the backlight, buzzer and keyboard. The luminosity of the backlight and the loudness of the buzzer
are controlled by a PWM (Pulse Width Modulation) and melody volume control signals.
The PWM are outputs only.

I/O Pin Assignments

Signal Gemini Pin GD90 Use

LT 134 This pin is used by general purpose I/O (10)
BU 120 Buzzer
6 Bit PWM

The PWM is clocked at 13/3 MHz.

Tones are generated by using Timer 1 to switch the buzzer PWM on and off at the frequency of Timer 1. By altering the value
of Timer 1, ringing tones can be played.
During hands free operation, the ringing tone is derived from the DSP tone generator.

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8 VEGA
8.1 Introduction
VEGA contains the interface circuits to the Audio, RF and auxiliary analogue functions for the baseband circuit.

8.2 Functional Description

TIMING JTAG
SIGMA
FILTER
DELTA
10 bit
BURST GMSK I DAC FILTER
STORE MOD 10 bit FILTER
Q DAC
SIGMA
FILTER
8 bit DELTA
FILTER SIGMA-DELTA
8 bit
FILTER 10 bit
SIGMA-DELTA 8 bit
DAC
8 bit DAC
RAMP DATA
DAC
SP INTERFACE
13 bit
DSP INTERFACE
DAC
10088-1

Figure 8.1: VEGA Block Diagram

8.2.1 Uplink I and Q

VEGA performs GMSK modulation on Data samples received from GEMINI at 270 kbits per second.

Timing interface

Din Burst Burst Timing Offset

Register Control Register

270 kHz

Cosine Low Pass ULIP

8 bit DAC
Table Filter
ULIN

Differential Gaussian
Integrator
Encoder Filter phase(i) 16 *270 kHz

Sine Low Pass ULQP

8 bit DAC
Table Filter
ULQN

Power Ramp-up
Register Shaper
Offset
Register

To Power
10089-1 control DAC

Figure 8.2: Functional structure of the baseband uplink path

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8.2.2 Downlink I and Q

Offset Offset
Calibration Register

SUB

DLIP Antialiasing Sigma_Delta SINC FIR

Filter Modulator Filter Filter
DLIN
To baseband
serial
interface
fs1=6.5 MHz fs2=1.08 MHz fs3=270.8 kHz

DLQP Antialiasing Sigma_Delta SINC FIR

Filter Modulator Filter Filter
DLQN
SUB

Offset Offset
Calibration Register
10090-1

Figure 8.3: Functional structure of the baseband downlink path

8.2.3 Power Amplifier Ramp

The PA Ramp is formed by two D/As. The first, a 5 bit D/A, defines the ramp shape; the second, an 8 bit D/A, defines the
maximum level.
The ramp shape is defined by 64 steps. The shape can be defined differently for rising and falling ramps. Typically a raised
cosine shape will be used as a starting basis of the ramp shape.

Ramp Down Ramp Up

35.00 35.00

30.00 30.00

25.00 25.00
5 bit D/A Value
5 bit D/A Value

20.00 20.00

15.00 15.00

10.00 10.00

5.00 5.00

0.00 0.00
21

51
21

51

12

42
24
18

27

30

33

36

54

60
39

48

57

63
15

45
0

9
12

42
24
18

27

30

33

36

54
39

48

57

60
15

45

63
0

Step Step
10091-1

Figure 8.4: Example for the PA ramp

The raised cosine shape will be modified to compensate for RF circuit characteristics.
The ramp time is selectable between each step being 1/16 of a bit and each step being 1/8 of a bit giving a maximum ramp
time of either 14.77 µs or 29.53 µs.
An 8 bit value is used to program the ramp output level.

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8.2.4 AFC Control

The 13 MHz system clock frequency is controlled by a 13 bit sigma-delta D/A in the VEGA chip

3/5V

1-BIT DAC
13-BIT DIGITAL AFC
& LOW-PASS
MODULATOR
FILTER

OUTPUT SWING
CONTROL
RINT1 RINT2 VTCXO

PROGRAMMATION REGISTER
CEXT

10092-1

Figure 8.5: AFC block diagram

8.2.5 Audio
VEGA provides the analogue interface for the digital audio samples processed by the DSP in GEMINI.
Voice Uplink Path

MICBIAS Bias
Generator

MICIP Microphone Sigma_Delta IIR To voice

SINC
PGA Bandpass serial
MICIN Amplifier Modulator Filter Filter interface

fs1=1MHz fs2=40KHz fs3=8.0KHz

AUXI Auxiliary

Amplifier
10093-1

Figure 8.6: Voice ADC block diagram

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VEGA

Voice Downlink Path

Auxiliary
AUXO
Amplifier

EARP Smoothing IIR From voice

Earphone Filter One bit Sigma_Delta SINC
Interpolation Bandpass serial
EARN Volume Cont DAC interface
Amplifier & PGA Modulator Filter Filter

fs1=1MHz fs2=40KHz fs3=8.0KHz

10094-1

Figure 8.7: Voice DAC block diagram

8.2.6 Auxiliary A/D

VEGA provides five A/D inputs.
GD90 takes advantage of the A/D inputs on VEGA allowing external power to be monitored with just two resistors each and no
need for a buffer transistor.

VEGA input Pin Number Use Range

ADIN1 36 Battery Voltage 000h = 0V
(BAT_VOLT) 3FFh = 5.5 V
ADIN2 37 Battery ID 000h ~ 135h = Ni-MH
(BAT_ID) 136h ~ 3FFh = Li, Li-polymer
ADIN3 38 Battery Temperature 084h = +70°C
(BAT_TEMP) 199h = +25°C
346h = -20°C
greater than 3F0h = No Battery
ADIN4 39 Adaptor Sense 000h ~ 176h = Data Adaptor connected
(ADP_SENSE) 177h ~ 1CFh = RS232 Direct Cable connected
20Fh ~ 293h = SMS Cable connected
299h ~ 334h = Headset Adaptor connected
other values = No accessory connected
ADIN5 40 Charging Current 000h = 0 mA
(CURRENT) 3FFh = 1200 mA

8.2.7 Charging Voltage Control DAC

Vega provides 10 bits DAC for AGC control. As GD90 does not control Rx gain by DAC, it uses it for charging control. The DAC
output is able to control accurately the charging voltage for Li+ and Li-polymer batteries. GD90 has electrical volume for
calibration of this DAC.

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 POWER SUPPLIES

9 POWER SUPPLIES
9.1 Introduction
This section describes the Power Supply Unit (PSU) used on the GD90 Main PCB and the method by which it is controlled.
The Battery life during GSM1800 operation benefits from lower transmit power and higher PA efficiency and is therefore more
efficient than when operating in GSM900.
This section has detailed information on:
1. An overview of the circuit functionality.
2. Powering-up the phone.
3. Powering-down the phone.
4. Power management.

9.2 Overview
The logic circuit uses three separate power supplies as follows:
1. 2.8 Volts supply is used for the main power supply, 2V8 provides power to the digital part of the baseband circuit (Gemini,
Memory and LCD). A2V8 is used to power the analogue part of the baseband circuit (Vega and voice memo).
2. 1.8 Volts is provided to power internal blocks within the Gemini (ARM, DSP, ASIC).
3. 5.0 Volts (SIM_PWR) is provided to power the SIM and the SIM interface. This is enabled only when it is necessary to
communicate with the SIM.
The RF circuit uses three power supplies each provided by a separate 2.8 Volt regulator within U401. They are VSRF and
VS_VCO which are present when the LO_EN signal is present, and VS_VXCO which are present with the signal RF_ON. The
power amplifiers are powered directly from the battery VBAT.

9.3 Power-up
The power-up procedure has two phases. If an initial check to see if the battery is in good condition is successful, the second
phase determines the source of the power-up request, key press, external power, accessory, etc. and acts accordingly.
The phone can be defined as powered-on whenever the linear regulators are active. It is not always obvious to the user that
the phone is powered-on as it may be in one of four modes:

Mode Description
Sleep In this mode the CPU has been prevented from deactivating the linear regulators by EXT_PWR.
There is no CPU activity.
Charge The CPU is alive but may perform only battery charging functions and monitor the power key.
Restricted LEDs light, beeps, can charge battery etc. but it is not permitted to use the radio.
Active The mobile is fully functional; LEDs light, beeps, search for network etc.

9.3.1 Battery Condition

The CPU must check the battery condition before deciding to power-up. The CPU can measure battery voltage and
temperature. If the battery temperature measurement is invalid, a non-standard battery has been fitted, the battery is missing
or the whole phone is operating far outside its specified temperature range, the phone is not powered-up. The CPU will regularly
monitor the battery condition while the phone is on.
If EXT_PWR is present, the regulators will be forced on and the CPU will be unable to deactivate them. If the CPU wants to
power-down, all it can do is to enter sleep mode.

Battery Voltage (V) Temp. reading nEXT_PWR Result

X (don't care) invalid 0.5 V Power-down (battery fault)
X invalid 1.2 V Sleep (battery fault)
<3.0 X <0.5 V Power-down (low battery)
<3.5 valid 1.2 V LOW
>3.5 valid X OK

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9.3.2 Power-up Sequence

The power-up sequence can be initiated by pressing the power key, or by applying a power source to the EXT_PWR signal
line. Both enable the linear regulators and the CPU becomes active. The CPU must then check the battery condition; if the
phone is not required to power-down or sleep immediately, the result must be OK or LOW. The CPU then checks to see if a
hands-free unit is connected by polling the nHF_SENSE signal, LOW when HF is connected.
Now the CPU can determine whether to remain powered-up or not, according to the truth-table shown below. In each case the
active parameters are shaded.

Battery Condition HF nEXT_PWR nIGNITION KBR0 LOGIC_PWR Mode

OK X X X 1 1 active
LOW X >1.2 V X 1 1 restricted
OK or LOW no >1.2 V X 0 1 charge
OK yes >1.2 V <0.5 V 0 1 active or charge
LOW yes >1.2 V <0.5 V 0 1 restricted or charge

With a hands-free unit connected, the phone can be configured via the MMI to power-up and down with transitions of the vehicle
ignition. These are sensed by the CPU on nIGNITION, LOW when the ignition is on.
Any other state than those in the table will cause the phone to deactivate the PSU by setting STAY_ALIVE LOW.
While the CPU is active, it must monitor the battery condition and accessory connectivity and change state accordingly.

Current Mode HF nEXT_PWR nIGNITION KBR0 Battery Condition New Mode

Charge X X X 1 OK active
Charge X 1.2 V X 1 LOW restricted
Restricted X X X 0 OK active

9.4 Power-down
There are two power-down procedures:

Procedure
Normal power-down
Emergency power-down
Description
In this case, the software has full control over the power-down procedure. Calls can be
terminated gracefully etc. In some cases the PSU is not deactivated but there is a
change of operating mode.
This situation is caused by battery removal and is flagged by EXTINT. In this case the
CPU only has time to perform a subset of the normal procedure. The priority is to
prevent corruption of SIM data.

The truth-table for the power state transitions are shown below, the cause of a transition is shaded. In some cases the phone
does not power-down completely but may enter a state of reduced functionality, e.g. from active to charge mode.
When the new mode is OFF or sleep, the CPU will set STAY_ALIVE LOW.

Current mode Battery Voltage HF nIGNITION EXTINT KBR0 nEXT_PWR power-down New mode
X X X 1 X <0.5 V normal OFF
X X X X 0 X X emergency OFF
X X X X 1 1 <0.5 V normal OFF
active <3.5 V X X 1 0 >1.2 V normal restricted
active <3.5 V no X 1 1 >1.2 V normal charge
active <3.5 V yes >2.5 V 1 1 X normal OFF
active <3.5 V yes <0.5 V 1 1 >1.2 V normal charge
active <3.5 V yes >2.5 V 1 0 X normal OFF
active X no X 1 1 >1.2 V normal charge
active X yes <0.5 V 1 1 >1.2 V normal charge
active X yes >2.5 V 1 1 X normal OFF
active X yes >2.5 V 1 0 >1.2 V normal OFF
active X X X 1 0 <0.5 V normal OFF

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 POWER SUPPLIES

9.5 Power Management

The power supply circuit supplies regulated power to the base-band parts, controls battery charging and monitors battery
usage.
The Power Management section consists of five parts as follows:
1. Power Source.
2. Power On/Off Control & Power Source Failure.
3. Voltage Regulation.
4. Battery Charging & Monitoring.
5. Accessory Control.
The power amplifiers used in the GD90 are powered directly from the battery supply to maximise the power available to them.
They operate at full specification between 3.0 and 3.6 Volts.

9.5.1 Power Source

Given the high-end nature of the GD90, Lithium-ion (Li+) cells are used for the standard battery pack. The advantages of using
Li+ cells are reduced weight, size and improved gravimetric and volumetric energy densities compared to that of the Nickel-
Metal-Hydride (NiMH).

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 MCUK990801G8
Technical Guide
VBAT EXT PWR 2V8 A2V8 2V8 1V8
Battery Trickle Charge
Circuit
3.8V MCU SERIAL INTERFACE
Reg Vega Gemini
U602 U601
VBAT 2V8 EXT_PWR
BAT_ID nR eset
BAT TEMP BAT_VOLT 13MHz
nADP DETECT CURRENT
Rapid
Protection NiM H:GND 13MHz VSET Charge nHF_ON
Circuit nRESET CHARGE_ON Control &
ADCON Battery
Monitoring
10k 25C PA ON Circuit
2V8
VBAT

VBAT 2V8

nPOWKEY
nEXT_PWR
nON_HOOK
nIGNITION
nLVA_INT
LOGIC_PWR
Accessory VBAT EXT PWR SIM5Vn3V

Section
Interface

– 42 –
VBAT 2V8 1V8
Power On/Off 3V3
nADP_SENSE Control & Power
1V8
Source Failure Backup
On/Off REG
IGNITION Circuit Battery
nHF_SENSE
nLOGIC_PWR
nHF_ON
2V8 A2V8 SIM_PWR VBAT VSRF VBAT VSVCO
nRADIO_MUTE
CHARGE_ON 5V Charge 2V8 2V8
ON_HOOK Pump DC/ REG REG
DC

3V3
nPCWKEY U401
VBAT VSVCXO

EXT
2V8 2V8
REG REG U350
POWER SUPPLIES

U508 TCVCXO
nRESET

13MHz

10079-1

Revision 0
Issue A
Figure 9.1: Power supply block diagramD70-0901
 POWER SUPPLIES

9.5.2 Power On/Off Control

The hardware model for the Power On/Off Control and Power Source Failure functions can be expressed by the following
boolean expression and logic diagram.
On/Off = VBAT + (LOGIC_PWR · RTC_INT · (nLVA_INT + (nPOWKEY · nIGNITION · nEXT_PWR)))

nLVA_INT

nPOWKEY
nIGNITION
nEXT_PWR

LOGIC_PWR On/Off

RTC_INT

VBAT

10080-1

Figure 9.2: Power On/Off Control & Power Source Failure Logic Diagram

On/Off: Initially this active low signal is under Hardware control, the purposes of which are as follows:
1) Enable 2V8, A2V8 & 2V5 voltage supplies to Baseband.
2) Enable VSRF & VSVCXO voltage supplies to RF.
3) Generation of 13 MHz Master Clock signal.
4) Set nRESET signal LOW.
5) Wait approximately 200 ms for the voltage output of the regulators and 13 MHz Clock to become stable. Allow reset of
GEMINI and VEGA internal blocks.
6) Set nRESET HIGH causing the ARM processor to start from address 0.

9.5.3 Power Source Failure

The SIM card contains EEPROM. If power fails while the SIM is active, the SIM may corrupt its memory as the power supply
drops out of specification.The nLVA_INT is a non-maskable interrupt to the CPU which forces exception processing whenever
the battery voltage falls below 2.8 V.
Also, the RTC will detect if Back-up fails. This is determined by Gemini at the next power-up.
nRESET is connected to the Gemini reset pin. A 2.4 V voltage detector in the charge ASIC generates the nRESET signal.

9.5.4 Voltage Regulation

The GD90 has the following power sources:
D2V8 : Baseband power supply for digital circuitry (GEMINI, Memory and LCD)
Voltage: 2.8 V ± 3 %
Current: 300 mA max.
Dropout: 100 mV max. (load = 200mA)

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POWER SUPPLIES

D1V8 : Power supply for GEMINI process version 1833C07 (ARM, DSP and ASIC)
Voltage 1.8 V ± 3 %
Current 120 mA max.
A2V8 : Baseband power supply for Analogue circuitry (VEGA and Voice-Memo)
Voltage 2.8 V ± 3 %
Current 100 mA max.
Dropout: same as D2V8
SIM5V : SIM power supply (SIM & GEMINI/SIM interface)
Voltage 5.0 V ± 5 %
Current 50 mA max.
EXT_PWR : Power supply for battery charger
Voltage 5.8 V ± 0.2 V
Current 720 mA ± 30 mA
2V5 :VSRF, voltage supply for RF circuit, only turned on when LO_EN signal is high
2V5 :VS_VCO, voltage supply for VCO, only turned on when LO_EN signal is high
2V5 :VS_VXCO, voltage supply for RF circuit, only turned on when RF_ON signal is high

9.5.5 Battery Charging & Monitoring

The status of the LCD battery icon is determined by the value of BAT_VOLT returned from VEGA, the battery ICON has four
states.
The battery charging is controlled by the CPU within the phone. If rechargeable cells are detected and the temperature is within
specified limits the charger starts a rapid charge algorithm.
When the battery is NiMH, charging is determined by -δV with time, temperature and voltage safe-guards. When the battery is
Li+ or Li-polymer, charging is determined by constant current and constant current voltage with time, temperature, current and
voltage safe-guards. A current limit no greater than the maximum charge current for any battery option must be provided by
the external power source.
In the case of deeply discharged batteries there may not be enough power in the battery to initiate a charge. Therefore, the
charging circuit must automatically start to trickle charge until there is enough power to switch on the phone.

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 POWER SUPPLIES

9.5.6 Accessory Control

GD90 can detect accessories connected to its I/O connector and control the power supply to them. These are controlled by the
signals detailed in the following table.

Inputs Outputs Peripherals

nON_HOOK nLogic_ HF_ON Charger

Ext_Pwr Ignition nHFsense adp_sense Peripherals
(*4) Power (in call) On

Low Low Low High X no no no H/F, (2nd H/S)

High X Low High High(*4) yes yes yes H/F, (2nd H/S)
High X Low High Low(*4) yes yes yes H/F, (2nd H/S)
Low Low Low Mid X no no no H/F, SMS
High X Low Mid X yes yes yes H/F, SMS

Low Low Low Mid-l X no no no H/F, PC

High X Low Mid-l X yes yes yes H/F, PC
Low Low Low Low X no no no H/F, DA
High X Low Low X yes yes yes H/F, DA
Low Low High High X yes no no none

High X High High X yes no yes Charger

Low Low High Mid-h X yes no(*1) no H/S
High X High Mid-h X yes no(*1) yes H/S, Charger
Low Low High Mid X yes no no SMS
Low Low High Mid-l X yes no no PC

Low Low High Low X yes no no DA

Low High X High X yes no(*2) no(*3) JIG
Low High X Mid-h X yes no(*2) n0(*3) JIG

When HF_ON is active, audio is directed to the handsfree connector and the HF audio circuit is ON.
1. Audio is directed to the bottom connector.
2. Initially, HF_ON is not active. It is able to control by Test Command.
3. This is dependent on battery connection.
4. nON_HOOK signal is connected to 2nd H/S. H/F will use this signal for switching the audio path. H/H detects this signal
and initiates ringing tones via the Buzzer.

Key
H/F Car kit with handsfree operation (full or basic operation).
2nd H/S Second handset for car option.
charger AC Adaptor, DC Adaptor, or H/F Charger.
DA PCMCIA Card data adaptor.
SMS SMS cable.
PC RS232C serial cable.
H/S Headset Adaptor.
JIG for Test purposes.

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 Printed in UK
UK990801500PJ