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Very high-speed and high-accuracy current-steering CMOS D/A converter

using a novel 3-D decoder

Article in Analog Integrated Circuits and Signal Processing · September 2009

DOI: 10.1007/s10470-009-9284-z

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Analog Integr Circ Sig Process (2009) 60:195–204
DOI 10.1007/s10470-009-9284-z
Very high-speed and high-accuracy current-steering CMOS D/A
converter using a novel 3-D decoder
Peiman Aliparast Æ Nasser Nasirzadeh
Received: 8 August 2008 / Revised: 12 January 2009 / Accepted: 21 January 2009 / Published online: 20 March 2009

Springer Science+Business Media, LLC 2009
Abstract In this paper a 10-bit 1.2-GSample/s Nyquist
current-steering CMOS digital-to-analog converter (DAC)
is presented. Segmentation (90%) has been used to get the
best DNL and reduce glitch energy. This segmentation ratio
guarantees the monotonicity. Higher performance is
achieved using a novel 3-D thermometer decoding method
which reduces the area, power consumption, and the number
of control signals of the digital section. Simulation results
show that the spurious-free-dynamic-range (SFDR) in
Nyquist rate is better than 65 dB for sampling frequency up
to 1.2-GSample/s. The analog voltage supply is 3.3 V while
the digital part of the chip operates at only 2.4 V. Total
power consumption in Nyquist rate measurement is
149 mW. The chip has been processed in a standard 0.35 lm
CMOS technology. Active area of chip is 1.97 mm2.
Keywords Current steering DAC

3-D thermometer decoding
High accuracy

Integrated circuits
CMOS
1 Introduction
Modern telecommunication systems, e.g. GSM and HDTV
require high-speed, high-accuracy DAC’s to enable
P. Aliparast (&)
Islamic AZAD University of Sofian, Sofian, Iran
e-mail: p.aliparast@sofianiau.ac.ir;
paymun.aliparast@gmail.com
P. Aliparast
University of Tabriz, Tabriz, Iran
e-mail: p-aliparast@tabrizu.ac.ir
N. Nasirzadeh
SERAJ Institute of Higher Education, Tabriz, Iran
e-mail: nnasirzadeh@seraj.ac.ir
integration of digital and analog systems on one chip.
Among available DAC structures like R-string, RC-hybrid
and other structures, current-steering DAC’s are preferred
because of their lower area, power consumption and com-
patibility with digital CMOS process [1]. Current-steering
DACs are based on a array of matched current sources which
are unity decoded or binary weighted [2]. Figure 1 shows a
typical block diagram of an n-bit segmented current-steering
DAC which uses the advantages of both architectures. Input
word is segmented between b less significant bits that switch
a binary weighted array and m = n - b most significant bits
that control switching of a unary current source array. The m
input bits are thermometer decoded to switch individually
each of the unary sources [3, 4, 5]. A dummy decoder is
placed in the binary weighted input path to equalize the
delay. A latch is placed just before the switch transistors of
each current source to minimize any timing error [6].
The performance of the DAC is specified through static
parameters: Integral Non-Linearity (INL), Differential Non-
Linearity (DNL) and parametric yield; and dynamic
parameters: glitch energy, settling time and SFDR [7]. Static
performance is mainly dominated by systematic and random
errors. Systematic errors caused by process, temperature and
electrical slow variation gradients are almost cancelled by
proper layout techniques [8]. Random errors are determined
solely by mismatch due to fast variation gradients. The
design of current-steering DAC starts with an architectural
selection to find the optimum segmentation ratio (m over n)
that minimizes the overall digital and analog area [9, 6, 10].
The INL is independent of the segmentation ratio and
depends only on the mismatch if the output impedance is
made large enough [2]. The DNL specification depends on
the segmentation ratio but it is always satisfied provided that
the INL is below 0.5 LSB for reasonable segmentation
ratios. The glitch energy is determined by the number of
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196 Analog Integr Circ Sig Process (2009) 60:195–204

– Negative
• Digital decoding with more area and power
consumption
• Increased number of control signals
Binary:
– Positive
• Low digital power consumption
• Small number of control signals

Fig. 1 A segmented current-steering DAC architecture – Negative

binary bits b, being the optimum architecture in this sense a • Monotonicity not guaranteed
totally unary DAC. However, this is unfeasible in practice • Larger DNL errors
due to the large area and delay that the thermometer decoder • Large glitch energy
would exhibit. The minimization of the glitch energy is then
done in circuit level design and layout of the switch and latch
Figure 3 also summarizes these points graphically.
array and current source cell [11].
Usually, to leverage the clear advantages of the thermo-
meter-coded architecture and to obtain a small area
simultaneously, a compromise is found by using segmen-
2 Binary weighted architecture versus unary decoded
tation [6]. The DAC is divided into two sub-DACs, one for
architecture
the MSBs and one for the LSBs. Thermometer coding is
used in the MSB where the accuracy is needed most.
Current-steering architectures differ from current dividing
Because of the reduced number of bits in this section, the
architectures in that they replicate a reference current
size is considerably smaller than a true thermometer coded
source rather than divide it. As shown in Fig. 2, the ref-
design. The LSB section can either be done using the bin-
erence source is simply replicated in each branch of the
ary-weighted or the thermometer-coded approach. We will
DAC, and each branch current is switched on or off based
refer to a fully binary-weighted design as 0% segmented,
on the input code. For the binary version, the reference
whereas a fully thermometer-coded design is referred to as
current is multiplied by a power of two, creating larger
100% segmented. For conventional designs, optimum seg-
currents to represent higher-magnitude digital signals. In
mentation is 75% [6]. We have used 90% segmentation to
the unit-element version, each current branch produces an
achieve the best performance in high-speed design. Using a
equal amount of current, and thus 2 N current source ele-
novel 3D decoding method we have improved digital area
ments are needed. Advantages and disadvantages of these
and power consumption which allows our 90% segmenta-
structures are summarized below:
tion to be as optimum as other designs.

Thermometer:
3 Novel thermometer decoding architecture
– Positive
• Low glitch energy Figure 4 shows a block diagram of a conventional row and
• Monotonicity column decoded 10-bit current-steering DAC. In this block
• Small DNL errors diagram, the lowest significant bit is applied to a dummy

Fig. 2 a Unit-element current-

steering DAC. b Binary current-
steering DAC

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Analog Integr Circ Sig Process (2009) 60:195–204 197

Fig. 3 Binary weighted versus

Unary-decoded

Fig. 4 Block diagram of a

conventional row and column
decoded 10-bit current-steering
DAC

decoder [12]. This decoder creates a delay proportional to
the Binary-to-Thermometer decoder and causes the signal
to arrive at the switches synchronously. The five LSB bits
are column decoded and the four MSB bits are row deco-
ded. Column decoder is a 5-input 31-output Binary-
to-Thermometer Decoder and row decoder is a 4-input
15-output Binary-to-Thermometer Decoder. Output of these
decoders controls 511 current cells in the main matrix. But if
we think about Binary-to-Thermometer Decoder structure
we understand that with b-bit increase of the input of the
decoder, area, complexity, number of control signal and
power consumption of the decoder increase with 2b. In fact

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198
Fig. 5 Block diagram of a
novel method row and column
and height decoded 10-bit 3-D
DAC
power and area are doubled with only one bit increase in the
input of the decoder and we can write:
Pð4 to 15BTDÞ ¼ 2  Pð3 to 7BTDÞ ð1Þ
Að4 to 15 BTDÞ ¼ 2  Að3 to 7 BTDÞ ð2Þ
thus:
Pð5 to 31 BTDÞ ¼ 4  Pð3 to 7 BTDÞ ð3Þ
Að5 to 31 BTDÞ ¼ 4  Að3 to 7 BTDÞ ð4Þ
where BTD is Binary-to-Thermometer Decoder, P is the
power consumption of the decoder and A is active area that
the decoder uses. Now consider Fig. 5 that shows a 3-D
decoding architecture. In this block diagram three BTD
have been used. Three bits for height, three bits for row and
three bits for column and every cell is selected with three
parameters (R, C and H). In fact we have only used three (3
to 7 BTD) instead of two (5 to 31 BTD) and (4 to 15 BTD)
thus power consumption and area of the circuit have been
improved two times because:
Pð4 to 15 BTDÞ ¼ 2  Pð3 to 7 BTDÞ ð5Þ
þPð5 to 31 BTDÞ ¼ 4  Pð3 to 7 BTDÞ ð6Þ
then:
Pð4 to 15 BTDÞ þ Pð5 to 31 BTDÞ ¼ 6  Pð3 to 7 BTDÞ
ð7Þ
And for the area we have:
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Analog Integr Circ Sig Process (2009) 60:195–204
Að4 to 15 BTDÞ ¼ 2  Að3 to 7 BTDÞ ð8Þ
þAð5 to 31 BTDÞ ¼ 4  Að3 to 7 BTDÞ ð9Þ
then:
Að4 to 15 BTDÞ þ Að5 to 31 BTDÞ ¼ 6  Að3 to 7 BTDÞ
ð10Þ
In this structure three LSB bits are column decoded,
three middle bits are row decoded and three MSB bits are
height decoded. On the other hand, we have only used 21
control signals instead of 46 control signals thus the
number of control signals has been decreased by 55 percent
so we can achieve the best speed and performance.
4 The current cell, latch and driver
Static and dynamic performance of current-steering DACs
is mostly determined by the accuracy of the current sour-
ces, finite output impedance, and switching time. Figure 6
shows a current source transistor MCS, an additional cas-
code transistor MCAS that increases the output impedance
and two complementary switch transistors MSW.
Figure 6(a) shows cascode current source and switch
structure for 1LSB while Fig. 6(b) shows the same struc-
ture for two LSB. In proposed 10-bit DAC one bit is binary
weighted so it uses the current source of Fig. 6(a) and
Analog Integr Circ Sig Process (2009) 60:195–204 199

Fig. 6 Current source cell

topology. a Binary weighted
current source cell. b Unary
weighted current source cell

remaining nine bits are thermometer decoded and need


r2 ðIÞ 1 2
4A2VT
unary current sources. To implement them, 511 current ¼ A b þ ð14Þ
I2 2W  LCSmin MV 2
sources and switches with structure of Fig. 6(b) have been
used. Note that the circuit of Fig. 6(b) is double of Fig. 6(a) where Ab, AVT, VGS and VT are process parameters,
and size of transistors are the same with Fig. 6(a). while I is the current generated by a given source and rI is
Since two D/A converters processed in the same tech- the relative standard deviation of one current source. The
nology do not necessarily have the same specifications due same aspect ratio can be obtained for different areas W 9 L,
to technological variations, it is of the utmost importance to except for the MCS transistor, because the usual INL-
know the relationship that exists between the specifications mismatch specification eliminates one degree of freedom.
of the circuit and the matching properties of used tech- The relative standard deviation of a unit current source
nology. For a current-steering D/A converter, the INL is r(I)/I has to be small enough to fulfil the INL \0.5 LSB
mainly determined by the matching behavior of the current specification given a parametric yield [12]:
sources. A parameter that is well suited for expressing this r2 ðIÞ INLUpperBound
technology versus DAC specification relation is the INL 2
  pffiffiffiffiffiffiffiffiffiffi ð15Þ
I inv  normal 0:5 þ yield
2 2N1
yield [5]. This INL yield is defined as the ratio of the
number of D/A converters with an INL smaller than one where inv-normal is the inverse cumulative normal
LSB to the total number of tested D/A converters. As distribution. The MCS transistor size is found by:
defined by Pelgrom, mismatch ‘‘is the process that causes " #
2 2
I A b 4A
time-independent random variations in physical quantities W2 ¼ þ V T
ð16Þ
of identically designed devices’’ [13]. Pelgrom’s paper has ln COX ðrII Þ2 MV 2 MV 4
become the de facto standard for analysis of transistor ln COX
matching, and thus his formula for the standard deviation L2 ¼ ½A2b MV 2 þ 4A2VT  ð17Þ
4IðrII Þ2
of saturation current for two identically sized devices has
been used for the design. This formula is: where ln COX is the MOS transistor gain factor, VT is the
2
r ðIÞ 2
4r ðVT Þ r ðbÞ 2 threshold voltage, AVT and Ab are their technology matching
¼ 2
þ 2 ð11Þ parameters, respectively and DV = (VGS - VT). Applying
I2 ðVGS  VT Þ b
Eqs. 16 and 17 we arrived in Wmin ¼ 4 lm and Lmin ¼ 5 lm
where for the current source. But in design of cascode current
A2VT sources, to achieve high speed, we need to choose the size
r2 ðVT Þ ¼ þ S2VT D2 ð12Þ of cascode transistor as small as possible. With different
W L
size for WCAS and WCS, we have to use contact in node Y
and (Fig. 6(a)) which increases parasitic capacitance and
r2 ðbÞ A2b decreases the speed. So in a trade off, we decided to
¼ þ S2b D2 : ð13Þ decrease WCS as small as possible and use the same size
b2 W L
with WCAS. In other words we have chosen WCAS ¼ WCS ¼
Most of these variables are process-dependent constants. 2 lm; and avoid using contact in node Y. To compensate for
Using these results, an equation for the minimum size reduction in WCS in Eq. 14, we increase the values of
device that still provides a reasonable current standard LCS ðLCS ¼ 10 lmÞ and DV while we keep LCAS at its mini-
deviation can be determined [11]: mum size 0.35 lm. Thus we do not use these Eqs. 16 and 17

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200
Fig. 7 Biasing scheme
and use only mismatch Eq. 14 to reach a minimum sizing of
current cell. With this method, the speed of switch is high
also INL \0.5 LSB is satisfied.
The small-signal output impedance for the current
source topology of Fig. 6(a) is given by:
Rout  gmSW gmCAS rdsSW rdsCAS rdsCS ð18Þ
The optimum MSW and MCAS gate bias voltages concerning
the output impedance are found by differentiating Rout with
respect to VgSW and VgCAS . For the SW and CAS gate bias
voltages that maximize output impedance are found as:
1 MSRD1 and MSRD2 has been given in Table 1, also SRD
VgCAS ¼ VT þ ðVomin þ 2MVCS þ 2MVCAS  MVSW Þ ð19Þ
3 output wave forms and its effect in reducing spike in node
1 VX is shown in Fig. 8(d). The capacitive coupling to the
VgSW ¼ VT þ ð2Vomin þ MVCS þ MVCAS þ MVSW Þ ð20Þ
3
Figure 7 shows the biasing scheme for the cascoded
current sources. The PMOS sections of the biasing circuits
are labelled as Global biasing while the NMOS sections are
labelled as Local biasing. In the actual implementation, the
global biasing is realized using a common-centroid layout
to reduce effects of gradients. The local biasing is separated
into four quadrants. There is no direct connection between
any two quadrants. This will improve both DNL as well as
INL performance [6]. A driver circuit with a reduced swing
placed between the latch and the switch reduces the clock
feedthrough to the output node as well [14, 15]. Figure 8(a)
shows a current source, switch, latch and driver cell. A new
swing-reduced-device (SRD) circuit is designed (shown in
Fig. 8(b)). The latch circuit complementary output levels
and non-symmetrical crossing point are designed to
minimize glitches [11]. The waveforms of the different
nodes are shown in Fig. 8(c) without SRD circuit and
Fig. 8(d) with SRD circuit. Signals with symmetrical
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Analog Integr Circ Sig Process (2009) 60:195–204
crossing point are fed from the left and SRD makes a
non-symmetrical crossing point which reduces the spike at
node VX considerably. In SRD circuit, MSRD1 is always on
and when MSRD2 is off, VgSW approaches 2.4 V (power
supply value of digital part). When MSRD2 is on with proper
sizing of MSRD2 ; VgSW can be set to desired value because
VgSW in this case will be equal to VSG of MSRD2 transistors.
In this circuit for complete switching of MSW transistors we
need 350 mV differential voltage, so VSG of MSRD2 is set to
2.05 V. On the other hand for non-symmetric crossing its
enough to choose bigger size for MSRD1 than MSRD2. Size of
analog output is minimized by limiting the amplitude of the
control signals just high enough to switch the tail current
completely to the desired output branch of the differential
pair. In addition the switch transistors are kept relatively
small in order to avoid large parasitic capacitances.
5 A few techniques to achieve very high speed
Clock distribution for 1.2 GHz is very difficult and getting
data in this speed is very hard thus we have used two
channels for digital section. Every channel works at
600 MHz and then results of two channels are combined at
the input of the switch to get 1.2 GHz. Figure 9 shows the
structure used for digital section of the DAC. Channel 1
samples input data with clock and channel two samples
input data with clock-not. A buffer just before switch
combines the output of two digital channels. It sends the
output of digital channel1 with clock and the output of
digital channel two with clock-not to the input of switch. In
Analog Integr Circ Sig Process (2009) 60:195–204 201

Fig. 8 Non-symmetrical crossing point reduces current source drain spike and clock feedthrough scheme, (a) Current source, switch, latch and
driver cell, (b) SRD circuit, (c) drain spike and driver voltages without SRD circuit, and (d) drain spike and driver voltages with SRD circuit

Table 1 Current source and SRD transistors dimensions and currents fact in one period of clock we take two samples of the input
code and in the output it seems that the circuit works at
Transistor Size ID
1.2 GHz. On other hand, we use master-slave operation in
MCS W = 2 lm, L = 10 lm 10 lA all digital circuits and use pipelining scheme, so in overall
MCAS W = 2 lm, L = 0.35 lm 10 lA the digital circuit only senses one gate-delay. For example
MSW W = 0.5 lm, L = 0.35 lm – the structure of one of 3-input 7-output Binary-to-Ther-
MSRD1 W = 1.5 lm, L = 2 lm – mometer Decoder has been shown in Fig. 10. Layout of all
MSRD2 W = 1 lm, L = 2 lm – digital section has been done manually to guarantee the
best speed, low power and minimum area.

6 Layout and simulation results

Figure 11 shows the complete layout of the DAC, latches

Fig. 9 Using two 600 MHz digital channels to achieve 1.2 Gsample/s
and switches which are grouped in a separated array placed
between the decoders and the current source arrays to
isolate these noisy digital circuits from the sensitive analog
circuits that generate the current. A guard ring has been
used to separate analog section from digital section. Layout
of the decoder circuit has been drawn manually and pipe-
lining used to reach the maximum speed and improvement
of the parasitic capacitance and sizing of transistors has
been done with simulation. Simulations have been per-
formed on a differential 50 X load. The internal node
interconnection capacitance has been estimated to be

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202 Analog Integr Circ Sig Process (2009) 60:195–204

Fig. 10 Gate level structure of

3-input 7-output Binary-to-
Thermometer Decoder

Nyquist rate measurement is 149 mW. SFDR is better than

65 dB in Nyquist rate. Figure 12 shows differential output
spectrum where DAC worked with 1.2 GSample/s speed
and input code near to Nyquist rate (589 MHz) with
10 mV(rms) noise voltage on analog power supply. Fig-
ures 13 and 14 show DNL and INL characteristics of
designed DAC for increasing input code from 0 to 1023.
The INL and DNL obtained from post layout four corner
Monte-Carlo simulations considering process mismatch
parameters are better than 0.37 LSB and 0.19 LSB,
respectively. Table 2 summarizes some of important per-
formance parameters of the DAC.

Fig. 11 Layout of designed 10-bit DAC

7 Conclusion
400 fF, and the output capacitance 1 pF. The analog volt-
age supply is 3.3 V while the digital part of the chip In this article a 3.3 V, 10-bit, current-steering, 9?1 seg-
operates at only 2.4 V. Total power consumption in the mented architecture Digital to Analog Converter has been

Fig. 12 Sinewave spectrum for

Fs = 1.2 GSample/s,
Fsig = 589 MHz

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Analog Integr Circ Sig Process (2009) 60:195–204 203

Fig. 13 DAC DNL

characteristic

Fig. 14 DAC INL

characteristic

Table 2 Performance summary

Technology 0.35 lm (1P4M) TSMC Mixed Mode CMOS

Resolution 10 bit
Update rate Up to 1.2 GS/s
Max. output swim 1Vpp diff.
DNL Better than 0.19LSB
INL Better than 0.37LSB
SFDR (589 MHz@1.2 GS/s) 65 dB
Analog Power consumpion (at 1.2 GS/s) 66 mW (20 mA from 3.3 V)
Digital Power consumpion (at 1.2 GS/s) 83 mW (34.5 mA from 2.4 V)
Total Power consumpion (at 1.2 GS/s) 149 mW
Analog/Digital voltage supply 3.3 V/2.4 V
Active area 1850 lm 9 1070 lm

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204 Analog Integr Circ Sig Process (2009) 60:195–204

presented. A novel 3-D thermometer decoding scheme has 10. Gonzalez, J. L., & Alarcon, E. (2001). Clock-jitter induced dis-
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lower supply voltage than analog part. This increases speed
and reduces power consumption of the digital part and at Peiman Aliparast was born in
the same time decreases power supply noise and improve Tabriz, Iran. He received B.Sc.
degree from Tabriz Islamic
the performance of the analog part. The technology used is AZAD University, Tabriz, Iran,
a 0.35 lm, single-poly four-metal, 3.3 V, standard TSMC in 2005 and M.Sc. degree from
Mixed Mode CMOS process. The active area of the DAC, Urmia University, Urmia, Iran,
as shown in Fig. 11, is 1850 lm 9 1070 lm. in 2007, both in electronics
engineering. He is currently
electronics PhD student in Tab-
Acknowledgments The authors would like to thank the referees for riz University. His research
their helpful suggestions and comments. interests are analog and digital
integrated circuit design for
fuzzy and neural network
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