16/14nm Library & STA

Requirements
Achieving Best STA Accuracy for Advanced Nodes

Jennifer Pyon
Senior Staff Corporate Applications Engineer, PrimeTime
March 23rd, 2015

© 2015 Synopsys, Inc. 1

 Outline

16/14nm Effects on Timing

Synopsys Solution
STA: Advanced Waveform Propagation
STA: Waveform Integrity DRC
Characterization: Library Quality

Summary

© 2015 Synopsys, Inc. 2

 16/14nm Effects on Timing

© 2015 Synopsys, Inc. 3

 16/14nm FinFET Device Structure
Evolving from Planar Technology

• 3-D versus planar gate structure

– Addresses short channel effects which make it harder for gate voltage to
deplete the channel and effectively turn off the transistor
– The 3-D structure raises the channel, creating “fins” so that the gate can
wrap around 3 sides of the channel, improving control

• Advantages
– Better performance
– Reduced leakage
• Disadvantages
– Increased Miller Capacitance

© 2015 Synopsys, Inc. 4

 16/14nm Effects on Timing

• Increased waveform distortion

• Increased cell sensitivity
• Longer tail effect
• Increased device sensitivity
• Increased coupling capacitance

© 2015 Synopsys, Inc. 5

 Increased Waveform Distortion
More Significant Miller Effect

• Significant increase in receiver Miller capacitance causes

larger waveform distortion
• Distorted waveform impacts cell delay and constraint

© 2015 Synopsys, Inc. 6

 Increased Cell Sensitivity
Lower Operating Voltage

• Lower operating voltage causes device to switch later

during transition – when input waveform is close to rail
• Cell is more sensitive to input waveform

© 2015 Synopsys, Inc. 7

 Longer Tail Effect
Increased Wire Resistance

• Increased wire resistance causes longer tails

• Tail has impact on output slew and delay

© 2015 Synopsys, Inc. 8

 Increased Device Sensitivity

• Smaller currents through the devices increase sensitivity

• Cell delay and slew are sensitive to input waveform shape
at the tail

© 2015 Synopsys, Inc. 9

 Increased Device Sensitivity
Library Cell Sensitivity – Sample Results

• Cells are more sensitive at

– Slow process corner
– Lower voltage
– Higher Vth

© 2015 Synopsys, Inc. 10

 Increased Coupling Capacitance

• Increased crosstalk due to narrow width, taller height, and

closer proximity of wires
• Increased crosstalk increases receiver cell delay

Output waveform:
Smaller coupling cap
InputVictim receiver input
waveform:
Larger coupling effect
Larger coupling Effect of increased coupling
Output
effect waveform:
at victim receiver output
Victim receiver input Larger coupling cap
Smaller coupling effect
Input waveform:
Smaller coupling

© 2015 Synopsys, Inc. 11

 Advanced Waveform Propagation

© 2015 Synopsys, Inc. 12

 Library Characterization Waveform

• Realistic characterization waveform should be used and

stored in the library
• Synopsys pre-driver and active waveforms are
recommended
Characterization input waveform

VDD

0.7*VDD

0.5*VDD

0.3*VDD Receiver output waveform

VSS
© 2015 Synopsys, Inc. 13
 Waveform Distortion Effect

• STA tool should be able to model the effects of waveform

distortion during delay calculation

Ideal characterization input waveform

VDD
SPICE waveform at receiver input

0.7*VDD
SPICE waveform at receiver output

Ideal Receiver output waveform

0.3*VDD

VSS

© 2015 Synopsys, Inc. 14

 Advanced Waveform Propagation

• Calculates and propagates entire piecewise linear waveform instead of just

delay/slew
• To accurately model waveform distortion and propagation, both CCS timing
and CCS noise library data are used
• PrimeTime advanced waveform propagation (AWP) maintains and improves
golden signoff accuracy for designs with large waveform distortion

CCS Timing Model CCS Noise Model

+
Receiver Model Driver Model
C1,C2 C1,C2 C1,C2 C1,C2
Miller Cap
C1,C2

C1,C2 C1,C2 C1,C2 C1,C2

C1,C2 + +
C1,C2 C1,C2 C1,C2 C1,C2
C1,C2
- - Vi
C1,C2 C1,C2 C1,C2 C1,C2
C1,C2

© 2015 Synopsys, Inc. 15

 Advanced Waveform Propagation
Improves STA Delay Calculation Accuracy – 16/14nm Results

Source: Synopsys customer testcase

Min delays Mean STD Dev Max delays Mean STD Dev
AWP 0.0% 0.5% AWP 0.1% 1.0%
No AWP -0.9% 1.4% No AWP -4.0% 1.64%

© 2015 Synopsys, Inc. 16

 Waveform Integrity DRC

© 2015 Synopsys, Inc. 17

 Distorted Waveforms
Accuracy Impact
Static Integrity Analysis
• Highly distorted waveforms
are not desired due to
susceptibility to variation
CLK CLK

• Accuracy impact can be

substantial at sequential
Dynamic Integrity Analysis
cells where setup/hold
constraints are checked VDD

0.7*VDD

• Traditional STA does not 0.3*VDD

have a way to detect such
VSS
waveforms in design
© 2015 Synopsys, Inc. 18
 Waveform Integrity DRC

• PrimeTime performs waveform integrity DRC check

report_constraint –waveform_integrity static –all_violators

Pin metric metric Slack

-----------------------------------------------------------------
test/U1/D 0.050000 0.075365 -0.025365 (VIOLATED)
test/U1/SI 0.050000 0.064172 -0.014172 (VIOLATED)
test/U2/D 0.050000 0.063944 -0.013944 (VIOLATED)
test/U2/CLK 0.050000 0.063894 -0.013894 (VIOLATED)
test/U3/CLK 0.050000 0.058196 -0.008196 (VIOLATED)
test/U3/SI 0.050000 0.056332 -0.006332 (VIOLATED)
test/U4/SI 0.050000 0.054937 -0.004937 (VIOLATED)
test/U5/CLK 0.050000 0.053780 -0.003780 (VIOLATED)
test/U6/D 0.050000 0.053270 -0.003270 (VIOLATED)

© 2015 Synopsys, Inc. 19

 Waveform Integrity DRC
Sample Results

• Larger distortion observed at slow corner and low voltage

corners

Voltage Process Number of Maximum

Corner Violators Distortion

0.6V FF 21838 10.6ps

0.9V FF 19575 7.5ps
0.5V SS 26325 64.0ps
0.7V SS 21227 17.9ps

© 2015 Synopsys, Inc. 20

 Library Requirements

© 2015 Synopsys, Inc. 21

 Library Quality

• Increased dependence on library quality in advanced

nodes

• Synopsys provides tools and methodology to achieve best

STA accuracy
– Use latest version of SiliconSmart and PrimeTime
– Characterization guidelines for library characterization tool
developers and users
– Library checking features in Library Compiler and SiliconSmart

© 2015 Synopsys, Inc. 22

 Library Checks

• SiliconSmart
Library Cell
• Circuit level design checks for
Design Checks modeling, design and structure

Library • SiliconSmart & Library Compiler

Characterization • Simulation and characterization errors,
cell sensitivity, consistency and
Checks monotonicity of library data

Signoff and • PrimeTime and Scripts

Correlation Setup • Correlation setup, delay calculation
Checks messages

© 2015 Synopsys, Inc. 23

 Library Cell Design Checks
Sample Checks Performed by SiliconSmart

Pass-transistor Logic Monotonic Constraint Tables

• Potential modeling
inaccuracy
• Add STA margin
with consideration
of performance
• A cause of GBA/PBA
bounding issue
• Fix cell’s constraint table

SiliconSmart

Coupling between Input Ports Hysteresis Effect

• Large ccap between ports • Ensure correct initial condition
cannot be modeled for characterization & correlation
• Fix the cell design • Need to model the worst case
during characterization

TA-08 Statistical Characterization and Library Qualification

(Tuesday, 3/24, 10:30-12:00) Standard Cell Qualification with SiliconSmart
© 2015 Synopsys, Inc. 24
 Library Characterization Checks
Sample Checks Performed by Library Compiler

NLDM/CCS Consistency CCSN Sensitivity

• Points to library data • Checks cell design
integrity robustness

Library Compiler

Output Signal Range Index Spacing using

• Detects cell design interpolation
issue • Checks
appropriate
index selection

Checking CCS data using check_library Command (SolvNet 1526124)

© 2015 Synopsys, Inc. 25
 Signoff and Correlation Setup Checks
Checks Performed by PrimeTime

NLDM SPICE accuracy

Correlation • < 0.1%. Confirm consistency between model,

Setup simulator version/options
• sim_validate_setup

Delay Calculation Message(RC-xxx)

• Check delay calculation failure/extrapolation

Signoff • RC-011, RC-104, RC-201, RC-202, RC-203

Correlating PrimeTime and SPICE Results with Simulation Link

(PrimeTime User Guide)
© 2015 Synopsys, Inc. 26
 Library Characterization Methodology
Guideline for 16/14nm
Characterization Waveform Slew Trip Points Table Size

7x7

• Recommend methodology for library characterization & validation

– Impact of characterization waveform, slew trip points, table size, index
spacing on accuracy
– Design-level accuracy validation
• Recommended settings for SiliconSmart & PrimeTime correlation
• Share trends in library characterization methodology

Library Characterization Methodology Guideline for PrimeTime

(Contact Synopsys Applications Consultant)
© 2015 Synopsys, Inc. 27
 Summary

• Advanced nodes introduce significant waveform

distortions & tighter accuracy requirements

• Best STA accuracy can be achieved with the following

– Knowledge of circuit design styles that are challenging to model
– Checking library quality
– Detection of waveform integrity issues
– Accurate STA delay calculation for distorted waveforms

• Use Synopsys’ solution and guidelines for best accuracy

– Library characterization guidelines
– Library checkers: SiliconSmart and Library Compiler
– Accuracy STA delay calculation: PrimeTime and IC Compiler
© 2015 Synopsys, Inc. 28
 Reference Documents

• Achieving Best STA Accuracy for Advanced Nodes (SolvNet 2106005)

• Library Characterization Methodology Guideline for PrimeTime
(Contact Synopsys Applications Consultant)
• Checking CCS Library Data using the check_library Command
(SolvNet 1526124)
• Library Quality Assurance System User Guide (SolvNet
documentation)
• Correlating PrimeTime and SPICE Results with Simulation Link
(PrimeTime User Guide)
• PrimeTime Accuracy Correlation System (Contact Synopsys
Applications Consultant)
• Accurate and Faster Timing Closure With TSMC 16-nm FinFET Using
Synopsys-Certified Signoff Flow (SolvNet 1675358)

© 2015 Synopsys, Inc. 29

 Thank You

© 2015 Synopsys, Inc. 30