Evaluation of Hyperscale & Physically Aware ECO

flows on Multi-million hierarchical design

ABSTRACT

The ASICs designed by our group are multi-million gate designs with multi levels of physical
hierarchy. This leads to many challenges on the timing closure and signoff front. Some of the major
ones are high full chip timing (FCT) runtimes, resulting in increased turnaround time (TAT) for
timing analysis and timing ECO generation. Another concern with our current approach is the
absence of accurate timing budgets for interface paths at block/macro level, which leads to block
level interface timing closure depending on FCT feedback. All these increases the turnaround time
and number of ECO loops between block & top.
To resolve the deficiencies of the current FCT approach and to have a scalable architecture for even
larger designs in the future, we evaluated the HyperScale Technology and Physically aware ECO flow.
HyperScale flow significantly reduces the FCT runtime, and is able to generate accurate IO budgets
for lower level blocks. Using physically aware ECO (PECO) flow in conjunction with HyperScale
reduces the runtime of ECO generation, and increased accuracy of ECOs ensures reduced number of
loops between block & top. We also evaluated the HyperScale Constraint Extractor flow. This flow
helps in ensuring consistency between block & top level constraints, thereby helping in reducing
design cycle time.
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Table of Contents
1. Introduction..................................................................................................................................................................................... 3
2. Design information ...................................................................................................................................................................... 3
3. Hyperscale Integration in the STA flow ............................................................................................................................ 4
4. HyperScale Constraint Extractor .......................................................................................................................................... 5
4.1 Background .......................................................................................................................................................................5
4.2 Proposed usage model of Constraint Extractor ..............................................................................................5
5. Timing correlation exercise .................................................................................................................................................... 6
5.1 Timing correlation evaluation results ( FullChip Flat VS HyperScale) ...............................................8
5.2 Timing correlation evaluation results ( FullChip Flat VS Block) ...........................................................8
6. HyperScale enabled ECO flow ................................................................................................................................................ 9
6.1 HyperScale ECO Flow and Implementation......................................................................................................9
6.2 Results ...............................................................................................................................................................................10
7. Conclusions ................................................................................................................................................................................... 10
8. References ..................................................................................................................................................................................... 10

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1. Introduction
In this paper we start with the design information of the test-case used for this evaluation and then
explain how the HyperScale flow is integrated into the full chip static timing analysis (STA) flow.
Next, we explore using Constraint Extractor (CE) feature within the framework of HyperScale flow to
propose top-down hierarchical constraint management model during early design stages. Next, we
describe how the correctness of HyperScale context push down and the Constraint Extractor were
evaluated by doing various kinds of timing correlation checks between Full Chip flat, Full Chip
HyperScale model and block level STA with top level HyperScale context. In the last part of the paper,
we capture how the ECO flow was tested on the Full Chip HyperScale based model.

2. Design information
The ASIC we selected as a test-case for HyperScale evaluation has about 65 million instances in 3
levels of physical hierarchy. The full chip (L1) consisted of I/O Interface blocks, phys, PLL, and Blocks.
Some of these were instantiated multiple times at the full chip level. The Blocks (L2) consisted of sub-
blocks and some logic. The sub-blocks (L3) were multiply instantiated, and the same partition was
used across more than one Block. In total the design had 34 unique units (IO Interface bocks, PLL,
Mega-blocks, partitions). Figure 1 shows by means of a simplified diagram, the physical partitioning
of the design.

Figure 1. Simplified diagram depicting the 3-level physical partitioning of the design

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3. Hyperscale Integration in the STA flow

In this section, we present the proposed usage of HyperScale constraint extractor, hierarchical timing
closure and physically aware ECO flows within our full chip STA flow. Figure 2 shows how HyperScale
is integrated in our design flow.
The STA flow starts with a full chip hierarchical Verilog netlist and Full-Chip sign-off constraints.
HyperScale Constraint Extractor run at full chip derives the Block constraints from Full-Chip sign-off
constraints. Block constraints has clock definition, clock relationships, clock uncertainties,
exceptions and Block-IO delays. One of the key goals in our design flow is to have the consistent set
of timing constraints between Full-Chip and Block runs. Generating the Block constraints from Full-
Chip constraints helps in achieving the goal. As the Constraint Extractor run is a pre-layout run,
Block-IO delays are not accurate at this point and reflect the equally division of clock period between
launch block and capture block.
Block physical design & STA run proceed with these constraints. Block STA run generates HyperScale
Model, which is a block abstract model for timing. Full Chip STA run uses Block HyperScale Models
instead of using block netlist & spef & called FullChip HS (HyperScale) run. This reduces the FullChip
STA run time and memory foot-print drastically.
FullChip HS STA run generates HyperScale Context for each block. HyperScale Context has the
complete information of the Block-IO e.g. IO delays, clock source latencies, AOCVM, CRPR & noise etc.
This makes the any further Block STA run almost sign-off accurate.
FullChip HS STA run can be used to generate the Timing ECO for inter-block paths. ECO run time for
FullChip HS STA run is very less as compared to FullChip Flat run.

Figure 2. HyperScale in the full chip STA Flow

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4. HyperScale Constraint Extractor

In this section, we explore using Constraint Extractor (CE) feature within the framework of
HyperScale flow based on a top-down hierarchical constraint management model.

4.1 Background
Integrating constraints from block-level and rolling them up to the top-level is a cumbersome task
and often requires dedicated resource to handle constraints in today’s multimillion gate designs. The
task is further complicated by multiply instantiated modules, multiple corners and operational
modes. Also, the implementation criteria in a block could vary considerably across its multiple
instantiations during verification in the context of the full design.
Detailed design knowledge is also required to be able to budget appropriately for interface timing,
and a typical solution is to over-constrain and overdesign.

Figure 3. Typical constraint management flow (L) Constraint Management with HyperScale
Constraint Extractor (R)

HyperScale flow offers substantial benefits in terms of chip-level STA runtimes. However, its usage is
contingent on having consistent constraints between the block and top level and the constraint
extractor (CE) feature offers a solution to maintain this consistency across hierarchies.
In our group, we recommend using CE not only to enable top-level hierarchical verification, but take
further advantage to drive block implementation using constraints extracted from top level
constraints. Consistency across different flows and hierarchies helps reduce potential issues from
mismatched constraints and benefits overall convergence times.

4.2 Proposed usage model of Constraint Extractor

Figure 3 describes the proposed usage of Constraint Extractor together with the constraint analyzer
in early physical design stages, with further explanation for each step in the process below.
1. On receiving top level constraints and design netlists for physical design, it is always a good
practice to verify the quality of timing constraints in Vendor Constraint Analyzer utility. It
helps catch potential issues in the constraints up front. For example, constraints that enable
confluence in a clock-tree branches create unintentional pessimism in analysis and should be
corrected.
2. Using CE, then, constraints for the required block hierarchies are extracted. Consider a
multilevel hierarchical design with 3 levels of hierarchy L1, L2 and L3. To extract constraints
for L2 or L3 blocks, simply specify the block names with set_hyperscale_config command. To
extract constraints for just the L2 wrapper block without L3 block, L3 can be black-boxed.

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3. Constraint analyzer with the hierarchical rulesets can help verify if any cross-boundary
constraints are dropped by CE. If there are such dropped constraints, they need to be put back
in the next steps manually.
4. Optionally, timing budgets from chip-level floor planning and implementation tools can be
used to override the boundary constraints at this point.
5. Although CE did not support handling multiple modes by itself, the extraction process can be
repeated for each top-level mode, to extract corresponding block-level mode specific files.
Now, at the block level, using the constraint analyzer with all the block-modes gives further
insight into the constraint coverage quality per mode. Once the constraints are verified, they
can be used with multi-mode place-and-route flow.

Figure 4. Constraint Extractor Usage Model

The above flow promises efficient and automated constraint roll-down and verification at each stage
in the design, reducing pessimism from constraint mismatches.

5. Timing correlation exercise

To establish the timing coverage and accuracy of the HyperScale flow, we carried out a timing
correlation study on full-chip design to identify and correct any potential issues. We provide the
details of this correlation exercise in this section.
The description of the testcase has been given in the beginning of the paper. Here, the Sub-Blocks
were assumed as flat, and HyperScale runs were limited to full chip and Blocks. The Constraint
Extractor is used to generate the constraints for Block. This eliminates constraint mismatch issues
between top and blocks, and makes the timing correlation work easier.

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Figure 5(a). HyperScale flow used for timing correlation exercise

Figure 5(a) shows the method used to evaluate the accuracy of Block HS Model. We compared the all
the inter-block timing paths between FullChip Flat STA run and FullChip HS STA run.

Figure 5(b). HyperScale flow used for timing correlation exercise

Figure 5(b) shows the method used to evaluate the accuracy of Block HS Context. We compared the
all the Block-IO & Block-REG2REG timing paths between FullChip Flat STA run and Block run with
HS Context. Timing paths comparison was also used to check the constraint accuracy of the Block
versus Full Chip.

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5.1 Timing correlation evaluation results ( FullChip Flat VS HyperScale)

Figure 6. Full Chip Flat vs Full Chip HyperScale Timing Correlation

a) MIM modelling is the biggest source of mis-correlation: Has been fixed in the latest tool
version, to be verified at our end.
b) Apart from MIM issues, setup is within 1% of clock period.
c) Apart from MIM issues, hold slack difference distribution is around 5ps.

5.2 Timing correlation evaluation results ( FullChip Flat VS Block)

Figure 7. Full Chip Flat vs Block Timing Correlation

a) Good correlation between FullChip & Block internal paths.

b) IO paths are more pessimistic because of GBA context.

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6. HyperScale enabled ECO flow

HyperScale enables ECOs to be run at the block-level and top-level accurately with the runtime and
capacity benefits of the HyperScale flow. This enables faster turnaround time for completing the ECO
process.

6.1 HyperScale ECO Flow and Implementation

Figure 9 below shows the HyperScale ECO flow, which is similar to Flat ECO flow.

Figure 8. HyperScale ECO flow

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6.2 Results

when bottom-up constraints flow is used, Constraint Analyzer feature of the tool helps in achieving
consistency between FullChip, mega-block & partition constraints.

Lastly, because of top level context, mega-blocks & partitions can now see accurate interface timing.
Consequently, these can focus on optimizing the interface paths without waiting for ECOs or
manual timing feedback from top level. Of course, the last mile closure will have to be still done
using HyperScale based ECO flows run at FCT level.

7. Conclusions
In this paper, we described how HyperScale fits in our physical design flow including the place-and-
route and STA flows. We described how the HyperScale constraint extractor is used to derive a
consistent set of constraints at all levels of design hierarchy to drive both implementation and STA.
We also covered how the timing constraints used for place-and-route are augmented with the
interface constraints derived from floorplanning and full-chip HyperScale runs. As part of the
HyperScale evaluation, we did an extensive timing correlation exercise with a full-chip timing
database. The details of the correlation were presented in this paper. Finally, we presented the
HyperScale ECO flow and results.

8. References
[1] Vendor Timing tool documentation.

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