A

MAJOR PROJECT REPORT

ON
“HYBRID LDPC-STBC CODES VLSI IMPLEMENTATION FOR
EFFICIENT SATELLITE COMMUNICATION SYSTEMS”

Dissertation submitted in the partial fulfillment of the academic requirements

For the award of the Degree of

BACHELOR OF TECHNOLOGY

IN

ELECTRONICS AND COMMUNICATION ENGINEERING

By
B. SRIKANTH 209P1A0410
S. JYOTHI 209P1A0413
A. SWAPNA 219P5A0410

UNDER THE ESTEEMED GUIDANCE OF

Mr P. SATEESH

Assistant Professor, ECE Department

Department of Electronics and Communication Engineering

SREE DATTHA GROUP OF INSTITUTIONS

(Approved by AICTE, Affiliated to JNTUH, NAAC accredited & NBA

Accredited programs: B. Tech in ECE, CSE, EEE, Mechanical, Civil)

Sheriguda, Ibrahimpatnam (M), Rangareddy (Dist.) -501510

2023-2024
 DECLARATION

This is to certify that the work reported in the present thesis titled “HYBRID

LDPC- STBC CODES VLSI IMPLEMENTATION FOR EFFICIENT SATELLITE

COMMUNICATION SYSTEMS ” a record work done by us in the Department of

Electronics and Communication Engineering in Sree Dattha Group of Institutions.

No part of the major project report is copied from books/journals/internet and where

ever the portion is taken, the same has been duly referred in the text the report is based on the

work done entirely by us, not copied from any other source.

B. Srikanth 209P1A0410

S. Jyothi 209P1A0413

A. Swapna 219P5A0410

i.
 SREE DATTHA GROUP OF INSTITUTIONS

(Approved by AICTE, Affiliated to JNTUH, NAAC accredited & NBA)

Sheriguda, Ibrahimpatnam (M), Rangareddy (Dist.), Telangana State.

DEPARTMENT OF ELECTRONICS &COMMUNICATION ENGINEERING

Certified that this bonafide record of the dissertation work entitled, “HBRID LDPC-

STBC CODES VLSI IMPLEMENTATION FOR EFFICIENT SATELLITE

COMMUNICATION SYSTEMS”, done by B. SRIKANTH (209P1A0410), S. JYOTHI

(209P1A0413), A. SWAPNA (219P5A0410) , submitted to the faculty of electronics

engineering, in a partial fulfillment of the requirement for the degree of BACHELOR OF

TECHNOLOGY with the specialization in ELECTRONICS AND COMMUNICATION

ENGINEERING from Sree Dattha Institute of Engineering and Science, Hyderabad during

the period 2019-2020.

INTERNAL GUIDE HOD DIRECTOR /PRINCIPAL

(Mr P.SATEESH) (Dr. MD.JAVEED) (Dr.M.SENTHIL KUMAR)

EXTERNAL
 ACKNOWLEDGEMENT
We would like to thank Chairman Sri. G.Panduranga Reddy Garu and Vice

Chairman Dr. G. Vibhav Reddy Garu for providing all the facilities to complete our major

project with in time.

We would like to express our deep sense of gratitude to Director/Principal Dr.

M.SENTHIL KUMAR Garu, Sree Dattha Group of Institutions, for his continuous

effort in creating a Competitive environment in our college and encouraging through this

course.

Working and writing our thesis in exchange at Sree Dattha Group of Institution

was a great opportunity and we would like to thank from the bottom of my heart.

Dr. Md. Javeed, HOD, Department of Electronics and communication engineering

for providing it to us. There was never such a resourceful and enriching time in our life.

We are thankful to Mr P. Sateesh, Asst. Professor in the department of Electronics

and Communication Engineering for supporting us in our entire project.

We are thankful to Mr P. Sateesh, Asst. Professor in the department of Electronics

and Communication Engineering, for giving the opportunity to work under him and lending

every support at every stage of this project work. We truly appreciate and value his esteemed

guidance and encouragement from the beginning to the end of this thesis. We are in debated

to him for having, helped us to shape the problem and providing insights towards the

solution. His trust and support inspired us in the most important moments of making right

decisions and we are glad to work with him.

B. SRIKANTH 209P1A0410
S. JYOTHI 209P1A0413
A. SWAPNA 219P5A0410

ii.
 ABSTRACT
Among the emerging technologies recently proposed as alternatives to the classic

CMOS, Quantum-dot cellular automata (QCA) is one of the most promising solutions to

design ultra-low power and very high speed digital circuits. Efficient QCA-based

implementations have been demonstrated for several binary and decimal arithmetic circuits,

but significant improvements are still possible if the logic gates inherently available within

the QCA technology are smartly exploited. This brief proposes a new approach to design

QCA-based BCD adders. Exploiting innovative logic formulations and purpose designed

QCA modules, computational speed significantly higher than existing counterparts are

achieved without sacrificing either the occupied area or the cells count

iii.
 INDEX

DECLARATION I

ACKNOWLEDGEMENT II

ABSTRACT III

LIST OF CONTENTS IV

LIST OF FIGURES VII

LIST OF TABLES X

ABBREVIATION XI

LIST OF CONTENTS

CHAPTER NO. CONTENT PAGE NO.

1 INTRODUCTION 1
1.1 overview 2

1.2 Research motivation 3

1.3 Existing system 5

1.4 Problem statement 6

1.5 Research objective 6

1.6 Performance matric 7

1.7 Advantages 8

1.8 Applications 9

iv
2 LITERATURE SURVEY 12

2.1 Introduction 12

2.2 Related work 12

2.3 Research gaps 29

3 EXISTING SYSTEM 34

3.1 Introduction 34

3.2 Hamming codes 34

3.3 Drawbacks 41

3.4 Summary 41

4 PROBLEM STATEMENT 42
4.1 Introduction 42

4.2 LDPC encoder and decoder 43

4.3 STBC encoder 46

4.4 Hybrid LDPC – STBC system 53

4.5 Summary 56

5 PROPOSED SYSTEM 57

6 RESULTS AND DISCUSSION 79

6.1 Existing system 79

6.2 Proposed results 81

6.3 performance comparisons 83

v
7 CONCLUSION AND FUTURE
SCOPE 86

7.1 Conclusion 86

7.2 Future scope 87

7.3 Reference 88

vi
 LIST OF FIGURES

FIGURE NO. NAME OF THE FIGURE PAGE NO.

1.1 Research motivation 3

3.1 Redundant bits coverage 36

3.2 Redundant bit positions 37

3.3 Transmitted data with

redundant bits 37

3.4 Finding R1 value 37

3.5 Finding R2 value 37

3.6 Finding R4 value 38

3.7 Finding R8 value 39

3.8 Data transfer 39

3.9 Error detection 40

4.1 LDPC encoder and decoder 43

4.2 STBC encoder and decoder 46

4.3 LDPC – STBC encoder 54

4.4 LDPC – STBC decoder 55

vii

5.1 Vivado start – up window 58

5.2 Create project dialog 59

5.3 Enter project name 60

5.4 Select project type 61

5.5 Add sources 62

5.6 Select Zynq 7000 part 64

5.7 Create project summary 65

5.8 Vivado project window 66

5.9 Add design sources 68

5.10 Add or create design sources

Using add source dialog 69

5.11 Create design source file 70

5.12 project1_demo appears in

Design sources 71

5.13 Add source to design constraint 72

5.14 Add or create design constrains

Using add source dialog 73

5.15 Start synthesis process and

monitor the synthesis log 74
viii
5.16 Start implementation process and
monitor the implementation log 75
5.17 Generate bitstream 76

5.18 Open hardware manager 77

5.19 Auto connect target 78

5.20 Vivado finds the Zynq device on

a blackboard and connects to it
successfully 78

6.1 Existing simulation results for

N=32 79

6.2 Existing area for N=32 79

6.3 Existing power for N=32 80

6.4 Existing set up delay for N=32 80

6.5 Existing hold delay for N=32 81

6.6 Proposed simulation results for

N=32 81

6.7 Proposed area for N=32 82

6.8 Proposed power for N=32 82

6.9 Proposed set up delay for N=32 83

6.10 Proposed hold delay for N=32 83

ix
LIST OF TABLES
TABLE NO. NAME OF THE TABLE PAGE NO.

2.1 Comparative analysis 30

6.1 Performance comparison of

Existing and proposed methods
For N=16 84

6.2 Performance comparison of

Existing and proposed methods
For N=32 84

6.3 performance comparison of

Existing and proposed methods
For N=64 85

x
ABBREVIATIONS

QCA Quantum-dot Cellular Automata

VLSI Very large-scale integration

CAD Computer aided design

ISE Integrated synthesis environment

RTL Register transfer level

CLA Carry-look ahead adder

BCD Binary coded decimal

HDL Hardware descriptive language

CL Correction logic

RCA Ripple carry adder

FPGA Field programmable gate array

CMOS Complementary metal-oxide semiconductor

LUT Look -up table

DFF D flip flop

CPLD Complex programmable logic device

ASIC Application specific integrated circuit

SOC System on chip

VHDL Very high speed integrated circuit hardware description language

EDA Electronic design automation

ECAD Electronic computer aided design

11