Program : B.

Tech
Subject Name: Digital System Design
Subject Code: EC-303
Semester: 3rd
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Unit-4: Registers and Counters: Asynchronous Ripple or serial counter. Asynchronous Up/Down counter
- Synchronous counters – Synchronous Up/Down counters – Programmable counters – Design of
Synchronous counters: state diagram-State table –State minimization –State assignment - Excitation
table and maps-Circuit. Implementation - Modulo–n counter, Registers – shift registers - Universal shift
registers. Shift register counters – Ring counter – Shift counters - Sequence generators.
.......................................................................................................................................................................
Asynchronous (Ripple) Counter: In the asynchronous counters the external clock pulse is applied to only
to the first (LSB) flip flop and the proceeding flip flops are triggered by the previous stage outputs. In
case of up counter the triggering pulse is Q of the previous stage and in case of down counter the
triggeri g pulse is Q . Thus the clock sig al ripples through the flip flops from first to the end flip flop.
Asynchronous Up Counter: The 3-bit asynchronous up counter is realised with JK flip flop as shown in
the Fig.4.1. The JK i puts are co ected ith logic . The F flip flop is co ected ith exter al clock
and other flip flops are triggered with previous stage output Q. The table shows the count sequence,
Fig.4.2 shows the waveform of the output of each flip flop, which shows that the clock frequency is
divided at each stage.
Q0 Q1 Q2
1

J0 Q0 J1 Q1 J2 Q2
CLK F0 F1 F2
Pulse
K0 Q0 K1 Q1 K2 Q2

Fig.4.1 : 3-Bit Asynchronous up Counter

Table : Count Sequence of Ripple Counter

Flip Flop Outputs
No. of Clock Pulse Remarks
Q2 Q1 Q0
0 0 0 0 No Change in Q0 , Q1 & Q2
1 0 0 1 Q0 Changes, Q1 & Q2 No Change
2 0 1 0 Q0 & Q1 Changes, Q2 No Change
3 0 1 1 Q0 Changes, Q1 & Q2 No Change
4 1 0 0 Q0 , Q1 & Q2 Changes
5 1 0 1 Q0 Changes, Q1 & Q2 No Change
6 1 1 0 Q0 & Q1 Changes, Q2 No Change
7 1 1 1 Q0 Changes, Q1 & Q2 No Change
8 0 0 0 Q0 , Q1 & Q2 Changes

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CLK T1 T2 T3 T4 T5 T6 T7 T8

Q0

Q1

Q2
Fig. 4.2 : Waveforms for 3-bit ripple counter

Asynchronous Down Counter: The 3-bit asynchronous down counter is realised with JK flip flop as
shown in the Fig.4.3. The JK i puts are co ected ith logic . The F flip flop is co ected ith
external clock and other flip flops are triggered with previous stage output Q Co ple e ted Output .
The table shows the count sequence.
Q0 Q1 Q2
1

J0 Q0 J1 Q1 J2 Q2
CLK F0 F1 F2
Pulse
K0 Q0 K1 Q1 K2 Q2

Fig.4.3 : 3-Bit Asynchronous Down Counter

Table : Count Sequence of Ripple Counter

Flip Flop Outputs
No. of Clock Pulse Remarks
Q2 Q1 Q0
0 0 0 0 No Change in Q0 , Q1 & Q2
1 1 1 1 Q0 , Q1 & Q2 Changes
2 1 1 0 Q0 Changes, Q1 & Q2 No Change
3 1 0 1 Q0 & Q1 Changes, Q2 No Change
4 1 0 0 Q0 Changes, Q1 & Q2 No Change
5 0 1 1 Q0 , Q1 & Q2 Changes
6 0 1 0 Q0 Changes, Q1 & Q2 No Change
7 0 0 1 Q0 & Q1 Changes, Q2 No Change
8 0 0 0 Q0 Changes, Q1 & Q2 No Change

Asynchronous Up-Down Counter: The up and down ripple counter can be realised with change in the
triggering mechanism of the flip flops. The two control signals are used to indicate the direction of count
sequence as shown in Fig.4.4. During up count sequence count-up is high and if count-down is high then
the count sequence is down. Always these two control signals are complement to each other.

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Count Up Q2
Q1
Q0 1
1 1
J2 Q2
J1 Q1
J0 Q0
F2
F1
CLK F0
Pulse K1 K2 Q2
K0 Q1
Q0

Count Down
Fig.4.4 : 3-Bit Asynchronous Up- Down Counter

Synchronous Counters: In the synchronous counters all the flip flops are triggered with common
external clock pulse. These counters are faster than the asynchronous counter and can be used to design
for any no. of sequence of counting.

Design Procedure of Synchronous Counter: Following are the steps followed in designing of
synchronous counter.
(i) Identify the no. of flip flops, based on the no. of count sequences.
(ii) Write the count sequence in the tabular form
(iii) Form the state table, determine the flip flop inputs from its excitation table for the desired next state
(iv) Obtain the Boolean expressions for the flip flop inputs in terms of flip flop outputs using K-Map.
(v) Draw the logic diagram as per the Boolean equation.

Example : Design 2- bit up synchronous counter using JK flip flop.

No. of Flip flops required are 2.
The state table for the 2-bit synchronous counter is as tabulated below.

Flip Flop Inputs

Present State Next State
FF1 FF0
Q1 Q0 Q 1+ Q 0+ J1 K1 J0 K0
0 0 0 1 0 X 1 X
0 1 1 0 1 X X 1
1 0 1 1 X 0 1 X
1 1 0 0 X 1 X 1

K-map to find the Boolean expressions for the flip flop inputs from the state table

Q0 Q0 Q0 Q0
0 1 0 1 Q1 0 1 Q1 0 1
Q1 Q1
0 0 1 0 X X 0 1 X 0 X 1
1 X X 1 0 1 1 1 X 1 X 1

J1=Q0 K1= Q0 J0=1 K0=1

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Q0 Q1
1
J0 Q0 J2 Q2
F0 F1

K0 Q0 K2 Q2

CLK
Pulse
Fig. 4.5 : Logic Diagram of 2-Bit Synchronous Counter

Synchronous BCD (Decade) Counter: In this counter there are ten states, which requires four flip flops.
Using four flip flops we get 16 states, out of which six states are unused states in this counter. The count
sequence and flip flop inputs are given in table. 4 flip flops are required to implement this counter.

Flip Flop Inputs

Present State Next State
FF3 FF2 FF1 FF0
Q3 Q2 Q1 Q 0 Q3 Q2 Q1 Q0 J3 K 3 J2 K2 J1 K1 J0 K0
0 0 0 0 0 0 0 1 0 X 0 X 0 X 1 X
0 0 0 1 0 0 1 0 0 X 0 X 1 X X 1
0 0 1 0 0 0 1 1 0 X 0 X X 0 1 X
0 0 1 1 0 1 0 0 0 X 1 X X 1 X 1
0 1 0 0 0 1 0 1 0 X X 0 0 X 1 X
0 1 0 1 0 1 1 0 0 X X 0 1 X X 1
0 1 1 0 0 1 1 1 0 X X 0 X 0 1 X
0 1 1 1 1 0 0 0 1 X X 1 X 1 X 1
1 0 0 0 1 0 0 1 X 0 0 X 0 X 1 X
1 0 0 1 0 0 0 0 X 1 0 X 0 X X 1

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Q1 Q0 Q1 Q0 Q1 Q0 Q1 Q0
00 01 11 10 Q 3Q2 00 01 11 10 Q 3Q2 00 01 11 10 Q3Q 2 00 01 11 10
Q 3Q 2
00 0 0 0 0 00 X X X X 00 0 0 1 0 00 X X X X
01 0 0 1 0 01 X X X X 01 X X X X 01 0 0 1 0

11 X X X X 11 X X X X 11 X X X X 11 X X X X
10 X X X X 10 0 1 X X 10 0 0 X X 10 X X X X

J3 = Q 2 Q 1 Q 0 K3= Q0 J2 = Q 1 Q 0 K2= Q1Q0

Q1 Q0 Q1 Q0 Q1 Q0 Q1 Q0
Q 3Q 2 00 01 11 10 Q3Q 2 00 01 11 10 Q 3Q2 00 01 11 10 Q 3Q2 00 01 11 10
00 0 1 X X 00 X X 1 0 00 1 X X 1 00 X 1 1 X
01 0 1 X X 01 X X 1 0 01 1 X X 1 01 X 1 1 X
11 X X X X 11 X X X X 11 X X X X 11 X X X X
10 0 0 X X 10 X X X X 10 1 X X X 10 X 1 X X

J1 = Q 3 Q 0 K1= Q0 J0 = 1 K0= 1

1 J0 Q0 J1 Q1 J2 Q2 J3 Q3
F0 F1 F2 F3

K0 Q K1 Q K2 Q K3 Q
1

CLK
Pulse Fig.4.6 : Synchronous BCD Counter

Example: Design MOD-6 counter using JK flip flop and terminate the unused states to initial value 0.

(i) No. of flip flops required are --- 3 as the no. of sequence are 6
(ii) State Table & Input Signals
Present State Next State Flip Flop Inputs
Q2 Q1 Q0 Q2+ Q1+ Q0+ J2 K2 J1 K1 J0 K0
0 0 0 0 0 1 0 X 0 X 1 X
0 0 1 0 1 0 0 X 1 X X 1
0 1 0 0 1 1 0 X X 0 1 X
0 1 1 1 0 0 1 X X 1 X 1
1 0 0 1 0 1 X 0 0 X 1 X
1 0 1 0 0 0 X 1 0 X X 1
1 1 0 0 0 0 X 1 X 1 0 X
1 1 1 0 0 0 X 1 X 1 X 1
K – Map for the flip flop inputs

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Q1 Q0 Q1 Q0
Q2 00 01 11 10 Q2 00 01 11 10
0 0 0 1 0 0 X X X X
1 X X X X 1 0 1 1 1

J2=Q1Q0 K2=Q1 + Q0
Q1 Q0 Q1 Q0
Q2 00 01 11 10 Q2 00 01 11 10
0 0 1 X X 0 X X 1 0
1 0 0 X X 1 X X 1 1

J1=Q2Q0 K1=Q2 + Q0

Q1 Q0 Q1 Q0
Q2 00 01 11 10 Q2 00 01 11 10
0 1 X X 1 0 1 X X 1
1 1 X X 0 1 1 X X 1

J0=Q2 + Q1 K0=1

Q0 Q1 Q2

J0 Q0 J1 Q1 J2 Q2
F0 F1 F1

K0 Q0 K1 Q1 K2 Q2
1

CLK
Pulse Fig.4.7 : Logic Diagram of Mod-6 Counter
Example: Design a counter which can count the sequence 0,1,3,2,4,5,7,6 and repeats using JK flip flop

(i) No. of flip flops required are --- 3 as the no. of sequence are 8
(ii) State Table & Input Signals
Present State Next State Flip Flop Inputs
+ + +
Q2 Q1 Q0 Q2 Q1 Q0 J2 K2 J1 K1 J0 K0
0 0 0 0 0 1 0 X 0 X 1 X
0 0 1 0 1 1 0 X 1 X X 0
0 1 1 0 1 0 0 X X 0 X 1
0 1 0 1 0 0 1 X X 1 0 X
1 0 0 1 0 1 X 0 0 X 1 X
1 0 1 1 1 1 X 0 1 X X 0
1 1 1 1 1 0 X 0 X 0 X 1
1 1 0 0 0 0 X 1 X 1 0 X
K – Map for the flip flop inputs

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Q1 Q0 Q1 Q0
Q2 00 01 11 10 Q2 00 01 11 10
0 0 0 0 1 0 X X X X
1 X X X X 1 0 0 0 1

J2=Q1Q0 K2=Q1Q0
Q1 Q0 Q1 Q0
Q2 00 01 11 10 Q2 00 01 11 10
0 0 1 X X 0 X X 0 1
1 0 1 X X 1 X X 0 1

J1=Q0 K1= Q0

Q1 Q0 Q1 Q0
Q2 00 01 11 10 Q2 00 01 11 10
0 1 X X 0 0 X 0 1 X
1 1 X X 0 1 X 0 1 X

J0=Q1 K0=Q1

Q0 Q1 Q2

J0 Q0 J1 Q1 J2 Q2
F0 F1 F1

K0 Q0 K1 Q1 K2 Q2

CLK
Pulse Fig.4.8 : Logic Diagram

Registers: It is a group of flip flops used to hold the binary data. One flip flop can hold 1-bit binary
information. An n-bit register needs n flip flops to store n-bit data. The register can store the data which
is called as loading of register in two ways. If all the bits are loaded simultaneously with a single clock
pulse, then it is called as parallel loading. If only one bit is stored at a time into the register, then it is
called as serial loading. In serial storage, a n-bit data storage requires n clock pulse.

Shift Registers: The shift registers are capable of shifting binary data from left to right or right to left. A
shift register is an array of flip flops connected in cascade. All flip flops receive a common clock pulse
which triggers the shift from one stage to another. Shift registers are classified into four types based on
the way in which data is stored and retrieved.
(i) Serial In Serial Out (SISO) Register (ii) Serial In Parallel Out (SIPO) Register
(iii) Parallel In Serial Out (PISO) Register (iv) Parallel In Parallel Out (PIPO) Register

(i) Serial In Serial Out (SISO) Shift Register: The shift registers are the cascade of array of flip flops. In this
type of shift register, the data is loaded serially and retrieved serially as shown in Fig. below. A common
clock pulse applied to all the flip flops shifts the data one bit position to the right for every clock pulse.
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Serial Serial
Input D Q1 D Q2 D Q3 D Q4 Output
F1 F2 F3 F4

Q Q Q Q
CLK
Pulse
Fig. 4.9 : 4-Bit Serial In Serial Out Shift Register

e.g., Co sider the data i put to this shift register as 1 . This data is applied at flip flop F a d the
table below shown how the data is shifted and reaches the output terminal. From the table it is
observed that 4 clock pulses are required to load the data and 4 clock pulses to retrieve the data. The
no. of clock pulse required to complete the data storage & retrieve operation is double the no. of bits
shifting in the SISO shift register. The advantage of this type of register is the data bus width, which is a
single line.
Serial Loading of Data Serial Retrieved Data
Flip Flop Output Clock Flip Flop Output
Input Data Clock Pulse (CP) Output Data
Q1 Q2 Q3 Q4 Pulse (CP) Q1 Q2 Q3 Q4
1011 0 0 0 0 Initial Condition After 4 CP 1 0 1 1
1 0 0 0 After 1 CP After 5 CP X 1 0 1 1
1 1 0 0 After 2 CP After 6 CP X X 1 0 11
0 1 1 0 After 3 CP After 7 CP X X X 1 011
1 0 1 1 After 4 CP After 8 CP X X X X 1011

(ii) Serial In Parallel Out (SIPO) Shift Register: In this type of shift register, the data is loaded serially and
retrieved parallel as shown in Fig. below. A common clock pulse applied to all the flip flops shifts the
data one bit position to the right for every clock pulse. Once all the data is loaded into the registers, the
information can be retrieved simultaneously.
Parallel Output

Q0 Q1 Q2 Q3
Serial
Input D Q D Q D Q D Q
F1 F2 F3 F4

Q Q Q Q
CLK
Pulse
Fig.4.10 : 4-Bit Serial In Parallel Out Shift Register
e.g., Co sider the data i put to the register as , the data is applied to first flip flop a d retrie ed
simultaneously from all the flip flops. The table below shows the operation of serial in parallel out shift
register. The data storage requires 4 clock pulses and after 4th clock pulse the data is available
simultaneously at the output. Therefore the no. of clock pulse required for complete operation is equal
to the no. of bits of data. The output data line width is equal to the no. of bits of data. This is also called

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as serial to parallel converter.

Serial Loading of Data

Flip Flop Output Parallel Retrieve of Data
Input Data Clock Pulse (CP)
Q1 Q2 Q3 Q4
1101 0 0 0 0 Initial Condition Serial Input 1 1 0 1
1 0 0 0 After 1 CP
0 1 0 0 After 2 CP Parallel Output
1 0 1 0 After 3 CP
1 1 0 1 After 4 CP After 4 clock pulse the data is available at the output.

(iii) Parallel In Serial Out (PISO) Shift Register: It is also called as parallel to serial converter. The binary
data is loaded into the flip flops simultaneously to all the flip flops by the preset enable bit as shown in
the Fig. . The stored data is then read serially by applying the clock pulse. Since the data is loaded
parallel into the flip flops and read serially, this shift register is called as PISO shift register.

e. g., Co sider the data i put . The table shows how the data is retrieved serially. It requires 4
clock pulses to complete the operation.

Flip Flop Output Serial Retrieve of Data

Clock Pulse (CP) Output Data
Q1 Q2 Q3 Q 4 Parallel Input
Initial Condition 1 0 1 1
After 1 CP X 1 0 1 1
After 2 CP X X 1 0 11 1 0 1 1
After 3 CP X X X 1 011 Serial Output
After 4 CP X X X X 1011

The input data line width is equal to the no. of bits. The clock pulse required to retrieve the information
is also equal to the no. of data bits.

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Parallel Input

Enable D0 D1 D2 D3

Serial
Output
D Q D Q D Q D Q
F1 F2 F3 F4

Q Q Q Q
CLK
Pulse
Fig. 4.11 : 4-Bit Parallel In Serial Out Shift Register

(iv) Parallel In Parallel Out (PIPO) Shift Register: In this type of shift register, the data is loaded parallel to
all the flip flops simultaneously and retrieved parallel as shown in Fig. below. The data is loaded by the
preset enable pulse into all the registers. It is then available at all the outputs of flip flops.

Parallel Input

D0 D1 D2 D3

D Q D Q D Q D Q
F1 F2 F3 F4

Q Q Q Q
CLK
Pulse
Q0 Q1 Q2 Q3

Parallel Output

Fig.4.12 : 4-Bit Parallel In Parallel Out Shift Register

Parallel Input
e.g., Co sider the data i put to the register as , the data is
applied to simultaneously to all the flip flop and retrieved
simultaneously from all the flip flops. It requires data input line 1 1 0 1
width and output line width equal to the bit size.
Parallel Output

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Universal Shift Registers : Universal shift register has the features of all the four types of shift register
SISO, SIPO, PISO and PIPO along with right and left shift operation. The logic diagram includes the flip
flops & multiplexer to select the method of operation as shown in the Fig. below.
Parallel Outputs

A4 A3 A2 A1

Clear Q Q Q Q
D D D D

Clk (CP)

S1

S0
32 1 0 32 1 0 32 1 0 32 1 0

Serial Input
Serial Input for
for Shift-Left
Shift-Right I4 I3 I2 I1

Parallel Inputs
Fig. 4.13 : 4- Bit Universal Shift Register

The functional table shows the operation of universal shift register based on the mode control bits.

Mode Control
Register Operation
S1 S0
0 0 No change
0 1 Shift right operation with serial input transferred into A4
1 0 Shift left operation with serial input transferred into A1
1 1 Parallel Load

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Ring Counter: It is a shift register configuration in which output of the last stage is feedback to input of
first stage. A 4-bit ring counter arrangement using D flip flop is as shown in the Fig.4.14 below. The
initial count sequence can be loaded into the registers with preset enable signal. After first clock pulse
the data is shift to the right by one position and last flip flop data is loaded into first. Once four clock
pulses are applied the count sequence repeats.

D Q1 D Q2 D Q3 D Q4
F1 F2 F3 F4

Q Q Q Q
CLK
Pulse
Fig.4.14 : 4-Bit Ring Counter

Ring Counter Count Sequence

Flip Flop Outputs 1001

Clock Pulse
Q1 Q2 Q3 Q4
1 0 0 1 Initial State
0011 1100
1 1 0 0 1
0 1 1 0 2
0 0 1 1 3
1 0 0 1 4 0110
Fig.4.15 : State Diagram

Johnson Counter: It is also called as Twisted-Ring counter. The Johnson counter configuration is obtained
by modifying the basic ring counter. The complemented output of the last stage is feedback to input of
first stage. The 3-bit Johnson counter configuration is as shown in the Fig.4.16 below.

D1 Q1 D2 Q2 D3 Q3
F1 F2 F3

Q1 Q2 Q3
CLK
Pulse
Fig. 4.16 : 3-Bit Johnson Counter

The operation of the Johnson counter is described by the state diagram and its function table indicates
the output of each flip flop at each clock pulse.

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Johnson Counter Count Sequence

000
Flip Flop Output
Clock Pulse
Q1 Q2 Q3 100
0 0 0 Initial State 001
1 0 0 1
1 1 0 2
1 1 1 3 011 110
0 1 1 4
0 0 1 5 111
0 0 0 6
Fig.4.17 : State Diagram

Sequence Generator: This is logic system which generates the sequences with respect to the applied
clock pulse. The length of the sequence is the number of successive bits in sequence before the pattern
repeats. For example if there are 6 bits repeating then the sequence length is 6. The bit pattern
01101,11010 and 10101 constitutes the same sequence, because the generator repeats the pattern over
and over again. Thus we can read the sequence in any way. The block diagram of sequence generator is
as shown in Fig. 4.18. It consists of D flip flop along with control decoder logic to determine the next
state of flip flop outputs.

Next State
Decoder Logic
f(Q1,Q2,......Qn)

D1 Q1 D2 Q2 D3 Qn
F1 F2 F3

Q1 Q2 Q3
CLK
Pulse
Fig. 4.18 : 3-Bit Johson Counter

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