Program : B.

Tech
Subject Name: Digital System Design
Subject Code: EC-303
Semester: 3rd
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Unit-3: Sequential Logic Design: Building blocks like S-R, JK and Master-Slave JK FF, Edge triggered FF,
Finite state machines, Design of synchronous FSM, Algorithmic State Machines charts. Designing
synchronous circuits like Pulse train generator, Pseudo Random Binary Sequence generator, Clock
generation
.......................................................................................................................................................................

Latches : The latch is a bistable multivibrator element with two stable states. It has two outputs
complement to each other. Latch is a basic sequential component which test its input signal always and
changes its output accordingly. Two NOR gates are crossed coupled to get the bistable behaviour of the
latch. The logic diagram is as shown in the Fig. below.

Truth Table of SR Latch

R Inputs Outputs Comment
(Reset) Q
S R Q Q(t+1)
0 0 0 0 No Change
0 0 1 1 (Previous Output)
0 1 0 0 Reset(0)
Q 0 1 1 0
S
(Set) 1 0 0 1 Set (1)
1 0 1 1
Fig.3.1 : SR Latch using NOR Gates 1 1 0 x Prohibited State
1 1 1 x

Flip-Flops : The flip-flop is a basic building block of sequential components. It produces the output
depending on the present input and the past output/input of the logic. The block diagram of the flip flop
is as shown in the Fig. below. Sequential circuit consists of a combinational circuit and a
feedback/memory element.

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Combinational
Input Output
Circuit

Feedback
(Memory)
Element

Fig.3.2 : Block Diagram of Sequential Circuit

These circuits are binary cells which can store 1-bit information. Since this is a sequential component, its
operation is controlled by a clock signal. The output of the flip-flop is determine by its inputs at the
triggering point of the component. The four types of flip-flops are discussed, namely SR, D, JK & T
flip-flops.

Clocked RS Flip-Flop :

The SR flip flop is the basic flip-flop component. It is Set (S) and Reset (R) flip-flop, its sequence of
operation is It is realised with NOR logic connected in feedback configuration.

R
S Q Q

CLK CLK

R Q Q

S
Fig.3.3 : Symbol of SR Flip-Flop
Fig.3.4 : Clocked Logic Diagram of SR Flip-Flop

Inputs Outputs Remark

S R Q Q(t+1)
0 0 0 0 No Change in the Output
0 0 1 1 (Previous Output)
0 1 0 0 Reset(0)
0 1 1 0

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1 0 0 1 Set (1) SR Flip-Flop Functional Table

1 0 1 1
1 1 0 x Indeterminate Characteristic Table of SR Flip-Flop
1 1 1 x (Forbidden Condition) S R Q(t+1)
0 0 Q(t)
0 1 0
1 0 1
1 1 Indeterminate

Characteristic equation of SR Flip-flop is given as

Q (t+1) = “ + ‘ Q t
Q(t+1) ---- Next State ; Q(t) ----- Present State

D Flip-Flop: It is the modified SR flip-flop as shown in the Fig. below. When both the inputs of SR flip-
flop are at logi , the the output is i deter i ate. This indeterminate state of SR flip-flop is overcome
in D flip-flop by connecting the inputs complement to each other always. The D flip-flop is the basic
build element of memory devices. It can store 1 bit of data in the flip-flop.

D R
S Q Q

CLK CLK

R Q Q
S
Fig.3.5 : Symbol of D Flip-Flop D
Fig.3.6 : Clocked Logic Diagram of D Flip-Flop

The characteristic table and characteristic equation are given in the below table

D Flip-Flop Functional Table Characteristic Table

D Q(t) Q(t+1) D Q(t+1)
0 0 0 0 0
0 1 0 1 1
1 0 1
Characteristic equation of D flip-flop
1 1 1
Q(t) =D

JK Flip-Flop: In SR flip-flop one of the state is indeterminate. This indeterminate state is permissible in JK
flip-flop. When both J and K inputs of JK flip-flop are at logi , the the output is the complement of
the previous output. The symbolic and logic diagram of JK flip-flop are as shown in the Fig. below. When
both the inputs of JK flip-flop are at logi , the output toggles etwee a d . I this tra sitio if
the duration of the clock pulse is greater than the propagation delay of the component, then the output
os illate etwee a d . It is alled as ra e arou d o ditio .

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K
J Q Q

CLK CLK

K Q Q
J

Fig.3.7 : Symbol of JK Flip-Flop

Fig.3.8 : Clocked Logic Diagram of JK Flip-Flop

JK Flip-Flop Functional Table

Inputs Outputs Remark Characteristic Table of JK Flip-Flop

J K Q Q(t+1)
J K Q(t+1)
0 0 0 0 No Change in the Output
0 0 Q(t)
0 0 1 1 (Previous Output)
0 1 0
0 1 0 0 Reset(0)
1 0 1
0 1 1 0
1 1 Q t Toggle
1 0 0 1 Set (1)
1 0 1 1 Characteristic equation of JK Flip-flop is given as
Q t+ = JQ + K Q
1 1 0 1 Toggle condition
Q(t+1) ---- Next State ; Q(t) ----- Present State
1 1 1 0

T Flip-Flop: The T flip-flop is the toggle flip-flop, which is the special condition of JK flip-flop. It consist of
only one input tied together as shown in the Fig. below. It is used in applications where the continuous
sequence of counting is necessary. The output of this flip-flop is u ha ged if the T i put is a d it
toggle etwee a d if the T i put is .

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T
T J Q K Q

CLK CLK

K Q Q
J

Fig.3.9 : Symbol of T Flip-Flop

Fig.3.10 : Logic Diagram of T Flip-Flop

D Flip-Flop Functional Table Characteristic Table

T Q(t) Q(t+1) T Q(t+1)
0 0 0 0 Q(t)
0 1 0 1 Q t
1 0 1
Characteristic equation of T flip-flop
1 1 0
Q t = TQ + T Q = T Q

Race Around Condition : The race around condition occurs in JK flip-flop, when both J & K are at logic
. This The output of JK flip-flop becomes uncertain in this conditions. If the clock pulse is grater than
the change in the input pulse or the propagation delay of the component, then the output may change
multiple times. This ha ge etwee a d akes the output of the flip flop u ertai . The
o ditio of ha gi g etwee a d due to differe e i the lo k a d i put pulse ha ge is alled
as race around condition. This can be overcome by using master slave configuration or the appropriate
use of the clock signal in the operation. The Fig. below indicates the uncertain output condition.

Clock
Pulse

Output Output is
uncertain
tp
Fig.3.11 : Race Around Condition in JK Flip-Flop Output

Triggering of Flip-Flop: The state of the flip-flop output is switched by the change in the input signal.
This change is called a trigger and the transition it causes is said to trigger the flip-flop. There are two
ways of triggering the flip-flop (i) Edge Triggering (ii) Level Triggering. Fig. below shows these triggering
methods.

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High Level

Positive Negative Edge

Edge
Low Level
Fig. 3.12: Clock Pulse

(i) Edge Triggering: The flip-flop is trigger in the edge of the clock pulse in this type of triggering. The flip
flop output changes during the edge of the clock pulse.
Positive Edge Triggering: The flip-flop is triggered during the positive edge of the clock pulse. During the
rising edge of the clock pulse (as shown in Fig. above) the output of the flip will change according to its
inputs. The symbolic representation of the flip flop is as shown in Fig. below.
Negative Edge Triggering: The flip-flop is triggered during the negative edge of the clock pulse. During
the falling edge of the clock pulse (as shown in Fig. above) the output of the flip will change according to
its inputs. The symbolic representation of the flip flop is as shown in Fig. below.

S Q S Q

CLK CLK

R Q R Q

Fig.3.13 : Positive Edge Triggered Flip-Flop Fig. 3.14 : Negative Edge Triggered Flip-
Flop
(i) Level Triggering: The flip-flop is trigger in the level of the clock pulse in this type of triggering. The flip
flop output changes during the level of the clock pulse.
Positive Level Triggering: The flip-flop is triggered during the positive level of the clock pulse. During the
high level of the clock pulse (as shown in Fig. above) the output of the flip will change according to its
inputs. The symbolic representation of the flip flop is as shown in Fig. below.
Negative Level Triggering: The flip-flop is triggered during the negative edge of the clock pulse. During
the falling edge of the clock pulse (as shown in Fig. above) the output of the flip will change according to
its inputs. The symbolic representation of the flip flop is as shown in Fig. below.

S Q S Q

CLK CLK

R Q R Q

Fig.3.15 : Positive Level Triggered Flip-Flop Fig. 3.16 : Negative Level Triggered Flip-Flop

Master-Slave JK Flip-Flop : The master-slave JK flip-flop is configured to over come the race around
condition in JK flip-flop. The configuration is as shown in the Fig. below. The master is triggered when
the clock is high and the slave is follows the master when the clock pulse goes low.

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S Q S Q
J

CLK Master CLK Slave

K
R Q R Q

Fig.3.17 : Master- Slave JK Flip=Flop

Flip-Flop Excitation Tables:

It specifies the inputs of the flip-flop, when the next state and present state are know. It is the condition
for input signal to get the appropriate output next state. This excitation table is being used during the
design of counters, registers or any of the sequential circuits. The excitation table of all the flip-slop is as
tabulated in the below table.

Q(t) Q)t+1) S R J K D T
0 0 0 X 0 X 0 0
0 1 1 0 1 X 1 1
1 0 0 1 X 1 0 1
1 1 X 0 X 0 1 0

Realization of one flip flop using other flip flops: Using the excitation table we can find the relation
between one flip flop with other flip flop. From the Boolean expression for the input variables we can
realise one flip flop from other flip flop.

D S Q S Q

CLK T CLK

R Q R Q

Fig.3.18 : D Flip-Flop using SR Flip-Flop

Fig.3.19 : T Flip-Flop using SR Flip-Flop

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D Q T Q
T D
CLK CLK

Q Q

Fig. 3.20: T Flip-Flop using D Flip-Flop Fig. 3.21: D Flip-Flop using T Flip-Flop

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