NXP Edge Processing

Layerscape Access 5G Solutions

Confidential NDA ONLY

Q2 2020

CONFIDENTIAL AND PROPRIETARY

PUBLIC 1
 NXP End-to-End Solutions for 5G Edge
Core Network
Home
& SMB 5G
Dense Residential and Enterprise
Repeater
5G Integrated
Small Cell / IAB

5G Femto
Cell
5G
FWA
NXP NXP
Broadband WIFI
Gateway Radio
O-RAN
Small Cell
FWA = Fixed Wireless Access CU/DU/RU

5G Macro

2 CONFIDENTIAL AND PROPRIETARY

NXP 5G Access
Edge Launch
– to date

MWC, Barcelona, February, 2019

MWC, Los Angeles, October, 2019

3 CONFIDENTIAL AND PROPRIETARY NXP Confidential and Proprietary

 Solution Features
NXP 5G End-to-End Communications
GTM Message
Digital Baseband & Control:
• Cost, power optimized
Infrastructure Portfolio
hardware
From antenna to CPU, NXP offers a robust portfolio of 5G technologies that deliver best-of-
• Rich software ecosystem class performance and security for infrastructure, industrial, and automotive applications.

RF Front End: • Layerscape Access family of programmable processors for infrastructure, premises, fixed-
wireless access, and small cells.
• Low, medium, high power
• Multi-chip module solutions • AirFast family of multi-chip modules for 5G cellular base stations

Customer Benefits
• Most optimized solutions
• Fast Time to Market
• Flexible development models
NXP’s 5G solutions deliver proven, open infrastructure solutions, scalable across multiple
system types, and adaptable to different implementations or future specification changes.
To learn more visit nxp.com/5G
APPLICATIONS

Carrier Benefits
• Easier 5G Access Edge deployments Automotive Industrial Communication
& IoT Infrastructure
• Tackling the challenge of numerous
4
frequency bands in various regions
CONFIDENTIAL AND PROPRIETARY NXP Confidential and Proprietary
• Unlocks Innovation
 The 5G Access Edge

What is the 5G Access Edge?

The 5G Access Edge is the set of interface
equipment between the 5G core and the
end-user, not including mobile devices
(UEs) or servers.

New 5G Deployment Options

• Previously the wireless
infrastructure was vendor-
specific, proprietary & offered
fewer choices.
• New Open Radio Access
Network (O-RAN) prescribes an
open framework for a variety of
network and deployment options.

NXP Confidential and Proprietary PUBLIC 5

 NXP Layerscape Access Programmable Baseband Processors
Layerscape Processors Ecosystem Partners Reference & Development Designs

Layerscape Access Baseband

Processors • >1Tflop vector engines
LA12XX • 50Gbps I/O Reference Design:
• 8-10W LA1575 PoC VSPA
• LA1200 – DU coprocessor • Integrated ADC/DACs Software Development system Orderable today as part of Early
• LA122X – CPE • Integrated FEC Access Program
• LA123X – small cell

Layerscape Access
Baseband Processors
LA9XXX
• LA935X – Radio Unit
• LA931X - Repeater
Layerscape Access
Baseband Processors
LA1575
• LA1575 – Proof of Concept
• 3x vector engines
• 2.5 GbE I/O Reference Design:
• 2W LA12XX CPE
• Integrated ADC/DACs Development system Orderable Q1 2020 as part of
Early Access Program
Hardware
• 4x vector engines
• 10 GbE & PCIe I/O Orderable Q1 2020 as part of
Reference Design:
• Integrated FEC Early Access Program
• Quad ARM v8
LA93XX RU
Development system

• 2-16 Arm v8 CPUs

Layerscape
Communication SoCs:
• LX2160 – CU/DU
• LS10XX – Integrated Small
Cell, RU, CPE
• 2.5-100 GbE I/O
Reference Design:
• 1-16 PCIe lanes Systems
• 4-30W LX2160
PCIe iNIC CU
• eCPRI offload
Reference system Orderable today
• Integrated Security &
Virtualization

6 CONFIDENTIAL AND PROPRIETARY

Layerscape Access Single Architecture, Multiple 5G Solutions

Fixed
Integrated
Wireless
Small Cell
LA1230 LA1220 Access NSA view; SA also available

LS10xx LS10xx
Layerscape
Access
LS10xx LX2160

LA1210
Radio Distributed
Unit
LA935x LA1200 Unit

7 CONFIDENTIAL AND PROPRIETARY

 5G SPLIT OPTIONS
LX2160/LX2080/
LS104x LA123x

High Low High Low High Low

RRC PDCP RF
RLC RLC MAC MAC PHY PHY

Data
Opt 1 Opt 2 Opt 3 Opt 4 Opt 5 Opt 6 Opt 7 Opt 8
High Low High Low High Low
RRC PDCP RF
RLC RLC MAC MAC PHY PHY

Data HUB
DU
RU
6
4
-
b
i
t
D
D
R
4
M
A A A A e
7 7 7 7 m
2 2 2 2 o
2MB L2 cache r
y
Secure Boot C
Coherent Interconnect (CCI-400) o
Trust Zone n
t
Flash Controller, QuadSPI IO MMU IO MMU rIO MMU

LX2xxx LX2160 ACCL

Power Management o
Parse, Classify, l
2x SD/SDIO//eMMC Queue Distribute, Autorespond l
Mgr. e
4x UART

SATA 3.0
PCIe 3.0
PCIe 3.0
r

PCIe 3.0
SEC
4x I2C
Buffer
SPI, GPIO, JTAG
Mgr.
3x USB3.0 w/ PHY

8-Lane 10GHz SERDES

LS10xx LA9353
LA121x
8 CONFIDENTIAL AND PROPRIETARY NXP Confidential and Proprietary
NXP LAYERSCAPE ACCESS PRODUCTS
• Open, flexible, power and
price optimized O-RAN
solution processors.

• Sub-6GHz or mmWave
support

• High Performance Forward

Error Correction hardware

• Zero-IF I/Q radio interfaces

• Proven, ARM-based Software

Ecosystem Partners
9 CONFIDENTIAL AND PROPRIETARY
Core and Memory complex LA1224 High Performance
• 4x e200@ <640MHz (equivalent to ARM M7)
• RF Management/control Baseband Processor
• Timing, frame structure control
• 4-8x VSPA3-16@ <640MHz (=1.3TFLOP)
• Floating point SIMD compute, 32 CMAC HP
/clock
• 2MB on-chip SRAM (temp data store)
Connectivity and I/O
• 2x PCIe gen3 up to 8 lanes total
• 2T2R {I+Q} 4GSPS ADC/DAC complex
• Dual channel, <1GHz RF channel b/w
mmWave bands
• 4T4R {I+Q} 425MSPS ADC/850 MSPS DAC
complex
• Dual channel, <200MHz RF channel b/w
<7GHz bands
Acceleration
• Forward Error Correction: LDPC (5G/3GPP,
gNB/UE)
• Forward Error Correction: Polar (5G/3GPP, Ideal, software defined, open baseband processor for:
gNB/UE) • <6GHz or mmWave 5G Small Cell
• Forward Error Correction: LDPC (802.11ad/ay) • <6GHz or mmWave 5G FWA CPE / Mesh
• <6GHz or mmWave 5G RU
Low speed I/O and RFIC control • O-RAN CU/DU L1 / Error Correction offload co-processor
• Low-speed SPI/JTAG/UART/I2C • <6GHz or mmWave General market / mil-aero, civilian safety SDR
• Fast RFIC management through LLPC
• On-chip
10 CONFIDENTIAL AND
PLL, timebase PROPRIETARY
/ frame timer generator NXP Confidential and Proprietary
 Core & Memory Subsystem
LA9353 SoC • 2x e200 @ 312MHz, each with
• 16K I-Cache, 16K D-Cache
FECU FECU FECU
e200 e200 • 64K DMEM
VSPA-16 VSPA-16 VSPA-16 • 2MByte On-Chip SRAM
16KB 16KB 16KB 16KB
D I D I • 3x VSPA-16 @625 MHz
144KB 320KB 144KB 320KB 144KB 320KB
64KB 64KB D I D I D I • Integrated Reed Solomon, scrambler, CRC
units (~2+ Gbps)
PLL (system, DCS)
Interconnect (non-coherent)
• Security offload
Timer
• AES-256 crypto up to 2Gbps
UART 2MB
SEC,
On-Chip
ADC/DAC
DMA Interfaces
I2C, d/qSPI, GPIO, JTAG SRAM
• Integrated data converters
RGMII 1/2.5 Gbps • up to 424MSPS ADC x4
Eth controller

ADC
ADC
DAC
DAC
ADC
ADC
DAC
DAC
• Each pair of ADCs can be interleaved to
give 848MSPS effective
• up to 848MSPS DAC x4
Cost and power efficient, software • Timer outputs
defined, open baseband processor 1-Lane 2x 2x 2x 2x • dSPI + qSPI, I2C, GPIO, JTAG, UART
1/2.5 GHz analog analog analog analog
for: SERDES In Out In Out Network IO
• <6GHz or mmWave 5G RU
• Custom FWA or Wireless Data Link
• 1/2.5Gbps SGMII / SerDes and RGMII
• <6GHz General market / mil-aero, civilian Other Parameters
safety SDR • 16nm FinFet technology
• <2.5W
• 9x9mm FC-BGA package
11 CONFIDENTIAL AND PROPRIETARY NXP Confidential and Proprietary
Modular and Scalable Solutions for 5G NR CU/DU/RU
2T2R~4T4R 4T4R~16T16R 4T4R~16T16R
Radio Unit (RU) Radio Unit (RU) Radio Unit (RU)
10-25 10-25
RU 10GbE
LS102x
GbE
LS10xx
GbE
LS104x
2.5GbE PCIe PCIe

LA9353
LX2160 Discrete LA121x Discrete LA121x NXP
LX2160 LX2160
2-2.5W
iNIC RF 7.5-10W
iNIC RF 7.5-10W
iNIC RFIC

Distributed Unit (DU) gen1 Distributed Unit (DU) gen2

CU/DU Target 4x4R4T

(2x LX2160 + LA120x
Target 4x4R4T
(2x LX2160 +
FPGA LA1200
accelerator
accelerator 1x FPGA) accelerator 2x LA1200)
40W 10W
PCIe 25GbE PCIe 25GbE

LX2160 LX2160
LX2160
L1/L2 LX2160
L1/L2
iNIC
30W iNIC
30W

2019 Q1 2020
NXP Confidential and Proprietary PUBLIC 12
CPE and Integrated Small Cell Solutions for 5G NR
100MHz 4R4T NSA (SA)
Customer Premises Equipment (CPE)
1/2.5/
NXP
CPE 10GbE
LS10xx
LA
1224 RFIC
PCIe
PCIe CPE
2x400MHz 2R2T NSA (SA)
Customer Premises Equipment (CPE)
1/2.5/ GDM 5W LTE
10GbE LA mmWave … 7243A RFIC
LS10xx
1225 RFIC
PCIe
PCIe 2x400MHz 2R2T
Integrated Small Cell
GDM 5W LTE 1/2.5/
7243A RFIC 10GbE LA mmWave …
LS10xx
1235 RFIC
PCIe
Small
100MHz 4R4T Cell
Integrated Small Cell
1/2.5/
10GbE LA
LS10xx Discrete
1234
PCIe

2019 2020
NXP Confidential and Proprietary PUBLIC 13
 DISTRIBUTED UNIT
EXAMPLES

14 CONFIDENTIAL AND PROPRIETARY

Layerscape Access
DU Platform
DU Tile Unit
10 / 25GbE To CU

LA1200 PCIe
Multicore Processor
Lookaside LX2160
Accelerator 8RT/100MHz
FEC offoad 4 Layer • 16-Core ARM64b SoC (A72 @2.2GHz) Multicore
− 282GFLOP (32b) or 563 GOP (16b)
− Multiple datapath accelerators and highspeed PCIe and Ethernet
• High Performance Ethernet subsystem
10 / 25GbE
To RU − 130Gbps Ethernet bandwidth and L2 switching
− Including QoS, IEEE1588, eCPRI classification
• Look-aside FECA accelerator
• DU design supported by broad ecosystem − 5G DCI/UCI (Polar) encoder and decoder
− L1, L2 Software partners − 5G Shared Channel (LDPC) encoder and decoder
− ODMs for system hardware development

NXP Confidential and Proprietary PUBLIC 15

BONNYRIGG SYSTEM BOARD
Flexible Configuration options

➢ DU + LA1200 offload
• LX2 x16 core ARM
− 8 cores for 7.2 split Arm Neon
L1 processing
− 8 cores for L2-3 processing
• LA1200 for Forward Error
Correction
− LDPC or Polar offload
− X8 PCIe to Host for 50Gbps
connectivity

➢ RU 7.2 Split Dev System

• 4T4R w/ NXP Yucca RFIC
• LA1214 configuration for 7.2
lower phy
• Headroom for DFE: DPD,
CFR
➢ Integrated Small Cell

LA12xx LX2160
16 CONFIDENTIAL AND PROPRIETARY NXP Confidential and Proprietary
LA1200: SDR Accelerator Core and Memory complex
• 4x MPU@ <640MHz (equivalent to ARM M7)
• 8x VSPA3-16@ <640MHz (=1.3TFLOP)
• Float SIMD compute, 32 CMAC HP/clock
SDR Accelerator • 2MB on-chip SRAM (temp data store)
FECA Accelerator IP
VSPA Connectivity and I/O
e200 VSPA • 2x PCIe gen3 (50 + 50GBps throughput)
e200 VectorDSP
DSP
MPU Vector Acceleration
MPU • F5G DCI/UCI (Polar) decoder (2.5 Gbps)
IRAM, DRAM • Support all K, N, E per 5G specs
• Programmable frozen bit location vector
Interconnect • 5G DCI/UCI (Polar) encoder (0.6 Gbps)
• Support all K, N, E per 5G specs
DMA

LDPC, • Programmable frozen bit location vector

PCIe gen3

• 5G Shared Channel (LDPC) decoder (9 Gbps) (10 iter.)

Polar FEC
x4/x8

• Supports early termination

2x

• Support all K, N, E per 5G specs

SRAM

6MB
2MB

• 5G Shared Channel (LDPC) encoder (13 Gbps)

SRAM • Support all K, N, E per 5G specs
• 802.11ad decoder (15 Gbps)
• 1/2, 3/4, 5/8, 13/16 Code Rates
8 Lane • 802.11ad encoder (40 Gbps)
8G SerDes • 1/2, 3/4, 5/8, 13/16 Code Rates
Product availability
• Availability and timeline: 2020
To Host • TSMC 16FFC technology node
• 7.5-10W @105c (use-case dependent)

17 CONFIDENTIAL AND PROPRIETARY NXP Confidential and Proprietary

DU System Baseband Unit: LX2160+LA1200 based
2x4R4T/100MHz DU Baseband Unit Backplane
Connector • LA1200: Lookaside accelerator FEC offoad
Re- Re- Re-
DDR (4GB) DDR (4GB) Tim Tim Tim
− 5G DCI/UCI (Polar) encoder and decoder

Gen 3 x4
− 5G Shared Channel (LDPC) encoder and decoder

PCIe
DDR4

DDR4

SFI

SFI
bus

bus
− UL and DL bit processing
Temp 64bDDR4 64bDDR4 SerDes 2
Fan
SFP Clk Other − Partial UL and DL symbol processing
I2C

RTC I2C Clk Clk

... 100, Gen clocks
125MHz 100,
UART

UART 160
Conn. MHz
• LX2160: L1/L2/L3 processing for the DU

SPI
DAC VCXO
RCW/

Clk
Rst

CPLD

1588
NXP

in
3GPP Clk,122.88M
JTAG LX2160
JTAG

conn. • High capacity density

I2C
I2C

GPIO,

GPIO
IRQ
NOR − 2x 4R4T@100MHz or equivalent
QSPI

UART
Flash LA1200 UART
PHY Coprocessor Conn. − ~5Gbps MAC/PHY throughput
SerDes 3
PCIe

SerDes
eMMC eSDHC Gen 3
JTAG

JTAG
x8
conn.
SerDes 1 RGMII UART GPIO
• Fronthaul: 4x 10GbE (SFP) shown
RGMII
XFI

XFI

XFI

XFI

XFI

XFI

PPS, 10MHz

Re- Re- Re- Re- Re- Re-

PHY − Lowest-cost
GPS bus

Tim Tim Tim Tim Tim Tim

− Alternative: 25/50/100GbE options
SFI

SFI

SFI

SFI

SFI

SFI

10G 10G 10G 10G 10G 10G

SFP SFP SFP SFP SFP SFP
+ + + + + + RJ45 RJ45
conn. conn.
SMA
• Backhaul: 2x 10GbE + PCIe g3 x4
Fronthaul 10G x 4 Backhaul 10G x 4 OAM, GPS
(RU Interface) (CU Interface) − Aggregation option through backplane
Front Panel
18 CONFIDENTIAL AND PROPRIETARY
DU System Reference Design DDR DIMM

GPS Module

Backhaul:
PCIe g3 x4

LX2160
Fronthaul
&
Backhaul
LA1200 Interfaces
Lookaside
accelerator
FEC offoad

L1/L2/L3
19 CONFIDENTIAL AND PROPRIETARY NXP Confidential and Proprietary processing
 RADIO UNIT
EXAMPLES

20 CONFIDENTIAL AND PROPRIETARY

Existing 5G RU design for 2T2R summary (Option 7.2)

DU FPGA FPGA ADI/TI PA

2x2 ant

Low-PHY + Partial DFE TRX + PA / Antenna

O-RAN + FFT partial DFE
Fronthaul +
eCPRI

DU FPGA ADI/TI PA
2x2 ant

DFE + FFT/Low-PHY + TRX + PA / Antenna

O-RAN Fronthaul / eCPRI partial DFE
NXP Confidential and Proprietary PUBLIC 21
RU Solution Architecture: NXP LA121x
• Complete RU Digital Front End
2/4 ant
− Cost/power optimized DFE (<10W per 4T4R) LA121x
− 4 antenna / LA12xx, multi-device scaling support IQ
10/25 AFE
− On-chip DAC/ADC (de)
GbE
− Analog (baseband) IQ interface to IQ modulator LS1xxx PCIe 4T4R mod 2/4 ant
LX2xxx DFE
− Classical DFE processing chain covering FFT, DUC, CFR, DU
DPD, DDC, calibration host Proc IQ
(de) AFE
− Potential baseband offload for beam forming, RACH mod

• Layerscape host
− GbE to PCIe conversion
− eCPRI encapsulation/decapsulation
Functional Partitioning
IQ Compen.
Beam Gain/DC
eCPRI IFFT DUC CFR DPD D/A 0° 90° PA
form Ctrl
Interpolate

LayerScape LA1230
NXP Confidential and Proprietary PUBLIC 22
Option 7-2: NXP RU Design w/ eCPRI
Fronthaul/ DUC/IQ, DDC/IQ
eCPRI CFR, DPD +
LOW-PHY
2x2

I/Q (de) mod

2.5G

1 X Yucc /
LA935x

discrete
10G
LS1xxxx 2.5G LA935x

4x4

2 X Yucc /
I/Q (de) mod

discrete
10G PCIe GEN3 x 2
LS1023 or LA1214
LS1043

PCIe GEN3 x 2
8x8

4 X Yucc /
10G

I/Q (de) mod

LA1214

discrete
LS1088 or
10G higher PCIe GEN3 x 2
LA1214

• W/ IQ sampling rate of 122.88Mhz and 32-bit IQ data width, the throughput is ~3.9Gbps and ~2.8Gbps after FFT. Compression is needed
for LA9358 (e.g. u-LAW from O-RAN spec)
• Synchronization among multi-LA935x or multi-LA121x (need to run with the same reference clock at IQ and PCIe interfaces)
• eCPRI encapsulation code/algorithm can be reused between RU and DU

NXP Confidential and Proprietary PUBLIC 23

 RU Functional Mapping
• The functional mapping is generic for <6GHz (FR1) and mmWave (FR2) both
• Note that in an FR2 implementation:
− beamforming is done in the analog (or hybrid) domain
− CFR and DPD are simplified / optional

Radio Unit (RU)

Multicore ARM (Layerscape) DSP (Layerscape Access)
Digital Unit (DU) DPAA ARM Software VSPA Software DCS
Hardware
ARM (Layerscape) RF Board
ORAN eCPRI
eCPRI eCPRI De- IQ IQ Beam Interpo- Interpo- QER/DC
Low PHY / Classify/ iFFT+CP CFR DPD DAC Mod PA
Tx deframe Comp Buffer Buffer Forming late late Offset
eCPRI Switch
7-2

1588
GPS Boot/Init Linux/RT
S-Plane

eCPRI IQ IQ Beam Deci QER/DC

Comp FFT+CP ADC De-Mod LNA
frame Buffer Buffer Forming mate Offset

RACH

DPD SRX

To next RU/
device

NXP Confidential and Proprietary PUBLIC 24

Arm Specific Functional Mapping
Radio Unit (RU)
Multicore ARM (Layerscape) DSP (Layerscape Access)
Digital Unit (DU) DPAA ARM Software VSPA Software DCS
Hardware
ARM (Layerscape) RF Board
ORAN eCPRI
eCPRI eCPRI De- IQ IQ Beam Interpo- Interpo- QER/DC
Low PHY / Classify/ iFFT+CP CFR DPD DAC Mod PA
Tx deframe Comp Buffer Buffer Forming late late Offset
eCPRI Switch
7-2

1588
GPS Boot/Init Linux/RT
S-Plane

eCPRI IQ IQ Beam Deci QER/DC

Comp FFT+CP ADC De-Mod LNA
frame Buffer Buffer Forming mate Offset

RACH

DPD SRX

To next RU/
device

• eCPRI frame receive/transmit operation (everything that needs to

happen to get the software to the start of the eCPRI header – this
is handled by HW
− This includes the time it takes to wake up the Linux application
dealing with the eCPRI frame, but this latency can be brought
down to near-zero by means of DPDK polling mode
• eCPRI / O-RAN FH CU framing/de-framing: this is a (DPDK) SW
function that parses the eCPRI headers and this is what Arm
cores are good at. This doesn’t include any DSP-like functions
• The IQ extraction and (optional) de-compression: this is the
building/consumption of the IQ buffer that the VSPA cores use /
generate

NXP Confidential and Proprietary PUBLIC 25

 RU System: 4R4T-8R8T, sub 6GHz, <100MHz
• eCPRI/Ethernet
DDR (1GB) − <2x 10GbE Backhaul (DU,
100,
125MHz Clk Other cascading)

DDR4
bus
Clk
Gen clocks
− Option 7-1, 7-2, etc
32bDDR4 100,

UART
UART
Conn. 160 ▪ SW programmed eCPRI

RCW/
Rst
CPLD MHz

Clk
UART JTAG From RF LO
JTAG I2C

JTAG
conn. To RF LO Conn. conn. − Integrated 1588 support
eMMC eSDHC
LO PLL
Temp I2C UART JTAG

SPI
DAC VCXO
Fan LS1043/
Modulator

ADC/
SFP

DAC
I2C

RTC I2C LS1026/

De-Modulator • 4R4T Low-PHY+DPD

GPIO, 1588
... LS1046

in
Modulator

ADC/ ADC/
10GbE LA121x −

DAC DAC
10G PHY LA1200 De-Modulator
Integrated ADC/DAC
SerDes

(to DU)

GPIO
IRQ
Low-PHY, DFE
10GbE 10G PHY Modulator − SW defined CFR/DPD
(cascading) De-Modulator
SerDes

SerDes
RGMII

1GbE RJ45
PHY Modulator − Cascade option to 8R8T

ADC/
ADC/

DAC
(OAM) conn. UART GPIO DAC De-Modulator
Optional
GPS

PPS
bus

Cascading DPD
• Discrete RF Front End

SerDes
RJ45 LA1200
SMA 4T4T
conn. Low-PHY, DFE − Best-in-class mod/de-mod
− Discrete or FEM based RF
PA/LNA

26 CONFIDENTIAL AND PROPRIETARY NXP Confidential and Proprietary

RU System Reference Design DDR DIMM

GPS Module

Backhaul:
PCIe g3 x8

LX2160
2x 10GbE
Low-Speed LA121x 25GbE
RF interfaces eCPRI
Backhaul
(DU, cascading)
Option 7-1, 7-2, etc

High-Speed
Proxy for LS10xx
27
Low-PHY
CONFIDENTIAL AND PROPRIETARY
DFE NXP Confidential and Proprietary
RF interfaces
 INTEGRATED
SMALL CELL
EXAMPLES
28 CONFIDENTIAL AND PROPRIETARY
Integrated Small Cell Example Diagram
VALUE PROPOSITIONS
I2C devcies

UART JTAG
Level
shifter
I2C
multiplexer
Thermal
sensor
RTC • Scalable solutions for supporting different power
UART1 JTAG I2C
Power
monitor
I2C/GPIO
expander
and performance requirements :
DDR
SFP
control
EEPROM • FR1 & FR2,
DDR4

PCIe x2
Marvell • 2T2R to 4T4R.
IFC
NAND flash 11ax Level
shifter
UART • Single or multi sector options
QSPI x2, x4 transcevier

qSPI flash UART

Predriver
•
Balun
USB3.0 USB3.0 USB Gain PAM
Most cost and power effective solutions.
re-driver switch LS1046A I2C
Level I2C ADC/DAC Mod/ Block
LS1046 shifter Demod
Analog Level
SD/
eMMC
Or
UART
Level UART
Balun
Gain
RF226Block Rx FEM • End-to-End solution for Small Cell. Antenna-to-
switch shifter shifter
LA1234
LA1220 Airfast IP interface. IAB option.
1588 LX2 PCIex4 “Yucca”
PTP Balun Predriver
PA/LNA
SD eMMC
x2 Gain PAM
•
Power PCIe ADC/DAC

supply
x1
analog
x4 Mod/
Demod
Block Complete SW solutions (multiple ecosystem
switch Balun
Clock/
PLL Gain Rx FEM partners) with a very open, flexible model.
SIM Block
CPLD PCIe
slot Level
shifter • Broad Choice of ODM partners
SGMII

• Demo’s of full radio designs (both HW and SW)

XFI1 XFI2 (RGMII)

10G
25G 10G 1G
PHY
PHY PHY PHY mmWave Array • Discrete FR1 3.5GHz
LA1235 Option • Yucca RFIC 2.5 to 5GHz
NXP Partner RF • Movandi and other FR2 solutions

Highlight all NXP parts with orange color RF T/R Block see next slide

COMPANY CONFIDENTIAL
 5G N78 8T8R OUTDOOR SMALL/MICROCELL
TARGET SPECIFICATION

Function Description DDR

Airfast

Yucca
IQ PA
5G NR SA R15, Field Upgradable
3GPP RAN Technology SFP/ Airfast
Optional: 5G NR SA, R16 SFP28 LA12xx LNA
PCIe
RF Ctrl
3GPP Frequency and Carrier 5G NR – n78 n78, 3300 -3800 MHz, C Band TDD PHY
Airfast
GPS Modem

Yucca
Configuration PA
80, 90,100 MHz carriers
IQ Airfast
To 256QAM, Active User Count to 100 users Timing LNA
Capacity LX2
~20 Gbps peak
L2+
8T8R MIMO
ARM
Antenna Array Airfast
GPP

Yucca
5W Per Channel IQ PA
Airfast
Timing IEEE1588 or GPS PCIe LA12xx LNA
RF Ctrl
PHY
10/25 GbE Airfast
Modem

Yucca
PA
Backhaul Configuration 3GPP split-2, 6 FAPI. Airfast
IQ
LNA
S1/X2 with IPSec support, IPv4, IPv6 optional
Outdoor deployment
Operating Environment
Ambient temp: -30C to +55C

NXP Component COMPANY CONFIDENTIAL

COMPANY CONFIDENTIAL
 5G N78 4T4R OUTDOOR SMALL CELL
TARGET SPECIFICATION

Function Description DDR

Airfast

Yucca
IQ PA
5G NR SA R15, Field Upgradable
3GPP RAN Technology SFP/ Airfast
Optional: 5G NR SA, R16 SFP28 LA12xx LNA
PCIe
RF Ctrl
3GPP Frequency and Carrier 5G NR – n78 n78, 3300 -3800 MHz, C Band TDD PHY
Airfast
GPS Modem

Yucca
Configuration PA
80, 90,100 MHz carriers
IQ Airfast
To 256QAM, Active User Count to 100 users Timing LNA
Capacity LS1
~20 Gbps peak
L2+
8T8R MIMO
ARM
Antenna Array
5W Per Channel GPP

Timing IEEE1588 or GPS

10, 10+10 GbE

Backhaul Configuration 3GPP split-2, 6 FAPI.

S1/X2 with IPSec support, IPv4, IPv6 optional

Outdoor deployment
Operating Environment
Ambient temp: -30C to +55C

NXP Component COMPANY CONFIDENTIAL

COMPANY CONFIDENTIAL
 5G N78 4T4R OUTDOOR SMALL/MICROCELL
TARGET SPECIFICATION

Function Description DDR

PA

Yucca
IQ
5G NR SA R15, Field Upgradable
3GPP RAN Technology SFP/
SFP28 LNA
Optional: 5G NR SA, R16 PCIe LA12xx
RF Ctrl
3GPP Frequency and Carrier 5G NR – n78 n78, 3300 -3800 MHz, C Band TDD PHY
GPS Modem PA

Yucca
Configuration 80, 90,100 MHz carriers
IQ LNA
To 256QAM, Active User Count to 100 users Timing
Capacity LS1
~20 Gbps peak
L2+
4T4R MIMO
ARM
Antenna Array
250mWW Per Channel GPP

Timing IEEE1588 or GPS

10, 10+10 GbE

Backhaul Configuration 3GPP split-2, 6 FAPI.

S1/X2 with IPSec support, IPv4, IPv6 optional

Indoor deployment
Operating Environment
Ambient temp: 0C to +55C

NXP Component COMPANY CONFIDENTIAL

COMPANY CONFIDENTIAL
 Integrated Small Cell (ISC): mmWave or sub 6GHz & IAB option
DDR (1GB)
100,
125MHz Clk Other
• mmWave, sub 6GHz or mix

DDR4
bus
Gen
Clk
clocks options
32bDDR4 100,

UART
UART
Conn. 160

RCW/
• 1x LA123X + Host + RF sub

Rst
CPLD MHz

Clk
UART JTAG From RF LO
JTAG I2C system for integrated small

JTAG
To RF LO Conn. conn.
conn.
eMMC eSDHC cell.
LO PLL
Temp I2C UART JTAG

SPI
DAC VCXO
Fan LS1043/
Modulator

ADC/
SFP

DAC
I2C
RTC I2C LS1026/ mmWave • Options for DFE support for
De-Modulator
LX2xxx

GPIO, 1588
... LS1046
higher power sub 6GHz 4T4R

in
Array
D
Modulator

ADC/ ADC/
10GbE Multicore

DAC DAC
10G PHY LA1200 De-Modulator
SerDes

(to DU) LA123x

GPIO
Arm

IRQ
Low-PHY, DFE
10GbE 10G PHY Or 1-2 Yucca
Modulator
• Optional second LA123x modem
(cascading) De-Modulator
sub 6GHz plus RF sub system for IAB
SerDes

SerDes
RGMII

1GbE RJ45
PHY Modulator configuration

ADC/
ADC/

DAC
(OAM) conn. UART GPIO DAC
modules
De-Modulator
Optional D
GPS

PPS
bus

PCIe
GenCascading DPD
3 x4
• Support for Movandi,

SerDes
RJ45
conn.
SMA LA1200 4T4T Anokiwave & SiversIMA
Low-PHY, DFE D mmWave solution
Optional
IAB with • Yucca 2T2R sub 6GHz
Module Q1 2021 – Agave
additional 1T1R discrete reference
modem module June 2020.

33 CONFIDENTIAL AND PROPRIETARY NXP Confidential and Proprietary

ISC/IAB Reference Design DDR DIMM
Optional
GPS Module Wi-Fi / BLE
PCIe M.2
Optional
PCIe g3 x8

Low-Speed LX2160
RF interfaces 2x 10GbE
LA123x 25GbE
IP traffic
Option to
Optional core
Second Network
“Inverness”
mmWave
Modem module
PCIe x4 to LX2

ISC & IAB L2+ Stacks

34
High-Speed
CONFIDENTIAL AND PROPRIETARY Sub 6GHz or
RF interfaces & power NXP Confidential and Proprietary
mmWave baseband
 CPE / FWA
EXAMPLE

35 CONFIDENTIAL AND PROPRIETARY

 5G mmWAVE CPE & Femto Cell
REFERENCE AND EXAMPLE

Function Description DDR

28/39GHz
IQ PA

Mod
5G NR NSA R15, SW Field Upgradable
3GPP RAN Technology RJ45/ 28/39GHz
SFP LS10xx
Capable to support 5G NR SA, R16 PCIe LA12xx PA
L2+ RF Ctrl
3GPP Frequency and 5G NR – FR2 TDD; single band operation ARM
PHY
28/39GHz

De-Mod
Modem
Carrier Configuration GPP LNA
400MHz (800MHz) OBW, 50/100/200/400 MHz carriers
IQ 28/39GHz
≤64QAM, 16…64 Active Users; can be increased subject to QoS LNA
Capacity GPS Timing
2.5Gbps (5Gbps)

WiFi Optional, enabled through plug-in board

2x2 MIMO (H/V), 16 elements, analog beamforming

Antenna Array
39dBm EIRP (Po, 1db) (tbc) – indoor use case

Power Supply ≤30W (tbc) wall wart or 802.3at/bt (tbc)

Timing IEEE1588

2.5 GbE (optional: 5/10GbE)

Backhaul Configuration
S1/X2 with IPSec support, IPv4, IPv6. 3GPP split-2 optional NXP Inverness Development Platform
Indoor deployment Femto (outdoor for CPE)
Operating Environment
36 Ambient temp: 0C to +55C
CONFIDENTIAL AND PROPRIETARY
COMPANY CONFIDENTIAL
 YUCCA
SUB-6GHZ
RFIC
37 CONFIDENTIAL AND PROPRIETARY
 • 5G: 2x2 I/Q Modulator-Demodulator for TDD
Yucca Transceiver 5GNR 2.5-5 GHz bands
• Multiple chips connected in parallel for 4x4, 8x8,
etc.
• High-Band: 4.2-5GHz for USA, China, &
Japan
• Mid-Band: 3.3-4.2GHz for Worldwide use
• Low-Band: 2.5-3.0GHz for China, Korea use
• TX EVM (160MHz)
• -6dBm: -1dBm → -36dB (typ) /-33dB (max)
• -70dBm: -6dBm → -43dB (typ) / -40dB (max)
• RX EVM (160MHz)
• <-40dB: -50dBm → -20dBm
• <-20dB: -70dBm → -12dBm
• <-10dB: -80dBm → -6dBm
• Selectable RF bandwidths: 20,25,30,40,…,100,
200 MHz
• 5th order Butterworth baseband filter
• LLCP: Lightweight LVDS Comm Protocol
⚫ Custom low noise digital interface minimizes radio
desense
⚫ High speed 640 Mbps data rate for fast
AGC/programming updates
⚫ Digital RF RSSI Detector to detect wideband
interference
64 pin QFN Package • Engineering samples Q1-2021; Production Q3-
Integrated Baluns
38 CONFIDENTIAL AND PROPRIETARY for $1-2 cost savings 2021
 SCHEDULE,
DEVELOPMENT &
ORDERING
39 CONFIDENTIAL AND PROPRIETARY
Silicon Status Update
NXP Device Function Availability Comments
Processor
LS1043 SoC Quad A53 10GbE
LS1046 SoC Quad A72 10GbE Production now
LX2160 SoC 16x A72 10/25 GbE
LA935x 2T2R Baseband 3x VSPA Sampling Volume Q3 ‘20
LA1200 Forward Error Correction Offload Polar, LDPC
In house bring up
LA1210 4T4R Baseband 8x VSPA
Volume Q4 ‘20
LA1220 FWA Baseband 8x VSPA, FECA Customer Samples
April ’20
LA1230 Integrated Small Cell Baseband 8x VSPA, FECA
LA1224-RDB “Bonnyrigg” Multi Function Development system Bring up now Customers Q2
Yucca Tri Band RFIC sub 6GHz Samples Q4 ‘20

All the elements are now ready

40 CONFIDENTIAL AND PROPRIETARY
for O-RAN solutions
NXP Confidential and Proprietary
5G Solution Ecosystem
• Ecosystem to develop
the complete solution
Chipset
NXP, FPGA, • Target parallel
RFIC, AFE
execution to ensure
fast time to market
Integration CU Software
• Specialists for each of
Partners NXP, Partners
the areas
− Companion chipsets
L1/L2 DU − Operating system
ODM Software
− DPDK, Virtualization,
Accelerators
− PDCP/Transport
− L1&L2
RU, RU
Acceleration − ODM hardware
ODM, OEM − Integration partners

41 CONFIDENTIAL AND PROPRIETARY

O-RAN Plugfest Demo
Hosted at CMCC in Beijing; CTC, CU, BT, DoCoMo, Orange, RJIO participating
• ArrayComm + Altran presented demo at a
live session over the Web as integrated test
thread #3
− E2E demo on LX2 RDB to a commercial UE
− CIG LX2160-based DU demonstrated a DL
driving RU to a Keysight TM500 UE
− Baicells FPGA accelerator card and CIG
integrated FPGA accelerator

• RU from multiple vendors connected

− Baicells
− CIG
− Vavitel

• Windriver presented the integration of

Docker platform with L1/L2 software on NXP
ARM platform

• NXP reported update of Layerscape Access

Edge and ecosystem development
42 CONFIDENTIAL AND PROPRIETARY
 NXP 5G Edge Access with
Low Latency Gaming Demo
S1

e-CPRI (option 7-2)

X2 S1

Redfinger Cloud Gaming Server

LTE Small Cell Based on NXP LX2160 ARM

NXP 5G
Features
Reference Design
Commercial 5G 5G NSA EPC
Standard 3GPP R.15
CIG DU System 5G Processing handset
with NXP LX2160 ARM BBU Platform CIG DU with LX2160 and
with > 500 Mbps Low Latency, FPGA acceleration
throughput Cloud Gaming Application
RRU platform 3rd party RRU (O-RAN)
Fronthaul Option 7-2 eCPRI
interface Option 8-1: CPRI
Frequency 3.5GHz
band
5G Radio Unit System Up to 100 MHz, multiple
bandwidth CCs
Modulation Up to 256QAM
Samsung S10 Beamforming digital and analog
5G Mobile beamforming
43 CONFIDENTIAL AND PROPRIETARY
 REFERENCE
BOARDS

44 CONFIDENTIAL AND PROPRIETARY

 Bonnyrigg Multifunction 5G Development Platform
Enclosure Dimensions in inches(15.394 x 10.236 x 1.75) inches
1U Dimensions requirement (in): 16.92in x 11.81in x 1.75in

• RU Development with sub 6GHz “Yucca” plug in cards – up to 4T4R

Low Speed antennas
slots for 2x 2T2R • DU Development via Integrated LX2 for ARM Neon L1-3, eCPRI
Plug in Yucca sub 6GHz
encapsulation and tightly coupled PCIe x8 lanes to LA1200 for FEC offload
modules

High Speed edge High Speed

interface for mmWave Ethernet for
transceiver/antenna network / eCPRI
45 CONFIDENTIAL AND PROPRIETARY
 “Bonnyrigg”LA1224-RDB Host GPP
LX2160 M.2 PCIe
Flexible Configuration options PCIe x8 Lane DDR4-SoDIMM 16 cores 2.0 GHz
GPS
Module
1) Distributed Unit
eSDHC
o LX2 + LA1200 FEC offload Flash

2) Radio Unit 2T2R ➔ 4T4R

o Sub 6GHz with plug-in RFIC
11ac
o mmWave with plug-in partner array
& BLE
M.2 PCIe
3) Integrated Small Cell 2T2R ➔ 4T4R
25
o Sub 6GHz with plug-in RFIC
Low GbE
o mmWave with plug-in partner array Speed RF
10
o multi-sector or IAB Small Cell Interfaces
GbE
o plug-in “Inverness” card

4) CPE / FWA USB

3.0
o Sub 6GHz with plug-in RFIC
Console
o mmWave with plug-in partner array mmWave Mgmt
Module RJ-45
5) 802.11ay / TIP or General VSPA Power
development LA1224 HS RF
o Via 60GHz mmWave RFIC plug-in Baseband I/O High Speed
Processor Points RF Interface ATX Power
o Marvell Wi-Fi 6 option via PCIe
46 CONFIDENTIAL AND PROPRIETARY Available to Access NXP
Agreement Customers
Confidential Starting April 2020
and Proprietary
 VSPA DEVELOPMENT
TOOLS

47 CONFIDENTIAL AND PROPRIETARY

CodeWarrior Development Studio for VSPA
A Complete Development Environment Under Eclipse

• Functional
•Configuration Wizards • Compiler & Linker
• Cycle Accurate
•Plug-In Architecture support for multi-
• VSPA ISS
•3rd party community core

• Multi-core Run/Stop of
Modeling Build targets simultaneously
• Access to all on-chip
• Extensive debug hooks - IDE Simulation
On-Chip Emulation, resources
TAP/Emulator Control, • One master project for
Performance Debug Multiple cores
Debug and Profiling Unit,
Trace Buffer Analysis • CW TAP and Ethernet TAP
• Trace / Code / Multi-Core • Trace Hardware
Performance Viewer, Trace
Debug
• Post-process trace data
using scripts
• Offline trace importer

For all stages of development

Pre-Silicon
Develop on Silicon Analyze & Tune
Development

48 CONFIDENTIAL AND PROPRIETARY

 Supported Kernel Library (I)
Function Name Notes Custom Digital UpConvertors TD-QEC, Mixers, Interpolation stages
(DUC)
Radix 2 DIF FFT/IFFT Sizes: 32, 64, 128, 256, 512, 1024, 2048, 4096 Custom Digital TD-QEC, Mixers, Decimation stages
Complex Precision: half-fixed, half-float, single DownConvertors (DDC)
Radix 2 DIT FFT/IFFT Sizes: 32, 64, 128, 256, 512, 1024, 2048, 4096 IQ Split Split IQ streams into I and Q streams
Complex Precision: half-fixed, half-float, single IQ Merge Merge I and Q streams to IQ stream
Mixed radix DFTs All 5G NR UL DFT sizes up to 3240
Overdrive and Level control Peak measurement and peak limiter
Bit-reversal Forward and backward direction bit-reversal for radix2 FFT
sizes Baseband Mixer
Digit-reversal Forward and backward direction digit-reversal for mixed radix
1D auto-correlator
DFT sizes
Half-subcarrier shifter For different FFT sizes 1D cross-correlator
Fractional rate change Dn3Up2, Dn5Up4, Dn8Up5, Up3Dn2, Up5Dn4, Up8Dn5 Gain and DC offset
filters application
Integer interpolation filters Rate: Up2, Up4, Up16, Up32 Sub-sample shift detector
Type of taps: Half-band real taps, non half-band real and
complex taps Complex gain detector Using reference waveform and method of least squares
Precision: half and single taps, half and single data Sub-sample shift filter
Uses pre-adder for symmetric real taps
Crest Factor Reduction
FIR Filter Type of taps: Half-band real taps, non half-band real and
complex taps Polynomial calculator and
Precision: half and single taps, half and single data accumulator
Uses pre-adder for symmetric real taps Digital PreDistortion
Integer decimation filters Rate: Dn2, Dn4, Dn8, Dn16 LLS Adapter Linear least squares based coefficients calculator for closed
Type of taps: Non half-band real and complex taps loop DPD
Precision: half and single taps, half and single data
Uses pre-adder for symmetric real taps RLS Adapter Recursive least squares based coefficients calculator for
closed loop DPD

49 CONFIDENTIAL AND PROPRIETARY

Supported Kernel Library (II)
Power meter Radar detector For WiFi
Histogram calculator Coarse Frequency error detector
CDF & PDF Calculator
Scalar times Vector Fine Frequency error tracker Using pilots
Vector times vector Element by element multiply of two equal length vectors
Vector times matrix Sample timing offset detector Using pilots
Matrix times matrix
Vector inner product Frequency offset corrector Compensators in time and frequency domains
Vector outer product
Matrix inversion Using Cholesky, or, QRD Sample timing offset corrector Compensators in time and frequency domains
Demodulator 4 or 8 bit LLR calculation for Types: BPSK, QPSK, 16QAM, 64QAM, 256QAM,
1024QAM, differential modulations
Tone rotation For WiFi
Modulator Modulation from bitstream for Types: BPSK, QPSK, 16QAM, 64QAM, 256QAM,
Arc tangent calculator For phase angle calculation
1024QAM, differential modulations
I/Q Imbalance estimator
Radio Demod Demodulator for FM, HD radio
SISO Channel estimator Frequency domain SISO least squares based channel estimator I/Q Imbalance compensator
MIMO Channel estimator Frequency domain MIMO least squares based channel estimator
Zero-forcing beamformer For sizes: 2x1, 2x2, 4x1, 4x2, 4x3, 4x4, 8x1, 8x2, 8x3, 8x4, 8x5, 8x6, 8x7, 8x8
Channel smoothing Frequency domain smoothing of channel coefficients calculator
Channel profile estimator Estimator for channel delay spread SSB Detection & Processing For 5G NR cell search

AGC Software based automatic gain control Phase Noise Estimator

STF detection Preamble detector for WiFi Phase Noise Compensator
LTF boundary detector Sample timing detector for WiFi
MRC Maximal ratio combiner and detector TD QEC Time domain I/Q imbalance correction
SISO Equalizer Computation of FD equalizer for SISO
FD QEC Frequency domain I/Q imbalance correction
MIMO Equalizer Computation of FD equalizer for MIMO-MMSE for sizes: 2x1, 2x2, 4x1, 4x2, 4x3, 4x4,
8x1, 8x2, 8x3, 8x4, 8x5, 8x6, 8x7, 8x8 Zadoff-Chu sequence generator For 3GPP PRACH, etc

Channel noise variance For SISO receivers

estimator PN sequence generators For 3GPP DMRS, etc
Channel noise covariance For MIMO receivers
matrix estimator Frequency domain cross-
correlator

50 CONFIDENTIAL AND PROPRIETARY

 ENGAGEMENT

51 CONFIDENTIAL AND PROPRIETARY

Access Agreement
Access Agreement Deliverables:
Description Pricing
per Application
Access NXP & Customer Secure Extranet Included
Collateral Device, SW, HW and ISM collateral Included
Training On-line and on premises training (optional) Included
Support 200Hrs Included
Development Hardware LA12XX Development Platform Included

Development RF Cards sub6GHz interface card, mmWave sold separately Included

Development SW Codewarrior IDE suite plus VSPA tools add-on Included

Library SW VSPA intrinsic library – source Included

Total

1. An executed Access Agreement is required for access to any and all of the above items.
2. Access Agreement are per application (ex: DU, Integrated Small Cell, RU). Multi-application discounts may be applied.
3. Additional source licensing or development services agreement to be negotiated separately.

52 CONFIDENTIAL AND PROPRIETARY

 BACK UP

53 CONFIDENTIAL AND PROPRIETARY

54 CONFIDENTIAL AND PROPRIETARY