PROJECT: Implementation of 16-to-1 multiplexer in

Verilog using Vivado 2018.2

TABLE OF CONTENTS
1. Introduction
2. Objectives
3. Design and implementation
-Verilog code for 16-to-1 multiplexer
4. Test bench code
-Test bench code
-Simulation procedure
5. Results
6. Conclusion

INTRODUCTION
A multiplexer often abbreviated as “mux”, is an electronic
device that selects one of the several input signals and
forwards the selected input into a single line. The primary
function of a multiplexer is to manage multiple data lines and
condense them into a single output line. This project involves
designing a 16-to-1multiplexer in Verilog and verifying its
functionality using Vivado 2018.2.

OBJECTIVES
- To design a 16-to-1multiplexer in Verilog.
- To create a test bench for verifying the functionality of the
demultiplexer.
- To simulate and analyse the results using Vivado 2018.2.
 DESIGN AND IMPLEMENTATION
The 1-to-16 demultiplexer has:
-One output data signal(dout)
-4-select lines which determines which input is selected as
output
-16 input data signals(din)
Only one of the sixteen input lines only one is selected as a
output using select lines.

VERILOG CODE FOR 16-TO-1 MULTIPLEXER

-File name-mux16to1 (mux16to1.v)
CODE
`timescale 1ns / 1ps
module mux16to1 (
input wire [15:0] data, // 16-bit input data
input wire [3:0] sel, // 4-bit selector
output wire out // Output
);

assign out = data[sel];

endmodule
TEST BENCH CODE
-File name: tb_mux16to1 (tb_mux16to1.v)
CODE
`timescale 1ns / 1ps
module tb_mux16to1;

reg [15:0] data; // 16-bit input data

reg [3:0] sel; // 4-bit selector
wire out; // Output

// Instantiate the multiplexer

mux16to1 uut (
.data(data),
.sel(sel),
.out(out)
);

initial begin
// Initialize inputs
data = 16'b1010101010101010;
sel = 4'b0000;
 // Apply test vectors
#10 sel = 4'b0000; // Select data[0]
#10 sel = 4'b0001; // Select data[1]
#10 sel = 4'b0010; // Select data[2]
#10 sel = 4'b0011; // Select data[3]
#10 sel = 4'b0100; // Select data[4]
#10 sel = 4'b0101; // Select data[5]
#10 sel = 4'b0110; // Select data[6]
#10 sel = 4'b0111; // Select data[7]
#10 sel = 4'b1000; // Select data[8]
#10 sel = 4'b1001; // Select data[9]
#10 sel = 4'b1010; // Select data[10]
#10 sel = 4'b1011; // Select data[11]
#10 sel = 4'b1100; // Select data[12]
#10 sel = 4'b1101; // Select data[13]
#10 sel = 4'b1110; // Select data[14]
#10 sel = 4'b1111; // Select data[15]

// Add more tests if needed

#10 $finish; // End simulation

end
initial begin
// Monitor signals
$monitor("At time %t, sel = %b, out = %b", $time, sel,
out);
end

endmodule

SIMULATION PROCEDEURE
1. Open Vivado 2018.2 and create a new project.
2. Add the mux_1to16.v and tb_mux_1to16.v files to the
project.
3. Set tb_mux_1to16 as the top module for simulation.
4. Run the simulation and observe the results in the waveform
viewer.

RESULT
The simulation output should show the dout signals being
correctly driven by the din input based on the values of the
select lines. Each input should be ‘1’ when selected and ‘0’
otherwise, verifying the correct operation of the 16-to-1
multiplexer.
 CONCLUSION
The 16-to-1multiplexer was successfully designed and
verified using Vivado 2018.2. The simulation results confirm
that the demultiplexer operates correctly, routing the input
signal to the appropriate output based on the select signal.