be_computer-engineering_semester-3_2022_november_digital-electronics-and-logic-design-deld-pattern-2019

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Total No. of Questions : 8] SEAT No.

8
23
PA-1237 [Total No. of Pages : 2

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[5925]-259

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S.E. (Computer Engineering)

2s
6:4
DIGITAL ELECTRONICS AND LOGIC DESIGN

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3:3
(2019 Pattern) (Semester - III) (210245)

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31
1/0 13
Time : 2½ Hours] [Max. Marks : 70
0
2/2
Instructions to the candidates:
.23 GP

1) Attempt Q1 or Q2, Q3 or Q4, Q5 or Q6, Q7 or Q8.


E

2) Neat diagrams must be drawn wherever necessary.


80

8
C

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3) Assume suitable data, if necessary.

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16

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8.2

2s
Q1) a) What are sequential circuits? Explain excitation table of JK flipflop. [6]
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6:4
b) Convert Following Flipflops: [6]
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49

3:3
i) SR to JK
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ii) JK to D
01
02

c) What is MOD counter? Design MOD - 24 counter using 7490. [6]


2/2
GP

OR
1/0
CE
80

Q2) a) What are sequential circuits? Explain SR flipflop using a suitable example.[6]

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23
.23

b) Convert Following Flipflops: [6]


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i) JK to T
8.2

2s

ii) SR to D
.24

6:4
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c) Design sequence detector using MS JK flipflop for sequence 1101. [6]


49

3:3
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31
01

Q3) a) Draw ASM chart for 2-bit UP counter using multiplexer controller method.[6]
02
2/2
GP

b) Draw a block diagram of the PLA device and explain. [6]


1/0

c) Implement following Boolean function using PAL. [5]


CE
80

F1 =  m ( 0,2,3,4,5,6,7,8,10,11,15 )
.23

F2 =  m (1,2,8,12,13)
16
8.2

OR
.24
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P.T.O.
Q4) a) What is an ASM Chart? Design the ASM chart for a 2-bit binary counter

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23
having one enable line E such that when: [6]

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E = 1 (count enabled) and

tat
E = 0 (counting is disabled).

2s
b) Implement 3 bit binary to gray code converter using PLA. [6]

6:4
c) A combinational Circuit is defined by the following function: [5]

02 91
3:3
F1( A,B,C ) =  m ( 0,1,3,7 )

0
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1/0 13
F2 ( A,B,C ) =  m (1,2,5,6 )
0
2/2
.23 GP

Implement this circuit with PLA.


E
80

8
Q5) a) Explain the operation of TTL NAND gate. [6]
C

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b) Compare TTL and CMOS families and also draw CMOS-NOR Gate.[6]

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16

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c) Define the following terms and mention the standard values for TTL
8.2

logic Family: [6]

2s
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6:4
i) Noise Margin
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ii) Power Dissipation


3:3
30

iii) Propagation Delay


31

OR
01
02
2/2

Q6) a) Explain TTL open collector. [6]


GP

b) Draw and explain the circuit diagram of the CMOS Inverter. [6]
1/0
CE

c) Draw two input standard TTL NAND gate circuit and explain their
80

8
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operation. [6]
.23

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16

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Q7) a) What is Microprocessor? Explain the system bus in brief. [6]
8.2

2s

b) Which are various functional units of microprocessors? Explain ALU in


.24

6:4

brief. [6]
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3:3

c) How Basic Arithmetic operations are performed using ALU IC 74181?[5]


30
31

OR
01
02

Q8) a) What is Microprocessor? Explain various operations of the


2/2

microprocessor. [6]
GP
1/0

b) Explain the Memory organization of the microprocessor. [6]


CE
80

c) Explain the 4-bit Multiplier circuit using ALU and shift registers in brief.[5]
.23
16


8.2
.24

[5925]-259
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