HASEE A420P e450

5 4 3 2 1
D
E450 D
Sandy Bridge Mobile PROCESSOR

With Cougar Point-M
C C
B
June 2010 B
Revision 0.2
HASEE TECHNOLOGY INC.,

A A
Cover Page
Draw by Size CAGE Code DWG NO Rev

LIZX B <Cage Code> 0.2
Thursday, May 22, 2014 Scale Model Sheet

E450 1 of 50
5 4 3 2 1
www.teknisi-indonesia.com
5 4 3 2 1
SO-DIMM0 CK505
D Sandy Bridge Page 10 D
Page 3-9 Dual channel DDR3

SO-DIMM1
Page 11
FDI DMI
CRT
Page 12
PCIE PORT1 WIFI
VGA DC RAILs
Page 25
LVDS & EDP LVDS
Cougar Point-M PCIE PORT2 3G
Page 13 SYSTEM CHARGER
HDA Page 26
Page 14-22 ISL6251
USB1.1/2.0 PCIE PORT0 10M/100M LAN
C HDA CODEC RJ45 C
Page 30
Page 41 SYSTEM VR
SATA 0(6G)
RT8205
SATA HDD
Page 42 CHIPSET/DDR2 VR
PORT8 SATA 2
USB JACK SATA ODD RT8202A
PORT9 SATA 1(6G)eSATA
SPI
USB JACK
LPC
PORT0
eSATA CPU & IGPU VR
PORT5
Card Reader SPI FLASH ISL95831
PORT10
BLUETOOTH
PORT4 KEYBOARD
PCIe EC +V1.8S
PORT2
PCIe Page 24 Touch Pad RT8284N
PORT3
B CAMERA B
Touch PORT11
Screen

A A
Block Diagram

B <Cage Code> 0.2

E450 2 of 50
5 4 3 2 1
5 4 3 2 1
U1A
J22 PEG_COMP
PEG_ICOMPI J21 DP Compensation Signals
B27 PEG_ICOMPO H22
16 DMI_TXN0 DMI_RX#[0] PEG_RCOMPO 4,6,13,20,21,24,32,36,48 +V1.05S_VCCP
B25
16 DMI_TXN1 DMI_RX#[1]
A25
16 DMI_TXN2 DMI_RX#[2] PEG_RXN[15:0]
B24 K33 PEG_RXN0
D 16 DMI_TXN3 DMI_RX#[3] PEG_RX#[0] M35 PEG_RXN1 D
B28 PEG_RX#[1] L34 PEG_RXN2 R7
16 DMI_TXP0 B26 DMI_RX[0] PEG_RX#[2] J35 PEG_RXN3
DMI_RX[1] PEG_RX#[3] 24.9/1%
16 DMI_TXP1
DMI
A24 J32 PEG_RXN4
16 DMI_TXP2 B23 DMI_RX[2] PEG_RX#[4] H34 PEG_RXN5
16 DMI_TXP3 DMI_RX[3] PEG_RX#[5] H31 PEG_RXN6
G21 PEG_RX#[6] G33 PEG_RXN7
16 DMI_RXN0 E22 DMI_TX#[0] PEG_RX#[7] G30 PEG_RXN8 PEG_COMP
16 DMI_RXN1 F21 DMI_TX#[1] PEG_RX#[8] F35 PEG_RXN9
16 DMI_RXN2 DMI_TX#[2] PEG_RX#[9]
D21 E34 PEG_RXN10
16 DMI_RXN3 DMI_TX#[3] PEG_RX#[10] E32 PEG_RXN11
G22 PEG_RX#[11] D33 PEG_RXN12
16 DMI_RXP0 DMI_TX[0] PEG_RX#[12]
D22 D31 PEG_RXN13
PCI EXPRESS* - GRAPHICS

F20 B33 PEG_RXN14
16 DMI_RXP2 C21 DMI_TX[2] PEG_RX#[14] C32 PEG_RXN15
PEG_RXP[15:0]
J33 PEG_RXP0
PEG_RX[0] L35 PEG_RXP1
PEG_RX[1] K34 PEG_RXP2
16 FDI_TXN[7:0] FDI_TXN0 A21 PEG_RX[2] H35 PEG_RXP3 PEG Compensation Signals
FDI_TXN1 H19 FDI0_TX#[0] PEG_RX[3] H32 PEG_RXP4
FDI_TXN2 E19 FDI0_TX#[1] PEG_RX[4] G34 PEG_RXP5 4,6,13,20,21,24,32,36,48 +V1.05S_VCCP
FDI_TXN3 F18 FDI0_TX#[2] PEG_RX[5] G31 PEG_RXP6
Intel(R) FDI
FDI_TXN4 B21 FDI0_TX#[3] PEG_RX[6] F33 PEG_RXP7
C FDI1_TX#[0] PEG_RX[7] C
FDI_TXN5 C20 F30 PEG_RXP8
FDI_TXN6 D18 FDI1_TX#[1] PEG_RX[8] E35 PEG_RXP9 R6
FDI_TXN7 E17 FDI1_TX#[2] PEG_RX[9] E33 PEG_RXP10
FDI1_TX#[3] PEG_RX[10] 24.9/1%
F32 PEG_RXP11
PEG_RX[11] D34 PEG_RXP12
16 FDI_TXP[7:0] FDI_TXP0 A22 PEG_RX[12] E31 PEG_RXP13
FDI_TXP1 G19 FDI0_TX[0] PEG_RX[13] C33 PEG_RXP14
FDI_TXP2 E20 FDI0_TX[1] PEG_RX[14] B32 PEG_RXP15 DP_COMP
FDI_TXP3 G18 FDI0_TX[2] PEG_RX[15]
FDI_TXP4 B20 FDI0_TX[3] M29 PEG_TXN0 PEG_TXN[15:0]
FDI_TXP5 C19 FDI1_TX[0] PEG_TX#[0] M32 PEG_TXN1
FDI_TXP6 D19 FDI1_TX[1] PEG_TX#[1] M31 PEG_TXN2
FDI_TXP7 F17 FDI1_TX[2] PEG_TX#[2] L32 PEG_TXN3
FDI1_TX[3] PEG_TX#[3] L29 PEG_TXN4
J18 PEG_TX#[4] K31 PEG_TXN5
16 FDI_FSYNC0 FDI0_FSYNC PEG_TX#[5]
J17 K28 PEG_TXN6
16 FDI_FSYNC1 FDI1_FSYNC PEG_TX#[6] J30 PEG_TXN7
H20 PEG_TX#[7] J28 PEG_TXN8
16 FDI_INT FDI_INT PEG_TX#[8] H29 PEG_TXN9
J19 PEG_TX#[9] G27 PEG_TXN10
16 FDI_LSYNC0 FDI0_LSYNC PEG_TX#[10]
H17 E29 PEG_TXN11
16 FDI_LSYNC1 FDI1_LSYNC PEG_TX#[11] F27 PEG_TXN12
PEG_TX#[12] D28 PEG_TXN13
PEG_TX#[13] F26 PEG_TXN14
B B
PEG_TX#[14] E25 PEG_TXN15
DP_COMP A18 PEG_TX#[15]
A17 eDP_COMPIO M28 PEG_TXP0 PEG_TXP[15:0]
B16 eDP_ICOMPO PEG_TX[0] M33 PEG_TXP1
13 -DP_HPD eDP_HPD PEG_TX[1] M30 PEG_TXP2
PEG_TX[2] L31 PEG_TXP3
C15 PEG_TX[3] L28 PEG_TXP4
13 DP_AUXP eDP_AUX PEG_TX[4]
D15 K30 PEG_TXP5
13 DP_AUXN eDP_AUX# PEG_TX[5]
eDP
K27 PEG_TXP6
PEG_TX[6] J29 PEG_TXP7
13 DP_TXP[1:0] DP_TXP0 C17 PEG_TX[7] J27 PEG_TXP8
DP_TXP1 F16 eDP_TX[0] PEG_TX[8] H28 PEG_TXP9
C16 eDP_TX[1] PEG_TX[9] G28 PEG_TXP10
G15 eDP_TX[2] PEG_TX[10] E28 PEG_TXP11
eDP_TX[3] PEG_TX[11] F28 PEG_TXP12
13 DP_TXN[1:0] DP_TXN0 C18 PEG_TX[12] D27 PEG_TXP13
DP_TXN1 E16 eDP_TX#[0] PEG_TX[13] E26 PEG_TXP14
D16 eDP_TX#[1] PEG_TX[14] D25 PEG_TXP15
F15 eDP_TX#[2] PEG_TX[15]
eDP_TX#[3]
Sandy Bridge_rPGA_Rev1p0 HASEE TECHNOLOGY INC.,

A A
SANDYBRIDGE 1/7

B <Cage Code> 0.2

E450 3 of 50
5 4 3 2 1
5 4 3 2 1
U1B
PU/PD for JTAG signals
DEL
3,6,13,20,21,24,32,36,48 +V1.05S_VCCP
A28 R17 0
CLK_EXP_P 15
MISC
CLOCKS
C26 BCLK A27 R18 0
19 -H_SNB_IVB PROC_SELECT# BCLK# CLK_EXP_N 15
DEL
D D
TP2 1 -TP_SKTOCC_R AN34 XDP_TMS R31 51
SKTOCC# A16 CLK_DP_P_R R19 0
DPLL_REF_CLK CLK_DP_P 15
this signal should have an exposed test point for easy debug access. A15 CLK_DP_N_R R20 0 XDP_TDI_R R32 51
DPLL_REF_CLK# CLK_DP_N 15
-XDP_PREQ R33 51/NC
-H_CATERR AL33
CATERR#
THERMAL
XDP_TCK R34 51
R8 0 H_PECI_ISO AN33 R8
19,24 H_PECI PECI SM_DRAMRST# -CPUDRAMRST 5 -XDP_TRST R35 51
DDR3
MISC
R0402
R9 56/1% -H_PROCHOT_D AL32 AK1 SM_RCOMP_0

24,38 -H_PROCHOT PROCHOT# SM_RCOMP[0] A5 SM_RCOMP_1
SM_RCOMP[1] A4 SM_RCOMP_2
SM_RCOMP[2]
R10 0 -H_THRMTRIP_R AN32
19 -H_THRMTRIP THERMTRIP#
R0402
AP29
PRDY# AP27 -XDP_PRDY 48
PREQ# -XDP_PREQ 48
AR26
TCK XDP_TCK 48
PWR MANAGEMENT
AR27
JTAG & BPM

TMS XDP_TMS 48
R11 0 H_PM_SYNC_R AM34 AP30
16 H_PM_SYNC PM_SYNC TRST# -XDP_TRST 48
C R0402 AR28 XDP_TDI_R R14 0 C
TDI XDP_TDI 48
AP26 XDP_TDO_R R15 0
R12 0 H_CPUPWRGD_R AP33 TDO XDP_TDO 48
19,48 H_CPUPWRGD UNCOREPWRGOOD
R0402
AL35 -H_DBR_R R16 0
PM_SYS_PWRGD_BUF R13 130 VDDPWRGOOD_R V8 DBR# -XDP_DBRESET 48
SM_DRAMPWROK
XDP_BPM[0:7] 48
R0402 AT28 XDP_BPM0_R R887 0 XDP_BPM0
BPM#[0] AR29 XDP_BPM1_R R888 0 XDP_BPM1
BPM#[1] AR30 XDP_BPM2_R R889 0 XDP_BPM2
-BUF_CPU_RST AR33 BPM#[2] AT30 XDP_BPM3_R R890 0 XDP_BPM3
RESET# BPM#[3] AP32 XDP_BPM4_R R891 0 XDP_BPM4
H_CPUPWRGD_R BPM#[4] AR31 XDP_BPM5_R R892 0 XDP_BPM5
BPM#[5] AT31 XDP_BPM6_R R893 0 XDP_BPM6
BPM#[6]
BPM#[7]
AR32 XDP_BPM7_R R894 0 XDP_BPM7 For platforms that do not implement the S3 Power Reduction circuitry:
R25-->No stuff R23--->Stuff
R26--->No stuff Q40--->No stuff Q65--->No stuff
R30
10k Sandy Bridge_rPGA_Rev1p0
R22 0/NC PM_SYS_PWRGD
34,37 +V1.5S_PWRGD
+V1.05S_VCCP 3,6,13,20,21,24,32,36,48
Buffered Reset to CPU
+V3.3A 10,11,12,13,14,15,16,17,18,19,20,21,23,24,25,26,31,32,33,37,38,41,44,46,48
+V3.3S 10,11,12,13,14,15,16,17,18,19,20,21,23,24,25,26,31,32,33,37,38,41,44,46,48
Ver02
R900 +V3.3A 14,15,16,18,19,21,24,25,26,28,30,33,34,37,44,46,48
75 R25 +V1.5S_CPU 7
B B
C278
200/NC
0.1UF C397
Q64 C0402
16 PM_DRAM_PWRGD
1
0.1UF R24
2 5 Q65 C0402 Q67 200
NC
18,48 -PLT_RST A VCC
1
3 4 BUFO_CPU_RST R899 43 -BUF_CPU_RST
GND Y PM_SYS_PWRGD 2 5 2 5
B
3 A VCC 4 3 A VCC 4 PM_SYS_PWRGD_BUF
GND Y GND Y
SN74LVC1G07DCKR R901 PM_SYS_PWRGD 就是 +V1.5S_CPU的PwrGd
sc70_5 0/NC
sc70_5 74ahc1g09/NC SN74LVC1G07DCKR/NC
R26
39/NC
CAD Note: Place pull up resistor within 2 inches of CPU R23 0
3
3,6,13,20,21,24,32,36,48 +V1.05S_VCCP
1
CLOSE TO CPU Q40

R126 1 2N7002/NC
32,33,34,37 -SLPS3_CONTROL
62
2
Processor Pullups DDR3 Compensation Signals
2
-H_PROCHOT
3,6,13,20,21,24,32,36,48 +V1.05S_VCCP SM_RCOMP_0

SM_RCOMP_1
SM_RCOMP_2
A
R160
49.9/1%/NC
R27 R28 R29
HASEE TECHNOLOGY INC., A
200/1%25.5/1%140/1%
SANDYBRIDGE 2/7
-H_CATERR

LIZX Custom <Cage Code> 0.2

E450 4 of 50
5 4 3 2 1
5 4 3 2 1
U1C U1D
AB6 AE2
10 M_A_DQ[63:0] SA_CLK[0] M_CLK_DDR0 10 11 M_B_DQ[63:0] SB_CLK[0] M_B_CLK_DDR0 11
AA6 AD2
M_A_DQ0 C5 SA_CLK#[0] V9 -M_CLK_DDR0 10 M_B_DQ0 C9 SB_CLK#[0] R9 -M_B_CLK_DDR0 11
M_A_DQ1 D5 SA_DQ[0] SA_CKE[0] M_CKE0 10 M_B_DQ1 A7 SB_DQ[0] SB_CKE[0] M_B_CKE0 11
D M_A_DQ2 D3 SA_DQ[1] M_B_DQ2 D10 SB_DQ[1] D
M_A_DQ3 D2 SA_DQ[2] M_B_DQ3 C8 SB_DQ[2]
M_A_DQ4 D6 SA_DQ[3] AA5 M_B_DQ4 A9 SB_DQ[3] AE1
M_A_DQ5 C6 SA_DQ[4] SA_CLK[1] AB5 M_CLK_DDR1 10 M_B_DQ5 A8 SB_DQ[4] SB_CLK[1] AD1 M_B_CLK_DDR1 11
M_A_DQ6 C2 SA_DQ[5] SA_CLK#[1] V10 -M_CLK_DDR1 10 M_B_DQ6 D9 SB_DQ[5] SB_CLK#[1] R10 -M_B_CLK_DDR1 11
M_A_DQ7 C3 SA_DQ[6] SA_CKE[1] M_CKE1 10 M_B_DQ7 D8 SB_DQ[6] SB_CKE[1] M_B_CKE1 11
M_A_DQ8 F10 SA_DQ[7] M_B_DQ8 G4 SB_DQ[7]
M_A_DQ9 F8 SA_DQ[8] M_B_DQ9 F4 SB_DQ[8]
M_A_DQ10 G10 SA_DQ[9] AB4 M_B_DQ10 F1 SB_DQ[9] AB2
M_A_DQ11 G9 SA_DQ[10] RSVD_TP[1] AA4 M_B_DQ11 G1 SB_DQ[10] RSVD_TP[11] AA2
M_A_DQ12 F9 SA_DQ[11] RSVD_TP[2] W9 M_B_DQ12 G5 SB_DQ[11] RSVD_TP[12] T9
M_A_DQ13 F7 SA_DQ[12] RSVD_TP[3] M_B_DQ13 F5 SB_DQ[12] RSVD_TP[13]
M_A_DQ14 G8 SA_DQ[13] M_B_DQ14 F2 SB_DQ[13]
M_A_DQ15 G7 SA_DQ[14] M_B_DQ15 G2 SB_DQ[14]
M_A_DQ16 K4 SA_DQ[15] AB3 M_B_DQ16 J7 SB_DQ[15] AA1
M_A_DQ17 K5 SA_DQ[16] RSVD_TP[4] AA3 M_B_DQ17 J8 SB_DQ[16] RSVD_TP[14] AB1
M_A_DQ18 K1 SA_DQ[17] RSVD_TP[5] W10 M_B_DQ18 K10 SB_DQ[17] RSVD_TP[15] T10
M_A_DQ19 J1 SA_DQ[18] RSVD_TP[6] M_B_DQ19 K9 SB_DQ[18] RSVD_TP[16]
M_A_DQ20 J5 SA_DQ[19] M_B_DQ20 J9 SB_DQ[19]
M_A_DQ21 J4 SA_DQ[20] M_B_DQ21 J10 SB_DQ[20]
M_A_DQ22 J2 SA_DQ[21] AK3 M_B_DQ22 K8 SB_DQ[21] AD3
M_A_DQ23 K2 SA_DQ[22] SA_CS#[0] AL3 -M_CS0 10 M_B_DQ23 K7 SB_DQ[22] SB_CS#[0] AE3 -M_B_CS0 11
M_A_DQ24 M8 SA_DQ[23] SA_CS#[1] AG1 -M_CS1 10 M_B_DQ24 M5 SB_DQ[23] SB_CS#[1] AD6 -M_B_CS1 11
M_A_DQ25 N10 SA_DQ[24] RSVD_TP[7] AH1 M_B_DQ25 N4 SB_DQ[24] RSVD_TP[17] AE6
M_A_DQ26 N8 SA_DQ[25] RSVD_TP[8] M_B_DQ26 N2 SB_DQ[25] RSVD_TP[18]
M_A_DQ27 N7 SA_DQ[26] M_B_DQ27 N1 SB_DQ[26]
M_A_DQ28 M10 SA_DQ[27] M_B_DQ28 M4 SB_DQ[27]
M_A_DQ29 M9 SA_DQ[28] AH3 M_B_DQ29 N5 SB_DQ[28] AE4
SA_DQ[29] SA_ODT[0] SB_DQ[29] SB_ODT[0]
DDR SYSTEM MEMORY B

M_A_DQ30 N9 AG3 M_ODT0 10 M_B_DQ30 M2 AD4 M_B_ODT0 11
DDR SYSTEM MEMORY A

M_A_DQ31 M7 SA_DQ[30] SA_ODT[1] AG2 M_ODT1 10 M_B_DQ31 M1 SB_DQ[30] SB_ODT[1] AD5 M_B_ODT1 11
M_A_DQ32 AG6 SA_DQ[31] RSVD_TP[9] AH2 M_B_DQ32 AM5 SB_DQ[31] RSVD_TP[19] AE5
M_A_DQ33 AG5 SA_DQ[32] RSVD_TP[10] M_B_DQ33 AM6 SB_DQ[32] RSVD_TP[20]
C M_A_DQ34 AK6 SA_DQ[33] M_B_DQ34 AR3 SB_DQ[33] C
M_A_DQ35 AK5 SA_DQ[34] M_B_DQ35 AP3 SB_DQ[34]
SA_DQ[35] -M_A_DQS[7:0] 10 SB_DQ[35] -M_B_DQS[7:0] 11
M_A_DQ36 AH5 M_B_DQ36 AN3
M_A_DQ37 AH6 SA_DQ[36] C4 -M_A_DQS0 M_B_DQ37 AN2 SB_DQ[36] D7 -M_B_DQS0
M_A_DQ38 AJ5 SA_DQ[37] SA_DQS#[0] G6 -M_A_DQS1 M_B_DQ38 AN1 SB_DQ[37] SB_DQS#[0] F3 -M_B_DQS1
M_A_DQ39 AJ6 SA_DQ[38] SA_DQS#[1] J3 -M_A_DQS2 M_B_DQ39 AP2 SB_DQ[38] SB_DQS#[1] K6 -M_B_DQS2
M_A_DQ40 AJ8 SA_DQ[39] SA_DQS#[2] M6 -M_A_DQS3 M_B_DQ40 AP5 SB_DQ[39] SB_DQS#[2] N3 -M_B_DQS3
M_A_DQ41 AK8 SA_DQ[40] SA_DQS#[3] AL6 -M_A_DQS4 M_B_DQ41 AN9 SB_DQ[40] SB_DQS#[3] AN5 -M_B_DQS4
M_A_DQ42 AJ9 SA_DQ[41] SA_DQS#[4] AM8 -M_A_DQS5 M_B_DQ42 AT5 SB_DQ[41] SB_DQS#[4] AP9 -M_B_DQS5
M_A_DQ43 AK9 SA_DQ[42] SA_DQS#[5] AR12 -M_A_DQS6 M_B_DQ43 AT6 SB_DQ[42] SB_DQS#[5] AK12 -M_B_DQS6
M_A_DQ44 AH8 SA_DQ[43] SA_DQS#[6] AM15 -M_A_DQS7 M_B_DQ44 AP6 SB_DQ[43] SB_DQS#[6] AP15 -M_B_DQS7
M_A_DQ45 AH9 SA_DQ[44] SA_DQS#[7] M_B_DQ45 AN8 SB_DQ[44] SB_DQS#[7]
M_A_DQ46 AL9 SA_DQ[45] M_B_DQ46 AR6 SB_DQ[45]
SA_DQ[47] M_A_DQS[7:0] 10 SB_DQ[47] M_B_DQS[7:0] 11
M_A_DQ48 AP11 M_B_DQ48 AR9
M_A_DQ49 AN11 SA_DQ[48] D4 M_A_DQS0 M_B_DQ49 AJ11 SB_DQ[48] C7 M_B_DQS0
M_A_DQ50 AL12 SA_DQ[49] SA_DQS[0] F6 M_A_DQS1 M_B_DQ50 AT8 SB_DQ[49] SB_DQS[0] G3 M_B_DQS1
M_A_DQ51 AM12 SA_DQ[50] SA_DQS[1] K3 M_A_DQS2 M_B_DQ51 AT9 SB_DQ[50] SB_DQS[1] J6 M_B_DQS2
M_A_DQ52 AM11 SA_DQ[51] SA_DQS[2] N6 M_A_DQS3 M_B_DQ52 AH11 SB_DQ[51] SB_DQS[2] M3 M_B_DQS3
M_A_DQ53 AL11 SA_DQ[52] SA_DQS[3] AL5 M_A_DQS4 M_B_DQ53 AR8 SB_DQ[52] SB_DQS[3] AN6 M_B_DQS4
M_A_DQ54 AP12 SA_DQ[53] SA_DQS[4] AM9 M_A_DQS5 M_B_DQ54 AJ12 SB_DQ[53] SB_DQS[4] AP8 M_B_DQS5
M_A_DQ55 AN12 SA_DQ[54] SA_DQS[5] AR11 M_A_DQS6 M_B_DQ55 AH12 SB_DQ[54] SB_DQS[5] AK11 M_B_DQS6
M_A_DQ56 AJ14 SA_DQ[55] SA_DQS[6] AM14 M_A_DQS7 M_B_DQ56 AT11 SB_DQ[55] SB_DQS[6] AP14 M_B_DQS7
M_A_DQ57 AH14 SA_DQ[56] SA_DQS[7] M_B_DQ57 AN14 SB_DQ[56] SB_DQS[7]
M_A_DQ59 AK15 SA_DQ[58] M_B_DQ59 AT14 SB_DQ[58]
M_A_DQ60 AL14 SA_DQ[59] M_A_A[15:0] 10 M_B_DQ60 AT12 SB_DQ[59] M_B_A[15:0] 11
M_A_DQ61 AK14 SA_DQ[60] AD10 M_A_A0 M_B_DQ61 AN15 SB_DQ[60] AA8 M_B_A0
M_A_DQ62 AJ15 SA_DQ[61] SA_MA[0] W1 M_A_A1 M_B_DQ62 AR15 SB_DQ[61] SB_MA[0] T7 M_B_A1
M_A_DQ63 AH15 SA_DQ[62] SA_MA[1] W2 M_A_A2 M_B_DQ63 AT15 SB_DQ[62] SB_MA[1] R7 M_B_A2
SA_DQ[63] SA_MA[2] W7 M_A_A3 SB_DQ[63] SB_MA[2] T6 M_B_A3
SA_MA[3] V3 M_A_A4 SB_MA[3] T2 M_B_A4
B SA_MA[4] V2 M_A_A5 SB_MA[4] T4 M_B_A5 B
SA_MA[5] W3 M_A_A6 SB_MA[5] T3 M_B_A6
AE10 SA_MA[6] W6 M_A_A7 AA9 SB_MA[6] R2 M_B_A7
10 M_A_BS0 AF10 SA_BS[0] SA_MA[7] V1 M_A_A8 11 M_B_BS0 AA7 SB_BS[0] SB_MA[7] T5 M_B_A8
10 M_A_BS1 V6 SA_BS[1] SA_MA[8] W5 M_A_A9 11 M_B_BS1 R6 SB_BS[1] SB_MA[8] R3 M_B_A9
10 M_A_BS2 SA_BS[2] SA_MA[9] AD8 M_A_A10 11 M_B_BS2 SB_BS[2] SB_MA[9] AB7 M_B_A10
SA_MA[10] V4 M_A_A11 SB_MA[10] R1 M_B_A11
SA_MA[11] W4 M_A_A12 SB_MA[11] T1 M_B_A12
AE8 SA_MA[12] AF8 M_A_A13 AA10 SB_MA[12] AB10 M_B_A13
10 -M_A_CAS AD9 SA_CAS# SA_MA[13] V5 M_A_A14 11 -M_B_CAS AB8 SB_CAS# SB_MA[13] R5 M_B_A14
10 -M_A_RAS AF9 SA_RAS# SA_MA[14] V7 M_A_A15 11 -M_B_RAS AB9 SB_RAS# SB_MA[14] R4 M_B_A15
10 -M_A_WE SA_WE# SA_MA[15] 11 -M_B_WE SB_WE# SB_MA[15]
+V1.5 7,10,11,34
Sandy Bridge_rPGA_Rev1p0 Sandy Bridge_rPGA_Rev1p0
R36 R41 0
15 DRAMRST_CNTRL_PCH DRAMRST_CNTRL
1K
R0402
R37 0/NC
Q2 R0402
2N7002
R38 1K -DDR3_DRAMRST_R 3 2 -CPUDRAMRST_R R39 0 -CPUDRAMRST

10,11 -DDR3_DRAMRST -CPUDRAMRST 4
R0402 R0402
A A
1

DRAMRST_CNTRL
R40
C6
4.99k/1%
SANDYBRIDGE 3/7
68nF
Custom <Cage Code> 0.2
5K OR 100K
5 www.teknisi-indonesia.com
4 3
Thursday, May 22, 2014
2
Scale Model
E450
1
Sheet
5 of 50
5 4 3 2 1
U1F POWER
+V1.05S_VCCP_R 3,4,13,20,21,24,32,36,48 +V1.05S_VCCP
+VCC_CORE
MB Bottom Socket Cavity:10 x 22 μF

R905 2m_1%
AG35
VCC1
AG34
VCC2 VCCIO1
AH13 C34 C35 C36 C37 C38 C39 C40 C41 C42 C43
PJP29 共LAY
AG33 AH10
AG32 VCC3 VCCIO2 AG10 22U 22U 22U 22U 22U 22U/NC 22U/NC 22U/NC 22U/NC 22U/NC 1 2
AG31 VCC4 VCCIO3 AC10 C0805 C0805 C0805 C0805 C0805 C0805 C0805 C0805 C0805 C0805
AG30 VCC5 VCCIO4 Y10
D D
+VCC_CORE AG29 VCC6 VCCIO5 U10
AG28 VCC7 VCCIO6 P10
AG27 VCC8 VCCIO7 L10
VCC9 VCCIO8
AG26
VCC10 VCCIO9
J14 MB Top Socket Cavity:9 x 22 μF VCCIO at CPU:2 x 330 μF
AF35 J13
AF34 VCC11 VCCIO10 J12
AF33 VCC12 VCCIO11 J11 PC52
VCC13 VCCIO12
1
AF32 H14 C46 C47 C48 C49 C50 C51 C52 C53 C54
AF31 VCC14 VCCIO13 H12
AF30 VCC15 VCCIO14 H11 22U 22U 22U 22U 22U 22U 22U 22U/NC 22U/NC
2
C63 C64 C65 C66 C67 AF29 VCC16 VCCIO15 G14 C0805 C0805 C0805 C0805 C0805 C0805 C0805 C0805 C0805 330uF/2.5V
AF28 VCC17 VCCIO16 G13
PEG AND DDR

10U 10U 10U 10U 10U AF27 VCC18 VCCIO17 G12
C0805 C0805 C0805 C0805 C0805 AF26 VCC19 VCCIO18 F14
AD35 VCC20 VCCIO19 F13
AD32 VCC23 VCCIO22 E14
AD31 VCC24 VCCIO23 E12 3,4,13,20,21,24,32,36,48 +V1.05S_VCCP
C68 C69 C70 C71 C72 AD30 VCC25 VCCIO24
AD29 VCC26 E11
10U 10U 10U 10U 10U AD28 VCC27 VCCIO25 D14
C0805 C0805 C0805 C0805 C0805 AD27 VCC28 VCCIO26 D13
VCC29 VCCIO27 R48 closed
AD26
AC35 VCC30 VCCIO28
D12
D11
to IMVP
VCC31 VCCIO29 54.9/1%
AC34 C14
AC33 VCC32 VCCIO30 C13 H_CPU_SVIDCLK R49 0
AC32 VCC33 VCCIO31 C12 VR_SVID_CLK 38
AC31 VCC34 VCCIO32 C11
AC30 VCC35 VCCIO33 B14
AC29 VCC36 VCCIO34 B12 3,4,13,20,21,24,32,36,48 +V1.05S_VCCP
AC28 VCC37 VCCIO35 A14
AC27 VCC38 VCCIO36 A13
VCC39 VCCIO37 3,4,13,20,21,24,32,36,48 +V1.05S_VCCP
C
AC26
AA35 VCC40 VCCIO38
A12
A11
closed to ? C
AA34 VCC41 VCCIO39 R50
AA33 VCC42 J23 R43 0
VCC43 VCCIO40 75/1%
C73 C74 C75 C76 C77 C78 C79 C80 AA32
AA31 VCC44 R0402 -H_CPU_SVIDALRT R51 43/1% -H_CPU_SVIDALRT_R R52 0
VCC45 -VR_SVID_ALERT 38
22U
C0805
22U
C0805
22U
C0805
22U
C0805
22U
C0805
22U
C0805
22U
C0805
22U
C0805
AA30
AA29 VCC46 电流多少？？
AA28 VCC47 电阻的库要对应
AA27 VCC48
AA26 VCC49 3,4,13,20,21,24,32,36,48 +V1.05S_VCCP 3,4,13,20,21,24,32,36,48 +V1.05S_VCCP
CORE SUPPLY
Y35 VCC50
Y34 VCC51
Y33 VCC52
VCC53
C81 C82 C83 C84 C85 C86 C87 C88 Y32
VCC54 closed to IMVP
22U 22U 22U 22U 22U 22U 22U 22U
Y31
Y30 VCC55 closed to cpu R53 R55
VCC56 130/1% 130/1%
C0805 C0805 C0805 C0805 C0805 C0805 C0805 C0805 Y29
Y28 VCC57 H_CPU_SVIDDAT R54 0
VCC58 VR_SVID_DATA 38
Y27
Y26 VCC59
V35 VCC60
SVID
VCC61
V34
V33 VCC62 VIDALERT#
AJ29
AJ30
-H_CPU_SVIDALRT
H_CPU_SVIDCLK
Layout Refer to the DG
V32 VCC63
VCC64
VIDSCLK
VIDSOUT
AJ28 H_CPU_SVIDDAT Important!!!(25M速率的信号)
V31
V30 VCC65
V29 VCC66
V28 VCC67
V27 VCC68
V26 VCC69
U35 VCC70
U34 VCC71
U33 VCC72
U32 VCC73
U31 VCC74
B B
U30 VCC75
U29 VCC76
U28 VCC77
U27 VCC78 +VCC_CORE
U26 VCC79
PC55 PC60 PC59 PC64 R35 VCC80
VCC81
1
R34
R33 VCC82
R32 VCC83 R46
2
330uF/2.5V 330uF/2.5V 330uF/2.5V/NC330uF/2.5V/NC R31 VCC84

VCC85 100
R30
R29 VCC86
SENSE LINES
R28 VCC87
R27 VCC88 AJ35 VCC_SENSE_R R44 0
R26 VCC89 VCC_SENSE AJ34 VSS_SENSE_R R45 0 VCCSENSE 38
P35 VCC90 VSS_SENSE VSSSENSE 38
P34 VCC91
P33 VCC92 R47
P32 VCC93 B10
VCC94 VCCIO_SENSE 100
P31 A10 VCCP_SENSE 36
P30 VCC95 VSSIO_SENSE VSSP_SENSE 36
P29 VCC96
P28 VCC97
P27 VCC98
P26 VCC99
VCC100
Sandy Bridge_rPGA_Rev1p0
A A

SANDYBRIDGE 4/7

E450 6 of 50
5 4 3 2 1
5 4 3 2 1
+V1.5 5,10,11,34
5,10,11,34 +V1.5
+V1.5S_CPU 4
PQ45
R99 2N7002/NC PJP28
1 2
10K/1% 3 2 +V_SM_VREF_CNT
+V_SM_VREF
R0402 Q22
+VCC_GFXCORE
PJP30
+VGFX_CORE
POWER +V_SM_VREF R57
100k 8
IRF8707TRPBF/NC
3
1
U1G 7 2
1 2 R100 6 1
D D
C170 5
SENSE
LINES
R563 2m_1% AT24 AK35 10K/1%
AT23 VAXG1 VAXG_SENSE AK34 VCCGT_SENSE 38 R0402 0.1uF
4
AT21 VAXG2 VSSAXG_SENSE VSSGT_SENSE 38 C0402
C89 C90 C91 C92 C93 C94 C95 C96 AT20 VAXG3 R59 0
AT18 VAXG4
22U 22U 22U 22U 22U 22U 22U 22U AT17 VAXG5
C0805 C0805 C0805 C0805 C0805 C0805 C0805 C0805 AR24 VAXG6
AR23 VAXG7 R58 0/NC
VAXG8 33,34 -S3_CONTROL
AR21
AR20 VAXG9
VREF
AR18 VAXG10 C120
AR17 VAXG11
AP24 VAXG12 AL1 +V_SM_VREF_CNT 470p/NC
AP23 VAXG13 SM_VREF C0402
C97 C98 C99 C100 C101 C102 AP21 VAXG14
AP20 VAXG15
22U 22U 22U 22U 22U/NC 22U/NC AP18 VAXG16
C0805 C0805 C0805 C0805 C0805 C0805 AP17 VAXG17
AN24 VAXG18
VAXG19 +V1.5S_CPU 4
AN23 +V1.5S_VCCDDQ
AN21 VAXG20
VAXG21 PJP31
AN20
VAXG22
DDR3 -1.5V RAILS

AN18 1 2 +V1.5 5,10,11,34
AN17 VAXG23
GRAPHICS
PC63 AM24 VAXG24 AF7 R565 2m_1%
VAXG25 VDDQ1
1
AM23 AF4 +V1.5S_VCCDDQ

AM21 VAXG26 VDDQ2 AF1 PC58
VAXG27 VDDQ3
1
AM20 AC7 C108 C109 C110 C111 C112 C113
2
330uF/2.5V AM18 VAXG28 VDDQ4 AC4

C C
AM17 VAXG29 VDDQ5 AC1 10U 10U 10U 10U 10U 10U C114 C115 C123 C124
2
AL24 VAXG30 VDDQ6 Y7 330uF/2.5VC0603 C0603 C0603 C0603 C0603 C0603
AL23 VAXG31 VDDQ7 Y4 0.1U 0.1U 0.1U 0.1U
AL21 VAXG32 VDDQ8 Y1 C0402 C0402 C0402 C0402
AL20 VAXG33 VDDQ9 U7
AK24 VAXG36 VDDQ12 P7
AK20 VAXG39 VDDQ15
AK18 VAXG40
AK17 VAXG41
AJ24 VAXG42
AJ23 VAXG43
AJ21 VAXG44
AJ20 VAXG45 +V0.85S_VCCUSA 32,37 +V0.85S
AJ18 VAXG46
VAXG47 PJP32
AJ17
AH24 VAXG48 1 2
SA RAIL
AH23 VAXG49
AH21 VAXG50 M27 R566 2m_1%
AH20 VAXG51 VCCSA1 M26
AH18 VAXG52 VCCSA2 L26 MAX 6A
AH17 VAXG53 VCCSA3 J26 C116 C117 C118 C119
VAXG54 VCCSA4 J25
VCCSA5 J24 10U/NC 10U 10U 10U
VCCSA6 H26 C0603 C0603 C0603 C0603
VCCSA7 H25
B
20,34 +V1.8S +V1.8S_VCCSFR VCCSA8 B
1.8V RAIL
1.2A MAX
R564 0 B6 H23
MISC
A6 VCCPLL1 VCCSA_SENSE VCCUSA_SENSE 37
PC57 A2 VCCPLL2
VCCPLL3
1
C105 C106 C107 R56

C22 H_FC_C22 0/NC
10U 1UF 1UF FC_C22 C24
2
C0603 C0402 C0402 330uF/2.5V VCCSA_VID1 VCCSA_SEL 37
VCCSA_VID1:
H_FC_C22 For Huron River platforms,
this pin must have a pull
down resistor to ground
R61
10k
VCCSA_SEL
A
R805
10K
SANDYBRIDGE 5/7


E450 7 of 50
5 4 3 2 1
5 4 3 2 1
U1I
U1H
D D
AT35 AJ22
AT32 VSS1 VSS81 AJ19 T35 F22
AT29 VSS2 VSS82 AJ16 T34 VSS161 VSS234 F19
AT27 VSS3 VSS83 AJ13 T33 VSS162 VSS235 E30
AT7 VSS10 VSS90 AH35 T26 VSS169 VSS242 E10
AT4 VSS11 VSS91 AH34 P9 VSS170 VSS243 E9
AT3 VSS12 VSS92 AH32 P8 VSS171 VSS244 E8
AR25 VSS13 VSS93 AH30 P6 VSS172 VSS245 E7
AR13 VSS17 VSS97 AH25 N35 VSS176 VSS249 E3
AR4 VSS20 VSS100 AH16 N32 VSS179 VSS252 D35
AR2 VSS21 VSS101 AH7 N31 VSS180 VSS253 D32
AP34 VSS22 VSS102 AH4 N30 VSS181 VSS254 D29
AP31 VSS23 VSS103 AG9 N29 VSS182 VSS255 D26
AP22 VSS26 VSS106 AF6 N26 VSS185 VSS258 C34
AP19 VSS27 VSS107 AF5 M34 VSS186 VSS259 C31
AP16 VSS28 VSS108 AF3 L33 VSS187 VSS260 C28
AP13 VSS29 VSS109 AF2 L30 VSS188 VSS261 C27
C C
AP10 VSS30 VSS110 AE35 L27 VSS189 VSS262 C25
AN30 VSS34 VSS114 AE31 L5 VSS193 VSS266 B22
VSS35 VSS115 VSS194 VSS267
VSS
AN27 AE30 L4 B19
VSS36 VSS116 VSS195 VSS268
VSS
AN25 AE29 L3 B17
AN16 VSS39 VSS119 AE26 K35 VSS198 VSS271 B11
AN13 VSS40 VSS120 AE9 K32 VSS199 VSS272 B9
AN10 VSS41 VSS121 AD7 K29 VSS200 VSS273 B8
AN7 VSS42 VSS122 AC9 K26 VSS201 VSS274 B7
AN4 VSS43 VSS123 AC8 J34 VSS202 VSS275 B5
AM29 VSS44 VSS124 AC6 J31 VSS203 VSS276 B3
AM25 VSS45 VSS125 AC5 H33 VSS204 VSS277 B2
AM22 VSS46 VSS126 AC3 H30 VSS205 VSS278 A35
AM19 VSS47 VSS127 AC2 H27 VSS206 VSS279 A32
AM16 VSS48 VSS128 AB35 H24 VSS207 VSS280 A29
AM3 VSS53 VSS133 AB30 H10 VSS212 VSS285
AM2 VSS54 VSS134 AB29 H9 VSS213
AM1 VSS55 VSS135 AB28 H8 VSS214
AL34 VSS56 VSS136 AB27 H7 VSS215
AL31 VSS57 VSS137 AB26 H6 VSS216
AL28 VSS58 VSS138 Y9 H5 VSS217
B
AL25 VSS59 VSS139 Y8 H4 VSS218 B
AL13 VSS63 VSS143 Y2 G35 VSS222
AL10 VSS64 VSS144 W35 G32 VSS223
AK33 VSS68 VSS148 W31 G20 VSS227
AK25 VSS71 VSS151 W28 F34 VSS230
AK16 VSS74 VSS154 U9 VSS233
AK13 VSS75 VSS155 U8
AK10 VSS76 VSS156 U6
AK7 VSS77 VSS157 U5
AK4 VSS78 VSS158 U3
AJ25 VSS79 VSS159 U2
VSS80 VSS160
A
SANDYBRIDGE 6/7


E450 8 of 50
5 4 3 2 1
5 4 3 2 1
U1E CFG2
L7
RSVD28 AG7
CFG0 AK28 RSVD29 AE7 R63 CFG6
48 CFG0 CFG[0] RSVD30
CFG1 AK29 AK2 1k/NC
CFG2 AL26 CFG[1] RSVD31 W8
D CFG3 AL27 CFG[2] RSVD32 CFG5 D
CFG4 AK26 CFG[3]
CFG5 AL29 CFG[4] AT26
CFG6 AL30 CFG[5] RSVD33 AM33
CFG7 AM31 CFG[6] RSVD34 AJ27
CFG[7] RSVD35
CFG8 AM32
CFG[8] PEG Static Lane Reversal - CFG2 is for the 16x R64 R67
CFG9 AM30 1k/NC 1k/NC
CFG10 AM28 CFG[9]
CFG[10]
CFG11 AM26
CFG[11] 1:(Default) Normal Operation; Lane # definition
CFG12 AN28
CFG[12] CFG2 matches socket pin map definition
R164 CFG13 AN31 T8
CFG14 AN26 CFG[13] RSVD37 J16 0:Lane Reversed
1K/NC CFG[14] RSVD38
CFG15 AM27 H16
CFG16 AK31 CFG[15] RSVD39 G16
CFG17 AN29 CFG[16] RSVD40
CFG[17]
PCIE Port Bifurcation Straps
AR35
RSVD41
AJ31
VAXG_VAL_SENSE RSVD42
AT34 11: (Default) x16 - Device 1 functions 1 and 2 disabled
AH31
VSSAXG_VAL_SENSE RSVD43
AT33 CFG[6:5]
AJ33
VCC_VAL_SENSE RSVD44
AP35 10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled
AH33 AR34
VSS_VAL_SENSE RSVD45
C 01: Reserved - (Device 1 function 1 disabled ; function 2 enabled)
C
AJ26
RSVD5 00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
RESERVED
B34
B4 RSVD46 A33
D1 RSVD6 RSVD47 A34
RSVD7 RSVD48 B35
RSVD49 C35
RSVD50
F25
F24 RSVD8
F23 RSVD9 CFG4
RSVD10
D24
RSVD11 RSVD51
AJ32 Display Port Presence Strap(EDP)
G25 AK32
G24 RSVD12 RSVD52
RSVD13
E23
RSVD14 1:(Default) Disabled; No Physical Display Port
D23
RSVD15
R65 CFG4 attached to Embedded Display Port
C30 AH27 1k/NC
A31 RSVD16 VCC_DIE_SENSE 0:Enabled; An external Display Port device is
B30 RSVD17 connected to the Embedded Display Port
B29 RSVD18
D30 RSVD19 AN35
RSVD20 RSVD54 CLK_XDP_ITP_P 23
B B31 AM35 B
RSVD21 RSVD55 CLK_XDP_ITP_N 23
A30
C29 RSVD22
RSVD23
J20 CFG7
B18 RSVD24 AT2
RSVD25 RSVD56
A19
VCCIO_SEL RSVD57
AT1 PEG DEFER TRAINING
AR1
RSVD58
J15
RSVD27
R66 1: (Default) PEG Train immediately following
1k/NC CFG7 xxRESETB de assertion
B1 0: PEG Wait for BIOS for training
KEY

A A
SANDYBRIDGE 7/7

B <Cage Code> 0.2

E450 9 of 50
5 4 3 2 1
5 4 3 2 1
SODIMM-A H5.2
5 M_A_A[15:0]
J2A M_A_DQ[63:0] 5
M_A_A0 98 5 M_A_DQ0
M_A_A1 97 A0 DQ0 7 M_A_DQ1
M_A_A2 96 A1 DQ1 15 M_A_DQ2
M_A_A3 95 A2 DQ2 17 M_A_DQ3 5,7,11,34 +V1.5
M_A_A4 92 A3 DQ3 4 M_A_DQ4 J2B
M_A_A5 91 A4 DQ4 6 M_A_DQ5
M_A_A6 90 A5 DQ5 16 M_A_DQ6 75 44
M_A_A7 86 A6 DQ6 18 M_A_DQ7 76 VDD1 VSS16 48
D M_A_A10 107 A9 DQ9 33 M_A_DQ10 87 VDD4 VSS19 55 D
M_A_A11 84 A10/AP DQ10 35 M_A_DQ11 88 VDD5 VSS20 60
M_A_A13 119 A12/BC# DQ12 24 M_A_DQ13 94 VDD7 VSS22 65
A15 DQ15 39 M_A_DQ16 105 VDD10 VSS25 72
109 DQ16 41 M_A_DQ17 106 VDD11 VSS26 127
5 M_A_BS0 108 BA0 DQ17 51 M_A_DQ18 111 VDD12 VSS27 128
5 M_A_BS1 BA1 DQ18 +V3.3S 4,11,12,13,14,15,16,17,18,19,20,21,23,24,25,26,31,32,33,37,38,41,44,46,48
79 53 M_A_DQ19 112 VDD13 VSS28 133
5 M_A_BS2 114 BA2 DQ19 40 M_A_DQ20 117 VDD14 VSS29 134
5 -M_CS0 121 S0# DQ20 42 M_A_DQ21 118 VDD15 VSS30 138
5 -M_CS1 101 S1# DQ21 50 M_A_DQ22 123 VDD16 VSS31 139
5 M_CLK_DDR0 103 CK0 DQ22 52 M_A_DQ23 124 VDD17 VSS32 144
5 -M_CLK_DDR0 102 CK0# DQ23 57 M_A_DQ24 VDD18 VSS33 145
5 M_CLK_DDR1 104 CK1 DQ24 59 M_A_DQ25 VSS34 150
5 -M_CLK_DDR1 CK1# DQ25 R72 0 VSS35 5,7,11,34 +V1.5
73 67 M_A_DQ26 199 151
5 M_CKE0 74 CKE0 DQ26 69 M_A_DQ27 VDDSPD VSS36 155
5 M_CKE1 115 CKE1 DQ27 56 M_A_DQ28 R0603 77 VSS37 156
5 -M_A_CAS 110 CAS# DQ28 58 M_A_DQ29 122 NC1 VSS38 161
5 -M_A_RAS RAS# DQ29 C146 C148 NC2 VSS39
113 68 M_A_DQ30 125 162 R205
5 -M_A_WE WE# DQ30 0.1uF 1uF NCTEST VSS40
SA0_DIM0 197
SA0 DQ31
70 M_A_DQ31 To EC VSS41
167
SA1_DIM0 201 129 M_A_DQ32 C0402 C0402 198 168
SA1 DQ32 11,24 TS_DIMM EVENT# VSS42 10K/1%
202 131 M_A_DQ33 30 172
11 SODIMM0_1_SMB_CLK_R SCL DQ33 5,11 -DDR3_DRAMRST RESET# VSS43 R0402
200 141 M_A_DQ34 173
11 SODIMM0_1_SMB_DATA_R SDA DQ34 VSS44
143 M_A_DQ35 178
116 DQ35 130 M_A_DQ36 DIMM0_VREF_A 1 VSS45 179 DIMM0_VREF_B
5 M_ODT0 120 ODT0 DQ36 132 M_A_DQ37 DIMM0_VREF_B 126 VREF_DQ VSS46 184
5 M_ODT1 ODT1 DQ37 140 M_A_DQ38 VREF_CA VSS47 185
DQ38 5,7,11,34 +V1.5 VSS48 R214
142 M_A_DQ39 189
M_A_DM0 11 DQ39 147 M_A_DQ40 2 VSS49 190 10K/1% C458
M_A_DM1 28 DM0 DQ40 149 M_A_DQ41 3 VSS1 VSS50 195 0.1uF
DM1 DQ41 VSS2 VSS51 R0402
C M_A_DM2 46 157 M_A_DQ42 8 196 11,32,34 +V0.75 C0402 C
M_A_DM3 63 DM2 DQ42 159 M_A_DQ43 9 VSS3 VSS52
DM3 DQ43 R68 VSS4
M_A_DM4 136 146 M_A_DQ44 13
M_A_DM5 153 DM4 DQ44 148 M_A_DQ45 14 VSS5
DM5 DQ45 10K/1% VSS6
M_A_DM6 170 158 M_A_DQ46 19 203
M_A_DM7 187 DM6 DQ46 160 M_A_DQ47 R0402 20 VSS7 VTT1 204
DM7 DQ47 163 M_A_DQ48 25 VSS8 VTT2
5 M_A_DQS[7:0]
M_A_DQS0 12 DQ48 165 M_A_DQ49 DIMM0_VREF_A 26 VSS9
M_A_DQS1 29 DQS0 DQ49 175 M_A_DQ50 31 VSS10
M_A_DQS2 47 DQS1 DQ50 177 M_A_DQ51 32 VSS11
M_A_DQS3 64 DQS2 DQ51 164 M_A_DQ52 R69 37 VSS12
M_A_DQS4 137 DQS3 DQ52 166 M_A_DQ53 10K/1% C138 38 VSS13 G1
M_A_DQS5 154 DQS4 DQ53 174 M_A_DQ54 0.1uF 43 VSS14 G1 G2
DQS5 DQ54 R0402 VSS15 G2
M_A_DQS6 171 176 M_A_DQ55 C0402
M_A_DQS7 188 DQS6 DQ55 181 M_A_DQ56
5 -M_A_DQS[7:0]
-M_A_DQS0 10 DQS7 DQ56 183 M_A_DQ57
-M_A_DQS1 27 DQS#0 DQ57 191 M_A_DQ58
-M_A_DQS2 45 DQS#1 DQ58 193 M_A_DQ59
-M_A_DQS3 62 DQS#2 DQ59 180 M_A_DQ60 CON204_DDR3-SODIMM-RVS-4H
-M_A_DQS4 135 DQS#3 DQ60 182 M_A_DQ61
DQS#4 DQ61 D88131-001
-M_A_DQS5 152 192 M_A_DQ62 5,7,11,34 +V1.5
-M_A_DQS6 169 DQS#5 DQ62 194 M_A_DQ63
-M_A_DQS7 186 DQS#6 DQ63
DQS#7
CON204_DDR3-SODIMM-RVS-4H
D88131-001
R209 0 SODIMM0_1_SMB_CLK_R
15,23,48 SMB_CLK_S C122
R210 0 SODIMM0_1_SMB_DATA_R
15,23,48 SMB_DATA_S C154 C149 C151 C140 C141 C142 C143 C144 C145 1.0uF
B 10% B
10uF 10uF 10uF 10uF 10uF 10uF 1.0uF 1.0uF 1.0uF
C0603 C0603 C0402 C0402 C0402 .
C0603 C0603 C0603 C0603
+V3.3S 4,11,12,13,14,15,16,17,18,19,20,21,23,24,25,26,31,32,33,37,38,41,44,46,48
R88 R89
10K/1%/NC 10K/1%/NC
R0402 R0402 11,32,34 +V0.75
+V3.3S 4,11,12,13,14,15,16,17,18,19,20,21,23,24,25,26,31,32,33,37,38,41,44,46,48
SA0_DIM0
SA1_DIM0 C131 C137 C125 C126 C188 C199
1uF 1uF 1uF 1uF 10uF 10uF
10% 10% 10% 10% C0603 C0603
R78 . . . .
R74
10K/1%
10K/1% R90
R0402
R0402 10K
R0402
TS_DIMM
A A

DIMM 0

4 3
2
Scale Model
E450
1
Sheet
10 of 50
5 4 3 2 1
SODIMM-B H9.2
5 M_B_A[15:0]
J1A M_B_DQ[63:0] 5
M_B_A0 98 5 M_B_DQ0
M_B_A1 97 A0 DQ0 7 M_B_DQ1
M_B_A2 96 A1 DQ1 15 M_B_DQ2
M_B_A3 95 A2 DQ2 17 M_B_DQ3 5,7,10,34 +V1.5
M_B_A4 92 A3 DQ3 4 M_B_DQ4 J1B
M_B_A5 91 A4 DQ4 6 M_B_DQ5
M_B_A6 90 A5 DQ5 16 M_B_DQ6 75 44
M_B_A7 86 A6 DQ6 18 M_B_DQ7 76 VDD1 VSS16 48
D M_B_A11 84 A10/AP DQ10 35 M_B_DQ11 88 VDD5 VSS20 60 D
M_B_A13 119 A12/BC# DQ12 24 M_B_DQ13 94 VDD7 VSS22 65
A15 DQ15 39 M_B_DQ16 105 VDD10 VSS25 72
109 DQ16 41 M_B_DQ17 106 VDD11 VSS26 127
5 M_B_BS0 108 BA0 DQ17 51 M_B_DQ18 111 VDD12 VSS27 128
5 M_B_BS1 BA1 DQ18 +V3.3S 4,10,12,13,14,15,16,17,18,19,20,21,23,24,25,26,31,32,33,37,38,41,44,46,48
79 53 M_B_DQ19 112 VDD13 VSS28 133
5 M_B_BS2 114 BA2 DQ19 40 M_B_DQ20 117 VDD14 VSS29 134
5 -M_B_CS0 121 S0# DQ20 42 M_B_DQ21 118 VDD15 VSS30 138
5 -M_B_CS1 101 S1# DQ21 50 M_B_DQ22 123 VDD16 VSS31 139
5 M_B_CLK_DDR0 103 CK0 DQ22 52 M_B_DQ23 124 VDD17 VSS32 144
5 -M_B_CLK_DDR0 102 CK0# DQ23 57 M_B_DQ24 VDD18 VSS33 145
5 M_B_CLK_DDR1 104 CK1 DQ24 59 M_B_DQ25 VSS34 150
5 -M_B_CLK_DDR1 73 CK1# DQ25 67 M_B_DQ26 R200 0 199 VSS35 151
5 M_B_CKE0 74 CKE0 DQ26 69 M_B_DQ27 VDDSPD VSS36 155
5 M_B_CKE1 115 CKE1 DQ27 56 M_B_DQ28 R0603 77 VSS37 156
5 -M_B_CAS 110 CAS# DQ28 58 M_B_DQ29 122 NC1 VSS38 161
5 -M_B_RAS RAS# DQ29 C447 C449 NC2 VSS39
113 68 M_B_DQ30 125 162
5 -M_B_WE WE# DQ30 0.1uF 1uF NCTEST VSS40
SA0_DIM1 197 70 M_B_DQ31 167
SA1_DIM1 201 SA0 DQ31 129 M_B_DQ32 C0402 C0402 198 VSS41 168
SA1 DQ32 10,24 TS_DIMM EVENT# VSS42 5,7,10,34 +V1.5
202 131 M_B_DQ33 30 172
10 SODIMM0_1_SMB_CLK_R SCL DQ33 5,10 -DDR3_DRAMRST RESET# VSS43
200 141 M_B_DQ34 173
10 SODIMM0_1_SMB_DATA_R SDA DQ34 VSS44
143 M_B_DQ35 178
116 DQ35 130 M_B_DQ36 DIMM1_VREF_A 1 VSS45 179
5 M_B_ODT0 120 ODT0 DQ36 132 M_B_DQ37 DIMM1_VREF_B 126 VREF_DQ VSS46 184
5 M_B_ODT1 ODT1 DQ37 VREF_CA VSS47 R215
140 M_B_DQ38 5,7,10,34 +V1.5 185
DQ38 142 M_B_DQ39 VSS48 189
DQ39 VSS49 10K/1%
M_B_DM0 11 147 M_B_DQ40 2 190
M_B_DM1 28 DM0 DQ40 149 M_B_DQ41 3 VSS1 VSS50 195 R0402
M_B_DM2 46 DM1 DQ41 157 M_B_DQ42 8 VSS2 VSS51 196
C M_B_DM3 63 DM2 DQ42 159 M_B_DQ43 9 VSS3 VSS52 DIMM1_VREF_B C
DM3 DQ43 R79 VSS4
M_B_DM4 136 146 M_B_DQ44 13 10,32,34 +V0.75
M_B_DM5 153 DM4 DQ44 148 M_B_DQ45 14 VSS5
DM5 DQ45 10K/1% VSS6 R216
M_B_DM6 170 158 M_B_DQ46 19 203
M_B_DM7 187 DM6 DQ46 160 M_B_DQ47 R0402 20 VSS7 VTT1 204 10K/1% C459
DM7 DQ47 163 M_B_DQ48 25 VSS8 VTT2 0.1uF
5 M_B_DQS[7:0] R0402
M_B_DQS0 12 DQ48 165 M_B_DQ49 DIMM1_VREF_A 26 VSS9 C0402
M_B_DQS1 29 DQS0 DQ49 175 M_B_DQ50 31 VSS10
M_B_DQS2 47 DQS1 DQ50 177 M_B_DQ51 32 VSS11
M_B_DQS3 64 DQS2 DQ51 164 M_B_DQ52 R196 37 VSS12
M_B_DQS4 137 DQS3 DQ52 166 M_B_DQ53 10K/1% C441 38 VSS13 G1
M_B_DQS5 154 DQS4 DQ53 174 M_B_DQ54 0.1uF 43 VSS14 G1 G2
DQS5 DQ54 R0402 VSS15 G2
M_B_DQS6 171 176 M_B_DQ55 C0402
M_B_DQS7 188 DQS6 DQ55 181 M_B_DQ56
5 -M_B_DQS[7:0]
-M_B_DQS0 10 DQS7 DQ56 183 M_B_DQ57
-M_B_DQS1 27 DQS#0 DQ57 191 M_B_DQ58
-M_B_DQS2 45 DQS#1 DQ58 193 M_B_DQ59
-M_B_DQS3 62 DQS#2 DQ59 180 M_B_DQ60 CON204_DDR3-SODIMM-RVS-4H
-M_B_DQS4 135 DQS#3 DQ60 182 M_B_DQ61
DQS#4 DQ61 ddr3_std_9_2h_lotes
-M_B_DQS5 152 192 M_B_DQ62 5,7,10,34 +V1.5
-M_B_DQS6 169 DQS#5 DQ62 194 M_B_DQ63
-M_B_DQS7 186 DQS#6 DQ63
DQS#7
CON204_DDR3-SODIMM-RVS-4H
ddr3_std_9_2h_lotes
C437
C440 C456 C457 C442 C443 C444 C448 C450 C453 1.0uF
10uF 10uF 10uF 10uF 10uF 10uF 1.0uF 1.0uF 1.0uF 10%
B . B
C0603 C0603 C0402 C0402 C0402
C0603 C0603 C0603 C0603
+V3.3S 4,10,12,13,14,15,16,17,18,19,20,21,23,24,25,26,31,32,33,37,38,41,44,46,48
R129 R202
10K/1%/NC 10K/1%
R0402 R0402 10,32,34 +V0.75
SA0_DIM1
SA1_DIM1 C454 C455 C451 C452 C233 C244
1uF 1uF 1uF 1uF 10uF 10uF
10% 10% 10% 10% C0603 C0603
R201 . . . .
R77
10K/1%
R0402 10K/1%/NC
R0402
A A

DIMM 1

4 3
2
Scale Model
E450
1
Sheet
11 of 50
5 4 3 2 1
+V5S 13,15,20,21,28,29,31,32,33,34,36,37,38,41,42,43,44
+V3.3S 4,10,11,13,14,15,16,17,18,19,20,21,23,24,25,26,31,32,33,37,38,41,44,46,48
+V3.3S 4,10,11,13,14,15,16,17,18,19,20,21,23,24,25,26,31,32,33,37,38,41,44,46,48
+V3.3S 4,10,11,13,14,15,16,17,18,19,20,21,23,24,25,26,31,32,33,37,38,41,44,46,48
CRT_DDC_CLK and DATA:

MCH to panel ctl. Open drain
with weak pullup of ~10-20k to
3.3V rail. Require voltage
1
translation from 3.3V to 5V on
1
board
R732 R733 R222 R223 BAT54S
D 2.2K 2.2K 2.2K 2.2K D
5% 5% 5% 5% D77 BAT54S
. . . . D78
3
1
3
Q6
BSS138
.
CRT_DDC_CLK 2 3 R392 47 CRT_PU_DDC_CLK
17 CRT_DDC_CLK R393 47 CRT_PU_DDC_DAT
1
Q7 C216
BSS138 47PF C222
. 5% 47PF
CRT_DDC_DATA 2 3 5%
17 CRT_DDC_DATA
.
CRT_BLUE FB6 47ohm@100MHz BLUE
17 CRT_BLUE
CRT_R_HSYNC
R224 C206
150/1% 10pF
. 5%
. CRT_R_VSYNC
.
C214 C215
CRT_GREEN FB7 47ohm@100MHz GREEN
17 CRT_GREEN 47PF 47PF
3
5% 5%
3
D73
R225 C208 D74 BAT54S
150/1% 10pF BAT54S
. 5%
1
.
1
C C
.
CRT_RED FB8 47ohm@100MHz RED
17 CRT_RED
+V5S 13,15,20,21,28,29,31,32,33,34,36,37,38,41,42,43,44
R226 C210
150/1% 10pF
. 5%
.
L51
F7 SMD1812P150TS-1.5A
+V3.3S 4,10,11,13,14,15,16,17,18,19,20,21,23,24,25,26,31,32,33,37,38,41,44,46,48
C235
220Z/3A 100M
0.1uF
20%
.
C234
0.1uF
5%
8
J5 PACKAGE: 同E100
CRT_PU_DDC_CLK 15
7 vga_C10517-102-ALLTOP
. CRT_R_VSYNC 14
BLUE FB11 47ohm@100MHz 6
CRT_R_HSYNC 13
C209 C371 5
22pF 10pF CRT_PU_DDC_DAT 12
5% 5% 4
. . 11
CRT_L2_BLUE 3
. 10
CRT_HSYNC CRT_R_HSYNC GREEN FB12 47ohm@100MHz CRT_L2_GREEN 2 GND0
17 CRT_HSYNC
9
C211 C372 1 GND1
CRT_VSYNC CRT_R_VSYNC 22pF 10pF
17 CRT_VSYNC
B 5% 5% CRT-CON B
. .
.
RED FB13 47ohm@100MHz CRT_L2_RED
3
D70
C212 C373 BAT54S
3
22pF 10pF
3
5% 5% D71
D72
1
. . BAT54S
BAT54S
1
2
1
+V3.3S 4,10,11,13,14,15,16,17,18,19,20,21,23,24,25,26,31,32,33,37,38,41,44,46,48
C225
0.1uF
5%
+V3.3S 4,10,11,13,14,15,16,17,18,19,20,21,23,24,25,26,31,32,33,37,38,41,44,46,48
+V3.3S 4,10,11,13,14,15,16,17,18,19,20,21,23,24,25,26,31,32,33,37,38,41,44,46,48
C224
0.1uF
5%
A A

VGA
C <Cage Code> 0.2

E450 12 of 50
5 4 3 2 1
5 4 3 2 1
D D
+V3.3S 4,10,11,12,14,15,16,17,18,19,20,21,23,24,25,26,31,32,33,37,38,41,44,46,48
R412 .
0/NC 5%
FB5
2 3
LVDS-CON
LCD LOGIC--2A
C788
C789
100ohm@100MHz/3A R212
1 1
100K Q38
5%
SI2301BDS
0.1uF
0.1uF
+V3.3S 4,10,11,12,14,15,16,17,18,19,20,21,23,24,25,26,31,32,33,37,38,41,44,46,48
17 LVDS_VDD_EN R675 47
3
.
R213 4,10,11,12,14,15,16,17,18,19,20,21,23,24,25,26,31,32,33,37,38,41,44,46,48 +V3.3S
100K Q39
5% C787 1 2N7002 C202 C258
.
0.1uF 0.1uF 0.1uF
10% 10%
2
R678 R676
VIN 27,28,33,34,35,36,37,38,39,40
J4 2.2K 2.2K
32
R396 DDC_PWR
C 0 2 1 DDC_CLK C
4 3 LVDS_DDC_CLK 17
BL_CTL DDC_DATA
6 5 LVDS_DDC_DATA 17
5% R394 0 5% BL_ON DATAN0 LA_DATAN0 17
8 7 DATAP0 R859 0
10 9 R860 0 LA_DATAP0 17
EMB_HPD
R870 0 12 11 DATAN1
14 13 R861 0 LA_DATAN1 17
LCD_BLT_VCC 90_100MHz DATAP1 LA_DATAP1 17
L19
C783
16 15 R862 0
C201 4 3 18 17 DATAN2
0.1uF/25V 18 USB_PN3 20 19 R863 0 LA_DATAN2 17
C203 C204 DATAP2
10% 22 21 R864 0 LA_DATAP2 17
0.1uF/25V 0.1uF/25V 1 2 VCC_CAM
18 USB_PP3 24 23
10% 10% CLKN
26 25 LA_CLKN 17
CLKP
10uF/25V
41 MIC1_OUT 28 27 LA_CLKP 17
30 29
31
+V3.3S 4,10,11,12,14,15,16,17,18,19,20,21,23,24,25,26,31,32,33,37,38,41,44,46,48
B
R552
FOR EDP B
20K
D17
BAT54A DP_TXN0 C402 0.1uF/10%/NC DATAN0
3 DP_TXN0 DP_TXP0 C401 0.1uF/10%/NC DATAP0
LCD_SW 1 3 BL_ON 3 DP_TXP0 3,4,6,20,21,24,32,36,48 +V1.05S_VCCP
24 LCD_SW
DP_TXN1 C404 0.1uF/10%/NC DATAN1
2 C786 3 DP_TXN1 DP_TXP1 C403 0.1uF/10%/NC DATAP1
17 L_BKLT_EN 3 DP_TXP1
R211 R872
100K +V3.3S 4,10,11,12,14,15,16,17,18,19,20,21,23,24,25,26,31,32,33,37,38,41,44,46,48 Place pull up resistor within 2 inches of CPU
R395 0.1uF
100K
5% R875
.
1K/NC
-DP_HPD 3
3
100K/NC
C410 0.1uF/10%/NC DATAP2 Q63
3 DP_AUXP C409 0.1uF/10%/NC DATAN2 EMB_HPD 1 2N7002/NC
3 DP_AUXN
R873 R871
2
PR13 L_CTRL_CLK、L_CTRL_DATA、
SMB_THRM_CLK、SMB_THRM_DATA
3
PR11 10K
WEB_CAM 1 D82 100K/NC ALS_INTR# 这些信号都没有接！！ 100K/NC
1
24 WEB_CAM Q35 SI2301BDS

1
10K MMBT3904
2 3
2
+V5S 12,15,20,21,28,29,31,32,33,34,36,37,38,41,42,43,44
A R446 0/NC A
FB28 VCC_CAM
L_BKLT_CTRL R665 100/NC

17 L_BKLT_CTRL
C354
C356 0.1uF LCD_ADJ_PWM R664 100 BL_CTL LVDS
10% 24 LCD_ADJ_PWM
10uF

E450 13 of 50
5 4 3 2 1
5 4 3 2 1
CMOS SET RTC_RST#

21,24,27,28 +V3.3A_KSC
4,15,16,18,19,21,24,25,26,28,30,33,34,37,44,46,48 Clear Cmos GND

+V3.3A
R269 16,21 +V3.3A_RTC INTVRMEN-Integrated SUS
KEEP CMOS OPEN 1.05V VRM Enable
VER10 0 4,10,11,12,13,15,16,17,18,19,20,21,23,24,25,26,31,32,33,37,38,41,44,46,48 +V3.3S
R268 R0402
C251 -RTC_RST High - Enable Internal VRs
0/NC C153 18pF
D10 1uF
R0402 BAT54C C0402
2 C0402 -LDRQ0 R260 10K
4
1 3 R231 20K R229 -PCH_DRQ1 R261 10K
D 3 2 10M D
R0402 C252 Y3 INT_SERIRQ R250 10K
32.768KHz R0402 U2A
1uF
1
R252 -SATA_DET0 R246 10K
1K C0402
RTC_X1 A20 C38
R232 20K RTCX1 FWH0 / LAD0 LPC_AD0 24,44
R0402 A38
LPC
C243 18pF FWH1 / LAD1 LPC_AD1 24,44
RTC_X2 C20 B37
R227 RTCX2 FWH2 / LAD2 LPC_AD2 24,44
R0402 C37
C253 FWH3 / LAD3 LPC_AD3 24,44
1M C0402 D20
1uF RTCRST# D36
R0402 G22 FWH4 / LFRAME# -LPC_FRAME 24,44
C0402 SRTCRST# E36
RTC
LDRQ0# -LDRQ0 24
K22 K36
INTRUDER# LDRQ1# / GPIO23 -PCH_DRQ1
16,21 +V3.3A_RTC
PCH_INTVRMEN C17 V5
INTVRMEN SERIRQ INT_SERIRQ 24
R234 330K
J8
Ver02
1
AM3 SATA_RXN0_C C272 0.01uF SATA_RXN0 42

batt R0402 SATA0RXN
R236 33 HDA_BIT_CLK_R N34 AM1 SATA_RXP0_C C132 0.01uF SATA_RXP0 42
3
4
HDA_BCLK SATA0RXP
SATA 6G
TPM Settings SRTC_RST# 41 HDA_BIT_CLK AP7 SATA_TXN0_C C250 0.01uF
SATA0TXN SATA_TXN0 42
R787 0 HDA_SYNC_R1 R740 33 HDA_SYNC_R L34 AP5 SATA_TXP0_C C248 0.01uF SATA_TXP0 42
41 HDA_SYNC HDA_SYNC SATA0TXP
Clear ME RTC registers GND R237 0 PCH_HDA_SPKR T10 AM10 SATA_RXN2_C C606 0.01uF SATA_RXN2 42
HDA_SPKR SPKR SATA1RXN AM8 SATA_RXP2_C 0.01uF
C599 SATA_RXP2 42
R741 33 K34 SATA1RXP AP11 SATA_TXN2_C HDA_SYNC 3 2 HDA_SYNC_R1
C605 0.01uF SATA_TXN2 42
Keep ME RTC registers OPEN 41 -HDA_RST HDA_RST# SATA1TXN AP10 SATA_TXP2_C C603 0.01uF SATA_TXP2 42
SATA1TXP
1
E34 AD7 4,15,16,18,19,21,24,25,26,28,30,33,34,37,44,46,48 +V3.3A Q46
41 HDA_SDATAIN0
1
HDA_SDIN0 SATA2RXN AD5
G34 SATA2RXP AH5 SI2301BDS/NC
HDA_SDIN1 SATA2TXN AH4
SATA2TXP
C34 SATA2、SATA3不可用 R247
IHDA
HDA_SDIN2 AB8
C 4,15,16,18,19,21,24,25,26,28,30,33,34,37,44,46,48 +V3.3A SATA3RXN 10K/NC C
A34 AB10
HDA_SDIN3 SATA3RXP AF3
SATA3TXN AF1
SATA3TXP
3
R238 33 HDA_SDOUT_R A36
SATA
PCH_JTAG_TMS R253 210/1% 41 HDA_SDOUT HDA_SDO Y7
SATA4RXN Y5 Q51
PCH_JTAG_TDI R254 210/1% C36 SATA4RXP AD3 1 2N7002/NC
HDA_DOCK_EN# / GPIO33 SATA4TXN -PM_SLP_S5
AD1
SATA4TXP
PCH_JTAG_TDO R255 210/1% N32 Ver02
2
HDA_DOCK_RST# / GPIO13 Y3
SATA5RXN Y1
SATA5RXP AB3
SATA5TXN 21 +V1.05S_VCC_SATA
PCH_JTAG_TMS R256 100/1% PCH_JTAG_TCK_BUF J3 AB1
48 PCH_JTAG_TCK_BUF JTAG_TCK SATA5TXP
PCH_JTAG_TDI R257 100/1% H7 Y11 SATA_COMP R228 37.4/1%
JTAG
48 PCH_JTAG_TMS JTAG_TMS SATAICOMPO
PCH_JTAG_TDO R258 100/1% K5 Y10
48 PCH_JTAG_TDI JTAG_TDI SATAICOMPI 21 +V1.05S_SATA3
PCH_JTAG_TCK_BUF R259 51 H1
48 PCH_JTAG_TDO JTAG_TDO AB12 SATA3_COMPR230 49.9/1%
SATA3RCOMPO
AB13
4,10,11,12,13,15,16,17,18,19,20,21,23,24,25,26,31,32,33,37,38,41,44,46,48 +V3.3S
SATA3COMPI
T3 AH1 RBIAS_SATA3 R233 750/1%

SPI_CLK SPI_CLK SATA3RBIAS R244
+V3.3S 4,10,11,12,13,15,16,17,18,19,20,21,23,24,25,26,31,32,33,37,38,41,44,46,48
R241 20/1% -SPI_CS0_R Y14 10K
-SPI_CS0 SPI_CS0#
R242 20/1% -SPI_CS1_R T1
SPI
-SPI_CS1 SPI_CS1# P3
+V3.3S 4,10,11,12,13,15,16,17,18,19,20,21,23,24,25,26,31,32,33,37,38,41,44,46,48 SATALED# -SATA_LED 46
C640
R786 V4 V14 -SATA_DET0
3.3K 10% SPI_SI SPI_MOSI SATA0GP / GPIO21
B B
5% U28 U3 P1 BBS_BIT0
. SPI_SO SPI_MISO SATA1GP / GPIO19 BBS_BIT0 18
3 8 0.1uF
WP VCC
1 -SPI_CS0 CougarPoint_Rev_1p0
SPI_CE 6 SPI_CLK R790
SPI_SCK 5 SPI_SI 3.3K
SPI_SI 2 SPI_SO 5%
SPI_SO .
4 7 4,15,16,18,19,21,24,25,26,28,30,33,34,37,44,46,48 +V3.3A
GND SPI_HOLD
W25X32
Use 33R series-resistor per device R245
if using two SPI devices 1K
Closed to flash R251 - Flash Descriptor Security Overide
Low = Disabled (NoStuff)- Default HDA_SYNC_R
HDA_SDOUT High = Enabled (Stuff)
4,15,16,18,19,21,24,25,26,28,30,33,34,37,44,46,48 +V3.3A PLL On Die Voltage Regulator Selection
HDA_SDOUT_R 3 2 R251 1k/NC

Low - PLL ODVR powered by 1.8V;
HDA_SYNC High - PLL ODVR powered by 1.5V
1
Q43
1
SI2301BDS
Ver02 24 GPIO33_CONTROL
GPIO控制和E220相反
A A
Ver02 4,10,11,12,13,15,16,17,18,19,20,21,23,24,25,26,31,32,33,37,38,41,44,46,48 +V3.3S

Spi1 Del
R249 - NO REBOOT PCH 1/9
Disabled when Low -- (NoStuff) DEFAULT
Enabled when HIGH -- (Stuff)
R249 1K/NC HDA_SPKR Custom <Cage Code> 0.2
4 3
2
Scale Model
E450
1
Sheet
14 of 50
5 4 3 2 1
U2B
25 PCIE_RXN1_SLOT1 BG34
BJ34 PERN1 E12
25 PCIE_RXP1_SLOT1 PERP1 SMBALERT# / GPIO11 PCH_GPIO11
C280 0.1uF PCIE_TXN1_C AV32
25 PCIE_TXN1_SLOT1 PETN1
25 PCIE_TXP1_SLOT1
C279 0.1uF PCIE_TXP1_C AU32
PETP1 SMBCLK
H14
SMB_CLK_A_ICH 25,26 PCH Master
26 PCIE_RXN2_SLOT2 BE34 C9
PERN2 SMBDATA SMB_DATA_A_ICH 25,26
26 PCIE_RXP2_SLOT2 BF34
0.1uF PCIE_TXN2_C BB32 PERP2
26 PCIE_TXN2_SLOT2 C282
C281 0.1uF PCIE_TXP2_C AY32 PETN2
SMBUS
26 PCIE_TXP2_SLOT2 PETP2 A12
D SML0ALERT# / GPIO60 DRAMRST_CNTRL_PCH 5 D
30 PCIE_RXN3_LAN BG36
PERN3 PCH Master and Slave
30 PCIE_RXP3_LAN BJ36 C8
PERP3 SML0CLK SML0_CLK
C284 0.1uF PCIE_TXN3_C AV34
30 PCIE_TXN3_LAN PETN3
C283 0.1uF PCIE_TXP3_C AU34 G12
30 PCIE_TXP3_LAN PETP3 SML0DATA SML0_DATA
BF36
BE36 PERN4
AY34 PERP4 C13
PETN4 SML1ALERT# / PCHHOT# / GPIO74 PCH_GPIO74
BB34
PETP4 E14 PCH Slave
PCI-E*
SML1CLK / GPIO58 SML1_CLK 24
BG37
BH37 PERN5 M16
PERP5 SML1DATA / GPIO75 SML1_DATA 24
AY36
BB36 PETN5
PETP5
BJ38 CLK_BUF_CPYCLK_N R291 10k
BG38 PERN6 CLK_BUF_CPYCLK_P R292 10k
Controller
AU36 PERP6 M7
PETN6 CL_CLK1 CL_CLK
AV36 CLK_BUF_EXP_N R293 10k
PETP6 CLK_BUF_EXP_P R294 10k
Link
BG40 T11 CLK_BUF_DOT96_N R295 10k
PERN7 CL_DATA1 CL_DATA
BJ40 CLK_BUF_DOT96_P R296 10k
AY40 PERP7 CLK_BUF_CKSSCD_N R297 10k
BB40 PETN7 P10 CLK_BUF_CKSSCD_P R298 10k
PETP7 CL_RST1# -CL_RST
CLK_BUF_REF14 R299 10k
BE38
BC38 PERN8
PERP8
AW38
PETN8 Ver02
AY38
PETP8 External pull-up resistor required
if used for CLKREQ# functionality. CLOCK TERMINATION for FCIM
M10
PEG_A_CLKRQ# / GPIO47 -PEG_CLKREQ
Y40
Y39 CLKOUT_PCIE0N
CLKOUT_PCIE0P AB37
CLK_PCIE_PEG_N
CLOCKS
J2 CLKOUT_PEG_A_N AB38
-CLK_SLOT0_OE PCIECLKRQ0# / GPIO73 CLKOUT_PEG_A_P CLK_PCIE_PEG_P
C R262 0 CLK_PCH_SRC1_N AB49 AV22 CLKOUT_DMI_N C

25 CLK_PCIE_SLOT1_N R263 0 CLK_PCH_SRC1_P AB47 CLKOUT_PCIE1N CLKOUT_DMI_N AU22 CLKOUT_DMI_P CLK_EXP_N 4
25 CLK_PCIE_SLOT1_P CLKOUT_PCIE1P CLKOUT_DMI_P CLK_EXP_P 4
M1
25 -CLK_SLOT1_OE PCIECLKRQ1# / GPIO18 AM12 4,14,16,18,19,21,24,25,26,28,30,33,34,37,44,46,48 +V3.3A
CLKOUT_DP_N AM13 CLK_DP_N 4
R264 0 CLK_PCH_SRC2_N AA48 CLKOUT_DP_P CLK_DP_P 4
26 CLK_PCIE_SLOT2_N R265 0 CLK_PCH_SRC2_P AA47 CLKOUT_PCIE2N
CLKOUT_PCIE2P PCH_GPIO11 R304 10K
26 CLK_PCIE_SLOT2_P BF18
CLKIN_DMI_N CLK_BUF_EXP_N 23 R305 1K
V10 BE18 DRAMRST_CNTRL_PCH
26 -CLK_SLOT2_OE PCIECLKRQ2# / GPIO20 CLKIN_DMI_P CLK_BUF_EXP_P 23
4,10,11,12,13,14,16,17,18,19,20,21,23,24,25,26,31,32,33,37,38,41,44,46,48 +V3.3S
R266 0 CLK_PCH_SRC3_N Y37 BJ30
30 -CLK_PCIE_LAN R267 0 CLKOUT_PCIE3N CLKIN_GND1_N CLK_BUF_CPYCLK_N 23
CLK_PCH_SRC3_P Y36 BG30
30 CLK_PCIE_LAN CLKOUT_PCIE3P CLKIN_GND1_P CLK_BUF_CPYCLK_P 23
SML0_CLK R310 2.2K
R451 0 A8
30 CLKREQB PCIECLKRQ3# / GPIO25 G24 SML0_DATA R311 2.2K
CLK_BUF_DOT96_N 23 -DGPU_PRSNT R300 10K
CLKIN_DOT_96N E24
CLKIN_DOT_96P CLK_BUF_DOT96_P 23 R301 10K
Y43 -PEG_CLKREQ
Y45 CLKOUT_PCIE4N
CLKOUT_PCIE4P AK7
CLKIN_SATA_N CLK_BUF_CKSSCD_N 23
L12 AK5 SML1_CLK R181 2.2K
-CLK_SLOT4_OE PCIECLKRQ4# / GPIO26 CLKIN_SATA_P CLK_BUF_CKSSCD_P 23
SML1_DATA R302 2.2K
V45 K45
CLKOUT_PCIE5N REFCLK14IN CLK_BUF_REF14 23 PCH_GPIO74 R303 10K
V46
CLKOUT_PCIE5P
L14 H45
-CLK_SLOT5_OE PCIECLKRQ5# / GPIO44 CLKIN_PCILOOPBACK CLK_PCI_FB 18
18pF C130
AB42 V47 XTAL25_IN
AB40 CLKOUT_PEG_B_N XTAL25_IN V49 XTAL25_OUT
CLKOUT_PEG_B_P XTAL25_OUT C0402
21 +VCCDIFFCLKN
E6
1
-DMC_CLKREQ PEG_B_CLKRQ# / GPIO56 R358 Y4
Y47 XCLK_RCOMP R284 90.9/1%
V40 XCLK_RCOMP 1M D_25MHz
CLKOUT_PCIE6N
2
V42
B CLKOUT_PCIE6P B
18pF C273
T13
-CLK_SLOT6_OE PCIECLKRQ6# / GPIO45
V38 K43 CLK_PCH_PCI_SIO_DOCK_R C0402
FLEX CLOCKS
可以不用上拉 V37 CLKOUT_PCIE7N CLKOUTFLEX0 / GPIO64

CLKOUT_PCIE7P F47
CLKOUTFLEX1 / GPIO65 -DGPU_PRSNT
K12
-CLK_SLOT7_OE PCIECLKRQ7# / GPIO46 H47 CLK_FLEX2
R278 0 AK14 CLKOUTFLEX2 / GPIO66
48 PCIE_CLK_XDP_N CLKOUT_ITPXDP_N 4,14,16,18,19,21,24,25,26,28,30,33,34,37,44,46,48 +V3.3A
R279 0 AK13 K49 CLK_48M_R R285 22/NC
48 PCIE_CLK_XDP_P CLKOUT_ITPXDP_P CLKOUTFLEX3 / GPIO67 CLK_48M 29
FOR CARDREADER WITH NO CRYSTAL
CougarPoint_Rev_1p0
-DMC_CLKREQ R883 10K
-CLK_SLOT0_OE R832 10K
+V3.3A 4,14,16,18,19,21,24,25,26,28,30,33,34,37,44,46,48
+V5S 12,13,20,21,28,29,31,32,33,34,36,37,38,41,42,43,44 SLOT5和SLOT7公板没有上拉
+V3.3S 4,10,11,12,13,14,16,17,18,19,20,21,23,24,25,26,31,32,33,37,38,41,44,46,48
R152 R153
4.7K 4.7K R154 R155
5% 5% 4.7K 4.7K
. . 5% 5%
1
A A
. .
SMB_CLK_A_ICH 3 2
SMB_CLK_S 10,23,48
1
Q3
SMB_DATA_A_ICH BSS138 3 2
SMB_DATA_S 10,23,48
PCH 2/9
Q4
BSS138 Draw by Size CAGE Code DWG NO Rev
C <Cage Code> 0.2

E450 15 of 50
5 4 3 2 1
5 4 3 2 1
U2C
BC24 BJ14
3 DMI_RXN0 DMI0RXN FDI_RXN0 FDI_TXN0 3
BE20 AY14
BG18 BE14
BG20 BH13
BC12
FDI_RXN4 FDI_TXN4 3
BE24 BJ12
3 DMI_RXP0 DMI0RXP FDI_RXN5 FDI_TXN5 3
BC20 BG10
3 DMI_RXP1 DMI1RXP FDI_RXN6 FDI_TXN6 3
BJ18 BG9
D 3 DMI_RXP2 DMI2RXP FDI_RXN7 FDI_TXN7 3 D
BJ20
3 DMI_RXP3 DMI3RXP BG14
FDI_RXP0 FDI_TXP0 3
AW24 BB14
3 DMI_TXN0 DMI0TXN FDI_RXP1 FDI_TXP1 3
AW20 BF14
BB18 BG13
AV18 BE12
DMI
FDI
20 +V1.05S_VCC_EXP 3 DMI_TXN3 DMI3TXN FDI_RXP4 FDI_TXP4 3
BG12
FDI_RXP5 FDI_TXP5 3
AY24 BJ10
3 DMI_TXP0 DMI0TXP FDI_RXP6 FDI_TXP6 3
AY20 BH9
3 DMI_TXP1 DMI1TXP FDI_RXP7 FDI_TXP7 3
R313 AY18
3 DMI_TXP2 AU18 DMI2TXP
3 DMI_TXP3 DMI3TXP AW16 FDI_INT_R R324 0
49.9/1% FDI_INT FDI_INT 3
BJ24 AV12 FDI_FSYNC0_R R325 0
DMI_ZCOMP FDI_FSYNC0 FDI_FSYNC0 3
DMI_COMP_R BG25 BC10 FDI_FSYNC1_R R326 0 14,21 +V3.3A_RTC
DMI_IRCOMP FDI_FSYNC1 FDI_FSYNC1 3
R312 750/1% RBIAS_CPY BH21 AV14 FDI_LSYNC0_R R327 0
DMI2RBIAS FDI_LSYNC0 FDI_LSYNC0 3
BB10 FDI_LSYNC1_R R328 0
FDI_LSYNC1 FDI_LSYNC1 3 DSWODVREN R336 330K
A18 DSWODVREN R337 330K/NC

DSWVRMEN R329 0 -PM_RSMRST_R
System Power Management

R314 0/NC -SUSACK_R C12 E22
-SUSACK SUSACK# DPWROK PCH_DPWROK
C
48 -PM_SYSRST
R315 0 -PM_SYSRST_R K3
SYS_RESET# WAKE#
B9
-PCIE_WAKE 25,26,30 DSWODVREN - On Die DSW VR Enable C
HIGH ENABLED(DEFAULT)
P12 N3
37,48 SYS_PWROK SYS_PWROK CLKRUN# / GPIO32 -PM_CLKRUN 24
LOW DISABLED
L22 G8
24,38 PM_PCH_PWROK PWROK SUS_STAT# / GPIO61 -PM_SUS_STAT 24
R321 0
R316 0/NC APWROK_R L10 N14

PM_APWROK APWROK SUSCLK / GPIO62 SUS_CLK
B13 D10 -SLP_S5_R R330 0

4 PM_DRAM_PWRGD DRAMPWROK SLP_S5# / GPIO63 -PM_SLP_S5 24
R317 0 -PM_RSMRST_R C21 H4 -SLP_S4_R R331 0

24,48 -PM_RSMRST RSMRST# SLP_S4# -PM_SLP_S4 24,34
R318 0 SUS_PWR_ACK_R K16 F4 -SLP_S3_R R332 0

24 SUS_PWR_ACK SUSWARN#/SUSPWRDNACK/GPIO30 SLP_S3# -PM_SLP_S3 24,32,33,34,35
48 -PM_PWRBTN_R
R319 0 E20 G10 -SLP_A_R R333 0/NC
24 -PM_PWRBTN PWRBTN# SLP_A#
24 AC_PRESENT
R320 0 AC_PRESENT_R H20
ACPRESENT / GPIO31 SLP_SUS#
G16 -SLP_DSW_R R334 0
-PM_SLP_SUS 24
ADD -PM_SLP_SUS TO EC
R322 0 -PM_BATLOW_R E10 AP14

24 -PM_BATLOW BATLOW# / GPIO72 PMSYNCH H_PM_SYNC 4
B B
A10 K14 -SLP_LAN_R R335 0
-PM_RI RI# SLP_LAN# / GPIO29 -PM_SLP_LAN
4,14,15,18,19,21,24,25,26,28,30,33,34,37,44,46,48 +V3.3A
If not using integrated LAN, SLP_LAN signal may be left as NC.
CougarPoint_Rev_1p0
APWROK: -PM_RI R338 10K

For platforms not supporting Intel AMT
it can be connected to PWROK. 4,10,11,12,13,14,15,17,18,19,20,21,23,24,25,26,31,32,33,37,38,41,44,46,48 +V3.3S
-PCIE_WAKE R373 1K
4,10,11,12,13,14,15,17,18,19,20,21,23,24,25,26,31,32,33,37,38,41,44,46,48 +V3.3S R382 10K
AC_PRESENT
-PM_CLKRUN R376 8.2K
SUS_PWR_ACK R452 10K

R865 -PM_RSMRST_R R391 10K
SUS_PWR_ACK_R R323 0 -SUSACK_R 8.2K -PM_BATLOW_R R453 8.2K
-PM_SLP_LAN R454 10K
-PM_SYSRST_R
A
PCH 3/9--DMI,FDI,GPIO


E450 16 of 50
5 4 3 2 1
5 4 3 2 1
U2D
J47 AP43
13 L_BKLT_EN M45 L_BKLTEN SDVO_TVCLKINN AP45
13 LVDS_VDD_EN L_VDD_EN SDVO_TVCLKINP
P45 AM42
13 L_BKLT_CTRL L_BKLTCTL SDVO_STALLN AM40
D
T40 SDVO_STALLP D
13 LVDS_DDC_CLK K47 L_DDC_CLK AP39
13 LVDS_DDC_DATA L_DDC_DATA SDVO_INTN AP40
T45 SDVO_INTP
L_CTRL_CLK P39 L_CTRL_CLK
L_CTRL_DATA L_CTRL_DATA
AF37 P38
LVDS_VBG AF36 LVD_IBG SDVO_CTRLCLK M39
LVD_VBG SDVO_CTRLDATA
R339 AE48
AE47 LVD_VREFH AT49
2.37K/1% LVD_VREFL DDPB_AUXN AT47
DDPB_AUXP AT40 DPB_HPD_Q
AK39 DDPB_HPD
LVDS
13 LA_CLKN AK40 LVDSA_CLK# AV42
13 LA_CLKP LVDSA_CLK DDPB_0N AV40
AN48 DDPB_0P AV45
13 LA_DATAN0 AM47 LVDSA_DATA#0 DDPB_1N AV46
Digital Display Interface

13 LA_DATAN1 AK47 LVDSA_DATA#1 DDPB_1P AU48
13 LA_DATAN2 AJ48 LVDSA_DATA#2 DDPB_2N AU47
LVDSA_DATA#3 DDPB_2P AV47
AN47 DDPB_3N AV49
13 LA_DATAP0 AM49 LVDSA_DATA0 DDPB_3P
13 LA_DATAP1 AK49 LVDSA_DATA1
13 LA_DATAP2 AJ47 LVDSA_DATA2 P46
LVDSA_DATA3 DDPC_CTRLCLK P42
DDPC_CTRLDATA
AF40
AF39 LVDSB_CLK# AP47
LVDSB_CLK DDPC_AUXN AP49
C C
AH45 DDPC_AUXP AT38 DPC_HPD_Q
AH47 LVDSB_DATA#0 DDPC_HPD
AF49 LVDSB_DATA#1 AY47
AF45 LVDSB_DATA#2 DDPC_0N AY49
LVDSB_DATA#3 DDPC_0P AY43
AH43 DDPC_1N AY45
AH49 LVDSB_DATA0 DDPC_1P BA47
AF47 LVDSB_DATA1 DDPC_2N BA48
AF43 LVDSB_DATA2 DDPC_2P BB47
LVDSB_DATA3 DDPC_3N BB49
DDPC_3P
N48 M43
12 CRT_BLUE CRT_BLUE DDPD_CTRLCLK HDMID_CTRL_CLK 31
P49 M36
12 CRT_GREEN CRT_GREEN DDPD_CTRLDATA HDMID_CTRL_DATA 31
T49
12 CRT_RED CRT_RED
AT45
CRT
T39 DDPD_AUXN AT43
12 CRT_DDC_CLK M40 CRT_DDC_CLK DDPD_AUXP BH41 DPD_HPD_Q
CRT_DDC_DATA DDPD_HPD -TMDSB_DATA2 C370 0.1uF
12 CRT_DDC_DATA -FLT_HDMI_TX2_L 31
-TMDSB_DATA1 C369 0.1uF
BB43 -TMDSB_DATA2 -TMDSB_DATA0 C359 0.1uF
. -FLT_HDMI_TX1_L 31
R340 33 HSYNC M47 DDPD_0N BB45 TMDSB_DATA2 -FLT_HDMI_TX0_L 31
CRT_HSYNC DDPD_0P -TMDSB_CLK C366 0.1uF
.
12 CRT_HSYNC R341 33 VSYNC M49 BF44 -TMDSB_DATA1 -FLT_HDMI_CLK_L 31
CRT_VSYNC DDPD_1N .
12 CRT_VSYNC BE44 TMDSB_DATA1
DDPD_1P .
BF42 -TMDSB_DATA0
T43 DDPD_2N BE42 TMDSB_DATA0
T42 DAC_IREF DDPD_2P BJ42 -TMDSB_CLK
CRT_IRTN DDPD_3N TMDSB_DATA2 C139 0.1uF
BG42 TMDSB_CLK TMDSB_DATA1 C355 0.1uF FLT_HDMI_TX2_L 31
DDPD_3P FLT_HDMI_TX1_L 31
B
TMDSB_DATA0 C136 0.1uF
. B
R342 CougarPoint_Rev_1p0 TMDSB_CLK C150 0.1uF
. FLT_HDMI_TX0_L 31
1K/0.5% . FLT_HDMI_CLK_L 31
.
0,11,12,13,14,15,16,18,19,20,21,23,24,25,26,31,32,33,37,38,41,44,46,48 +V3.3S DPC_HPD_Q

DPB_HPD_Q
R399
R407
100K/NC
100K/NC
R730 R731
NOTE
2.2K 2.2K
L_CTRL_CLK
L_CTRL_DATA
4,10,11,12,13,14,15,16,18,19,20,21,23,24,25,26,31,32,33,37,38,41,44,46,48 +V3.3S
R408

1
A 1M A
R414 150/1%
CRT_BLUE
DPD_HPD_Q 2 3
R415 150/1% HDMID_HPD 31
CRT_GREEN
CRT_RED R416 150/1% Q9 BSS138 PCH 4/9-LVDS,DDI


E450 17 of 50
5 4 3 2 1
5 4 3 2 1
U2E
AY7 4,10,11,12,13,14,15,16,17,19,20,21,23,24,25,26,31,32,33,37,38,41,44,46,48 +V3.3S
RSVD1 AV7
TP1_PCH BG26 RSVD2 AU3
TP2_PCH BJ26 TP1 RSVD3 BG4
TP3_PCH BH25 TP2 RSVD4
TP4_PCH BJ16 TP3 AT10
TP5_PCH BG16 TP4 RSVD5 BC8 -DGPU_PWR_EN R360 10K
TP6_PCH AH38 TP5 RSVD6 -DGPU_HOLD_RST R361 10K
TP7_PCH AH37 TP6 AU2 -DGPU_SELECT R363 10K
TP8_PCH AK43 TP7 RSVD7 AT4 -EDID_SELECT R366 10K/NC
TP9_PCH AK45 TP8 RSVD8 AT3
D TP9 RSVD9 4,10,11,12,13,14,15,16,17,19,20,21,23,24,25,26,31,32,33,37,38,41,44,46,48 +V3.3S D
TP10_PCH C18 AT1
TP11_PCH N30 TP10 RSVD10 AY3 -DGPU_PWM_SELECT
R365 10K/NC
TP12_PCH H3 TP11 RSVD11 AT5
TP13_PCH AH12 TP12 RSVD12 AV3
TP14_PCH AM4 TP13 RSVD13 AV1
TP15_PCH AM5 TP14 RSVD14 BB1 -INT_PIRQA R354 8.2K
TP16_PCH Y13 TP15 RSVD15 BA3 -INT_PIRQB R355 8.2K
TP17_PCH K24 TP16 RSVD16 BB5 -INT_PIRQC R356 8.2K
TP18_PCH L24 TP17 RSVD17 BB3 -INT_PIRQD R357 8.2K
TP19_PCH AB46 TP18 RSVD18 BB7
TP20_PCH AB45 TP19 RSVD19 BE8 -MPC_PWR_CTRL R359 10K
RSVD
TP20 RSVD20 BD4 -SATA_ODD_DA R362 10K
RSVD21 BF6
RSVD22
19,20 +V_NVRAM_VCCQ 库和公板对不上 -NV_R_B R353 10K
TP21_PCH B21 AV5 NV_ALE
TP22_PCH M20 TP21 RSVD23 AV10 NV_RCOMP
TP23_PCH AY16 TP22 RSVD24
TP24_PCH BG46 TP23 AT8 -NV_R_B
R798 TP24 RSVD25 R437
1K/NC AY5 32.4/1%
RSVD26 BA2
TP25_PCH BE28 RSVD27
TP26_PCH BC30 TP25 AT12
TP27_PCH BE32 TP26 RSVD28 BF3
NV_ALE TP28_PCH BJ32 TP27 RSVD29
TP29_PCH BC28 TP28
TP30_PCH BE30 TP29
TP31_PCH BF32 TP30
TP31
Dabury Technology Enabled TP32_PCH BG32
TP32 USBP0N
C24
USB_PN0
C TP33_PCH AV26 A24 C
TP33 USBP0P USB_PP0
TP34_PCH BB26 C25
TP34 USBP1N USB_PN1 43
NV_ALE High = Enabled TP35_PCH AU28
TP35 USBP1P
B25
USB_PP1 43
Low = Disabled (default TP36_PCH AY30 C26
TP37_PCH AU26 A26
TP37 USBP2P USB_PP2 26
TP38_PCH AY26 K28
TP39_PCH AV28 H28
TP39 USBP3P USB_PP3 13
TP40_PCH AW30 E28
D28
USBP4P USB_PP4 25
C28
USBP5N USB_PN5 29
A28
USBP5P USB_PP5 29
A16 swap override Strap--(R344) USBP6N
C29
USB_PN6
B29
USBP6P USB_PP6
-INT_PIRQA K40 N28
PIRQA# USBP7N USB_PN7
Low = A16 swap -INT_PIRQB K38 M28
PCI
PIRQB# USBP7P USB_PP7
STP_A16OVR override -INT_PIRQC H38
PIRQC# USBP8N
L30
USB_PN8 44
PCI_GNT#3 -INT_PIRQD G38 K30
High = Default PIRQD# USBP8P G30
USB_PP8 44
USBP9N USB_PN9 44
C46 E30
USB
-DGPU_HOLD_RST REQ1# / GPIO50 USBP9P USB_PP9 44
C44 C30
-DGPU_SELECT REQ2# / GPIO52 USBP10N USB_PN10 44
E40 A30
-DGPU_PWR_EN REQ3# / GPIO54 USBP10P USB_PP10 44
L32
USBP11N USB_PN11 44
BBS_BIT1 D47 K32
-EDID_SELECT GNT1# / GPIO51 USBP11P USB_PP11 44
E42 G32
-DGPU_PWM_SELECT GNT2# / GPIO53 USBP12N USB_PN12
STP_A16OVR F46 E32
GNT3# / GPIO55 USBP12P USB_PP12
C32
USBP13N USB_PN13
R344 A32
USBP13P USB_PP13
-MPC_PWR_CTRL_J R345 0/NC -MPC_PWR_CTRL G42
G40 PIRQE# / GPIO2
-SATA_ODD_DA PIRQF# / GPIO3
1K/NC R346 C42 C33 USB_BIAS R435
B EXTTS_SNI_DRV0_PCH PIRQG# / GPIO4 USBRBIAS# B
D44
EXTTS_SNI_DRV1_PCH PIRQH# / GPIO5 22.6/1%
1K B33
K10 USBRBIAS
-PCI_PME PME#
0 R762 14 BBS_BIT0
R737 0 C6 A14 BBS_BIT1
4,48 -PLT_RST PLTRST# OC0# / GPIO59 K20 10K R760 -USB_OC0 43
OC1# / GPIO40 B17 10K R758 R343 R248
Ver02 CLK_PCI_SIO_R H49 OC2# / GPIO41 C16 10K R759
R352 22 CLK_PCI_TPM_R H43 CLKOUT_PCI0 OC3# / GPIO42 L16 0 R757 1k/NC
24 CLK_PCI_EC_REF R349 22 CLK_PCI_FB_R J48 CLKOUT_PCI1 OC4# / GPIO43 A16 10K R750 -USB_OC4 44 1K/NC
15 CLK_PCI_FB R350 22 CLK_PCI_LPC_R K42 CLKOUT_PCI2 OC5# / GPIO9 D14 10K R749
44 CLK_PCI_LPC R351 22 CLK_PCI_KBC_R H40 CLKOUT_PCI3 OC6# / GPIO10 C14 0 R746
24 CLK_PCI_KBC CLKOUT_PCI4 OC7# / GPIO14 -EC_WAKE_SCI 24
CougarPoint_Rev_1p0
4,10,11,12,13,14,15,16,17,19,20,21,23,24,25,26,31,32,33,37,38,41,44,46,48 +V3.3S 4,14,15,16,19,21,24,25,26,28,30,33,34,37,44,46,48 +V3.3A BBS_BIT1 BBS_BIT0 Boot BIOS Location
0 0 LPC
0 1 RESERVED
1 0 ----------
R345 - MPC Switch Control 1 1 SPI
C289
MPC OFF -- (NoStuff) DEFAULT
MPC ON -- (Stuff) 0.1uF
A U3
5
1 -PLT_RST
24,25,26,30,44 -BUF_PLT_RST 4
2
PCH 5/9--PCI,USB,NVRAM
R481
3
74AHC1G08
100k

E450 18 of 50
5 4 3 2 1
5 4 3 2 1
PLACE R378 CLOSE TO THE BRANCHING POINT

( TO CPT and NVRAM CONNECTOR) 4,10,11,12,13,14,15,16,17,18,20,21,23,24,25,26,31,32,33,37,38,41,44,46,48 +V3.3S
4,14,15,16,18,21,24,25,26,28,30,33,34,37,44,46,48 +V3.3A
18,20 +V_NVRAM_VCCQ 4,10,11,12,13,14,15,16,17,18,20,21,23,24,25,26,31,32,33,37,38,41,44,46,48 +V3.3S
U2F
-HOST_ALERT1 R485 1k
S_GPIO R364 100 T7 C40 SATA_ODD_PWRGT -HOST_ALERT2 R486 10k
BMBUSY# / GPIO0 TACH4 / GPIO68 PM_LANPHY_ENABLE R833 10K
R436 A42 B41 RSVD_TESTMODE
R457 24 -EC_EXTSMI TACH1 / GPIO1 TACH5 / GPIO69
2.2K
1K/NC -DGPU_HPD_INTR H36 C41 R490 1.5K 4,10,11,12,13,14,15,16,17,18,20,21,23,24,25,26,31,32,33,37,38,41,44,46,48 +V3.3S
TACH2 / GPIO6 TACH6 / GPIO70
E38 A40 R495 1.5K
D 24 -EC_RUNTIME_SCI TACH3 / GPIO7 TACH7 / GPIO71 D
-H_RCIN R489 10k
R378 1K NV_CLE -ICC_EN C10
4 -H_SNB_IVB GPIO8 -EC_EXTSMI R502 10k
PM_LANPHY_ENABLE C4 -CRIT_TEMP_REP R491 10k
LAN_PHY_PWR_CTRL / GPIO12 -SATA_DET4 R492 10k
DMI & FDI Termination Voltage G2 P4 -EC_RUNTIME_SCI R574 10k
26 -HOST_ALERT1 GPIO15 A20GATE H_A20GATE 24 PECI_EC 4,24
AU16 H_PECI_R R372 0/NC
PECI H_PECI 4,24
Set to Vss when LOW -SATA_DET4 U2
SATA4GP / GPIO16
NV_CLE Set to Vcc when HIGH RCIN#
P5
-H_RCIN 24 -DGPU_HPD_INTR R498 10k
GPIO
DGPU_PWROK R577 10k
DGPU_PWROK D40 AY11
CPU/MISC
TACH0 / GPIO17 PROCPWRGD H_CPUPWRGD 4,48
BIOS_REC T5 AY10 -PCH_THRMTRIP_R R375 392
SCLOCK / GPIO22 THRMTRIP# -H_THRMTRIP 4
-HOST_ALERT2 E8 T14 -INIT3_3V -SATA_PWR_EN0 R379 10K/NC
GPIO24 / MEM_LED INIT3_3V#
-SATA_PWR_EN0 E16 AY1 NV_CLE GPIO27:
GPIO27 DF_TVS Can be configured as wake input to allow wakes from Deep Sleep.
P8 If not used then use 8.2-kΩ to 10-kΩ pull-down to GND.
PLL_ODVR_EN GPIO28 AH8 PCH_TS_VSS1 R377 0
7,38,41,44,46,48 +V3.3S TS_VSS1
K1 4,14,15,16,18,21,24,25,26,28,30,33,34,37,44,46,48 +V3.3A
23 -STP_PCI STP_PCI# / GPIO34 AK11 PCH_TS_VSS2 R380 0
TS_VSS2
K4
GPIO35
R619 10k GPIO8 is no longer ICC strap
R834 AH10 PCH_TS_VSS3 R381 0
TEST MODE SETUP -SATA_ODD_PRSNT V8 TS_VSS3
10K R482 NC DEFAULT SATA2GP / GPIO36 AK10 PCH_TS_VSS4 R409 0
FDI_OVRVLTG M5 TS_VSS4 -ICC_EN R383 1K/NC
RSVD_TESTMODE SATA3GP / GPIO37
C MFG_MODE N2 P37 C
SLOAD / GPIO38 NC_1
R482 GFX_CRB_DET M3 R384 0/NC
SDATAOUT0 / GPIO39
10K/NC 4,14,15,16,18,21,24,25,26,28,30,33,34,37,44,46,48 +V3.3A R383 - Integrated Clock Chip Enable
TEST_SET_UP V13 BG2
SDATAOUT1 / GPIO48 VSS_NCTF_15
24 -CRIT_TEMP_REP
R371 0 V3
SATA5GP / GPIO49 VSS_NCTF_16
BG48 HIGH (R383 - NC)- DISABLED [DEFAULT]
C121 ICC_EN# LOW (R383 - STUFF)- ENABLED
TEST_DET D6 BH3
GPIO57 VSS_NCTF_17 0.1U/NC
BH47 C0402
VSS_NCTF_18
U4
5
A4 BJ4
VSS_NCTF_1 VSS_NCTF_19 1
37 CK_PWRGD_R
A44 BJ44 4
VSS_NCTF_2 VSS_NCTF_20 -ICC_EN 2 CK505_PWRGD 23
A45 BJ45
VSS_NCTF_3 VSS_NCTF_21
R487
NCTF
4,10,11,12,13,14,15,16,17,18,20,21,23,24,25,26,31,32,33,37,38,41,44,46,48 +V3.3S
3
A46 BJ46 74AHC1G08/NC
VSS_NCTF_4 VSS_NCTF_22 1K/NC
A5 BJ5
R503 A6 BJ6
10K B3 C2
R388 0/NC TEST_SET_UP VSS_NCTF_7 VSS_NCTF_25
B47
C48 PLL ON DIE VR ENABLE
BD1 D1 PLL_ODVR_EN R385 1K/NC PLL_ODVR_EN ENABLED -- HIGH (R385 NC) DEFAULT
B DISABLED -- LOW (R385 STUFF) B
Configurable CPU output buffer BD49
D49
High = Strong (Default) BE1

E1
TEST_SET_UP Low = Weak BE49 E49
BF1 F1
4,10,11,12,13,14,15,16,17,18,20,21,23,24,25,26,31,32,33,37,38,41,44,46,48 +V3.3S
BF49 F49 4,10,11,12,13,14,15,16,17,18,20,21,23,24,25,26,31,32,33,37,38,41,44,46,48 +V3.3S
3,37,38,41,44,46,48 +V3.3S CougarPoint_Rev_1p0 FDI_OVRVLTG R386 1K/1%/NC -SATA_ODD_PRSNT R387 200K/1%
4,14,15,16,18,21,24,25,26,28,30,33,34,37,44,46,48 +V3.3A R488

100K FDI TERMINATION VOLTAGE OVERRIDE DMI TERMINATION VOLTAGE OVERRIDE
R493 4,10,11,12,13,14,15,16,17,18,20,21,23,24,25,26,31,32,33,37,38,41,44,46,48 +V3.3S
10K/NC GPIO37 LOW - Tx, Rx terminated LOW - Tx, Rx terminated
R497
(FDI_OVRVLTG) to same voltage GPIO36 to same voltage
10K/NC (DC Coupling Mode) (SATA_ODD_PRSNT#) (DC Coupling Mode)
4,10,11,12,13,14,15,16,17,18,20,21,23,24,25,26,31,32,33,37,38,41,44,46,48 +V3.3S
4,10,11,12,13,14,15,16,17,18,20,21,23,24,25,26,31,32,33,37,38,41,44,46,48 +V3.3S R506 DEFAULT DEFAULT
GFX_CRB_DET
TEST_DET 10K
R501
R494
10K MFG_MODE
R505
100K
R499
1K/1%
R507
A
100K BIOS_REC
S_GPIO
0/NC HASEE TECHNOLOGY INC., A
R500 - BIOS RECOVERY

R500 DISABLE -- (NC) DEFAULT(high)
INTERNAL GFX EXTERNAL GFX
0/NC ENABLE -- (STUFF)low R504 R504 - SGPIO PCH 6/9--GPIO,VSS
0/NC (NC) DEFAULT
STUFF R494 R493
UNSTUFF Custom <Cage Code> 0.2
R493 R494
E120 19 of 50
5 4 3 2 1
5 4 3 2 1
4,10,11,12,13,14,15,16,17,18,19,21,23,24,25,26,31,32,33,37,38,41,44,46,48 +V3.3S
R513
0/NC
21,23,32,35,48 +V1.05S +VCCA_DAC_1_2 +V3.3G_LDO
+V1.05S_PCH_VCC U2G POWER FB10 R0402
R636 C297 C296

0
AA23 U48 0.1uF
C298 300Z@100MHz,1A ??A
AC23 VCCCORE[1] VCCADAC
0.01uF FB0603
R0805 VCCCORE[2]
CRT
C293 C308 C307 C306 AD21 10U
D
C0402 C0402 C0402 AD23 VCCCORE[3] U47 C0603 D
VCCCORE[4] VSSADAC
1.3A
VCC CORE
10uF C0603 1.0uF 1.0uF 1.0uF AF21 C0402 C0402 4,10,11,12,13,14,15,16,17,18,19,21,23,24,25,26,31,32,33,37,38,41,44,46,48 +V3.3S
AF23 VCCCORE[5]
AG21 VCCCORE[6]
AG23 VCCCORE[7]
AG24 VCCCORE[8] AK36 V3.3S_VCCA_LVD 0 R527
AG26 VCCCORE[9] VCCALVDS
AG27 VCCCORE[10] AK37 R0402
AG29 VCCCORE[11] VSSALVDS
VCCCORE[12] 7,34 +V1.8S
AJ23
LVDS
AJ26 VCCCORE[13] AM37
AJ27 VCCCORE[14] VCCTX_LVDS[1]
AJ29 VCCCORE[15] AM38 +VCC_TX_LVDS L506 0.1UH
AJ31 VCCCORE[16] VCCTX_LVDS[2] L0603 COMMON
VCCCORE[17]
21,23,32,35,48 +V1.05S +V1.05S_PCH_VCCDPLL_EXP VCCTX_LVDS[3]
AP36 C311
C0402
C310
C0402
C299
0.06A
R508 0 AP37 0.01uF 0.01uF 22U C0805
AN19 VCCTX_LVDS[4]
VCCIO[28]
21,23,32,35,48 +V1.05S R0603 +V1.05S_VCCAPLL_EXP
FB16 4,10,11,12,13,14,15,16,17,18,19,21,23,24,25,26,31,32,33,37,38,41,44,46,48 +V3.3S
BJ22
NO STUFF VCCAPLLEXP
C309 V33
HVCMOS
AN16 VCC3_3[6]
50OHM/NC VCCIO[15] 0
V3.3S_VCC_GIO R529
. 10uF/NC C0603
AN17
VCCIO[16] R0603
VCC3_3[7]
V34 C302
0.266A
21,23,32,35,48 +V1.05S AN21 0.1uF
16 +V1.05S_VCC_EXP VCCIO[17] C0402
C C
R604 0 AN26
VCCIO[18]
3,4,6,13,21,24,32,36,48 +V1.05S_VCCP
C301 C290 C292 C294 AN27 AT16 +VCCAFDI_VRM
R1206 C300 VCCIO[19] VCCVRM[3]
+V1.05S_VCC_DMI
AP21
1.0uF 1.0uF 1.0uF 1.0uF VCCIO[20]
2.925A 10uF
C0402
C0402 C0402 C0402
AP23
VCCIO[21] VCCDMI[1]
AT20 0 R530
C0603
DMI
R0603 21,23,32,35,48 +V1.05S
AP24 C303
VCCIO
VCCIO[22]
AP26 AB36 1.0uF +V1.05S_VCC_DMI_CCI
VCCIO[23] VCCCLKDMI C0402
AT24 C304 R0402
VCCIO[24] L507 10UH/NC
+VCC_DMI_CCI_R 0/NC R579
1.0uF C305 L0603 COMMON
AN33 C0402 0 R532
VCCIO[25]
10uF/NC C0603 R0402
16,17,18,19,21,23,24,25,26,31,32,33,37,38,41,44,46,48 +V3.3S +V3.3S_VCCA3GBG AN34 AG16
VCCIO[26] VCCDFTERM[1]
R509 0 18,19 +V_NVRAM_VCCQ 7,34 +V1.8S
BH29 AG17
DFT / SPI
VCC3_3[3] VCCDFTERM[2]
R0603 C295
AJ16 0 R533
21,23,32,35,48 +V1.05S VCCDFTERM[3]
0.1uF R0805
R639 0/NC C0402 +VCCAFDI_VRM AP16 C312
VCCVRM[2] AJ17
+V1.05S_VCCAPLL_FDI VCCDFTERM[4]
R0402 0.1uF
21,23,32,35,48 +V1.05S BG6 C04024,10,11,12,13,14,15,16,17,18,19,21,23,24,25,26,31,32,33,37,38,41,44,46,48 +V3.3S
B VccAFDIPLL B
+V1.05S_VCCDPLL_FDI
R510 0
AP17
VCCIO[27] 0
FDI
V1 +V3.3M_VCCPSPI R534
R0603 +V1.05S_VCC_DMI VCCSPI
AU20 C313 R0402
VCCDMI[2]
1.0uF
CougarPoint_Rev_1p0 C0402
+V5S 12,13,15,21,28,29,31,32,33,34,36,37,38,41,42,43,44 21 +VCCAFDI_VRM

Q34
+V3.3G_LDO
2 25,26,32,34 +V1.5S
VOUT1
ADJ
3 4
VIN VOUT2
R629 0
1
LM1117_ADJ R389 C393 7,34 +V1.8S

sot223-4 200
R0402 10uF R601 R0402 0/NC
C0603
A
R390
21,23,32,35,48 +V1.05S R625 R0402 0/X HASEE TECHNOLOGY INC., A
330 NO STUFF
R0402
R0402
PCH 7/9--POWER1


E450 20 of 50
5 4 3 2 1
5 4 3 2 1
20,23,32,35,48 +V1.05S
Note: C315 - STUFFED ONLY FOR CPT INTERPOSER;
UNSTUFF FOR CPT 4,14,15,16,18,19,24,25,26,28,30,33,34,37,44,46,48
20,23,32,35,48
+V3.3A
+V1.05S
U2J POWER +V1.05S_VCCUSBCORE
R535 R0402 0/NC +VCCACLKAD49 N26 R546 0

24,27,28,33 +V3.3A_KSC VCCACLK VCCIO[29]
R536R0402 0 P26 C335 R0402
R537R0402 0/NC +VCCPDSW T16 VCCIO[30]
VCCDSW3_3 P28
VCCIO[31] 1.0uF
C314 C0402
PCH_VCCDSW V12 T27
C315 DCPSUSBYP VCCIO[32]
0.1uF 4,14,15,16,18,19,24,25,26,28,30,33,34,37,44,46,48 +V3.3A
D 20,23,32,35,48 +V1.05S C0402 T29 D
+V3.3S_VCC_CLKF33 T38 VCCIO[33]
0.1uF/NC VCC3_3[5]
T23 +V3.3A_VCCPUSB R547 0
L508 10UH/NC +VCCAPLL_CPY_PCH BH23 VCCSUS3_3[7]
20,23,32,35,48 +V1.05S VCCAPLLDMI2 R0402
L0603 COMMON
+VCCDPLL_CPY T24 C336 C337
C316 R539 0 AL29 VCCSUS3_3[8]
VCCIO[14] V23
USB
R0402 VCCSUS3_3[9] 0.1uF 0.1uF 4,14,15,16,18,19,24,25,26,28,30,33,34,37,44,46,48 +V3.3A
10uF/NC
C0603 +VCCSUS1 AL24 V24
DCPSUS[3] VCCSUS3_3[10]
2
C317 P24 20,23,32,35,48 +V1.05S
VCCSUS3_3[6] D3
BAT54S
1.0uF/NC AA19
C0402 VCCASW[1] T26 +VCCAUPLL R549 0
AA21 VCCIO[34] 33,34,35,37 +V5A
3
VCCASW[2] R0402
AA24 M26 +V5A_PCH_VCC5REFSUS R684 10
VCCASW[3] V5REF_SUS
4,10,11,12,13,14,15,16,17,18,19,20,23,24,25,26,31,32,33,37,38,41,44,46,48 +V3.3S
Clock and Miscellaneous

AA26
VCCASW[4] AN23 +VCCA_USBSUS
DCPSUS[4]
2
AA27 0.1uF
VCCASW[5] AN24 +V3.3A_VCCPSUS C339 C338 D4
VCCSUS3_3[1] BAT54S
AA29
VCCASW[6] 1.0uF/NC
AA31 12,13,15,20,28,29,31,32,33,34,36,37,38,41,42,43,44 +V5S
3
VCCASW[7]
AC26 P34 +V5S_PCH_VCC5REF R685 10
+V1.05M_VCCASW VCCASW[8] V5REF
20,23,32,35,48 +V1.05S 1.01A AC27
VCCASW[9]
C340
N20 4,14,15,16,18,19,24,25,26,28,30,33,34,37,44,46,48 +V3.3A 0.1uF
PCI/GPIO/LPC
R540 0 AC29 VCCSUS3_3[2]
VCCASW[10] N22 +V3.3A_VCCPSUS R686 0
R0805 C322 C321 C320 C319 C318 AC31 VCCSUS3_3[3]
VCCASW[11] P20 C341
C
AD29 VCCSUS3_3[4] C
22U 22U 1.0uF 1.0uF 1.0uF VCCASW[12] 1.0uF
C0805 C0805 C0402 C0402 C0402 P22
AD31 VCCSUS3_3[5] 4,10,11,12,13,14,15,16,17,18,19,20,23,24,25,26,31,32,33,37,38,41,44,46,48 +V3.3S
VCCASW[13]
W21 AA16 R687 0
VCCASW[14] VCC3_3[1]
W23 W16 C342
VCCASW[15] VCC3_3[8]
W24 T34 0.1uF
VCCASW[16] VCC3_3[4] C343
W26
VCCASW[17] 0.1uF
W29 4,10,11,12,13,14,15,16,17,18,19,20,23,24,25,26,31,32,33,37,38,41,44,46,48 +V3.3S
VCCASW[18]
W31 AJ2
VCCASW[19] VCC3_3[2] C344 20,23,32,35,48 +V1.05S
W33 14 +V1.05S_SATA3
VCCASW[20] AF13 0.1uF
VCCIO[5]
R689 0 20,23,32,35,48 +V1.05S
+VCCRTCEXT N16
DCPRTC AH13
20 +VCCAFDI_VRM VCCIO[12]
C323
Y49 AH14 C345 L509 10UH/NC
VCCVRM[4] VCCIO[13] C346 L0603 COMMON
0.1uF 1.0uF
C0402
AF14 10uF/NC
+V1.05S_VCCA_A_DPL BD47 VCCIO[6]
SATA
3,32,35,48 +V1.05S VCCADPLLA AK1 +V1.05S_VCCAPLL_SATA3
+V1.05S_VCCA_B_DPL BF47 VCCAPLLSATA
R541R0402 0 +VCCDIFFCLK VCCADPLLB
C32420,23,32,35,48 +V1.05S 15 +VCCDIFFCLKN AF11 +VCCAFDI_VRM 20,23,32,35,48 +V1.05S
AF17 VCCVRM[1]
VCCIO[7] 14 +V1.05S_VCC_SATA
R542R0603 0 AF33
1.0uF VCCDIFFCLKN[1] R691 0
C0402 C325 AF34 AC16
AG34 VCCDIFFCLKN[2] VCCIO[2] C347
B B
VCCDIFFCLKN[3] AC17
1.0uF +V1.05S_SSCVCC VCCIO[3] 1.0uF
C0402
R543R0402 0 AG33 AD17
C326 VCCSSC VCCIO[4]
C327
20,23,32,35,48 +V1.05S 1.0uF VCCSST V16 20,23,32,35,48 +V1.05S
C0402 DCPSST
0.1uF
C0402
R544R0402 0/NC V1.05M_VCCSUS T17 T21 R692 0
C328 V19 DCPSUS[1] VCCASW[22]
MISC
DCPSUS[2]
3,4,6,13,20,24,32,36,48 +V1.05S_VCCP
+V1.05S_VCCPCPU 1.0uF V21
VCCASW[23]
CPU
R545R0402 0 BJ8
C331 C330 C329 V_PROC_IO T19
VCCASW[21]
14,16 +V3.3A_RTC 4,14,15,16,18,19,24,25,26,28,30,33,34,37,44,46,48 +V3.3A
4.7uF 0.1uF 0.1uF +V3.3A_1.5A_VCCPAZSUS
R695 0
RTC
A22 P32
HDA
VCCRTC VCCSUSHDA
C348
C332 C333 C334 CougarPoint_Rev_1p0
0.1uF
0.1uF 0.1uF 1.0uF

C0402 C0402 C0402
20,23,32,35,48 +V1.05S
46,48 +V3.3S
A R662 A
0 VCCA_DPLL_R1 L510 10UH+V1.05S_VCCA_A_DPL
R551R0402 0/NC L0603 COMMON PC129 C362 C351
1
1.0uF
220uF/6.3V 10uF/NC
2
R550R0402 0 +V3.3S_VCC_CLKFF33_R1 L512 10UH +V3.3S_VCC_CLKF33

L0603 COMMON
C352 C353 R644
0 VCCA_DPLL_R2 L511 10UH+V1.05S_VCCA_B_DPL PCH 8/9--POWER2
10uF 1uF L0603 COMMON C349 C350
1
C0603 C0402 PC130

220uF/6.3V 10uF/NC 1.0uF
2

E450 21 of 50
5 4 3 2 1
5 4 3 2 1
U2I
AY4 H46
AY42 VSS[159] VSS[259] K18
AY46 VSS[160] VSS[260] K26
AY8 VSS[161] VSS[261] K39
B11 VSS[162] VSS[262] K46
B15 VSS[163] VSS[263] K7
B19 VSS[164] VSS[264] L18
B23 VSS[165] VSS[265] L2
U2H B27 VSS[166] VSS[266] L20
H5 B31 VSS[167] VSS[267] L26
VSS[0] B35 VSS[168] VSS[268] L28
D
AA17 AK38 B39 VSS[169] VSS[269] L36 D
AA2 VSS[1] VSS[80] AK4 B7 VSS[170] VSS[270] L48
AA3 VSS[2] VSS[81] AK42 F45 VSS[171] VSS[271] M12
AA33 VSS[3] VSS[82] AK46 BB12 VSS[172] VSS[272] P16
AA34 VSS[4] VSS[83] AK8 BB16 VSS[173] VSS[273] M18
AB11 VSS[5] VSS[84] AL16 BB20 VSS[174] VSS[274] M22
AC19 VSS[12] VSS[91] AL27 BB46 VSS[181] VSS[281] M42
AC2 VSS[13] VSS[92] AL31 BC14 VSS[182] VSS[282] M46
AC21 VSS[14] VSS[93] AL33 BC18 VSS[183] VSS[283] M8
AC24 VSS[15] VSS[94] AL34 BC2 VSS[184] VSS[284] N18
AC33 VSS[16] VSS[95] AL48 BC22 VSS[185] VSS[285] P30
AC34 VSS[17] VSS[96] AM11 BC26 VSS[186] VSS[286] N47
AC48 VSS[18] VSS[97] AM14 BC32 VSS[187] VSS[287] P11
AD10 VSS[19] VSS[98] AM36 BC34 VSS[188] VSS[288] P18
AD11 VSS[20] VSS[99] AM39 BC36 VSS[189] VSS[289] T33
AD24 VSS[24] VSS[103] AM7 BD46 VSS[193] VSS[293] P7
AD26 VSS[25] VSS[104] AN2 BD5 VSS[194] VSS[294] R2
AD27 VSS[26] VSS[105] AN29 BE22 VSS[195] VSS[295] R48
AD33 VSS[27] VSS[106] AN3 BE26 VSS[196] VSS[296] T12
AD34 VSS[28] VSS[107] AN31 BE40 VSS[197] VSS[297] T31
AD36 VSS[29] VSS[108] AP12 BF10 VSS[198] VSS[298] T37
C C
AD38 VSS[31] VSS[110] AP28 BF16 VSS[200] VSS[300] W34
AD42 VSS[35] VSS[114] AP4 BF26 VSS[204] VSS[304] V11
AD45 VSS[37] VSS[116] AP46 BD3 VSS[206] VSS[306] V26
AD8 VSS[39] VSS[118] AR2 BF38 VSS[208] VSS[308] V29
AE2 VSS[40] VSS[119] AR48 BF40 VSS[209] VSS[309] V31
AE3 VSS[41] VSS[120] AT11 BF8 VSS[210] VSS[310] V36
AF10 VSS[42] VSS[121] AT13 BG17 VSS[211] VSS[311] V39
AF12 VSS[43] VSS[122] AT18 BG21 VSS[212] VSS[312] V43
AD14 VSS[44] VSS[123] AT22 BG33 VSS[213] VSS[313] V7
AD16 VSS[45] VSS[124] AT26 BG44 VSS[214] VSS[314] W17
AF16 VSS[46] VSS[125] AT28 BG8 VSS[215] VSS[315] W19
AF19 VSS[47] VSS[126] AT30 BH11 VSS[216] VSS[316] W2
AF27 VSS[50] VSS[129] AT39 BH19 VSS[219] VSS[319] Y12
AF29 VSS[51] VSS[130] AT42 H10 VSS[220] VSS[320] Y38
AF4 VSS[54] VSS[133] AU24 BH33 VSS[223] VSS[323] Y46
AF42 VSS[55] VSS[134] AU30 BH35 VSS[224] VSS[324] Y8
AF46 VSS[56] VSS[135] AV16 BH39 VSS[225] VSS[325] BG29
AF5 VSS[57] VSS[136] AV20 BH43 VSS[226] VSS[328] N24
AF7 VSS[58] VSS[137] AV24 BH7 VSS[227] VSS[329] AJ3
B
AF8 VSS[59] VSS[138] AV30 D3 VSS[228] VSS[330] AD47 B
AG19 VSS[60] VSS[139] AV38 D12 VSS[229] VSS[331] B43
AG2 VSS[61] VSS[140] AV4 D16 VSS[230] VSS[333] BE10
AG31 VSS[62] VSS[141] AV43 D18 VSS[231] VSS[334] BG41
AG48 VSS[63] VSS[142] AV8 D22 VSS[232] VSS[335] G14
AH11 VSS[64] VSS[143] AW14 D24 VSS[233] VSS[337] H16
AH3 VSS[65] VSS[144] AW18 D26 VSS[234] VSS[338] T36
AH36 VSS[66] VSS[145] AW2 D30 VSS[235] VSS[340] BG22
AH39 VSS[67] VSS[146] AW22 D32 VSS[236] VSS[342] BG24
AH40 VSS[68] VSS[147] AW26 D34 VSS[237] VSS[343] C22
AH42 VSS[69] VSS[148] AW28 D38 VSS[238] VSS[344] AP13
AH46 VSS[70] VSS[149] AW32 D42 VSS[239] VSS[345] M14
AH7 VSS[71] VSS[150] AW34 D8 VSS[240] VSS[346] AP3
AJ19 VSS[72] VSS[151] AW36 E18 VSS[241] VSS[347] AP1
AJ21 VSS[73] VSS[152] AW40 E26 VSS[242] VSS[348] BE16
AJ24 VSS[74] VSS[153] AW48 G18 VSS[243] VSS[349] BC16
AJ33 VSS[75] VSS[154] AV11 G20 VSS[244] VSS[350] BG28
AJ34 VSS[76] VSS[155] AY12 G26 VSS[245] VSS[351] BJ28
AK12 VSS[77] VSS[156] AY22 G28 VSS[246] VSS[352]
AK3 VSS[78] VSS[157] AY28 G36 VSS[247]
VSS[79] VSS[158] G48 VSS[248]
CougarPoint_Rev_1p0 H12 VSS[249]
H18 VSS[250]
H22 VSS[251]
H24 VSS[252]
H26 VSS[253]
H30 VSS[254]
H32 VSS[255]
H34 VSS[256]
A F3 VSS[257]
VSS[258] HASEE TECHNOLOGY INC., A
CougarPoint_Rev_1p0
PCH 9/9--VSS


E450 22 of 50
5 4 3 2 1
5 4 3 2 1
+V3.3S 4,10,11,12,13,14,15,16,17,18,19,20,21,24,25,26,31,32,33,37,38,41,44,46,48
D D
FB29
100ohm@100MHz
FB0805 C187 C190 C200 C192 C205 C195

20,21,32,35,48 +V1.05S R836 10uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
0 10% 10% 10% 10% 10% 10%
R0603 . . . . . .
FB33
100ohm@100MHz/NC
FB0805 C419 C193 C194

10uF 0.1uF 0.1uF
20% 10% 10%
. . .
15
18
29
24
17
1
5
U6
VDDREF_3.3
VDDSRC_IO
VDDCPU_3.3
VDDSRC_3.3
VDDDOT96MHZ_3.3
VDD_27MHZ
VDDCPU_IO
4,10,11,12,13,14,15,16,17,18,19,20,21,24,25,26,31,32,33,37,38,41,44,46,48 +V3.3S
C C
23 R651 33/NC
CPUT0_LPR CLK_BUF_CPYCLK_P 15
R410 0 R400 32 22 R652. 33/NC
10K 10,15,48 SMB_CLK_S SCLK_3.3 CPUC0_LPR CLK_BUF_CPYCLK_N 15
0 R401 31 20 CLK_XDP_ITP_P_R R656. 33/NC
5% 10,15,48 SMB_DATA_S SDATA_3.3 CPUT1_LPR CLK_XDP_ITP_P 9
. 19 CLK_XDP_ITP_N_R R661. 33/NC Add CLK_XDP_ITP_P/CLK_XDP_IT_N
CPUC1_LPR CLK_XDP_ITP_N 9
10 R406. 0
SATAT_LPR CLK_BUF_CKSSCD_P 15
XTAL_IN 28 11 R654. 0
X1 SATAC_LPR CLK_BUF_CKSSCD_N 15
XTAL_OUT 27 13 CLK_BUF_EXP_P_R R515. 33
X2 SRCT1_LPR CLK_BUF_EXP_P 15
14 CLK_BUF_EXP_N_R R516. 33
SRCC1_LPR CLK_BUF_EXP_N 15
3 R403. 0
DOT96T_LPR CLK_BUF_DOT96_P 15
0/NC R908 16 4 R404. 0
19 -STP_PCI CPU_STOP# DOT96C_LPR CLK_BUF_DOT96_N 15
. 25 6 .
19 CK505_PWRGD CLKPWRGD/PD#_3.3 27MHZ_NONSS 7
27MHZ_SS 30 FSLC 10K R188 CPU_FSEL
GNDDOT96MHZ
REF_3L/FSLC_3.3** 5%
GND27MHZ
GNDSATA
5% 33 R190
GNDSRC
GNDCPU
GNDREF
CLK_BUF_REF14 15
PGND
C226
22PF/NC
CHANGE Y2 from SMT to DIP 10%
.
2
8
9
12
21
26
33
package
Y2
XTAL_IN
ICS9LRS3197
2 1 D_14.318MHz XTAL_OUT QFN32__5M
R398
C197 10M/NC C198
27pF 27pF
B B
0603 0603
. .
+V3.3S 4,10,11,12,13,14,15,16,17,18,19,20,21,24,25,26,31,32,33,37,38,41,44,46,48
R166
1K
5%
.
CPU_FSEL
R194
100/NC
5%
CPU frequency setting is 100 MHz

FSLC CPU
A 0
0 133MHZ HASEE TECHNOLOGY INC., A
1 100MHZ
CK505


E450 23 of 50
5 4 3 2 1
5 4 3 2 1
Add C435 for Npce791L +V3.3A_KSC 21,27,28,33

KBC_SCANOUT0
KBC_SCANOUT1
Change C578 to 10UF for 791L
KBC_SCANOUT2 Add R847\C368
KBC_SCANOUT3 +V3.3S 4,10,11,12,13,14,15,16,17,18,19,20,21,23,25,26,31,32,33,37,38,41,44,46,48
KBC_SCANOUT4
KBC_SCANOUT5
R812 0
KBC_SCANOUT6 Place one 0.1uF (X7R) capacitor on each VCC-GND 5%
KBC_SCANOUT7 pin pair (18/19, 45/46, 76/78, 88/89, 115/116) C582 C992
KBC_SCANOUT8 0.1uF 10uF
KBC_SCANOUT9 R811 0 10% 20%
KBC_SCANOUT10 5% . .
KBC_SCANOUT11 C435 C434 C422 C601 C577 C578
KBC_SCANOUT12 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 4.7uF C598
D KBC_SCANOUT13 10% 10% 10% 10% 10% 10% 0.1uF D
KBC_SCANOUT14 . . . . . . 10% C600 C993
KBC_SCANOUT15 . 0.1uF 10uF Place C993 close to pin102
KBC_SCANOUT[15:0] 44 Place C320 near pin 104 10% 20%
as much as possiable. +V3.3A_KSC EC_AGND . .
115
102
88
76
46
19
80
4
U86A
KBC_SCANIN0 C580 EC_AGND
VCC0
VCC1
VCC2
VCC3
VCC4
GPIO41
AVCC
VDD
KBC_SCANIN1
KBC_SCANIN2 0.1uF
KBC_SCANIN3 10% .
KBC_SCANIN4 104 124 -PM_SUS_STAT
KBC_SCANIN5 VREF LPCPD#/GPIO10/HGPIO00 -PM_SUS_STAT 16
EC_AGND 7 -LRST 100 R429 +V3.3S 4,10,11,12,13,14,15,16,17,18,19,20,21,23,25,26,31,32,33,37,38,41,44,46,48
KBC_SCANIN6 LRESET# -BUF_PLT_RST 18,25,26,30,44
KBC_SCANIN7 28 -BAT1_IN
-BAT1_IN
ADAPTOR_I
97
98 AD0/GPI90 A/D LCLK
2
3
CLK_PCI_KBC_L
-LPC_FRAME
33 R419
CLK_PCI_KBC 18
27 ADAPTOR_I AD1/GPI91 LFRAME# -LPC_FRAME 14,44
KBC_SCANIN[7:0] 44 99 6 -LDRQ
AD2/GPI92 LDRQ#/GPIO24/HGPIO01 -LDRQ0 14
AC_IN2 100 126 LPC_AD0 BAT54S D14
27 AC_IN2 AD3/GPI93 LAD0 LPC_AD0 14,44
-LID_IN 108 127 LPC_AD1 RC_IN_EC 3 1 -H_RCIN
44 -LID_IN AD4/GPIO05 LAD1 LPC_AD1 14,44 -H_RCIN 19
0 R425 -EC_SLP_S3 96 128 LPC_AD2
16,32,33,34,35 -PM_SLP_S3 AD5/GPIO04 LAD2 LPC_AD2 14,44
LPC LAD3
1
125
LPC_AD3
INT_SERIRQ
LPC_AD3 14,44 2
SERIRQ INT_SERIRQ 14
8 -PM_CLKRUN_L R421 0
CLKRUN#/GPIO11/HGPIO02 -PM_CLKRUN 16
27 BAT_LIM BAT_LIM 101 122 2
105 DA0/GPI94 KBRST# 121 D18 R422
DA1/GPI95 GA20 . BAT54S
21,27,28,33 +V3.3A_KSC 33 3V5V_VR_PWRGD
3V5V_VR_PWRGD 106
107 DA2/GPI96 D/A ECSCI#
29
9
-ECSCI
-EC_SMI 3 1
3 1
-EC_RUNTIME_SCI 19 8.2K
14 GPIO33_CONTROL DA3/GPI97 SMI# -EC_EXTSMI 19
123 -EC_WAKE_SCI_R R700 0/NC .
PWUREQ# -EC_WAKE_SCI 18
2
D15 5%
R413 a20gate_ec 3 1H_A20GATE
4.7K PCH_PWROK_EC
PCH_PWROK_EC 81
SWD/GPIO66 SP BAT54S D19 H_A20GATE 19
SMB SDA2
68
67
BAT_SMB_DATA
BAT_SMB_CLK
SMB_BAT1_DATA 28
BAT54S
2
SCL2 SMB_BAT1_CLK 28
69 SML1_DATA
SDA1 SML1_DATA 15
45 -PWR_SW_BTN -PWR_SW_BTN 64 70 SML1_CLK
D16 GPIO01 SCL1 SML1_CLK 15 21,27,28,33 +V3.3A_KSC
AC_IN 95
2 28 AC_IN 93 GPIO03
C560 94 GPIO06/HGPIO06
1 3 -PM_PWRBTN_R 119 GPIO07/HGPIO07 84
16 -PM_PWRBTN GPIO23 SPI_DI/GPIO77 21,27,28,33 +V3.3A_KSC R554
0.1uF -PCIE_DISABLE 109 83 SHBM
25 -PCIE_DISABLE -LED_BAT_GREEN 120 GPIO30 SP_DO/GPIO76/SHBM 82 10k/NC
BAT54S 46 -LED_BAT_EXIST -LED_BAT_RED 65 GPIO31 SPI_SCK/GPIO75 91 LCD_SW C365 0.1uF
LCD_SW 13 .
46 -LED_BAT_CHARGE GPIO32 GPIO81
46 LED_PWRSTS
LED_PWRSTS 66
GPIO33 SPI U30 5%
33 VCC3.3_EN VCC3.3_EN
R698 0
16
17 GPIO40 GPIO 8 6 R428 47 SCK
16,34 -PM_SLP_S4 GPIO42/TCK VCC CLK 1 SCS
C 20 111 BADDR1 C
16 -PM_SLP_S5 GPIO43/TMS SOUT_CR/GPIO83/BADDR1 R430 3.3K 3 CS
16 SUS_PWR_ACK 21 113
GPIO44/TDI SIN_CR/CIRRX/GPIO87 BLUETOOTH_ONOFF 44 R424 3.3K 7 WP
22 112 BADDR0
16 -PM_SLP_SUS GPIO45 GPIO84/HGPIO01/BADDR0 HOLD 5 R426 47 MOSI
0 R423 -EC_SLP_S4 23
16,34 -PM_SLP_S4 GPIO46/TRST# 4 DI 2 R427 15/1% MISO
-PROCHOT_EC 24 114 ALL_SYS_PWRGD_R 0 R420 ALL_SYS_PWRGD 37,38,48
GPIO47/JEN0# CIRTX/GPIO16/HGPIO04 GND DO
wiless_on_off 25 14 WEB_CAM
26 wiless_on_off GPIO50/TDO GPIO34/CIRRX2 WEB_CAM 13 W25P80-VSSIG
-PM_RSMRST 26 15 CHG_ON
16,48 -PM_RSMRST GPIO51 GPIO36 CHG_ON 27 D20
37,38 DELAY_VR_PWRGOOD DELAY_VR_PWRGOOD
0 R699
27
28 GPIO52/RDY# SER/IR 2 BAT54S
16 AC_PRESENT GPIO53
TRIS- 110
GPIO82/HGPIO00/TRIS# 73 batlow_ec 3 1
IRRX2_IRSL0/GPIO70 -PM_BATLOW 16
74
IRTX/GPIO71
STUFF the resistor R440
FIR IRRX1/GPIO72
75
-H_PROCHOT 4,38 CPU_VR_ON can float all EC

GPIOs
*10K/NC 44
VCORF
5% .
没有了
AGND
GND0
GND1
GND2
GND3
GND4
GND5
C361
R456 1uF
R581 R583
10%
7.5 .
116
89
78
45
18
5
103
. BADDR1 NPCE79NL 8.2K/NC 8.2K/NC
BADDR0 . .
3
5% 5%
BADDR SELECTION
Q45 1 0
2N7002 1 R882 -PROCHOT_EC 0 0 XOR-Tree Test Mode R739 0
0 R519 0 1 Core Defined
R455 Ver02 10k/nc R520 1 0 2Eh - 2Fh
2
1 1 164Eh - 164Fh(4E/4F for 791) EC_AGND

. 10k/nc
100K
5% . 18 CLK_PCI_EC_REF
.
5%
Ver02
C384 10pF/NC
C0402 U86B
4
SHBM 32.768KHz/NC R522

3 2 10M/NC XIN_B 77 53 KBC_SCANOUT0
+V3.3A 4,14,15,16,18,19,21,25,26,28,30,33,34,37,44,46,48 32KX1/32KCLKIN/EXTKCLK_791 KBSOUT0
SHARED BIOS ENABLE Y5 .R0402 52 KBC_SCANOUT1
10M/NC R718 KBSOUT1 51 KBC_SCANOUT2
1
R600 33K/NC KBSOUT2 50 KBC_SCANOUT3

R521 KBSOUT3
C385 10pF/NC XOUT_B 79 49 KBC_SCANOUT4
10k/NC 32KX2/GPIO02_791 KBSOUT4
R764 5% -EC_WAKE_SCI C0402 TP20 1 TP_EC_CLKOUT 30 48 KBC_SCANOUT5
10K . CLKOUT/GPIO55 KBSOUT5 47 KBC_SCANOUT6
5% R606 0 63
R0402 KBSOUT6 43 KBC_SCANOUT7
B B
19 -CRIT_TEMP_REP TB1/GPIO14/HGPIO04 KBSOUT7
10,11 TS_DIMM
. R605 0/NCR0402 117
31 TA2/GPIO20 KBC
KBSOUT8
42
41
KBC_SCANOUT8
-PM_EXTTS0
28 CPU_FAN_PWM CPU_FAN_PWM 32 TA1/GPIO56
A_PWM0
KBSOUT9
KBSOUT10
40
KBC_SCANOUT9
KBC_SCANOUT10 Note 1 : Since all GPIO belong to VSTBY power domain, and
LCD_ADJ_PWM 118 39 KBC_SCANOUT11
13 LCD_ADJ_PWM
41 BTL_ALARM BTL_ALARM 62 A_PWM1/GPIO21
B_PWM0/GPIO13
KBSOUT11
KBSOUT12/GPIO64
38 KBC_SCANOUT12 there are some special considerations below:
37 KBC_SCANOUT13
3,4,6,13,20,21,32,36,48 +V1.05S_VCCP
KBSOUT13/GPIO63
KBSOUT14/GPIO62
36 KBC_SCANOUT14 (1) If it is output to external VCC derived power domain
35 KBC_SCANOUT15
Ver02 4,19 PECI_EC
R374 43 13
12 PECI
KBSOUT15/GPIO61/XOR_OUT
KBSOUT16/GPIO60
34
33
circuit, this signal should be isolated by a diode such as
R847
0 11 VTT
PSDAT2/GPIO27
KBSOUT17/GPIO57/HGPIO03 TP_EC_XOROUT 1 TP21 KBRST# and GA20.
Ver02 C368 10
NOTE: 44 KBC_TP_DATA KBC_TP_DATA 71 PSCLC2/GPIO26
PSDAT1 KBSIN0
54 KBC_SCANIN0 (2) If it is input from external VCC derived power domain
PECI layout routing should be according 0.1uF
.
44 KBC_TP_CLK
KBC_TP_CLK 72
PSCLK1 PS/2 KBSIN1
55
56
KBC_SCANIN1
KBC_SCANIN2 circuit, this external circuit must consider not to float
to Intel's DG KBSIN2 57 KBC_SCANIN3
KBSIN3
MISO 86 KBSIN4
58
59
KBC_SCANIN4
KBC_SCANIN5
the GPIO input.
MOSI 87 F_SDI KBSIN5 60 KBC_SCANIN6
F_SDO KBSIN6
SCS 90
92 F_CS0# FIU KBSIN7
61 KBC_SCANIN7
SCK
F_SCK Note 2 :
85 R708 4.7K +V3.3A_KSC
VCC_POR#
(1) Each input pin should be driven or pulled.
NOTE:
R553
10k/NC
.
5% NPCE79NL (2) Each output-drain output pin should be pulled.
ALL_SYS_PWRGD TO PCH_PWROK_EC NOTE:
DELAY 99MS -PM_SLP_A DEL
+V3.3A 4,14,15,16,18,19,21,25,26,28,30,33,34,37,44,46,48
ADD -PM_SLP_SUS FROM PCH

1
C585
0.1uF
2
. U9
RSMRST# must be asserted for at least 10 ms after the
5
10% 74AHC1G08 R469 0

suspend power wells are valid 1
-PM_SLP_S3 16,32,33,34,35
A A
4
16,38 PM_PCH_PWROK 2 PCH_PWROK_EC
3
R471 0/NC
EC
.


E450 24 of 50
5 4 3 2 1
5 4 3 2 1
+V3.3A 4,14,15,16,18,19,21,24,26,28,30,33,34,37,44,46,48
D D
MINISLOT_V3.3
+V3.3S 4,10,11,12,13,14,15,16,17,18,19,20,21,23,24,26,31,32,33,37,38,41,44,46,48
C236 C237 C238
10uF 0.1uF 0.1uF
0603 20% 20%
20% . .
CON8
+V1.5S 20,26,32,34
1 2
R431 16,26,30 -PCIE_WAKE 3 WAKE# +3.3V_1 4
5 RSVD1 GND7 6
10K RSVD2 +1.5V_1
5% 7 8 SIM_POWER 44
15 -CLK_SLOT1_OE 9 CLKREQ# RSVD13 10 C239 C240 C357
GND1 RSVD14 SIM_DATA 44 +V3.3A 4,14,15,16,18,19,21,24,26,28,30,33,34,37,44,46,48
11 12 10uF 0.1uF 0.1uF
15 CLK_PCIE_SLOT1_N REFCLK- RSVD15 SIM_CLK 44
13 14 20% 10% 10%
15 CLK_PCIE_SLOT1_P REFCLK+ RSVD16 SIM_RST 44
15 16 USIM_External_VPP . . .
GND2 RSVD17
KEY
17 18
19 RSVD3 GND8 20
21 RSVD4 W_DISABLE# 22 -PCIE_DISABLE 24 C241 C242
23 GND3 PERST# 24 -BUF_PLT_RST 18,24,26,30,44 0.1uF 0.1uF
15 PCIE_RXN1_SLOT1 25 PER_N0 +3.3V_AUX 26 10% 20%
C
27 PER_P0 GND9
15 PCIE_RXP1_SLOT1 C
28 . .
29 GND4 +1.5V_2 30 SMB_CLK_A_R SMB_CLK_A_ICH 15,26
+V3.3A 4,14,15,16,18,19,21,24,26,28,30,33,34,37,44,46,48
31 GND5 SMB_CLK 32 SMB_DATA_A_R
15 PCIE_TXN1_SLOT1 SMB_DATA_A_ICH 15,26
33 PET_N0 SMB_DATA 34
15 PCIE_TXP1_SLOT1
35 PET_P0 GND10 36
USB_PN4 18
37 GND6 USB_D- 38
USB_PP4 18
39 RSVD5 USB_D+ 40
41 RSVD6 GND11 42 -LED_WWAN
43 RSVD7 LED_WWAN# 44 -LED_WLAN01
C165 C166 45 RSVD8 LED_WLAN# 46
0.1uF 10uF 47 RSVD9 LED_WPAN# 48
10% 20% 49 RSVD10 +1.5V_3 50
. . 51 RSVD11 GND12 52
53 RSVD12 +3.3V_2 54
55 GNDM1 GNDM2 56
EXP1 EXP2
MINI_PCIE
B B
2010.3.5
DEL D7
-LED_WWAN
-LED_WWAN_OUT 46
2
D2
-LED_WLAN01 3 1 BAT54S
-LED_WLAN 26,46

A A
MiniPCI-E 1

B <Cage Code> 0.2

E450 25 of 50
5 4 3 2 1
5 4 3 2 1
+V1.5S 20,25,32,34
+V3.3S 4,10,11,12,13,14,15,16,17,18,19,20,21,23,24,25,31,32,33,37,38,41,44,46,48 +V3.3A 4,14,15,16,18,19,21,24,25,28,30,33,34,37,44,46,48
C161 C156 C158 C160 C162 C164

D 10uF 0.1uF 0.1uF 10uF 0.1uF 0.1uF D
20% 10% 10% 20% 10% 10%
R432 . . . . . .
10K
5% CON6
.
1 2
16,25,30 -PCIE_WAKE 3 WAKE# +3.3V_1 4
5 RSVD1 GND7 6
7 RSVD2 +1.5V_1 8
15 -CLK_SLOT2_OE 9 CLKREQ# RSVD13 10
11 GND1 RSVD14 12
15 CLK_PCIE_SLOT2_N REFCLK- RSVD15
13 14
15 CLK_PCIE_SLOT2_P REFCLK+ RSVD16
15 16
GND2 RSVD17
KEY
17 18
19 RSVD3 GND8 20 R75 0
RSVD4 W_DISABLE# wiless_on_off 24 +V3.3A 4,14,15,16,18,19,21,24,25,28,30,33,34,37,44,46,48
21 22
23 GND3 PERST# 24 -BUF_PLT_RST 18,24,25,30,44
15 PCIE_RXN2_SLOT2 25 PER_N0 +3.3V_AUX 26
15 PCIE_RXP2_SLOT2 27 PER_P0 GND9 28 C163 C155 C159
29 GND4 +1.5V_2 30 SMB_CLK_A_ICH 10uF 0.1uF 0.1uF
31 GND5 SMB_CLK 32 SMB_DATA_A_ICH SMB_CLK_A_ICH 15,25 20% 10% 10%
C 15 PCIE_TXN2_SLOT2 PET_N0 SMB_DATA SMB_DATA_A_ICH 15,25 C
33 34 . . .
15 PCIE_TXP2_SLOT2 PET_P0 GND10
35 36
+V3.3A 4,14,15,16,18,19,21,24,25,28,30,33,34,37,44,46,48 GND6 USB_D- USB_PN2 18
37 38
R71 0 RSVD5 USB_D+ USB_PP2 18
39 40
41 RSVD6 GND11 42
43 RSVD7 LED_WWAN# 44
RSVD8 LED_WLAN# -LED_WLAN 25,46
45 46
47 RSVD9 LED_WPAN# 48
49 RSVD10 +1.5V_3 50
R289 0/NC 51 RSVD11 GND12 52
19 -HOST_ALERT1 RSVD12 +3.3V_2
53 54
55 GNDM1 GNDM2 56
R73 EXP1 EXP2
0 MINI_PCIE
B B

A A
MiniPCI-E 2

B <Cage Code> 0.2

E450 26 of 50
5 4 3 2 1
5 4 3 2 1
28 DC_IN D55 28 DC_IN_B

P N DC_IN 28
MMSD4148
28 DC_IN
C417
CSON
0.1uF/25V
C418
D VDD 1uF/25V D
R569 VIN 13,28,33,34,35,36,37,38,39,40
18/1% VDD
R556
PU1 0.1uF/25V
24
1
C421
R571 PC1
VDD
DCIN
R575 10K 100K/1% 20 10/1%
VDD CSIN
19 10U
2 CSIP
R557 C420 R572 WHEN VIN>17V ACSET 15
ACSET>1.56V VDDP
10K/1%
1
0.22uF C423
0 BAT54S 1uF/10V
PD1
NTMD4840
3
16
4 BOOT C424 0.1uF
5
6
7
8
CELLS 17 20mil VCHG
UGATE PQ1 L21
R560 10K/1% R558 2.49K/1% 8 R567 40m_1%
VREF 18 15mil 4
21,24,28,33 +V3.3A_KSC PR10
R602 10K/1% 9 ISL6251 PHASE 10uH 30% 100KHz CDRH104RNP-100NC
CHLIM
10U C589
10U C590
1
2
3
10U C425
10K 14 20mil
change R602 from 5K to 10K.(700MA to 1A) LGATE
3
24 ADAPTOR_I ADAPTOR_I R568 100 7 21

ICM CSOP
Q27
WHEN Vicm>1.44V 11 22 CSON
DISABLE CHARGER VADJ CSON C427
24 BAT_LIM 1 2N7002
C C426 3 6 C
EN VCOMP
0.1uF
2
23 5 1uF R524 2.2

ACPRN ICOMP R561
PGND
10
GND
ACLIM
24 CHG_ON R573 1K CHG_EN 10K/1%
12
13
3
VDD
Q24 C428 C429 C430
0.01uF 0.01uF 100pF VDD
21,24,28,33 +V3.3A_KSC PR3 1 2N7002 R570
100K/1% PJP3
1 2
2
10K PD2
2
PR4 WHEN "H" DISABLE CHARGER R523
AC_IN2 1 3 ACPRN 10K
24 AC_IN2
THIS SET WHEN VIN<18V DISABLE CHARGER
1K
BAT54S
VIN_CTRL
PD3
VIN_CTRL 28
3
2 Q15
ACPRN 1 3 1 2N7002
L44 220Z/3A 100M
2
BAT54S R559
C431 C432
VBAT 28 1M/NC
B L45 B
220Z/3A 100M VCHG
PJP15 2.2nF 220NF/16V
VBAT 1 2
VCC_BAT
VIN 13,28,33,34,35,36,37,38,39,40 VCC_BAT

VCC_BAT
PU2
FDS4435A
3 8
2 7
C561
1 6
5
10uF
4
DC_IN 28
PR7 1K
PR8
100K
A A

CHARGE VR


E450 27 of 50
5 4 3 2 1
5 4 3 2 1
27 DC_IN_B
27 DC_IN
45 DC_ALL_IN D81 21,24,27,33 +V3.3A_KSC

P N VIN 13,27,33,34,35,36,37,38,39,40
R789 12K R791 5K11 PJP13
1 2 SK34A
3
FDS4435A Q16 D68
Q18
3 8 27 DC_IN
2 7
P N
R593 33K/1% DC_IN_10V 1
F2 5A DC_IN_R R588 25mR/F/1W_2512 1 6 2N7002
5 SK34A
C529
2
For VIN Discharge quickly!
10K R599
0.1uF/25V
C530 D50 C535 PJP18 2009-07-27 AC_IN 24
D R595 R596 1 2 10K@H720 R584 AC_IN D
4
C526
0.01uF/50V 0.01uF/50V SK34A 0.01uF/50V 12K 12K R591
P
33K/1%
4,14,15,16,18,19,21,24,25,26,30,33,34,37,44,46,48 +V3.3A
R580 10K
470K/NC
3
R578
Q19
10K DC_IN_10V
1
3
2N7002
2
Q20
2N7002 1 VIN_CTRL
VIN_CTRL 27
R585 C534
2
R587
100K 2.2uF/25V
100K/1%
-BAT1_IN
For Battery Special

21,24,27,33 +V3.3A_KSC
VBAT 27
C R586 R592 R582 C

100K 4.7K 4.7K
System FAN connector C718
0.01uF/50V
C741
1uF/25V
5%
.
5%
.
5%
.
CON16
R555
J6
1K _NC BAT_SMB_CLK_L 1
BAT_SMB_DATA_L VCC 2
VCC
3
2 3 BAT_SMB_CLK_L PR25 150 SMB_BAT1_CLK
CLK SMB_BAT1_CLK 24
3
12,13,15,20,21,29,31,32,33,34,36,37,38,41,42,43,44 +V5S 4 D52 4 BAT_SMB_DATA_L PR26 150 SMB_BAT1_DATA
DATA SMB_BAT1_DATA 24
FAN1_VCC 3 D53 BAT54S/NC 5
BATIN -BAT1_IN 24
N
1 BAT54S/NC 6
8 GND 7
D51 C533 C536 fan PACK#1 GND
1
9
1
MMSD4148 PACK#2 C527 R576
1uF/25V 100K
1uF 5%
P
20%
3
10U FAN_CONN .
.
12,13,15,20,21,29,31,32,33,34,36,37,38,41,42,43,44 +V5S 21,24,27,33 +V3.3A_KSC D76
BATTERY CONN
BAT54S/NC
21,24,27,33 +V3.3A_KSC
1
R649
U48A 1K
8
R590
E
3 + 1K Q31
1 B
CPU_FAN R598 10K 2 21,24,27,33 +V3.3A_KSC
24 CPU_FAN_PWM -
2N2907A
C
C531 LM358 R594

4
1K
E
Q33
B
1uF
2N2907A
C
C532 R589 R597

2K(2.2K) 0402
0.1uF/NC 3K(3.4K) 0402
R650
1K
B B
12,13,15,20,21,29,31,32,33,34,36,37,38,41,42,43,44 +V5S
HOLE
H35 H36 H37 H38
Hole_P7_0D3_4 Hole_P7_0D3_4 Hole_P7_0D3_4 Hole_P7_0D3_4
H39 H40 H41 H42 H43 H44

hole_p7_0d2_8 hole_p7_0d2_8 T3 T4
hole_p7_0d2_8 hole_p7_0d2_8 hole_p7_0d2_8 hole_p7_0d2_8 T1 T2 T11 T12
TP TP
TP TP TP TP
T7 T8 T9 T10
T5 T6
H45 H46 H47 H48 H49 H50
hole_p7_0d2_8 hole_p7_0d2_8 hole_p7_0d2_8 hole_p7_0d2_8 hole_p7_0d2_8 hole_p7_0d2_8
H29 H30 H31
HOLE_P5_2D3_0 HOLE_P5_2D3_0 HOLE_P5_2D3_0
TP TP TP TP
TP TP
A A
H32 H33
HOLE_P6D2_8 HOLE_P6D2_8
H52 H51 H53 H54
Ver02
Hole_P5_0D1_2 Hole_P5_0D1_2 Hole_P5_0D1_2 Hole_P5_0D1_2
DC-IN FAN BAT


E450 28 of 50
5 4 3 2 1
5 4 3 2 1
VDD18
C499
2.2uF
C0603 .
D3.3V
D3.3V
SM_D7
SM_D6
SM_D5
D
C508 C501
0.1uF 4.7uF
C0402 C0603
U7
36
35
34
33
32
31
30
29
28
27
26
25
IT1337E-48
lqfp48__5m_335
REG18Vout
VSS
REG33Vout
REG33Vin
SM_D7
GPIO6
SM_D6
GPIO5
SM_D5
GPIO1
GPIO4
TC
REG5V
+V5S 12,13,15,20,21,28,31,32,33,34,36,37,38,41,42,43,44
FB34
100ohm@100MHz
37 24
CLK_12M_OUT 38 GPIO7 REG5Vin 23 LED_EN
SM_CE 39 Clk12M-out LED 22 SM_D4
SM_WP/SD-CLK 40 SM_CE SM_D4 21 RST C518 C522 C4 CN1
SM_WP RST
SM_WR
41
42 VSS IT1337E-48 GPIO3
20
19 CLKSEL
0.1uF
C0402
0.1uF
C0402
2.2uF SM_CE
SM_D1
1
2 SDWP
SM_WR ClkSel . C0603 SDD1
EE_SDA 43 18 SM_D3 SM_D0 3
EE_SDA SM_D3 SDD0
EE_SCL 44
EE_CLK SD/MS/xD SM_CD
17 4
SD_VSS
FLASH CARD SLOT

D3.3V 45 16 SM_ALE 5
D3.3V AVDD33 SM_ALE MS_VSS
R84 0 DP 46 15 PWR_SW2 SM_WPSW 6
18 USB_PP5 DP PWR_SW2 MSBS
R83 0 DM 47 14 D3.3V SM_WP/SD-CLK 7
18 USB_PN5 DM VDD33 SDCLK_O
48 13 SM_D1 8
AVSS VSS SM_D0 9 MSD1
C485 10 MSD0
PWR_SW2 SDVCC
0.1uF SM_D2 11
C0402 C543 12 MSD2
SM_WP_SW
0.1uF SM_RD 13 SDVSS
SM_RNB
MSINS
SM_CLE
Clk-48M
SM_D3 14
SM_RD
SM_D0
SM_D1
SM_D2
XTALO
VDD18
xD_CD
MSD3
XTALI
SM_WPSW 15
SM_WP/SD-CLK 16 SDCMD 25
17 MSCLK SDD24 24
PWR_SW2 MSVCC SDD23
SM_D3 18 23
1
2
3
4
5
6
7
8
9
10
11
12
C523 19 SDD3 SDD22 22
C C
MSVSS SDD21
C178 must be 4.7uF C650 SM_D2 20
SDD2
C0603 0.1uF SM_RNB 21
closed to SDCD
SM_WPSW
SD-connector
CLK_48M
XTALO
xD_CD
SM_RNB
SM_CLE
XTALI
SM_RD
SM_D0
SM_D1
SM_D2
VDD18
D3.3V CON 3in1 Taisol-144-1300003901 DMMS-T
dmms-t3in1_taisol
VDD18
R1
XTALI 33K
XTALO C496
Y1 0.1uF RST
C0402
12 MHz/20pF C495
R822 270K
4.7uF
C0603 IT1337E-48 PIN MUX
C489 C487
PINs SM/xD SD/MMC MS
05 SM_WPSW SD_CMD MS_BS
22pF 22pF
06 SM_RD MS_INS
ClkSel=0 selects the Clk48M clock input and 07 SM_RNB SD_CD
Clk12M_out pin should be connected to XTALI pin.
08 SM_D0 SD_D0 MS_D0
CLKSEL
CLK_48M
CLK_48M 15
R2
0/NC 18 SM_D3 SD_D3 MS_D3
CLK_12M_OUT R3 0/NC XTALI
When mount EEPROM(U27)
B Please remove jump 29 SM_D5 SD_D5 MS_D5 B
EE_SDA(R50),EE_SCL(R60) 32 SM_D6 SD_D6 MS_D6
D3.3V
U33
39 SM_CE SD_WP
1 8
A0 VCC
40 SM_WP SD_CLK MS_CLK
2 7
A1 WC
3 6 EE_SCL PWR_SW2
A2 SCL D3.3V
4 5 EE_SDA
GND SDA
24C02/NC R86 R87

IC8SO 0 0 R827
1K
R825 R826 R823 R824
47K(51K) 1M 2.2K 10K
S0=P12=EEP_SDA
xD_CD
S1=P13=EEP_SCK SM_WR
SM_CE
1.Normal mode=11 SM_RD
SM_RNB
R60=NC,R50=NC
2.enable MS/xD Logo
R60=0,R50=NC Reserved resistors to pass xD logo
3.Connector don't
have SD_WP pin
R60=0,R50=0
A A

CARD READER
C <Cage Code> 0.2

E450 29 of 50
5 4 3 2 1
5 4 3 2 1
Y6
4,14,15,16,18,19,21,24,25,26,28,33,34,37,44,46,48 +V3.3A
XTAL12 1 XTAL2
C29 C31
VDD33 0.1uF 0.1uF
C247 C249 C260 C262 D_25MHz/12pF
0.1uF 0.1uF 0.1uF 0.1uF
10% 10% 10% 10% R438
. . . . C168 C169 R103 10K
27pF 27pF
GND GND
D 2.49K/1% GND D
DVDD12 VDD33
DVDD12
U14
CTRL12A
VDD33
XTAL2
XTAL1
R449 0/NC EVDD12
RSET
LED0
GND
C254 C256 C257 C259 C261 EECS 1 8 VDD33
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF LED1/EESK 2 CS VCC 7 C25
10% 10% 10% 10% 10% LED2/EEDI 3 SK DC 6
. . . . . LED3/EEDO 4 DI ORG 5 GND 0.1uF
VDD12 DO GND
U11 AT93C46A(3.3V)/NC GND
48
47
46
45
44
43
42
41
40
39
38
37
R433 0/NC CTRL12A
C255 VDD33
VCTRL12A/SROUT12
NC/ENSWREG
CKTAL2
CKTAL1
NC/AVDD33
NC/LV_PLL
LED0
VDD33
GND
RSET
VCTR12DVDDSR
NC/VDDSR
0.1uF
10% R97 3.6K
.
VDD33 1 36 DVDD12 VDD33

MDI0+ 2 AVDD33 DVDD12 35 LED1/EESK
MDI0- 3 MDIP0 LED1/EESK 34 LED2/EEDI
4 MDIN0 LED2/EEDI 33 LED3/EEDO
MDI1+ 5 NC/FB12 LED3/EEDO 32 EECS
MDI1- 6 MDIP1 EECS 31 GND
R439
GND 7 MDIN1 GND 30 DVDD12
C
8 GND RTL8102EL/8111DL DVDD12 29 VDD33
C
9 NC/MDIP2 VDD33 28 ISOLATE

1K R441 15K
DVDD12 10 NC/MDIN2 ISOLATEB 27 PERSTB
DVDD12/AVDD12 PERSTB -BUF_PLT_RST 18,24,25,26,44
MDI0+
MDI1+
11 26 LANWAKEB
MDI0-
MDI1-
NC/MDIP3 LANWAKEB -PCIE_WAKE 16,25,26

12 25 CLKREQB
NC/MDIN3 CLKREQB CLKREQB 15
NC/SMDATA
REFCLK_N
NC/SMCLK
REFCLK_P
+V3.3A 4,14,15,16,18,19,21,24,25,26,28,33,34,37,44,46,48
DVDD12
EVDD12
R443R444 R445R447
HSON
EGND
HSOP
HSIN
HSIP
GND
49.9/NC 49.9/NC49.9/NC 49.9/NC R738
13
14
15
16
17
18
19
20
21
22
23
24
10K/NC
C377 C378
EVDD12
REFCLK+
DVDD12
REFCLK-
10nf/NC 10nf/NC
HSON
HSOP
HSIP
GND
HSIN
GND
CLKREQB
L25
TX+ 1 2 TX1+
15 PCIE_TXP3_LAN TX- 4 3 TX1-

15 PCIE_TXN3_LAN
B 15 CLK_PCIE_LAN B
. 90_100MHz
15 -CLK_PCIE_LAN L22
.
C245 0.1uF 10%
15 PCIE_RXP3_LAN RX+ 1 2 RX1+
C246 0.1uF 10%
15 PCIE_RXN3_LAN
RX- 4 3 RX1-
U83 CON5
90_100MHz
MDI1+ 1 16 RX+
RD+ RX+
MDI1- 2
RD- RX-
15 RX- TX1+ 1
MX1+ 9
9 Pin9\10 NC
3
RDCT3 RXCT
14 RXCT TX1- 2
MX1- 10
10 Ver02
4 13 RX1+ 3
5 NC NC3 12 RX1- 6 MX2+ 11
6 NC1 NC2 11 TXCT 4 MX2- 11 12
MDI0+ 7 TDCT4 TXCT 10 TX+ 5 MX3+ 12
MDI0- 8 TD+ TX+ 9 TX- 7 MX3-
C375 TD- TX- 8 MX4+
C379 MX4-
R450 R434 R442 R448 RJ45
0.01uF 0.01uF NS0013 75 75
75 75
conn RJ45 SMD AAR-RJ5-529-001-LITE

A
C376 A
C374
220pF/4KV
LAN
CHASSIS_GND
0.1uF
B <Cage Code> 0.2

E450 30 of 50
5 4 3 2 1
5 4 3 2 1
D D
4,10,11,12,13,14,15,16,17,18,19,20,21,23,24,25,26,32,33,37,38,41,44,46,48 +V3.3S
R195 R193
2.2K 2.2K
5% 5%
1
. .
2 3 HDMI_DDC_CLK
17 HDMID_CTRL_CLK
1
Q11
2 3 BSS138 HDMI_DDC_DATA
17 HDMID_CTRL_DATA
***
Refer to HDMI Cost Reduced Level Shifter Design Recommendation
Design Guide :Page 131 *** Q12
BSS138
C C
-FLT_HDMI_CLK_L R881 680
R0402 2010.3.5
FLT_HDMI_CLK_L R879 680
R0402
-FLT_HDMI_TX0_L R880 680
R0402
+V5S 12,13,15,20,21,28,29,32,33,34,36,37,38,41,42,43,44
FLT_HDMI_TX0_L R878 680
R0402 2
-FLT_HDMI_TX1_L R877 680 D7
R0402 BAT54S 1 3F3 SMD1812P150TS-1.5A
FLT_HDMI_TX1_L R869 680
R0402 C802 C803
R846 680 +V5S 12,13,15,20,21,28,29,32,33,34,36,37,38,41,42,43,44 0.01uF/NC 0.01uF
-FLT_HDMI_TX2_L
R0402
+V3.3S 4,10,11,12,13,14,15,16,17,18,19,20,21,23,24,25,26,32,33,37,38,41,44,46,48 10% 10%
FLT_HDMI_TX2_L R845 680 NO_STUFF .
1
R0402
3
BAT54S +V3.3S CON21

4,10,11,12,13,14,15,16,17,18,19,20,21,23,24,25,26,32,33,37,38,41,44,46,48
Q25 D83
20
SHELL1
3
2N7002 1 R876 0 21
FLT_HDMI_TX2_L 1 SHELL2
R0402 1% COMMON
2 D2+
D2 Shield
2
-FLT_HDMI_TX2_L 3
FLT_HDMI_TX1_L 4 D2-
5 D1+
-FLT_HDMI_TX1_L 6 D1 Shield
2010.3.5 D1-
R717 FLT_HDMI_TX0_L 7
27K/NC 8 D0+
R712 R711 -FLT_HDMI_TX0_L 9 D0 Shield
2.2K 2.2K FLT_HDMI_CLK_L 10 D0-
11 CK+
-FLT_HDMI_CLK_L 12 CK Shield
CE_REMOTE_OUT 13 CK-
14 CE Remote
HDMI_DDC_CLK 15 NC
HDMI_DDC_DATA 16 DDC CLK
B 17 DDC DATA B
18 GND
HDMI_HPDET_L R874 0 HDMI_HPDET 19 +5V
17 HDMID_HPD HP DET
-FLT_HDMI_CLK_L R0402 1% COMMON 22
17 -FLT_HDMI_CLK_L SHELL3
FLT_HDMI_CLK_L 23
17 FLT_HDMI_CLK_L R716 SHELL4
-FLT_HDMI_TX0_L 20K HDMI
17 -FLT_HDMI_TX0_L
FLT_HDMI_TX0_L
17 FLT_HDMI_TX0_L .
-FLT_HDMI_TX1_L
17 -FLT_HDMI_TX1_L
FLT_HDMI_TX1_L
17 FLT_HDMI_TX1_L
-FLT_HDMI_TX2_L
17 -FLT_HDMI_TX2_L +V5S 12,13,15,20,21,28,29,32,33,34,36,37,38,41,42,43,44
FLT_HDMI_TX2_L
17 FLT_HDMI_TX2_L +V5S 12,13,15,20,21,28,29,32,33,34,36,37,38,41,42,43,44
R609
R464
2
R603
2
NC R607
NC BAT54S
R472 D80 BAT54S
NC R467 D79
3
NC
3
R468
NC R470
NC
HDMI_DDC_CLK
NC HDMI_DDC_DATA
NC
A A

HDMI
C <Cage Code> 0.2

E450 31 of 50
5 4 3 2 1
5 4 3 2 1
+5V_AW
1
PD11
BAT54S
3
D D
+VCC_GFXCORE
R756 R753
100K
C559
10U
68
3
PR160
-SLPS3_CONTROL 4,33,34,37
0 PQ47
1 2N7002
2
R752
1M
3
PQ36
1 2N7002
16,24,33,34,35 -PM_SLP_S3
C C
20,21,23,35,48 +V1.05S
2
PR83
3,4,6,13,20,21,24,36,48 +V1.05S_VCCP
12,13,15,20,21,28,29,31,33,34,36,37,38,41,42,43,44 +V5S
10K R755
68
5%
.
R902
68
5%
R748 .
3
220
PQ46 .
3
3
1 2N7002
PQ41 PQ58
2
1 2N7002 1 2N7002
2
2
10,11,34 +V0.75 4,10,11,12,13,14,15,16,17,18,19,20,21,23,24,25,26,31,33,37,38,41,44,46,48 +V3.3S 7,37 +V0.85S
20,25,26,34 +V1.5S
R751
B R903 B
68
68 R754 5%
68 R747 .
470
3
3
.
3
3
PQ39
1 2N7002
PQ42 PQ60
PQ43
1 2N7002 1 2N7002
1 2N7002
2
2
2
A
SLEEP CONTRON/DISCHARGE

E450 32 of 50
5 4 3 2 1
5 4 3 2 1
13,27,28,34,35,36,37,38,39,40 VIN
R835
0
U31
820k
13 17 V5LDO
EN V5LDO C184
R608 R1470
D 4.7uF D
8 V3LDO
3.9 V3LDO C171
VIN 13,27,28,34,35,36,37,38,39,40
16
VIN
1
C175 4.7uF
13,27,28,34,35,36,37,38,39,40 VIN
R475 0.1uf/25V
R148
2
9 PC132 PC134 PC133
PC136 PC137 PC135 22 BOOT2
+5V_AW BOOT1 21,24,27,28 +V3.3A_KSC
5
6
7
8
0 Q36 10uF/25V 10uF/25V 1uF/25V
8
7
6
5
1uF/25V 10uF/25V 10uF/25V Q58 R473 0
10 4
UGATE2
2
1
4 21
UGATE1
1
PJP21 C180 IRF8707TRPBF PJP22
1
2
3
1
IRF8707TRPBF 0.1uF
3
2
1
5v C181 4.7UH
1
2
4.7UH 0.1uF 11 3.3VOUT
2
20 PHASE2 L31
L30 PHASE1 R474
8
7
6
5
5
6
7
8
R477 Q61 Q48 N.C
PC122 PC123 N.C. PC126
1
1
PC124
1
10U 4 4 PC127 PC125
1
0805 1uF C177 19 12 C174 10U
2
2
10V LGATE1 LGATE2
1
220uF/6.3V IRF8707TRPBF IRF8707TRPBFN.C R610 220uF/6.3V 0805
3
2
1
1
2
3
2
N.C. 13K C176 10V 1uF
2
1
C173 R612 N.C
2
N.C 30K 24
2 OUT1 7
OUT2
2
FB1
R614 5
FB2
1
20K
18 C183
SECFB N.C R611
C C
2
20K
VREF1 3 VREF1
R476 0 VREF
1
Operation Mode Selectable Input 14
SKIP#
Diode Emulation Mode : Connect to REF C182
R480 10K/NC 0.22uF
PWM Mode : Connect to GND
2
R613 0/NC 21,24,27,28 +V3.3A_KSC
V3LDO
Frequency Control
VREF1 4 1 ENILIM1
R478 0 TON ENILIM1
R102 C677 R157
100k/NC 91k 4,10,11,12,13,14,15,16,17,18,19,20,21,23,24,25,26,31,32,37,38,41,44,46,48 +V3.3S
Q62
4,14,15,16,18,19,21,24,25,26,28,30,34,37,44,46,48 +V3.3A IRF8707TRPBF
0.1uF/NC
8 3
7 2
R479 10K 23 6 ENILIM2 6 1
E.P.(PGND)
PGOOD ENLIM2
5
R158
24 3V5V_VR_PWRGD
PGND
C674
1
91k
PC121
0.01uF 0.1U
Ver02 -S3_CONTROL R792
25
15
2
RT8205 0
VIN 13,27,28,34,35,36,37,38,39,40
C551
PJP7 0.01uF
R839 -S3_CONTROL
-S3_CONTROL 7,34
1 2 100K
3
R766 R842
100K 1M
5% 5%
B . PQ52 . B
+5V_AW
R843 1 2N7002 Ver02
0/NC
2
R841
PQ50 270K
5%
1 2N7002 . 12,13,15,20,21,28,29,31,32,34,36,37,38,41,42,43,44 +V5S
16,24,32,34,35 -PM_SLP_S3
+V3.3M DEL Q66
IRF8707TRPBF
Replaced by +v3.3S
2
8 3
7 2
6 1
5
1
PC128
0.1U
-S3_CONTROL R840
2
0
C552
0.01uF
+5V_AW 21,24,27,28 +V3.3A_KSC
21,34,35,37 +V5A
Q47 4,14,15,16,18,19,21,24,25,26,28,30,34,37,44,46,48 +V3.3A
Q60

SI2301BDS VIN 13,27,28,34,35,36,37,38,39,40
IRF8707TRPBF
2 3 8 3
Ver02 7 2
6 1
1 1
Ver02 PR152 5
PR154 220K
C537
100K 0.1uF
4
A PC120 A
R617 10U
3
0805
5V/3.3V VR
3
100K 10V
PR153 PQ48 C524
PQ49 C525 1 2N7002 R763
24 VCC3.3_EN 1 2N7002 1M 0.022uF
5%
2
C528 0.1uF/NC .
1K
2
R837 R838 Draw by Size CAGE Code DWG NO Rev

100K 0.1uF/NC 10K/NC
5%
.
5%
.

E450 33 of 50
5 4 3 2 1
5 4 3 2 1
+V5A 21,33,35,37
D57
P N
VIN 13,27,28,33,35,36,37,38,39,40
1
C219 MMSD4148 1 R191 2
4.7uF 1M
2
C538 C540 C593 C594
2
U18
R794 0.1uF/25V 10UF/25V 10UF/25V 10UF/25V
10K 16
TON
1
13 1 R85 2
1
C185 BOOT 0
D D
N.C.
2
9
VDDP 12 1 R141 2
UGATE
5
6
7
8
0 Q41
2
+V1.5 5,7,10,11
1
R628
10 C213 4 AON6428L Ver02
0.1u L13
2
1uH PJP25
1
2
3
2 11 1 2
VDD PHASE
5
6
7
8
1
Q52
C218 R82 330uF/2.5V+ C498 + C506
1u 10 1 R81 2 N.C. 330uF/2.5V C497 C507
2
GND OC 10k 4 4.7uF 4.7uF
1
1 2
1
AON6718L R631
1
2
3
4 20K C220
37 1.5V_VR_PWRGD PGOOD
1
C217 C221 N.C.
2
EN/DEM:(>2.9V High) N.C.
2
Connect to VDD for diode-emulation mode, 8 1 R80 2 0.1uF
2
connect to GND for shutdown mode and LGATE 0
floating the pin for CCM mode
1
R641 0 15
16,24 -PM_SLP_S4 EN/DEM R632
1 1 R76 2 20K
VOUT
1
0
PR27
10K C186
2
5 N.C.
2
N.C.
14
N.C..
C 3 C
6 FB
GND1
7
PGND
RT8202A
5,7,10,11 +V1.5
+V5S 12,13,15,20,21,28,29,31,32,33,36,37,38,41,42,43,44
C517 R621 U32

1 5
VIN VCNTL 6 5,7,10,11 +V1.5
1uF VCNTL 7 C541
1K/1% VCNTL 8
3 VCNTL
REFEN 1uF
R622 C504
3
+V0.75 10,11,32
5
6
7
8
2 4 Q44
PQ44 GND OUTPUT
4,32,33,37 -SLPS3_CONTROL 1 2N7002 1K/1% 0.1uF RT9173 C521 C510
R669 0 4 IRF8707TRPBF
7,33 -S3_CONTROL
2
4,14,15,16,18,19,21,24,25,26,28,30,33,37,44,46,48 +V3.3A
+V1.5S 20,25,26,32
1
2
3
4.7uF 4.7uF C639
0.1uF
B B
R851
R848 10K +V1.5S和+V1.5S_CPU重复？
10K
+V1.8S_PWRGD 37
+V1.8S 7,20 C550
3
D96
3
R849 10K 1 D99 1 2N7002 10U
+V5A 21,33,35,37
when input voltage is lower than 5.5V MMBT3904
2
this diode is needed R850 C645
8K2/NC 1uF 4,14,15,16,18,19,21,24,25,26,28,30,33,37,44,46,48 +V3.3A
D56
P N
C596
Ver02
MMSD4148
R668
10U R666 10K
10K
+V1.5S_PWRGD 4,37
+V1.5S 20,25,26,32
3
2 1
VIN BOOT 7,20 +V1.8S D89
C646
3
4.7uH
R630 0 7 3 10nF PL7 R667 10K 1 D85 1 2N7002
16,24,32,33,35 -PM_SLP_S3 EN SW
RT8284N
>2.7 Logic High R624 MMBT3904
2
R615 NC C642 C641
GND(Exposed Pad)
C394 C395 R682

NC 22U 22U 0.22uF
9.53k 12K/NC
for EMI
Ver02 8 5
SS FB
Ver02
C647 R623
33NF 4 6 C644 R626 5.6K
GND COMP 3.3nF
A 10k A
U19
9
C624 0.1UF TPS51218

soft-start, time will be 15.5ms C643
33NF
time will be 5ms
1nF/NC
DDR VR,VTT,1.5S,1.8S
C <Cage Code> 0.2

E450 34 of 50
5 4 3 2 1
5 4 3 2 1
+V5A 21,33,34,37
D58
P N
VIN 13,27,28,33,34,36,37,38,39,40
1
C232 MMSD4148 1 R179 2
4.7uF 1M
2
C539 C542 C544
2
U16
R797 0.1uF/25V 10UF/25V 10UF/25V
10K 16
TON
1
13 1 R95 2
1
C227 BOOT 0
N.C.
2
D D
20,21,23,32,48 +V1.05S
9
VDDP 12 1 R96 2
UGATE
5
6
7
8
0 Q49
2
2
1
R793 PJP24
10 C229 4 IRF8707TRPBF
0.1u L17
1
2
2.2uH
1
2
3
2 11
VDD PHASE
5
6
7
8
1
Q54
C231 R94 330uF/2.5V+ C486
1u 10 1 R93 2 N.C. C488 C490
2
GND OC 10k 4 4.7uF 4.7uF
1
1 2
1
IRF8707TRPBF R795
1
2
3
R670 0 4 8.06K C263
37 +V1.05S_PWRGD PGOOD
1
C230 C265 N.C.
2
Ver03 N.C.
2
NC : Vccp substitute for V1.05s 8 1 R92 2 0.1uF
2
LGATE 0
1
R653 0 15
16,24,32,33,34 -PM_SLP_S3 EN/DEM R796
1 1 R91 2 20K
VOUT
2
1
0
R633 C228
2
5 N.C.
2
10K/NC N.C.
14
1
N.C..
3
6 FB
GND1
C C
7
PGND
RT8202A
SLP_A is replaced by SLP_S3

B
Be controlled by SLP_S3# for platforms that don’t support M3 B
A A

1.05M,1.05S
C <Cage Code> 0.2

E450 35 of 50
5 4 3 2 1
5 4 3 2 1
+V5S 12,13,15,20,21,28,29,31,32,33,34,37,38,41,42,43,44
D59
P N
VIN 13,27,28,33,34,35,37,38,39,40
1
C287 MMSD4148 1 R799 2
4.7uF 1M
2
D D
C648 C547 C604 C607
2
U21
R804 0.1uF/25V 10UF/25V 10UF/25V 10UF/25V
10K 16
TON
1
13 1 R109 2
1
C268 BOOT 0 20,21,23,32,48 +V1.05S
N.C.
2
3,4,6,13,20,21,24,32,48 +V1.05S_VCCP
PJP33
9
VDDP 12 1 R643 2 2 1
UGATE
5
6
7
8
0 Q50
2
R801 Ver03
C271 4 AON6428L PJP26
10 Stuff : Vccp substitute
0.1u L9
for V1.05s
2
0.45uH
1
2
3
1
2 11
VDD PHASE
5
6
7
8
1
Q56
C275 R108 R844 + C478
1u 10 1 R106 2 N.C. 100/1% C481 C484
2
GND OC 10k 4 330uF/2.5V 4.7uF 4.7uF
Ver02
1 2
2
AON6718L
1
2
3
4
37 +V1.05S_VCCP_PWRGD PGOOD
1
C274
1
C N.C. R802 C
1
8 1 R105 2 C358 3.9K/1% C291
LGATE 0 N.C.
2
0.1uF/NC
2
R107
1
37,38 PM_1.5S1.05SMPWRGD 15
0 EN/DEM R803
1 1 R104 2 10K/1% 0 R637 VCCP_SENSE 6
VOUT
1
0
C270
2
5 N.C.
2
N.C.
14 0 R648
N.C.. VSSP_SENSE 6
3
6 FB
GND1
7
PGND PJP6
1 2
RT8202A
B B
6 VCCP_SENSE ??
??
6 VSSP_SENSE
A
1.05S_VCCP

E450 36 of 50
5 4 3 2 1
5 4 3 2 1
+V5S 12,13,15,20,21,28,29,31,32,33,34,36,38,41,42,43,44
D60
P N
VIN 13,27,28,33,34,35,36,38,39,40
1
C390 MMSD4148 1 R800 2
4.7uF 1M
2
C649 C546 C548
2
U22
R809 0.1uF/25V 10UF/25V 10UF/25V
10K 16
TON
1
13 1 R115 2
1
C360 BOOT 0 7,32 +V0.85S
N.C.
2
D D
2
9 PJP27
VDDP 12 1 R645 2
UGATE
5
6
7
8
0 Q42
1
2
1
R806
10 C387 4 IRF8707TRPBF 330uF/2.5V
1
0.1u L18 + C480
2
2.2uH R828 C492 C500
1
2
3
2 11 100/1% 4.7uF 4.7uF
VDD PHASE
5
6
7
8
1
Q53
2
C389 R114
10 1 R112 2 N.C.
Ver02
1u
2
GND OC 10k 4
1 2
1
IRF8707TRPBF
1
2
3
1
4 R807 1 R909 2
+V0.85S_PWRGD PGOOD VCCUSA_SENSE 7
1
C388 C483 909/1% C479 Ver02 0
N.C. N.C.
2
8 1 R111 2 0.1uF/NC
2
LGATE 0
R113
1
36 +V1.05S_VCCP_PWRGD 15
0 EN/DEM R808
1
1 1 R110 2 15K/1%
VOUT 21,33,34,35 +V5A
1
0 R810
C386 7.5K/1%
2
5 N.C.
2
N.C.
2
14
N.C..
PR28
10K
3
3
6 FB Q10
C C
GND1
2N7002
1
3
7
PGND D88 1 1 R813 2
VCCSA_SEL 7
2
C493 10K
RT8202A 0.22uF MMBT3904
2
VER10
CPU VCCSA_SEL +V0.85S

SNB 0V 0.9V
1.05V 0.8V
+V3.3A 4,14,15,16,18,19,21,24,25,26,28,30,33,34,44,46,48
C555
+V3.3A 4,14,15,16,18,19,21,24,25,26,28,30,33,34,44,46,48
U23 0.1uF
5
74AHC1G08
+V3.3A 4,14,15,16,18,19,21,24,25,26,28,30,33,34,44,46,48
1
+V0.85S_PWRGD
R189 C558 4 ALL_SYS_PWRGD
ALL_SYS_PWRGD 24,38,48
D21 10K 2
36 +V1.05S_VCCP_PWRGD
BAT54A
U20 0.1uF
3
5
1.5V_VR_PWRGD 1 3 74AHC1G08 R655

34 1.5V_VR_PWRGD
V1.8S_V1.5VR_PWRDG 1 10K
3
+V1.8S_PWRGD 2 4 DDR_1.5S_1.8S_1.05S_PWRDG
34 +V1.8S_PWRGD
2 Q8
B B
2N7002
1
3
2
change 74AHC1G08 to Bat54a
R192
10K
D22
BAT54A 1
+V1.5S_PWRGD 1 3
4,34 +V1.5S_PWRGD +V3.3A 4,14,15,16,18,19,21,24,25,26,28,30,33,34,44,46,48
V1.5S_V1.05S_PWRDG
+V1.05S_PWRGD 2
35 +V1.05S_PWRGD
C564
0.1uF
R136
5
R124
1
24,38 DELAY_VR_PWRGOOD
0/NC 4 ALL_SYS_PCH_PWROK_EC
32,33,38,41,44,46,48 +V3.3S SYS_PWROK 16,48
ALL_SYS_PWRGD 2 1K
+V3.3A 4,14,15,16,18,19,21,24,25,26,28,30,33,34,44,46,48 U24
C563 74AHC1G08
3
R635 U15 0.1uF
5
33.2K
1% DDR_1.5S_1.8S_1.05S_PWRDG 1
.
4
2
3
R634 74AHC1G08 R101

100K 1K
1%
A . A
PM_1.5S1.05SMPWRGD 36,38

3
Q5
2N7002
1
4,32,33,34 -SLPS3_CONTROL R116
ALL_SYS_PWRGD
CK_PWRGD_R 19
0.85S & Power Sequence
2
0/NC
R117
24,38 DELAY_VR_PWRGOOD
0/NC C <Cage Code> 0.2

E450 37 of 50
5 4 3 2 1
5 4 3 2 1
1
+VCC_GFXCORE
1000PF
8.06K
R145
C14
R120
2 1
2
DNP: DO NOT POPULATE C22
2
2 1 10
2
VCCGT_SENSE 7
C269 330pF
C264 R172 C288 330pF C26
VSSGT_SENSE 7
1
1
2 1 2 1 2 1 2 1
R121
R135
47PF 270 1nF 1000pF 1 2
DNP
D D
C286 R150 R144
2
2 1 2 1 2 1 10
560PF 220K Ver02 2.43K

ISPG 40
如果data上有一个15ns低电平的毛刺， ISNG 40
R131改为100R NTCG 40
R131 0 1 R140 2
2 1 16.5K/NC
6 VR_SVID_DATA BOOTG 40
UGG 40
PHG 40
LGG 40
R128 0
+V3.3S 4,10,11,12,13,14,15,16,17,18,19,20,21,23,24,25,26,31,32,33,37,41,44,46,48
2 1
6 -VR_SVID_ALERT
48
47
46
45
44
43
42
41
40
39
38
37
PWM3_CPU
R163
1
COMPG
FBG
VSENG
RTNG
ISPG
ISNG
NTCG
BOOTG
UGG
PHG
LGG
PROG2
1 36 BOOT2
VWG BOOT2 BOOT2 39 +V5S 12,13,15,20,21,28,29,31,32,33,34,36,37,41,42,43,44
R173 0 R562
2
1.91K
2 1 2 35 UGATE2
6 VR_SVID_CLK IMONG UG2 UGATE2 39 1 2
3 34 PHASE2
PGOODG PH2 PHASE2 39
1
GTVR_PWRGOOD 0
+V3.3S 4,10,11,12,13,14,15,16,17,18,19,20,21,23,24,25,26,31,32,33,37,41,44,46,48
0
R130
4 33
SDA VSSP2
5 32 LGATE2
ALERT# LG2
1
LGATE2 39
2
C R156 6 31 C
SCLK U8 VDDP
1.91K IMVP7_VR_EN 7 30
VR_ON PWM3
1
1UF
1UF
ISL95831HRTZ
C223
C267
8 29 LGATE1
24,37 DELAY_VR_PWRGOOD PGOOD LG1 LGATE1 39
2
9 28
IMON VSSP1
10 27 PHASE1
4,24 -H_PROCHOT VR_HOT# PH1 PHASE1 39
C30 11 26 UGATE1
NTC UG1
1
2 1 UGATE1 39
47pf
C266
12 25 BOOT1
ISEN3 / FB2
OPEN VW BOOT1 BOOT1 39
R137 PLACE NEAR PQ5
2
R138 R137
PROG1
ISUMN
ISUMP
COMP
ISEN2
ISEN1
VSEN
2 1 2 1 49
VDD
RTN
EP
VIN
FB
DNP_3.83K_1% DNP_470K_ERT-J0EV474J
R161
R118
13
14
15
16
17
18
19
20
21
22
23
24
2 1
1 2
DNP_27.4K
4.3K
1
R165 VIN 13,27,28,33,34,35,36,37,39,40
1
2 1
1000PF
8.06K
R174
C13
0
2
+V5S 12,13,15,20,21,28,29,31,32,33,34,36,37,41,42,43,44
2
C172 DNP_10PF R149

R640 0 2 1 2 1
24,37,48 ALL_SYS_PWRGD
C20
ISEN2
1
1
R642 0/NC IMVP7_VR_EN
0.22UF
36,37 PM_1.5S1.05SMPWRGD
C21
1UF
ISEN1
39 ISEN2
2
R646 0/NC
16,24 PM_PCH_PWROK
B B
R146 C19 R168 C277
2 1 2 1 2 1 2 1 39 ISEN1
VSUM+
VSUM+ 39
C23 0.22UF
1
2 1
2.61K
DNP 33PF 499 470PF VSUM-
R139
C179 0.22UF
2 1
1
C17 R169 R167
0.22UF
0.033UF
10K_ERT-J1VR103J
2
11K
C32
C178
R171
2 1 2 1 2 1
1
150PF 316K 2.87K/1%
Ver02
R123
2
Ver02 Ver02
R127
2
1
330pF
C276 2 1 VSUM-
VSUM- 39
C18
2 1
1.2K/1%
1
330pF
0.1UF
6 VCCSENSE
C33
C27 R122
2 1 2 1
6 VSSSENSE
2
C285 * R123 PLACE NEAR L11
2 1 DNP_330pF DNP_100
1000pF
R170
2 1
A A

CPU VR1

E450 38 of 50
5 4 3 2 1
5 4 3 2 1
VIN 13,27,28,33,34,35,36,37,38,40
DNP: DO NOT POPULATE

PC32 PC33 PC34 PC35 PC28
5
6
7
8
PQ4
10uF/25V 10uF/25V 10uF/25V 10uF/25V 0.1uF/25V
UGATE2 4
38 UGATE2
AON6428L
1
2
3
D D
L10 +VCC_CORE
0.36uH
PHASE2
38 PHASE2
PC61
1
R5 C16
BOOT2 2 1 2 1
38 BOOT2
2
5
6
7
8
5
6
7
8
PQ7 PQ8 330uF/2.5V
2.2 0.22UF
R133 R119
LGATE2 4 4 ISEN2 2 1 2 1 ISEN1
38 LGATE2 ISEN1 38
AON6718L AON6718L 10K 10K/NC
1
2
3
1
2
3
If the layout of each phase to CPU
R132
VSUM+ 2 1
is symmetric.
R119,R160,R125,R164, can be
3.65K removed.
R134
They are used for phase current
VSUM- 2 1 balance adjustment.
1
VIN 13,27,28,33,34,35,36,37,38,40
PC36 PC37 PC38 PC39 PC29
5
6
7
8
PQ5
C 10uF/25V 10uF/25V 10uF/25V 10uF/25V 0.1uF/25V C
UGATE1 4
38 UGATE1
AON6428L
1
2
3
L11 +VCC_CORE
0.36uH
PHASE1
38 PHASE1
PC62
5
6
7
8
5
6
7
8
1
R142 C28 PQ9 PQ10
BOOT1 2 1 2 1
38 BOOT1
330uF/2.5V
2
2.2 0.22UF 4 4
R159 R125
LGATE1 AON6718L AON6718L ISEN1 2 1 2 1 ISEN2
38 LGATE1 ISEN2 38
1
2
3
1
2
3
10K 10K/NC
R151
VSUM+ 2 1
38 VSUM+
3.65K
R162
VSUM- 2 1
38 VSUM-
1
B B
A
CPU VR2

E450 39 of 50
5 4 3 2 1
5 4 3 2 1
VIN 13,27,28,33,34,35,36,37,38,39
C400
2 1 NTCG 38
OPEN
R187 R185 C654 C652 C653 C651 C655
2 1 2 1
10UF/25V10UF/25V10UF/25V10UF/25V 0.1uF/25V
D DNP_3.83K_1% DNP_470K_ERT-J0EV474J D
5
6
7
8
5
6
7
8
R186 PQ15 PQ16
2 1 +VCC_GFXCORE
2
DNP_27.4K
38 UGG 4 4
PJP23
AON6428L AON6428L
1
2
3
1
2
3
* R185 PLACE NEAR PQ15\PQ16 L12
1
0.45uH
38 PHG
PC56
1
R182 C399
38 BOOTG 2 1 2 1
5
6
7
8
5
6
7
8
PQ13 PQ14
2
2.2 0.22UF 330uF/2.5V
38 LGG 4 4
AON6718L AON6718L
1
2
3
1
2
3
C C
R183
38 ISPG 2 1
7.5K
10K
R178
Ver02
1
1
82nF
2200pF
10K_ERT-J1VR103J
2
11K
C364
C367
R180
2
1
R175
2
Ver02
R177 R184
2
38 ISNG 2 1 2 1
665/1% * R175 PLACE NEAR L12 1

1
0.1UF
C396
C363 R176
2 1 2 1
2
B B
DNP_220pF DNP_100

A A
Gforce VR
B <Cage Code> 0.2

E450 40 of 50
5 4 3 2 1
5 4 3 2 1
LINE2_VREFO C476 1UF
MVBIAS
MVBIAS
MIC1_VREFO_R MIC1_VREFO_L
C568 4.7K
R713
1UF Ver02
R220 0
HP_IN_BACK R680 0 MIC2 C570 1UF
AVDD MIC1_OUT 13
OUTL_IN C566
OUTR_IN
1UF
D D
C571 C573
MIC1 1UF
0.1UF 11K/NC R240
C505 C513
U26
36
35
34
33
32
31
30
29
28
27
26
25
+V5S 12,13,15,20,21,28,29,31,32,33,34,36,37,38,42,43,44 100PF 100PF
470PF/NC C55
Sense B
LINE_OUT_L
LINE_OUT_R
DCVOL
LINE2_VREFO
VREF
MIC1_VREFO_R
MIC2_VREFO
LINE1_VREFO
MIC1_VREFO_L
AVSS1
AVDD1
FB1 AVDD
37 24
MONO_OUT LINE1-R
38 23 U48B
100MHz/1.5A AVDD2 LINE1-L
4
LM358 1.1K/NC R221
39 22 C575 1UF AU_MIC1_R_LB 18K/NC - 6 4.7uF/NC C44
C554 HP_OUT_L MIC1-R 7
0.1UF R658 20K 40 21 C576 1UF AU_MIC1_L_LB + 5
JDREF MIC1-L R243 18K/NC R235 4.7K/NC
CE6 CE5 41 20 C45
8
HP_OUT_L CD-R R239 R724
10U 42 19
10U AVSS2 CD-GND 4.7uF/NC 18K/NC
43 18
GPIO0 ALC662 CD-L
MIC1_VREFO_L +V5S
44 17 MIC2 12,13,15,20,21,29,31,32,33,34,36,37,38,41,42,43,44
GPIO1 MIC2-R
45 16 MIC1
NC MIC2-L MIC1_VREFO_R 0/NC Ver03
46
DMIC_CLK LINE2-R
15 LINE2_R
R677 R705
Ver02 R725
GPIO2/DMIC_DATA
47 14 LINE2_L 4.7K 4.7K
SPDIFI/EAPD LINE2-L
DVDD_CORE
48 13 R679 0 R707 HP-IN
39.1K/NC
SDATA-OUT
SPDIFO Sense A
SDATA-IN
DVDD-IO
PCBEEP
RESET#
BIT-CLK
GPIO3
SYNC
DVSS
DVSS
MIC_JACK_SENSE_LB
+V5S
C R709 12,13,15,20,21,29,31,32,33,34,36,37,38,41,42,43,44 C
0/NC R681 51K R21775
1
10
11
12
AU_MIC1_R_LB
AU_MIC1_R_LB1 44
D1
R218 75
+V3.3S 4,10,11,12,13,14,15,16,17,18,19,20,21,23,24,25,26,31,32,33,37,38,44,46,48
2 AU_MIC1_L_LB
C569 AU_MIC1_L_LB1 44
R657 0
PC_BEEP BEEP1 3 1 BTL_ALARM
BTL_ALARM 24
C473 C474 C512
1UF 0.1UF 0.1UF C583 MIC_JACK_SENSE_LB
1uF BAT54S/NC MIC_JACK_SENSE_LB1 44
100PF
R663 0
4.7K
14 HDA_SDOUT
14 HDA_BIT_CLK
R659
HP_IN_BACK R660 39.1K
14 HDA_SDATAIN0 R402 33
14 HDA_SYNC
14 -HDA_RST
HP-IN HP-IN 44
C475
C515 C514 C502 R71475
C511 LINE2_R CE2 22U LINE2_R1 44
100PF 22PF 100PF 100PF 100PF
R20475
LINE2_L CE3 22U LINE2_L1 44
.
.
+V5S 12,13,15,20,21,28,29,31,32,33,34,36,37,38,42,43,44
SHUTDOWN R710 0NC
C503
B B
FB2 0.1uF/NC
100MHz/1.5A
C574
0.1uF
+V5S 12,13,15,20,21,28,29,31,32,33,34,36,37,38,42,43,44
CE1 CE4
C469 10U
10U
0.1UF
MS25004411-00
SPK_R2 FB14 1 100MHz/1.5A Z2207
SPK_R1 FB4 1 100MHz/1.5A Z2208 1
SPK_L1 FB17 1 100MHz/1.5A Z2209 2 6
SPK_L2 FB3 1 100MHz/1.5A Z2210 3 5
4
R701 R702
15
16
U27 CON4
6
10K/NC 10K
Ver03
PVDD
PVDD
VDD
C579 C581 C584 C586

220pF 220pF 220pF 220pF
1 2
11 GND Gain0 12
13 GND NC 3
R219 75K 20 GND Gain1
GND . . . .
OUTL_IN C572 4.7uF 5 8 SPK_L2
9 LIN- LOUT- 4 SPK_L1 R703 R704
OUTR_IN R405 75K C468 4.7uF 17 LIN+ LOUT+ 14 SPK_R2
RIN- ROUT- 10K 10K/NC
7 18 SPK_R1
. RIN+ ROUT+
ShutDown
BYPASS
21
. GND +V5S 12,13,15,20,21,28,29,31,32,33,34,36,37,38,42,43,44
A C472 C477 A
4.7uF 4.7uF EU6027A R706
10
19
. . 20K
SHUTDOWN Gain0 Gain1 Av(inv)

C471
4.7uF
0 0 6dB
. 0 1 10dB AUDIO
1 0 15.6dB
1 1 21.6dB
C <Cage Code> 0.2

E450 41 of 50
5 4 3 2 1
5 4 3 2 1
SATA-HDD
D
J3 PACKAGE: 同E100 D
sata_C166s6-100a_ALLTOP
S2 S1
14 SATA_TXP0 TX GND_2m_S_1
S3 S4
14 SATA_TXN0 TX# GND_2m_S_4
S6 S7
14 SATA_RXP0 RX GND_2m_S_7
S5
14 SATA_RXN0 RX#
P1 P4
P2 V_3.3_1 GND_1m_P_4 P5
+V5S 12,13,15,20,21,28,29,31,32,33,34,36,37,38,41,43,44 V_3.3_2 GND_2m_P_5
P3 P6
R715 V_3.3_3_PC GND_2m_P_6
FB18 100ohm@100MHz 0 P7
P8 V_5.0_7_PC
C587 C588 P9 V_5.0_8 P10
C591 0.1uF 0.1uF P11 V_5.0_9 GND_2m_P_10
22U 10% 10% P_Reserve_11 P12
. P13 GND_1m_P_12
P14 V_12_13_PC G1
P15 V_12_14 Mech1 G3
V_12_15 Mech2
G2
Mech3
G4
Mech4
CON SATA HDD CEN-TBF0-01307-21XX
sata_C166s6-100a_ALLTOP
C C
SATA-ODD
(PACKAGE:sata_91929_ACES)
J7 12,13,15,20,21,28,29,31,32,33,34,36,37,38,41,43,44 +V5S
S1
S2 GND1 P6 100ohm@100MHz FB24
14 SATA_RXP2 A+ +5V2
14 SATA_RXN2 S3 P5
A- MD
S4 P4 C592 C595
S5 GND2 GND5 P3 0.1uF 0.1uF C597
14 SATA_TXN2 B- DP 22U
14 SATA_TXP2 S6 P2 10% 10%
S7 B+ +5V1 P1 .
GND3 GND4
1 3
B
2 NC1 3 4 B
NC2 4
SATAODD
sata_91929_ACES
A
SATA HDD & ODD

5 4
www.teknisi-indonesia.com 3
Thursday, May 22, 2014 Scale
2
Model
E450
Sheet
1
42 of 50
5 4 3 2 1
+V5S 12,13,15,20,21,28,29,31,32,33,34,36,37,38,41,42,44
D D
F1
SMD1812P150TS-1.5A
FB15
R726 270K USB0_VCC USB0_VCC_FB
18 -USB_OC0
R727 50 OHM
C611 C610 C609 C608
.
22U 22U 22U 470PF
560K
J14
USB0_VCC_FB 1
L16 PWR 5
1 2 2 GND2 6
18 USB_PN1 D- GND3
3 7
4 3 USB0+ D+ GND4 8
18 USB_PP1 GND5
4
C GND1 C
90_100MHz
USB
320040-03GS-00H
R721 R719 R720
ESD-E12/X
ESD-E12/X
ESD-E12/X
B B

A A
ESATA & USB Ports

B <Cage Code> 0.2

E450 43 of 50
5 4 3 2 1
5 4 3 2 1
TOUCH PAD CONNECTOR

+V5S 12,13,15,20,21,28,29,31,32,33,34,36,37,38,41,42,43
24 KBC_SCANOUT[15:0] For K/B CONNECTOR

KBC_SCANOUT0 120ohm@100MHz_L0603
KBC_SCANOUT1 FB25
KBC_SCANOUT2 CON24
KBC_SCANOUT3 C623 C622
KBC_SCANOUT4 R743 R742 4.7uF 0.1uF ZI90-092D-12R0
KBC_SCANOUT5 KBC_SCANOUT15 24 10K 10K 10% 10% CON FFC CEN-ZI90-092D0-12R0
KBC_SCANOUT6 KBC_SCANOUT14 23 24 5% 5% . .
23 . .
KBC_SCANOUT7 KBC_SCANOUT13 22 1 13
KBC_SCANOUT8 KBC_SCANOUT12 21 22 120ohm@100MHz_L0603 2 1 13
KBC_SCANOUT9 KBC_SCANIN7 20 21 FB22 FB_TP_DATA 3 2
D 20 24 KBC_TP_DATA 3 D
KBC_SCANOUT10 KBC_SCANOUT11 19 FB_TP_CLK 4
KBC_SCANOUT11 KBC_SCANOUT10 18 19 FB26 5 4
18 24 KBC_TP_CLK 5
KBC_SCANOUT12 KBC_SCANIN6 17 6
KBC_SCANOUT13 KBC_SCANIN5 16 17 120ohm@100MHz_L0603 7 6
KBC_SCANOUT14 KBC_SCANOUT9 15 16 8 7
KBC_SCANOUT15 KBC_SCANIN4 14 15 26 TOUCH_PAD_RIGHT 9 8
24 KBC_SCANIN[7:0] 14 GND2 9
KBC_SCANIN0 KBC_SCANOUT8 13 10
KBC_SCANIN1 KBC_SCANOUT7 12 13 11 10 14
KBC_SCANIN2 KBC_SCANOUT6 11 12 25 TOUCH_PAD_LEFT 12 11 14
KBC_SCANIN3 KBC_SCANOUT5 10 11 GND1 12
KBC_SCANIN5 KBC_SCANOUT3 8 9 CON15
KBC_SCANIN6 KBC_SCANIN3 7 8 FB32
KBC_SCANOUT1 5 6 120ohm@100MHz_L0603
KBC_SCANOUT0 4 5
KBC_SCANIN2 3 4
KBC_SCANIN1 2 3
2
KBC_SCANIN0 1
1 TOUCH PAD LEFT/RIGHT BUTTON
TOUCHPAD (CON15)
E400 KEYBOARD CONN
88513-24x5x_aces
+V5S 12,13,15,20,21,28,29,31,32,33,34,36,37,38,41,42,43
线序已更改同 TM-00372-027
Doking Keyboard. 封装已更改同 E220
(DOK-6129B_US) Keyboard-CON 20100629
R744 R745
10K 10K
5% 5%
. .
SW2 SW3
C 1 3 3 1 C
TOUCH_PAD_LEFT 2 4 4 2 TOUCH_PAD_RIGHT
5 5
C625 C624
0.1uF 2P2T 12V/50MA SMD H=3.1mm STS-043-A 0.1uF
10% 2P2T 12V/50MA SMD H=3.1mm STS-043-A 10%
For LID SW . .
+V3.3A 4,14,15,16,18,19,21,24,25,26,28,30,33,34,37,46,48
R729 R734
1K 5%
51K
-LID_IN 24
PQ32
For BLUETOOTH
2
AH180-WG
MB & I/O-CON C614

1
C613
0.01uF
.
+V3.3S 12,13,15,20,21,28,29,31,32,33,34,36,37,38,41,42,43
0.1uF 10%
10% ver02
+V5S 12,13,15,20,21,28,29,31,32,33,34,36,37,38,41,42,43
3
J17
ZI90-092D0-24R0_cen 120ohm@100MHz_L0603
FB41
6
24pin CONN 18 USB_PN10 5
18 USB_PP10 4 8
24 3 7
24 24 BLUETOOTH_ONOFF
23 2
23 22 46 -LED_BLUETOOTH 1
22 21
21
20
20
19
-USB_OC4 18 For 3G SIM/UIM CARD C619 C618
0.1uF/NC FB40
BLURTOOTH
19 18 10%
B 18 USB_PN9 18 10U 120ohm@100MHz_L0603 B
17
17 USB_PP9 18
16
16 15 R736
26 15 14 0 J19 SIM-6P-TAISOL
GND2 14 USB_PN8 18
1
13 25 SIM_POWER SIM_POWER
13 12 USB_PP8 18 SIM_RST 1
12 25 SIM_RST 2
25 11 SIM_CLK
GND1 11 10 25 SIM_CLK 3 TP22
10 9 4
9 8 5
8 MIC_JACK_SENSE_LB1 41 6
7 SIM_DATA
10
11
7 AU_MIC1_R_LB1 41 25 SIM_DATA 7
8
9
6
6 AU_MIC1_L_LB1 41
5
5
4
4
HP-IN
LINE2_R1
41
41
For touch screen
3 R735
3 LINE2_L1 41 C615
2 0
2 1
1 0.1uF 5% +V5S 12,13,15,20,21,28,29,31,32,33,34,36,37,38,41,42,43
10% .
CON26 CON3
120ohm@100MHz_L0603
FB30
1
18 USB_PN11 2 6
18 USB_PP11 3 5
4
MS25004411-00
C617 C616 FB31
0.1uF/NC
PACKAGE Debug Connector 10U 10% 120ohm@100MHz_L0603
ZI90-092D0-24R0_cen +V3.3S 4,10,11,12,13,14,15,16,17,18,19,20,21,23,24,25,26,31,32,33,37,38,41,46,48
朝向
CON13
A A
1 2 LPC_AD1
18 CLK_PCI_LPC LPC_AD1 14,24
3 4 LPC_AD0
18,24,25,26,30 -BUF_PLT_RST LPC_AD0 14,24
-LPC_FRAME 5 6
14,24 -LPC_FRAME
14,24 LPC_AD3
14,24 LPC_AD2
LPC_AD3
LPC_AD2
7
9
8
10
HEADER 5X2/NC
Board Connector
C <Cage Code> 0.2

E450 44 of 50
5 4 3 2 1
5 4 3 2 1
DC IN-PORT
28 DC_ALL_IN CON7
D D
DC POWER JACK 20V 7A 2DC-G028B200 SINGATRON
L43
1
220Z/3A 100M P1
C621 2
P2
3
4
5
L42 0.1uF/25V
C0603
3
4
5
220Z/3A 100M
DC-GND
C C
POWER BUTTON
SW1
1 3
-PWR_SW_BTN_B 2 4
24 -PWR_SW_BTN
5
C620
0.1uF
10%
. 2P2T 12V/50MA SMD H=3.1mm STS-043-A
B B

A DC-PORT & POWER-BUTTON A

A <Cage Code> 0.2
Scale Model Sheet
Thursday, May 22, 2014 E450 45 of 50
5 4 3 2 1
5 4 3 2 1
PWRSTS WLAN BATT-LED HDD
LED2 LED3 LED1 LED4

LED
D D
TOP Left Right
+V3.3S 4,10,11,12,13,14,15,16,17,18,19,20,21,23,24,25,26,31,32,33,37,38,41,44,48
+V3.3A 4,14,15,16,18,19,21,24,25,26,28,30,33,34,37,44,48 +V3.3S 4,10,11,12,13,14,15,16,17,18,19,20,21,23,24,25,26,31,32,33,37,38,41,44,48
R814 R819 R821

R816 R818 R815 330 330 330
330 330 330 5% 5% 5%
5% 5% . . .
5% . . .
P
3
1
P
3
1
LED3 LED4
LED1 LED2 R817 D-LED
D-LED 10K
5%
.
N
C C
2
N
4
-LED_BAT_EXIST
24 -LED_BAT_EXIST
-LED_BAT_CHARGE -LED_WLAN
24 -LED_BAT_CHARGE 25,26 -LED_WLAN
-SATA_LED
14 -SATA_LED
LED_PWRSTS
24 LED_PWRSTS
+V3.3S 4,10,11,12,13,14,15,16,17,18,19,20,21,23,24,25,26,31,32,33,37,38,41,44,48
R820
10K
5%
B . B
D13
-LED_WWAN_OUT 1 3
25 -LED_WWAN_OUT
2
44 -LED_BLUETOOTH
BAT54A

A A
LED
B <Cage Code> 0.2

E450 46 of 50
5 4 3 2 1
5 4 3 2 1
I/O & MB-CON

GND-I/O
GND_CODEC-I/O
I/O & MB-CON
D +V5S-I/O D
ZI90-092D0-24R0_cen
24pin CONN
+V5S-I/O
1
1 2
2 3
3 4
4 5 F4 SMD1812P150TS-1.5A
5 6 -USB_OC4-I/O
6 7
7 USB_PN9-I/O
8
8 USB_PP9-I/O
9
9 10
25 10 11 FB35
R780
GND1 11 12 USB_PN8-I/O 10K
12 USB_PP8-I/O -USB_OC4-I/O
13
26 13 14 C631 C634 C633
GND2 14
15
16
17
15
16
17
MIC_JACK_SENSE_LB1-I/O
R779
15K
50OHM
. 10U 10U 10U
C632
470PF USB PORT
18
18 19 AU_MIC1_R_LB1-I/O
19 AU_MIC1_L_LB1-I/O
20
20 21 HP-IN-I/O
21 LINE2_R1-I/O
22
22 LINE2_L1-I/O
23
23 24 J12
24
1
90_100MHz PWR 5
CON27 4 3 2 GND2 6
USB_PN9-I/O D- GND3
3 7
1 2 D+ GND4 8
USB_PP9-I/O 4 GND5
GND1
L14
USB
R768 R767 R765
C C
ESD-E12/X
ESD-E12/X
ESD-E12/X
PACKAGE
ZI90-092D0-24R0_cen
朝向
FB36
C635 C638 C637

50OHM C636
. 10U 10U 10U 470PF
R778
MIC_JACK_SENSE_LB1-I/O
20K
MIC
C630 R777
J11
0.1uF 0/NC
L15 1
PWR 5
4 3 2 GND2 6
L3 PH5 USB_PN8-I/O 3 D- GND3 7
120ohm@100MHz 5 1 2 D+ GND4 8
3 USB_PP8-I/O 4 GND5
AU_MIC1_R_LB1-I/O R776 0 4 GND1
6 90_100MHz USB
L7 2 R783 R782 R781
AU_MIC1_L_LB1-I/O
120ohm@100MHz 1
ESD-E12/X
ESD-E12/X
ESD-E12/X
9
10
B B
R775 R774 C628 C629
100pF 100pF AAN8011-GA-20 6P PINK G-FLASH
0/NC 0/NC 5% 5%
HP-IN-I/O
R773
EARPHONE
20K
R771
0/NC
L5 PH6
120ohm@100MHz 5
3
LINE2_R1-I/O 4
R772 0
6 H58 H59
L6 2 HOLE_S7_0D2_8 HOLE_S7_0D2_8
LINE2_L1-I/O
120ohm@100MHz 1
A 9 A
R770 R769 10
C626 C627
100pF 100pF 0/NC 0/NC
5% 5%
6.0/3.2/14.00 6P LGT GREEN G-FLASH AAN8011-GC-20

H57
hole_p7_0d2_8
I/O BOARD USB & MIC-EARPHONE

E450 47 of 50
5 4 3 2 1
5 4 3 2 1
CON9
DEBUG FO CPU AND PCH
20,21,23,32,35 +V1.05S
4,14,15,16,18,19,21,24,25,26,28,30,33,34,37,44,46 +V3.3A 1 2
3 GND0 GND1 4
4 -XDP_PREQ OBSFN_A0 OBSFN_C0
5 6
4 -XDP_PRDY OBSFN_A1 OBSFN_C1
7 8
9 GND2 GND3 10 4,10,11,12,13,14,15,16,17,18,19,20,21,23,24,25,26,31,32,33,37,38,41,44,46 +V3.3S
4 XDP_BPM0 OBSDATA_A0 OBSDATA_C0
R858 11 12
4 XDP_BPM1 OBSDATA_A1 OBSDATA_C1 4,14,15,16,18,19,21,24,25,26,28,30,33,34,37,44,46 +V3.3A
10K/NC 13 14
15 GND4 GND5 16 -PM_RSMRST_XDP R638 1K/NC
4 XDP_BPM2 OBSDATA_A2 OBSDATA_C2 -PM_RSMRST 16,24
17 18
D 4 XDP_BPM3 OBSDATA_A3 OBSDATA_C3 3,4,6,13,20,21,24,32,36 +V1.05S_VCCP D
H_SYS_PWROK_XDP 19 20
21 GND6 GND7 22
4,25,26,28,30,33,34,37,44,46 +V3.3A 23 OBSFN_B0 OBSFN_D0 24 R897
25 OBSFN_B1 OBSFN_D1 26 0/NC
3,4,6,13,20,21,24,32,36 +V1.05S_VCCP 27 GND8 GND9 28
4 XDP_BPM4 OBSDATA_B0 OBSDATA_D0
29 30 R868
31 32 R853
R885 33 GND10 GND11 34 R884 0 1K
R886 35 36 0/NC R852
0 37 38 51
0/NC R854 1K HOOK0 39 GND12 GND13 40 CLK_XDP_P
4,19 H_CPUPWRGD PWRGOOD/HOOK0 ITPCLK/HOOK4 PCIE_CLK_XDP_P 15
R855 0 41 42 CLK_XDP_N
16 -PM_PWRBTN_R HOOK1 ITPCLK#/HOOK5 PCIE_CLK_XDP_N 15
43 44
R856 1K 45 VCC_OBS_AB VCC_OBS_CD 46 R627 1K
9 CFG0 HOOK2 RESET#/HOOK6 -PLT_RST 4,18
R857 0 H_SYS_PWROK_XDP 47 48
16,37 SYS_PWROK HOOK3 DBR#/HOOK7 -XDP_DBRESET 4
49 50
51 GND14 GND15 52 R697 0
10,15,23 SMB_DATA_S SDA TDO XDP_TDO 4
53 54 R693 0
10,15,23 SMB_CLK_S SCL TRSTN -XDP_TRST 4
55 56 R694 0
R867 0 57 TCK1 TDI 58 R696 0 XDP_TDI 4
4 XDP_TCK TCK0 TMS XDP_TMS 4
59 60
GND16 GND17
XDP R722 0/NC -XDP_DBRESET R690 0/NC

PCH_JTAG_TDO 14 -PM_SYSRST 16
R761 0/NC
PCH_JTAG_TMS 14
R866 0/NC
PCH_JTAG_TDI 14
R723 0/NC
PCH_JTAG_TCK_BUF 14
C C
For PCH debug with XDP, need to NO STUFF R364
To debug for pch:

Stuff: R858\R886\R772\R761\R866\R732
\R895\R897\R884\R638
Unstuff:R854\R885\R857\R867\R868\R856
R627\R697\R693\R694\R696\R278\R279
-PM_RSMRST_XDP R895 0/NC HOOK0
R896 0/NC
24,37,38 ALL_SYS_PWRGD
To debug for CPU:

Stuff: R885\R854\R856\R857\R867\R868\R627\R690
Unstuff:
B B
A A

XDP
LIZX Custom <Cage Code> 0.2
4 3
2
Scale Model
E450
1
Sheet
48 of 50
5 4 3 2 1
+V3.3A
+V3.3A_KSC
0Bat +VBAT 2Bat 6AC
Battery +V3.3A_KSC
Pack 4
+V5A -PWR_SW_BTN
0AC SYS VR 1 +V5A_KSC
+VIN SWITCH Power_button
5VA_3VA_PWRGD
AC
adapter +VIN +V5A_KSC Power Route
+VBAT
5
D D
+V5S
5VA_3VA_ON
-PWRSW
+V5A 3
+V3.3S SW
9 +V3.3A
EC
+V1.5S
+V1.5
15 PM_PCH_PWROK
SLP_S3#
8c
+V1.8S
delay 99ms 14 ALL_SYS_PWRGD
+V3.3A 9
1.8S VR
PM_PWRBTN#
PM_RSMRST#
+VBAT
7a 7b
C C
+V1.5
PWROK SLP_S5# 8a
SLP_S4#
DDR VR
9 SLP_S4# 8b
+V0.75
SLP_S3#
APWROK
APWROK:
For platforms not supporting Intel AMT
it can be connected to PWROK. PCH SLP_SM#
SLP_S3#
8c
8c
NO M3 Support,So SLP_M# can be leaved as No Connect
+V1.05S 9
PROCPWRGD
DRAMPWROK
PLTRST#
SYS_PWROK 21
SYS_PWROK
SLP_S3#
1.05S VR
B B
DELAY_VR_PWRGD 20
PM_DRAM_PWRGD 16
+V1.05S
SM_DRAMPWROK
+V1.5
PM_V*S_APWRGD
11 & H_CPUPWRGD 17
+V1.5S ALL_SYS_PWRGD 14
UNCOREPWRGOOD
&
CPU
+V1.8S
BUF_PLT_RST# 22
RSTIN#
+V1.05S_VCCP 18
+V0.85S SVID
11 12
PM_V*S_APWRGD 13
1.05S_VCCP VR 1.05S_VCCP_PWRGD
+V0.85S VR 0.85S_PWRGD
14
+VCC_CORE
18 IMVP7_SVID_DATA/CLK/ALERT#
A 19 A
ALL_SYS_PWRGD 14 +VCC_GFXCORE IMVP7

CK505
CPU VR HASEE TECHNOLOGY INC.,
DELAY_VR_PWRGD 20 PWR SEQUENCE BLOCK
LIZX C <Cage Code> 0.2

E450 49 of 50
5 4 3 2 1
5 4 3 2 1
Change List from Ver01 to Ver02 Change List from Ver02 to Ver03 Change List from Ver03 to Ver10
1、Page4,Pull-up R25 from +V3.3S changed to +V3.3A 1、Page35,add R670 1、Page14,add R268\R269
Page36,add PJP33
2、Page4, R25,R22,Q65,Q67 all NoStuff (Vccp substitute for V1.05s) 2、Page37,add C493
R23 Stuff
3、Page7, PQ45,Q22,R58 all NoStuff 2、Page41,con4 change

R59 Stuff add R725
4、Page14, U29、R243 、R618、R785、R787、R788、C641 Deleted (SPI1 Flash Del)
D R240、R616、R784 Deleted （SPI0 series-resistor Del） D
5、Page19,U4,C121,R487 all NOstuff
6、Page23,All NoStuff
7、Page24,C384,C385,Y5,R522,R600,R718 All NoStuff; R847,C368 Stuff

同时 Page18， R352 Stuff
R882 Stuff
8、Page28,H33\H32 change the footprint
9、Page33, PR152--〉220K,R842-->1M,C537-->0.1UF,C674-->0.01UF(Stuff)
10、Page36,C358 change and NC
11、Page37, C483 change and NC; R909-->Stuff

12、Page14, Isolate HDA_SYNC from the codec during the strap:
Add R787(Stuff),Q51,Q46,R247
13、Page44,J17(for bluetooth) pin6, from +V5s changed to +V3.3s
C
14、Layout J6和J14的库要更改及PCH上方邮票孔位置更改 C
15、About the Power:

L13(2.2u)-->1u---------------------------------------------+V1.5
C537(0.01U)-->0.1U-----------------------------------------+V5A
C178-->33nF,R167-->2.87K,R127-->1.2K all 1%--------------+VCORE
C364-->82nF,C367-->2200pF,R177-->665,R144-->2.43K,
R150-->220K,R172-->270,C286-->560pF,C288-->1nF,C264-->47pF-------+VGFORCE
16、Page34, add C641-->0.22uF,C645-->1uF

change C647 -->33nF
17、Page41,add R220 and amplifier for Mic in
B B

A A
PWR SEQUENCE BLOCK

LIZX B <Cage Code> 0.2

E450 50 of 50
5 4 3 2 1

HASEE A420P e450

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5 4 3 2 1

Sandy Bridge Mobile PROCESSOR

HASEE TECHNOLOGY INC.,

Draw by Size CAGE Code DWG NO Rev

Thursday, May 22, 2014 Scale Model Sheet

Page 3-9 Dual channel DDR3

HASEE TECHNOLOGY INC.,

Draw by Size CAGE Code DWG NO Rev

Thursday, May 22, 2014 Scale Model Sheet

PCI EXPRESS* - GRAPHICS

Sandy Bridge_rPGA_Rev1p0 HASEE TECHNOLOGY INC.,

Draw by Size CAGE Code DWG NO Rev

Thursday, May 22, 2014 Scale Model Sheet

R9 56/1% -H_PROCHOT_D AL32 AK1 SM_RCOMP_0

JTAG & BPM

18,48 -PLT_RST A VCC

CLOSE TO CPU Q40

3,6,13,20,21,24,32,36,48 +V1.05S_VCCP SM_RCOMP_0

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Thursday, May 22, 2014 Scale Model Sheet

DDR SYSTEM MEMORY B

DDR SYSTEM MEMORY A

R38 1K -DDR3_DRAMRST_R 3 2 -CPUDRAMRST_R R39 0 -CPUDRAMRST

HASEE TECHNOLOGY INC.,

MB Bottom Socket Cavity:10 x 22 μF

PEG AND DDR

330uF/2.5V 330uF/2.5V 330uF/2.5V/NC330uF/2.5V/NC R31 VCC84

HASEE TECHNOLOGY INC.,

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Thursday, May 22, 2014 Scale Model Sheet

DDR3 -1.5V RAILS

AM23 AF4 +V1.5S_VCCDDQ

330uF/2.5V AM18 VAXG28 VDDQ4 AC4

C105 C106 C107 R56

C0603 C0402 C0402 330uF/2.5V VCCSA_VID1 VCCSA_SEL 37

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Thursday, May 22, 2014 Scale Model Sheet

Draw by Size CAGE Code DWG NO Rev

Thursday, May 22, 2014 Scale Model Sheet

HASEE TECHNOLOGY INC.,

Draw by Size CAGE Code DWG NO Rev

Thursday, May 22, 2014 Scale Model Sheet

HASEE TECHNOLOGY INC.,

Draw by Size CAGE Code DWG NO Rev

HASEE TECHNOLOGY INC.,

Draw by Size CAGE Code DWG NO Rev

CRT_DDC_CLK and DATA:

HASEE TECHNOLOGY INC.,

Draw by Size CAGE Code DWG NO Rev

Thursday, May 22, 2014 Scale Model Sheet

24 WEB_CAM Q35 SI2301BDS

L_BKLT_CTRL R665 100/NC

Thursday, May 22, 2014 Scale Model Sheet

CMOS SET RTC_RST#

4,15,16,18,19,21,24,25,26,28,30,33,34,37,44,46,48 Clear Cmos GND

AM3 SATA_RXN0_C C272 0.01uF SATA_RXN0 42

T3 AH1 RBIAS_SATA3 R233 750/1%

4,15,16,18,19,21,24,25,26,28,30,33,34,37,44,46,48 +V3.3A PLL On Die Voltage Regulator Selection

HDA_SDOUT_R 3 2 R251 1k/NC

Ver02 4,10,11,12,13,15,16,17,18,19,20,21,23,24,25,26,31,32,33,37,38,41,44,46,48 +V3.3S

C R262 0 CLK_PCH_SRC1_N AB49 AV22 CLKOUT_DMI_N C

可以不用上拉 V37 CLKOUT_PCIE7N CLKOUTFLEX0 / GPIO64

-CLK_SLOT0_OE R832 10K

-CLK_SLOT4_OE R831 10K