A Low-Cost Control IC for Single-Transistor ZVS Cold-Cathode Fluorescent Lamp
Inverters and DC/DC Converters
Richard Red1
ELF1 S.A.
Derrey-la-Cabuche
CH-1756 Onnens FR
Switzerland
Abstract-The paper reviews the various inverter topologies
for cold-cathode fluorescent lamps, discusses the analysis and
control of the class E inverter, and introduces a new control IC
developed for such inverters and also for ZVS dddc converters.
The IC features a zero-voltage detector, switch overdissipation
protection, soft start, pulse-by-pulse current limit, overvoltage
protection, and onloff switching with a low-current stand-by
mode. The primary use of the IC is in inverters for cold-cathode
fluorescent lamps for display backlight applications, but the IC
is also suitable for controlling ZVS quasi-resonant and multi-
resonant dddc converters.
I. INTRODUCTION
This paper discusses a new low-cost, high-performance
control IC developed for single-transistor zero-voltage-
switching (“ZVS”) inverters and dc/dc converters. The IC
hosts a number of innovative features, including an internal
zero-voltage detector for ensuring ZVS operation under most
operating conditions, overdissipation protection of the power
switch for the case when ZVS is lost, soil start, pulse-by-pulse
current limit, overvoltageprotection, and ordoff control with a
low-current stand-by mode. The primary application is in
invertersfor coldcathode fluorescent lamps (“CCF”’). Such
lamps are widely used as backlight sources, for example in
displays for notebook computers. The IC is also suitable for
controlling ZVS quasi-resonant and multi-resonant dc/dc
converters.
The paper presents (1) the special inverter requirements of
cold-cathode fluorescent lamps, (2) a review of CCFL inverter
topologies, including a new class E-type single-transistor
reduced-partaunt circuit, (3) the analysis and control of the
class E CCFL inverter, (4) the architecture and description of
the new control IC, and (5) the application of the IC in a CCFL
inverter, together with experimental results.
11. INVERTER REQUIREMENTS FOR COLDCATHODE
FLUORESCENTLAMPS
Designing inverters for coldcathode fluorescent lamps for
backlight applications presents a special challenge for a
number of reasons:
$1 0.00 01997 IEEE
0-7803-3704-2/97 1042
Koji Arakawa
Toko, Inc.
18 Oaza Gomigaya
Tsurugashimashi
Saitama
350-02 Japan
0 The inverter must accept any terminating resistance from
zero to infinity.
0 The inverter must provide up to 2000 V peak ignition
voltage for the CCFL. In case the lamp is open, the output
voltage should be limitedto a safe value to prevent dielectric
breakdown.
0 The supply voltage varies over a wide range, e.g. 6 to 16 V.
0 High electrical efficiency and lamp efficacy (lumens per
watt) are essential, especially in battery-powered
applications.
0 The nominal operating voltage of the CCFL is in the
several-hundred-volt range. CCFLs, like all gas discharge
lamps, are very nonlinear and their characteristics depend
on t e m p m m and lamp age. Additionally, the lamps show
negative resistance at low frequency. The inverter must
provide proper ballasting for the lamp to prevent failure or
system instabilities, and to maintain constant output power
with varying supply voltage.
0 To ensure high efficacy and small interference, a
low-distortion sine-wave drive is needed.
0 Dc voltage across the lamp is not allowed because it will
lead to uneven light emission, due to redistribution of the
mercury ions inside the tube. Capacitive ballasting is not
acceptable if there is even-harmonic distortion in the drive
waveform, because that, together with the asymmetrical
nonlinearity of the lamp characteristic, will lead to dc
voltage across the lamp.
0 In many applications the inverter must be able to provide
dimming to the lamp.
0 Cost and size must be minimal.
111.-VIEW OF CCFL INVERTER TOPOLOGIES
Fig. 1 shows the most frequently used topology, the
push-pull current-source parallel-resonantinverter, or CSPRI
(sometimes incorrectly called Royer inverter), with a buck
converter (S, and D) added for power regulation. (Royer et al.
[11described a push-pull square-wave self-oscillating inverter,
where the timing was based on saturation of the core of the
output transformer. In CSPRI circuits used for powering
CCFL, the output voltage is a sine wave, and the timing is
usually based on the resonance of the transformer’s
magnetizing inductance and a capacitanm in parallel with the
primary winding. The basic idea of the CSPRI was probably
first presented in [2], well before [l]. The self-oscillating
CSPRI without the buck converter was introduced in [3], and
was called “current-switching Class D.”)
3
CCFL
p
@
II
L--- -4
-
-
Fig. 1. Current-wurce parallel-resonant inverter with buck pmegulator.
The CSPRVbuck-preregulator combination has several
disadvantages, including:
0 low efficiency due to two power switches in series;
0 reduced eflicacy due to distorted lamp voltage and current’;
0 large E M due to hard-switching buck preregulator and
unrelated switching frequencies of the preregulator and the
inverter; and
0 high cost due to complex circuit topology and expensive
control IC.
‘Note:The lamp voltage distortion is caused by two factors:
(1) the transformer’s leakage inductance, which is not absorbed
into the load network, and (2) the ripple current flowing into
the inverter section.
Fig. 2 shows the CS-ZVS (Current Synchronous Zero
Voltage Switching) half-bridge inverter [4]. The circuit is
more &&nt thanthe CSPRVbuck-preregulatorcombination,
but it has also a rather complex topology, with two controlled
switches, two magnetics, and three capacitors in the power
train. Other drawbacks of the circuit are:
0 The leakage inductance of the transformer is not absorbed
in the load network, leading to significant lamp voltage
distortion and reduced efficacy.
1043
I i\s4
Fig. 2. CS-ZVS inverter.
0 The topology is claimed to be proprietary, and can be used
only with an expensive single-source dedicated control IC.
0 When used with the dedicated control IC, the inverter
requires complementary (n-channel and p-channel)
MOSFETs; alternatively it would require a floating drive.
Fig. 3. Class E CCFL, inverter.
Fig. 3 shows the schematic of a single-transistor inverter,
based on the Class E topology [5]. That circuit has a number
of advantages, compared with the inverters of Figs. 1 and 2.
Those advantages are as follows:
Only one switch is required;that simplifies the drive circuit.
The leakage inductance of the transformer is absorbed in the
load network, leading to smooth lamp waveforms and high
efficacy.
The inverter is fed with an inductance (at least in the basic
version), therefore the interference current reflected back to
the source is small.
The switch voltage wavdorm is smooth with a low dv/dt, so
the capacitive interference is reduced.
The topology is public domain.
The class E inverter has two disadvantages, (1) relatively
high voltage (three to five times the supply voltage) across the
power switch and (2) a slightly asymmetrical output voltage
due to the inherent second-harmoniccomponent in the output
voltage of the inverter. At the low supply voltages used in
battery-powered equipment, the first disadvantage does not
present a serious limitation. The voltage asymmetry is more of
a concern due to the possible migration of mercury ions and
the resulting asymmetrical light emission of the CCFL..
However, by proper design of the load network of the inverter,
the asymmetq can be reduced to such a low level that it causes
no problem. Note also that in the class E inverter there is no
need for a Mast capacitor in series with the lamp, so a voltage
asymmetry does not lead to dc voltage across the lamp. The
reason for that is that the lamp is driven directly by a
transformer winding therefore no dc voltage can appear across
it. (Note: The dc voltage is the primary cause of the migration
of mercury ions, through the phenomenon of electrophoresis.)

Fig. 4. New Class E CCFL inverter with reduced part-count and reduced-size of
feed inductor.

In the class E inverter of Fig. 3 the resonant inductor L, is

in series with the primary winding of the output transformer.
This allows the absorption of the leakage inductance of the
transformer in the resonant network; it also offers the
possibility of integrating the resonant inductor with the
W o r m e r . The integration of two magnetic parts leads to the
reduction of the overall cost. By recognizing that in a practical
design the ac voltage across C, is much smaller than the ac
voltage across the switch S, and by changing the topology
through equivalent transformations similar to the ones used in
[6], the Vsec rating,and hence the size, of the feed inductor L,
can also be reduced. That, in turn, leads to further cost
reduction. Fig. 4 shows the resulting new class E inverter
variation. Fig. 5 shows the steps of transformation. The first
step is to move the bottom end of transformer T from the
negative terminal of the supply V, to the positive terminal.
The second step is to move the left-side terminal of the
inductor L, to the junction of inductor L2 and capacitor C,.
The third step is to integrate the external inductor L2 into the
W o r m e r , and thus to remove it. Because now there is a net
de: current in the transformer primary, an air gap must be
added to the core. The end result is a new minimum-part
count topology, where all parasitic and other hidden circuit
components are Eully utilized and the size of the feed inductor
is reduced.
Note that although the operating principle and the basic
waveforms of the circuits of Figs. 3 and 4 are similar, there is
a fundamental practical difference between the two
implementations, The circuit of Fig. 3 is current-fed and the
circuit of Fig. 4 is voltage-fed. This results in a larger ac
current in the dc supply, for the circuit of Fig. 4, as compared
with the circuit of Fig. 3.
b
Fig. 5. Steps oftopological transformation
Iv. ANALYSIS AND CONTROL OF THE CLASS E CCFL
INVERTER
Fig. 6 shows the typical switch voltage, switch current, and
drive signal waveforms of the Class E inverter. (The
waveforms are essentially the same for both the original circuit
in Fig. 3 and the new circuit in Fig. 4.) As can be seen, when
the switch is turned off, its voltage swings up, then down,
bringing the antiparallel diode into conduction and thus
ensuring ZVS. The switch is turned on between the time the
antiparallel diode comes into conduction and the time the
switch current changes polarity from negative to positive. The
currents in the series resonant circuit of C, and L, (in Fig. 3)
and in the lamp are sinusoidal, with a small amount of
second-harmonic distortion.
First-order design equations are available for the ideal
operation (50% duty ratio, small ripple current in the feed
inductor, both the switch voltage and its first derivative are
zero at turn-on, no parasitics, small output distortion) of the
class E inverter, e.g. [5], [7], [SI. Those equations are repeated
here for convenience (Table I).

1044
 -
qualitatively how the switch voltage waveform varies when the
component values in the load network are adjusted. For a
quantitative understanding of the trade-offs in selecting the
components of the inverter, and also for clarifying the control
(a) switch voltage requirements, computer simulation tools must be used. We

fl (b) switch current

(c) drive signal
Fig. 6. Typical waveforms of the Class E inverter.
refer to two programs, which are especially suitable for
analyzing class E inverters 191, [lo]. Reference [9] describes
a program dedicated to class E inverters and similar circuits,
and [lo] describes a general-purpose behavior-mode power-
electronics simulator. Both programs provide results
exceptionally quickly, orders of magnitude faster than SPICE.
A DecreaslngC,,L2 Increasing R Increasing C,

TABLE I.
FIRST-ORDER
DESIGN EQUATIONS

Network loaded Q:

Output power: /
DecreasingC,
I
Decreaolng R
\
lncreaslng C2,L2

0.577 v,“,
P = Fig. 7. Effeds of changing load-network components.
R
Second-harmonic distortion: The natural control technique for the class E inverter is
0.27 @ QL = 2 frequency control. Because in ZVS mode the time for
completingthe ringing acrossthe switch (i.e. essentially the off
-v2- -
0.51 (3)
-@ time) is rather constant, the practical implementation of
VI Q L l 3
frequency control is to control the on time of the switch.
. QL
C,(in parallel with the switch):
0.184 0.81 QL 0.7
(4)
2xfR

C, (in series with L,):

r
I
c, = [l +
QL - 1.788
(5)
I
I
I
2KfQLR I
I
I
Switch peak voltage: I
I
vsw.peak = 3.56Tn I
I
I
Notes: (1) In the expressions, R is the equivalent load I
I
resistance of the inverter. If the load is connected to the I
I
secondary winding of a transformer (e.g., as is the case in I
I
CCFL inverter applications), R is the load resistance I
transformed to the primary side. (2) Fig. 3 shows C,, C2,L,
and b. V, and V, are the fundamental and second harmonic Fig. 8. Functional block diagram of a controller for the class E CCFL inverter.
components of the load voltage, respectively.
Fig. 8 shows the functional block diagram of the controller
It is not possible to derive design equations for together with the inverter circuit. Note that in the figure we
characterizingthe class E inverter under off-nominal operating indicated the parasitic capacitance C, of the high-voltage
conditions. The effects of parasitic resistances can be transformer. As the voltage-gain plots of the load network (G,
accounted for exactly, in nominal-waveforms operation, that is b,T, C,, lamp resistance) of the inverter in Fig. 9 show, with
when vs = 0 and dvddt = 0 at switch turn-on time. Fig. 7 unlit CCFL that capacitanceprovides a resonance peak,which
[originally developed by the first author of (5)] shows can be beneficially used for starting the lamp.

1045

Fig. 9. Voltage-gain vs. fkquency plots of the load network of the class E
ccn inverter.
The control strategy of the class E CCFL inverter embodied
in the block diagram of Fig. 8 is explained using the plots and
locus in Fig. 9. The system starts at point A with a short on
time, i.e. at a high frequency. The short on time is established
by the soft-start circuit which initially pulls low the control
inputof the VCO. The VCO is the constant off-time, variable
on-time type. At start, the lamp is not lit. As the on time
increases due to the charging of the soft-startcapacitor (not
shown in the functional block schematic), the operating point
of the system moves toward the resonant peak. At point B the
lamp ignites and its impedance suddenly drops. The operating
point moves to C. The on time continues to increase, which
causes the operating point to move leftward (now on the
frequency-responseplot belonging to the low impedance of the
lit lamp), until the lamp current reaches the value set by the
lamp current detector and the error amplifier in point D.
Ifthe lamp is broken or missing and there is no ignition, the
voltage across the transformer secondary must be limited for
reason of safety. Limiting the voltage is best accomplished by
monitoring the primary winding of the transformer with an
overvoltage detector and retriggering the soft-start circuit.
Although not absolutely essential, a zero-voltage detector
can be added to the controller to monitor the voltage across the
MOSFET switch and to terminate the off time when that
voltage drops below a low level. There are two benefits in
doing so:(1) The system will be able to maintain zero-voltage
switching over a wider range of supply voltage and lamp power
Variations. (2) By immediately turning on the MOSFET after
the voltage across it swung to zero, the body diode will be
shunted earlier by the low RDs(oN) of the MOSFET, and that
reduces the conduction losses.
1046
v . NEWCONTROL IC FOR SINGLE-TRANSISTOR CCFL
INVERTERS
Although ZVS control ICs for single-transistorcircuits are
available fbm seveml vendors, none of those ICs is suitable for
controlling CCFL inverters. The main reasons are high cost,
limited supply voltage range, large power consumption, and
the lack of features requiredby typical CCFL applications (e.g.,
odoff control with low standby power or protection against
high voltage caused by open or missing lamp). Here we
present an IC, the TK75020,which was specifically developed
for such applications. Fig. 10 shows the detailed block
schematic of the IC. The IC has the following unique features:
Zero-voltage detection (ZVD), which turns on the power
switch when the switch voltage swings below 2 V. This
feature is useful for preventing the loss of soft switching
when the set off time is too long.
Overvoltage protection (OW),for limiting the peak output
voltage of the converter to a safe maximum in case the lamp
is open or missing.
User-programmable overdissipation protection (ODP), for
limiting the dissipation in the power switch in case the
zero-voltage switching is lost due to a too short off time.
An O d O f fpin, to turn odoff the IC. In the off state, the
supply current is about 2 a.
Single timing capacitor for setting the on time and the limit
for the off time.
A multi-hction on-time-setting pin, TodSS. The
maximum allowed on time is set by a resistor connected
between that pin and ground. During normal operation the
on time is controlled by the error amplifier whose output is
connected to the pin through a resistor. Soft-start or soft
restart (in case of overvoltage across the transformer or
when ZVS is lost) is provided by connecting a series RC
network between the pin and ground.
A current-limit pin, CL, for providing overcurrent
protection on a cycle-by-cycle basis.
To illustrate the effect of the zero-voltage detection in the
IC, Fig.11 shows the voltages (a) across the timing capacitor
of the IC, (b) across the power switch, and (c) at the drive pin.
As can be seen, due to the presence of ZVD, the drive signal
appears as soon as the voltage across the power switch swings
back to zero, although the off timing has not yet been
completed by that time.
The overvoltage-protection is accomplished by connecting
the O W pin to a divider across the primary winding of the
transformer. If the positive peak of the divided voltage exceeds
an internal 4-V threshold, the IC is stopped and a soft restart
takes place.
 E4 inv
N D
EA out

TonISS
OW

Toff"

VCC OVP

OnlOff DW

Ref C/L CT Gnd

Fig. 10.Detailed block schematic ofthe TK75020 IC

monitors the voltages at the drive pin and the ZVD pin.
During the interval when both pin voltages are high, indicating
the lack of ZVS, a constant current flows out from,the ODP
pin. That current pulse can be integrated with a
capacitorresistor parallel combination connected between the
pin and ground. When the pin voltage exceeds a threshold, the
IC is stopped and a soft restart takes place.
Current limiting is essential in PWM dc/dc converters but,
depending on the design,it can also be useful in quasi-resonant
and multi-resonant converters and inverters. The unique
f w of the current limiting circuit in the TK75020 is that it
shortens the programmed on time by increasing the discharge
rate of the timing capacitor. This is necessary to prevent a
large increase in the off time, which could lead to loss of Z V S .

W.EXPERIMENTAL CIRCUIT AND TEST RESULTS

Fig. 11. Voltages across the timing capacitor (a), across the power switch@),
and at the drive pin (c).
If zero-voltage-switching is lost (either because the set off
time is too long and the ZVD pin is not used, or because the off
time is too short), the switching loss (caused by the periodic
discharge of the parallel capacitor) can become excessive.
Protection against that loss is available in the IC. A circuit
Fig. 12 shows the typical application of the IC in a practical
class E CCFL inverter. This is also the experimental circuit
we used to take the test data presented below. The inverter is
capable of operating a 220-mm long lamp with 2.6-mm
diameter, over a lamp current range of 1to 5 mA and a supply
voltage range of 6 to 16 Vdc. The maximum available output
power is about 2.5 W, and the full-load electrical efficiency is
about 80%.

1047
 8% second-harmonicdistortion. Several thousand hours of life
test showed that there is no tendency for asymmetrical light
output (i.e. one end of the lamp being brighter than the other
end), indicatingthat the lamp can handle such a small amount
of asymmetrical excitation without problem. As other life tests
indicated, the dc voltage across the lamp would be of a greater
concern. A capacitor in series with the lamp could easily cause
a dc voltage in the range of 20 to 30 V, which would limit the
lamp life to a few hundred hours due to mercury migration.
Therefore a series capacitor is not recommended in the class E
inverter. Note that in our case there is practically no dc
voltage across the lamp due to the parallel transformer
winding.
Figs. 16a and 16b show the lamp voltage and lamp current
I & driven by the class E inverter (a) and by a commercially
available non-dimmable current-source parallel-resonant
Fig. 12. Application ofthe TK75020 in a practical class E CCFL inverter. inverter module (b). As can be seen, the class E inverter
produces sigmficantly smoother voltage and current waveforms
than the CSPRI. Dimming with a buck switching stage would
add further wiggles to the waveforms of the CSPRI, leading to
further reduction in system efficacy and increase in EM.
Fig. 17 shows the envelope of the output voltage without
lamp. The output voltage gradually increases to slightly above
2.2 kVpk, then the O W shuts off the inverter. After some
delay, another starting attempt takes place. During this
operation,the power consumption is very low (about 240 mW
at 12 V supply voltage). Note that the starting peak voltage is
independent from the supply voltage.

1
Fig. 13. Switch voltages (top traces, 10 V/div.) and lamp currents (bottom
traces,5 d d i v . ) . Lamp current: 5 "s, supply voltage: 6 V (a), 16 V (b).
Time scale: 2 pddiv.
I fundamental component

2,/ndhannmcI

Fig. 15. Spectrum ofthe lamp current. Scales: 10 dB/div., 50 W d i v .

Fig. 14. Switch voltages (top traces, 10 V/div.) and lamp currents(bottom
traces, 2 d d i v . ) . Lamp current: 1 "s, supply voltage: 6 V (a), 16 V (b).
Time scale: 2 pddiv.

Figs. 13a and 13b show the switch voltage and lamp current
waveforms at 5-mA lamp current and at 6-V (a) and 16-V (b)
supply voltages. Figs. 14a and 14b show the same waveforms
but at 1-mA lampcurrent. As can be seen, ZVS is maintained
over the full range of supply-voltage and lampcurrent
variations.
Fig. 15 shows the spectnun of the lamp current, at full load Fig. 16. Lamp voltages (top traces, 500 V/div.) and lamp currents (bottom
and at 12-V supply voltage. The second harmonic current is traces,5 d d i v . ) : (a) with class E inverter, (b) with commercially available
nm-dimmable CSPRI module. Time scales: (a) 2 pddiv., (b) 5 pfdiv.
below the fundamentalby about 22 dB, which corresponds to

1048

Fig. 17. Envelope of output voltage without lamp. Scales: 1 kV/div.,
20 d d i v .
Application schematic and test results are also available for
the inverter topology shown in Fig. 4, but are not presented
here due to space limitations. Applications have not yet been
developed for ZVS quasi-resonant or multi-resonant dc/dc
converters. However, due to the essentially identical control
requirements of those converters to that of the class E inverter,
adapting the IC to such applications should also be
straightforward. Fig. 18 shows the schematic of a multi-
resonant ZVS forward dc/dc converter, controlled by the
TK75020.
Fig. 18. Application of the TK75020 in a multi-resonant ZVS dc/& converter.
VII. SUMMARY
In this paper we reviewed the various CCFL inverter
topologies, discussed the analysis and control of the class E
inverter, introduced a new inverter topology, and presented a
new control IC developed for such inverters and also for ZVS
dc/dc converters. The IC features a zero-voltage detector,
1049
switch overdissipation protection, soft start, pulse-by-pulse
m n t limit,overvoltageprotection, and odoff switching with
a lowcurrent stand-by mode. Test results showed that the IC
is capable of controlling the class E CCFL inverter over a wide
range of supplyvoltage and lamp power in a cost-effective and
efficient way.
ACKNOWLEDGMENTS
The first author, R Redl, thanks Bryce Hesterman of
Magnetek for pointing out the misnomer associated with the
current-some parallel-resonant CCFL inverter, Urs Mader of
Maxim for the informationon mercury migration caused by the
dc voltage across the lamp, and Nathan Sokal of Design
Automation for the review of the manuscript and for the
countless stimulating discussions on class E technology.
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