Solid-State Electronics Vol. 37, No. 12, pp.

1967-1975, 1994
~ Pergamon Copyright © 1994 ElsevierScienceLtd
0038-1101(94)E0024-9 Printed in Great Britain. All rights reserved
0038-1101/94 $7.00+ 0.00

BRIEF REVIEW OF THE MOS DEVICE PHYSICS F O R

LOW T E M P E R A T U R E ELECTRONICS

F. BALESTRA and G. GHIBAUDO

Laboratoire de Physique des Composants ~i Semiconducteurs, URA CNRS, ENSERG/INPG,
23, rue des martyrs, B.P. 257, 38016 Grenoble, France

(Received 3 August 1993; in rev&ed form 18 January 1994)

Abstract--A brief review of the main physical phenomena involved in the cryogenic operation of CMOS
silicon devices down to liquid helium temperature is given. Going from solid state physics towards
electrical engineering point of views, several aspects such as the quantification of the inversion layer, the
electronic transport in the 2D electron or hole gases, the scattering mechanisms, the impurity freeze-out
in the substrate or in the lightly doped source and drain regions, the field-assisted impurity and impact
ionization phenomena, the influence of series resistance and other parasitic effects (kink effect, hysteresis,
transient, ...) which alter the device characteristics will be discussed. The short channel effects such as
drain induced barrier lowering, punch through, velocity overshoot will also be addressed.

1. INTRODUCTION the two-dimensional channel, the impurity freeze-out

The operation of C M O S devices at low and very low
temperature has received much attention during the
past years[l-15]. The device operation at low tem-
perature is of prime importance since it allows sub-
stantial increase of the circuit performances by
comparison to room temperature operation. More
specifically, this results in higher carrier mobility and
saturation velocity, better turn-on capabilities, i.e.
subthreshold slope, latch-up immunity, improved
reliability due to activated degradation processes,
reduced power consumption, decrease of leakage
currents, lowering of interconnection resistance, in-
creased thermal conductivity, reduction of thermal
noise . . . . Nevertheless, some disadvantages, which
derive from the operation of C M O S devices at low
temperature, still need to be understood in order to
overcome the problems due to a cryogenic operation.
For example, impurity freeze-out, kink effect, series
resistance effects, hysteresis behavior, anomalies in
transient response . . . may strongly affect the func-
tionality of the circuits. Other problems due to low
temperature are related to the major changes in the
fundamental mechanisms associated with the elec-
tronic transport, the time response and/or the fluctu-
ations in the device.
The aim of this paper is to give a brief review of
the main physical phenomena involved in the oper-
ation of C M O S silicon devices under cryogenic con-
ditions. F r o m solid state physics towards electrical
engineering, several issues will be discussed such as
the quantum mechanical approach of the inversion
layer[7], the ohmic[7] and non-ohmic[13] transport in
the 2D gas constituted by the quantum subbands, the
scattering mechanisms[8] which alter the mobility in
in the bulk substrate[9,10] or in the lightly doped
source and drain regions, the field assisted impurity
and impact ionization phenomena occurring near the
drain region in saturation regime[3,10], the influence
of series resistance and other parasitic effects (kink
effect[9,11,12], hysteresis[10,15], transient[3,4] . . . . ) on
the device performances. Furthermore, the character-
istics related to the scaling down of the device such
drain induced barrier lowering (DIBL)[5,6], punch
through, velocity overshoot[14] will also be ad-
dressed.
2. ELECTRONICTRANSPORTIN THE INVERSIONLAYER
2.1. Inversion layer quantum subbands
The energy quantization in the inversion layer is
clue to the confinement of the carriers in the potential
well caused by the band bending at the silicon-dioxide
interface[16,17]. The discretization of the energy in
the direction perpendicular to the interface results in
the formation of 2D subbands. In the triangular
potential well approximation, the energy levels E k
which define the subband edges with respect to the
conduction band E c are given by[16,17]:
E t : Ak(qhF,)z3/(2 m*) 1'3, (1)
where the AkS are the zeros of the Airy function, F~
is the surface electric field, q is the elementary charge,
m* is the effective mass depending on the silicon
surface orientation. Self-consistent Poisson's and
Schrodinger's calculations have shown that the tri-
angular potential approximation is good for electric
field up to 1 MV/cm[17,18].
The inversion charge of the channel Q~ can then be
obtained by adding all the contributions of each

1967
1968 F. BALESTRAand G. GHIBAUDO
subband assuming a constant 2D density of states
and using the Fermi-Dirac statistics[7,19]. It should
be mentioned that an experimental verification of the
inversion layer quantization has been demonstrated
by capacitance measurements on MOS transis-
tors[19]. Furthermore, a well-known proof for the
existence of 2D subbands in a MOS transistor is the
manifestation of the quantum Hall effect[20].
In practice, the quantization of the inversion layer
produces a shift of the charge threshold voltage
resulting from the leveling of the fundamental sub-
band edge AV~ "-- Eo/q[21 ]. This leads for example to
typical AV, of the order of 0.1 V for doping level
10JT/cm3.
The electronic transport coefficients in a 2D system
can be evaluated using the Kubo-Greenwood inte-
gral by summing, at first order, the parallel contri-
bution of each subbands while neglecting intervalley
scattering[7], such as
a ( r ) = y G~(T)
k
with
fZ ~c
ak(T) = ek(E)(-~f/~E)dE, (2)
k
where ak(E) is the energy conductivity function
which is proportional to the energy mobility function
Pk(E) and f is the Fermi-Dirac distribution. These
formulae can be applied whatever the statistical
degeneracy, and, in extended as well as in localized
states[7]. The effective mobility of the channel can
then be obtained as po~,= cr(T)/Qi.
2.2. Principal scattering processes and carrier mobilio,
The mobility /~k(E) at a given energy in each
subband can be determined as the inverse of the sum
of the scattering rates corresponding to all relevant
scattering modes (Mathiessen rule). The main scatter-
ing mechanisms which control the inversion layer
mobility are the Coulomb, the so-called surface
roughness and the phonon scattering modes[16]. The
Coulomb and the surface roughness processes prevail
at low temperatures, whereas the latter one is effective
mainly at room temperature. For Coulomb scatter-
ing, ,tik(E ) is inversely proportional to the charge
density and has a linear variation with energy[22].
For phonon scattering, pk(E) may vary as
F~n~~T ~[23],while, for surface roughness scattering,
the mobility should depend primarily on electric field
as F~2[16], Fee being the effective electric field in the
inversion layer.
Following Stern[24], one might consider in a sim-
plified approach that Pk (E) may have a bell-shaped
behavior with energy resulting from combining Cou-
lomb and surface roughness scatterings. This enables
us to provide a consistent picture of the effective
mobility calculated using eqn (2) both as a function
of inversion charge and temperature (4.2 K up to
300 K)[7]. In practice, the bell-shaped variation of
/~k(E) is experimentally inferred by the fact that. at
liquid helium temperature, where the inversion layer
is degenerate and where the fundamental subband
prevails,/t.fr also exhibits a bell-shaped function of Q,
of the form[25]
kleff= 21%/(Qi/Qm + Qm/Qi). (3)
The validity of eqn (3) has been confirmed exper-
imentally by studying the effects of stress-induced
interface charge and substrate voltage on the vari-
ation of the maximum mobility #m and the corre-
sponding inversion charge Qm[26],
The emergence of excited subbands and of the non
degeneracy at higher temperatures leads to more
complex behaviors which can only be approached
empirically. Several works have been made in order
to provide a universal description of the mobility as
a function of Fourand temperature[8,27 30]. In par-
ticular, an empirical mobility law which is valid from
T = 4.2 K up to 300 K has been demonstrated, gener-
alizing the very low temperature mobility law of
eqn (3) and the usual room temperature law[31]. In
fact, this generalized mobility law reads
Pen-=#g(Qi/Qc)"-:/[ 1 +(QUQc)" '], (4)
where Qc is a critical inversion charge and the expo-
nent n varies from 3 to 2 as the temperature varies
from very low to room temperature. Figure 1 illus-
trates the variations of the exponent n with tempera-
ture for various MOS technologies. It should be
noted that the simplicity of this mobility law enables
an accurate modeling of the transfer characteristics of
Si MOSFETs to be achieved in a wide range of
temperature[31].
4 --
WIL = Q 25/25
o 100/100
• 2/50
~- ~ ( ~ l x m ~ 50/5
e- • • 50/5
O
e~
o 2 "°~o • o . o ~ o"0~ .-
e~
1 I I I
0 100 200 300
Temperature (K)
Fig. 1. Variation of the mobility law exponent n with
temperature for various technologies. N channel devices
from: O, SGS-Thomson; O, LETI-LIR; I , Plessey; A,
CNET; A, CNET with oxynitride gate dielectrics; after
Ref.[31].
 MOS device physics for low temperature electronics
3 [-- Exp.
. / .....
>_. 2 I-I? Theo,.
~= II ' r = l l0K
~ i[-[, w/L=,OO/lOO
::~ ] : t°x=120nm
It I I
0 5 10
Vg (v)
Fig. 2. Experimental and theoretical variations of the field
effect mobility /~fe with gate voltage Vg exemplifying a
double-subband effect (after Ref.[34]).
Around the liquid nitrogen temperature, the field
effect mobility variations with gate voltage in n
channel MOS transistors show a pronounced spike
near threshold[32,33]. This phenomenon can be prop-
erly interpreted as a consequence of the contribution
of the first excited subband for (100) or (110) surface
orientations[34]. The amplitude of this behavior
which results from a higher density of states and a
higher mobility in the second subband, is reduced by
increasing the depletion charge via the bulk doping
and/or the substrate bias[34] (see Fig. 2).
2.3. High .field transport
As the longitudinal electric field increases, non-
ohmic conduction resulting from hot carrier effects
arise[16]. In inversion layers, according to a displaced
Maxwellian theory which involves elastic and acous-
tic phonon scatterings[16], the mobility should vary
as the squared electric field at very low temperature
and low electric field (< 10V/cm). The electronic
temperature may therefore change with respect to the
lattice temperature quadratically with the electric
field. Experimental results obtained on Si MOS tran-
sistors show only a qualitative agreement with this
prediction[13]. At high electric field ( > 103 104 V/cm),
velocity saturation due to intervalley and/or optical
phonon scatterings results in a strong decrease of the
mobility whatever the temperature[13,16]. The satu-
ration velocity ranges between 6 × 106 and 107 cm/s as
the temperature is changed form 300 K down to
4.2 K[13]. A simple empirical formula of the form
/~en=/~0/{ 1 + [F/(vs, t/#o)]2} ':z
is generally sufficient for the modeling of the mobility
reduction at high electric field F[13,16,35].
The above results have been obtained in the case of
long channel devices. As the devices are scaled down,
new features arise from the non stationary transport
which takes place in the channel[35-37]. In this
situation, the mean free path becomes comparable to
the channel length, and, in turn, the transit time is
1969
nearly equal to the scattering relaxation time. This
phenomena results in velocity overshoot and nearly
ballistic transport effects[36]. For silicon, velocity
overshoot appears as the momentum relaxation time
becomes smaller than the energy relaxation time. As
a result, the carrier velocity passes through a maxi-
mum as a function of time. The maximum velocity
can therefore overcome the velocity saturation by
50-100%[35], leading to a significant excess of
transconductance and drain current in short channel
MOS devices ( - 0.1 p m), especially at liquid nitrogen
I temperature[14,37] (see Fig. 3).
15
3. I M P U R I T Y F R E E Z E - O U T - R E L A T E D PHENOMENA
Impurity freeze-out becomes important for tem-
perature lower than 150 K for shallow-energy-level
dopants. At liquid nitrogen temperature, weak freeze-
out takes place, which is mainly annoying for LDD-
type devices and depletion-mode MOSFETs. For
temperatures below 30 K, strong freeze-out occurs (at
liquid helium temperature, practically no carriers
remain in the bands if no field is applied), which
affects all the devices and leads to a number of specific
phenomena. It is worth mentioning that strong impu-
rity freeze-out may occur at higher temperature for
other dopant species e.g. at 77 K for tellurium doped
MOS transistors[38].
3.1. Depletion-mode devices
Around liquid nitrogen temperature, an unusual
behavior is observed in the subthreshold region of
the transfer characteristics of depletion-mode
device (Fig. 4). Since the energy band structure
responds to the gate potential change, the impurity
ionization is changed. For P-channel devices, the
increase of (negative) gate voltage produces a shift
of the valence band towards the Fermi level. The
resulting band bending causes acceptors to become
]-~---- C h a n n e l m,[
4 -- ___ At S i - S i O 2 i n t e r f a c e VGS = 0 " 7 V
--'-- 20 .~ below interface VDS = 0.6 V
E
- - <,:x> v
/t . .\ 0.043 lam
7 ' ,k.~ ~ 77K
~, Vsat = 1.2 x 10 cm/s /j. ,x~.
(5) e- . . . . . . . . . . . . . . . . . . .
!
0 0.02 0,04 0.06 0.08 0.10
x-Directed distance (p_m)
Fig. 3. Variation of electron velocity along the channel
illustrating the velocityovershoot phenomenon in very short
channel devices (after Ref.[14]).
1970 F. BALESTRAand G. GmBAUDO
10-3
10-5 f - - - ~ " ~ " X ~ ~ \ ~ 300
I \\\ \\T-----,,o
9.2
\li"
lO 11
s arises when decreasing the temperature in the LDDs,
10-13 ~
-3 -2 1 0
vo~v~
Fig. 4. Evolution with temperature of the ld(Vg) character-
istics of a depletion-mode MOS device (P channel device;
after Ref.[42]).
frozen-out[39-41]. This effect has a strong impact on
the threshold voltage of the device as well.
For temperature above 150 K, freeze-out is very
weak as the gate voltage is increased, since the Fermi
level is well above the impurity level. When the
temperature decreases, the Fermi level approaches
the valence band and therefore boron ions start to be
deactivated at lower Vg values. On the other hand, at
very low temperature (9 K) the Fermi level ranges
between the acceptor level and the valence band, so
that these impurities are already frozen-out even at
Vg = 0. Any threshold voltage change can be expected
by increasing the gate voltage, for boron atoms are
never ionized (Fig. 4)[42].
Besides, another interesting feature, which is ob-
served for depletion-mode device operating at very
low temperature, is the suppression of the kink effect
in saturation even at liquid helium temperature[42].
This phenomenon, which appears by a change in the
output conductance for high drain voltage, is gener-
ally observed for enhancement-mode devices for tem-
perature lower than 30 K, as will be shown below.
It has been shown lately that the influence of
freeze-out on the operation of depletion-mode MOS-
FETs at liquid nitrogen temperature is reduced in
short-channel devices for high drain voltages[43].
This phenomenon has been attributed to the
Poole-Frenkel effect which increases as Vd increases.
In fact, the impurity ionization is enhanced for
short-channel devices by the lowering of the effective
barrier height due to the high lateral electric field. In
the case of a sub micrometer device, for not too small
Vd, the lateral electric field is quite large on the main
part of the channel which leads to significant impurity
ionization, resulting in an improvement of the drain
current characteristics. In the case of long-channel
device, the lateral electric field necessary to induce an
efficient impurity ionization is only large enough in
the drain region, which is insufficient to alter signifi-
cantly the device performances.
3.2. Influence qf LDD regions
For degenerately doped source and drain regions,
no freeze-out takes place until liquid helium tempera-
ture. However, for the lightly doped source and drain
regions (LDDs), freeze-out becomes important even
at liquid nitrogen temperature and therefore has a
strong impact on the electrical properties of the
devices. Indeed, important series resistance effect
leading to large degradation of the MOSFET per-
formance. For low applied voltages, the electrical
1 properties are optimum at intermediate temperature
and are lowered for very low temperature. Neverthe-
less, for high applied gate and drain voltages, an
interesting feature is observed, which is the increase
of the drain current until liquid helium temperature
(see Fig. 5). This phenomenon is related to a re-
duction of the parasitic LDD resistance due to the
partial ionization of the frozen-out impurities in the
LDDs caused by Poole-Frenkel effect or impact
ionization[44]. Therefore, high performance and re-
liable Si MOSFETs may be designed for low tem-
perature operation while using LDD technologies.
Nevertheless, the use of LDDs for improving the
hot-carrier-induced degradation immunity has not
been proved to be necessary[45].
3.3. Kink and hysteresis eff&'ts
At very low temperature (T < 30 K), enhancement-
mode bulk Si MOS transistors exhibit a change in the
output conductance at high drain voltages in satu-
ration which is called the kink effect (Fig. 6119,t2].
L = 5Bm LDD-1013/cm2 3(I
S
- - ~ \ V = 3V
6 2(I
4
" I (1
I
-- it V =2V ~
/ I g
! /
iiii
- I J
0 100 200 300
T (K)
Fig. 5. Variations with temperature of the saturation (solid)
and linear (dashed) drain current illustrating the impact of
the LDDs on the electrical performances (after Ref.[44]).
 MOS device physics for low temperature electronics
43I ZIL = 50/10S
2V
I
0 4 8 12 16
Vd(V)
Fig. 6. Typical Id( Vd) output characteristics of a MOSFET
illustrating the onset of kink effect at very low temperature
(after Ref.[9]).
This behavior is quite similar to the one observed in
silicon on insulator devices. The kink effect results
from a shift in the threshold voltage. Indeed, at very
low temperature, the equilibrium situation, reached
after a certain time which depends on temperature
and applied biases (see Section 3.4), can be described
by a depletion region with ionized impurities and a
frozen-out Si substrate. The impact ionization ma-
jority carrier current, generated in the drain space
charge region, can flow through the source junction
and through the we1119,12]. The avalanche-generated
current flowing from the drain to the source creates
in turn an internal substrate voltage at the source
substrate junction. The other part of the avalanche
current may constitute a space charge limited current
flowing through the well, which also forward biases
the substrate, both effects leading to a decrease in the
threshold voltage. For large enough substrate
voltage, the source-substrate junction becomes con-
ducting and causes the major part of the impact
ionization current to be collected by the source. For
the sake of simplicity, one may consider that the
avalanche current flows directly to the source, what-
ever the internal substrate voltage.
The excess drain current due to the parasitic sub-
strate biasing is, at first order, proportional to the
internal substrate bias change Vb near the source and
to the body transconductance gb = dlJdVb such as
Aid = gb Vb[46]. The body transconductance is related
to the gate transconductance gm=dld/dVg as
gb = (Cd/Cox)gm, where Cd and Cox are the depletion
and gate oxide capacitances, respectively.
The internal substrate bias change with respect to
the source is related to the substrate current /sub
flowing in the forward-biased source-substrate
junction through a classical diode formula or an
equation adapted for the very low temperature
case[46]. The substrate current generated by
1971
avalanche multiplication near the drain is related to
the drain current and the drain voltage by a classical
expression[47]. This model leads to a satisfactory
modeling of the kink effect in MOS transistors for
very low temperature operation[46]. Moreover, this
analysis has also been successfully applied to the case
of short-channel MOSFETs where a reduction of the
normalized kink effect Ald/los,t is obtained due to
combined effects of charge sharing and velocity satu-
ration via the lowering of the depletion capacitance
and the normalized saturation transconductance[11].
The critical drain voltage for which the kink effect
appears increases as the temperature is increased
(Fig. 6). This effect can be interpreted by the decrease
of the substrate current which flows from the drain to
the source and the decrease in the substrate resist-
ance, both effects leading to a lower internal potential
for the same applied voltages[9,12].
Hysteresis phenomena have also been observed in
the Id(Vd) characteristics[10,15,48], and are at-
tributed to transient effects which will be discussed in
the following section.
3.4. Transient behat~ior
At very low temperature (T ~ 30 K), in the strong
freeze-out regime, as a carrier is trapped in a shallow
level, it will remain in the trap for a certain time
before picking up enough thermal energy to escape.
However, in the liquid helium temperature range, the
substrate of a MOSFET could remain frozen-out
indefinitely if thermal energy provides the only
means to release the carriers from the shallow
traps. The application of a field of large enough
strength can induce ionization of trapped carriers and
depletion region formation. The transient time for
which an excess drain current is observed (the current
decreases when the depletion region is created)
depends on temperature and applied field. Three
types of field dependent ionization are generally
possible[3,4,49-53].
A first mechanism is the Poole-Frenkel ionization,
for which the barrier for thermal emission is lowered
by the application of a field. The change in the
magnitude of the barrier depends entirely on the field
F such as AE=q(qF/rcEsi) ~'2. As the field or the
temperature increase, the ionization time decreases,
which leads to shorter transients. At temperature
above 30 K, a field larger than 103 V/cm leads to short
transient times lower than 1/~s. However, in order to
have transient times at 4.2 K of the same amplitude,
one has to apply a field above 3 × 103V/cm[52].
A second possible mechanism of field dependent
ionization is by tunneling. At sufficient field strength,
the carrier is able to tunnel through the barrier into
the band. This phenomenon is thus weakly tempera-
ture dependent contrary to the Poole-Frenkel field-
assisted thermal ionization, but is an extremely
sensitive function of the electric field. Therefore,
when the temperature decreases (T < 30 K) and for
large enough field ( > 2 x 103V/cm), tunneling be-
1972
comes the dominant ionization process[52]. For lower
fields, the temperature for which tunneling is the main
ionization mechanism decreases. Tunneling may also
be phonon-assisted, but this process is rather unlikely
in the very low temperature range.
The third important mechanism is the shallow-level
impact ionization. When majority carriers are gener-
ated by avalanche multiplication for sufficient field
near the drain, these carriers flow through the sub-
strate and can induce the ionization of dopant impu-
rities by impact ionization (the so-called "forced
depletion layer formation"). The transient response
in the drain current of a M O S F E T originates from
the change with time of the forced depletion region
width, which depends on the substrate current and on
the rate of impact ionization and recombination by
thermal capture[10,50,51,53]. This kind of ionization
seems to be dominant at very low temperature
( < 10 K) for intermediate electric field. A typical
transient in the drain current of a M O S F E T is
displayed in Fig. 7 as a function of temperature[4].
The transient time generally increases as the tempera-
ture is lowered and decreases as the applied gate and
drain voltages are increased. Similar transients have
also been observed for MOS capacitors, diodes and
in the substrate current of M O S F E T s for very low
temperature operation in the strong freeze-out
regime[3,49,52].
Other types of transient effects can be due to device
self-heating. This feature produces a change in the
surface band structure and in the channel mobility,
both phenomena giving rise to a transient in drain
current[54,55]. However, this effect seems to be less
important than the previous ones in the liquid helium
temperature range.
4. I M P A C T IONIZATION PHENOMENON
TEMPERATURE
The impact ionization phenomenon from which
originates the substrate current is a key feature as
regard to the kink effect and the hot-carrier-induced
1.2 --
, j 22.5 K
1.0 --
~ 0.8 --
0.6 - -
0.4 -- @ 11.8
0.2
0 --
I J I I L I I I
0 0.5 | .0 1.5 2.0 2.5 3,0
Time (ms)
Fig. 7. Typical drain current transient as observed at low
temperature (after Ref.[4]).
F. BALESTRAand G. GHIBAUDO
80 --
60
:L:\
20
\\'<L. P MOS •
I L .I
0 100 200 300
T(K)
Fig. 8. Variation of the maximum substrate current l~,~......
with temperature T for N and P MOS devices
(W/'L = 50/10, Vd = 3 and -4.5 V: after Ref.[58]).
degradation. A detailed study of the substrate
current in MOS devices is therefore mandatory for
the qualification of a C M O S technology for cryogenic
application. Several models have been reported in
the past for the substrate current but they were
restricted to room and/or liquid nitrogen tempera-
tures[56,57]. In this section is presented the tempera-
ture dependence of the substrate current in MOS
devices operated between liquid helium and room
temperatures.
In Fig. 8 are reported the variation with tempera-
ture of the maximum substrate current /,t,b..... for
VERSUS constant drain voltage. The substrate current is found
to be much larger in N channel devices than in P
MOS transistors (almost 3 order of magnitude). This
is justified by the higher mobility and higher impact
ionization coefficient for electrons. As the tempera-
ture is reduced, the maximum substrate current is
enhanced by about a factor of 3 and 6 for N and P
channel devices, respectively.
The variation of l~ub/I d and of (l, uh/ l,l )/( V d - Vd~,, ),
Vd~t being the saturation drain voltage, have becn
plotted as a function of 1,'(Vd--~ / d,,,) for various
temperatures in order to check the validity of the
classical substrate current law[47]. It is worth noting
that the plots Lub/Id and (l, ub/Id)/(Va--Vd~,,,) VS
1/(Vd--Va~,) have been found to be practically
linear (better than 99% over 2-3 decades) over
the whole temperature range 20-300 K. for both
plots, independently of the gate voltage and device
I types[581. This is in fact due to the dominating
3.5 4.0 role of the exponential term in the substrate current
law.
Therefore, a satisfactory modeling of the substrate
to drain current ratio can be obtained over the whole
 MOS device physics for low temperature electronics 1973

temperature range 20-300 K by using the simple The charge sharing effect, which characterizes the
substrate current 1aw[58,59]: control loss of the gate on the depletion charge, is not
very much altered by the temperature reduction[5,61].
l~ub = A i d e x p [ - B / ( V d - Vds,t)], (6a)
This is due to the fact that the depletion layer width
or depends weakly on temperature[61].
Unlike charge sharing, the punch-through current
Is, b = A l d ( V d - Vd~,t)exp[--B/(V d- Vd~,t)], (6b) which flows between source and drain via the bulk is
where A and B are empirical constants related to the strongly modified by the cooling down. This is due to
impact ionization law coefficients as A = a~l and the activated behavior of the punch through with
B = b~l with 1 being the effective ionization length temperature such as[61],
near drain[47].
In, = I0 exp(-¢b/kT), (7)
The constants A and B have been extracted from
where ¢I) is the source-to-bulk barrier height. Thus, as
the y axis intercept and slope of the plots l s . b / l d vs
the temperature is reduced, the punch-through cur-
1/( Vd - Vd~,t),respectively. Figure 9 displays the evol-
utions with temperature of these parameters as ob- rent, which is mainly efficient in the weak inversion
tained for electrons and holes. region of the MOSFET operation, is strongly reduced
For both N and P channel transistors, the co- (see Fig. 10). The punch-through current may also
efficient B is almost constant with temperature (31-35 strongly modify the subthreshold swing and the
and 46-50 V), while A is a monotonically decreasing threshold voltage[61]. Therefore, the operation of
function of temperature. If l is assumed to be con- scaled down MOS devices at low temperature con-
stant with temperature, it implies that b~ and a~ have siderably improves the device characteristics.
the same temperature dependence as B and A. The DIBL which measures the modification of the
source surface potential by the electrostatic influence
5. SMALLGEOMETRYEFFECTSVERSUSTEMPERATURE of the drain voltage, is also reduced by the tempera-
ture lowering[5,6].
As the devices are scaled down, new physical
phenomena which may considerably alter the opera- 6. SUMMARYANDCONCLUSION
tionality of the device evolve. These limitations are
generally referred to as small geometry or short A brief review of the main physical phenomena
channel effects. The series resistance, the DIBL, the involved in the cryogenic operation of CMOS silicon
punch-through or the charge sharing effects represent devices down to liquid helium temperature has been
the major causes to these effects. given. Going from solid state physics towards electri-
The series resistance effects are considerably in- cal engineering point of views, several aspects such as
creased by the device cooling down. This is mainly the quantification of the inversion layer, the elec-
due to the higher carrier mobilities at low tempera- tronic transport in the 2D electron or hole gases, the
ture, although the contact and interconnection resist- scattering mechanisms, the impurity freeze-out in the
ances are reduced at low temperature[60]. substrate or in the lightly doped source and drain

100 - -- 0.4 80--

80
\ 0.3 60

60 "\ ° ""~" ° ~° "'~ ° • •

P MOS
e-

"V "\ 40
o~°'O-o~o~o~ N MOS
40

20
20
~ M~OSi ~ ~ t 0.1

I I I I I
100 200 300 0 100 200 300
T(K) T(K)
Fig. 9. Variations of the impact ionization law coefficients A and B with temperature T as obtained for
P and N MOS devices (after Ref.[58]).
1974 F. BALESTRA and G. GHIBAUDO
10-1
,o-r
1o . 5
~a~ 10-7
10 I1 i / L=0gBm
/
10 -13 / I
-I 0 I
Fig. I0. Weak inversion ld(V~) characteristics showing the suppression of punch-through vs temperature
(P channel device).
regions, the field-assisted impurity a n d i m p a c t ioniz-
a t i o n p h e n o m e n a , the influence o f series resistance
a n d o t h e r parasitic effects (kink effect, hysteresis,
transient . . . . ) w h i c h alter the device characteristics
have been discussed. T o s o m e extent, s h o r t c h a n n e l
effects such as D I B L , p u n c h t h r o u g h , velocity over-
s h o o t have also been addressed.
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