SURYA GROUP OF INSTITUTIONS

SURYA COLLEGE OF ENGINEERING AND TECHNOLOGY

CEC 334 ANALOG IC DESIGN
Year / Sem : III / VI QUESTION BANK
UNIT 1: SINGLE STAGE AMPLIFIERS
PART-A

1. Write the Advantages of Cascode Amplifier.

2. Define Noise
3. Define Gain
4. Define Bandwidth BW
5. Define ICMR
6. Define Power
7. Write the equation output impedance of source follower
8. Define MOS physics
9. Write the three amplifier configuration CS, CG & Source Follower Stages for Amplifier,
indicates the ones which have i) Lower output impedance ii) Lowest input impedance
10. Define CS Amplifier
11. Define Wilson Current Mirror
12. Define Current Mirror
13. Define Advantages of Cascode Stage Over Cascade Stage
14. Define Differential & Cascode Amplifiers
15. Purpose of using a differential amplifier with an active load
16. Define Folded Cascade Configuration
17. Define Voltage Reference.
18. Identify the Circuit which can be used as voltage buffer. Sketch the circuit and justify
your answer.(Jan 2022)
19. Derive input resistance of Common Gate Amplifier using equivalent Circuit. Use
resistive load. (Jan 2022)
20. Draw the Small signal model for an MOS Transistor.(Nov/Dec 2023)
21. Define threshold voltage as related to MOSFETs.(Nov/Dec 2023)

PART - B
1. Explain in detail about Common Source Stage with resistive load Circuit. Derive the
input and output resistance using small signal model with appropriate equations.(Jan
2022)
2. Explain in detail about Cascode stage and allowable voltages in cascade stage.(Jan 2022)
3. MOS Equivalent circuits & models
4. Cascade& folded cascade configuration with active load
5. For CS Amplifier, Derive Expression for Transfer Function From Small Signal
Equivalent Circuit
 6. Analyze the Operation of Differential Amplifier With Active Load. What is the Effect
of Parameter Mismatch on gain of Differential Amplifier
7. Draw the circuit of CG Amplifier With Active Load& Expression for input
Resistance ,Output Resistance& Voltage Gain
8. High Gain Amplifier Structures.

UNIT 2: HIGH FREQUENCY AND NOISE CHARACTERISITICS OF AMPLIFIERS

PART –A
1. List out the different types of noises associated with MOS devices.(Jan 2022)
2. Draw the ringing effect in the step response of a source follower with heavy capacitive
load. .(Jan 2022)
3. List out types of analysis used in difference amplifiers. .(Nov/Dec 2023)
4. What the voltage is generated from the band gap reference bias circuit? (Nov/Dec 2023)
5. Define Miller Effect
6. Define Noise in Single Stage Amplifiers
7. Define Noise Characteristics of Amplifiers
8. Define High Frequency
9. Define External & Internal Noise
10. Various Types of Noise that affect Performance of OP Amp
11. Draw a High frequency Model of a Cascode Stage
12. Types of Noise Encountered in OP Amps

PART-B
1. State Millers theorem. Illustrate any three applications of Miller effect with neat sketch.
(Jan 2022)
2. Explain the Statistical Characteristics of Noise with neat sketch.(Jan 2022)
3. Draw and explain a MOS differential amplifier with current mirror.(NOV/DEC 2023)
4. Detail Comparison between CS,CG and Source Follower Circuits with required diagram
(NOV/DEC 2023)
5. Explain Noise in Differential Amplifiers
6. Frequency response of CS, CG & Source Follower
7. Explain Schematic & Expressions, How Input Referred Noise Voltage in CS Stage in
Reduced if Transistor Functions as a Current Source
8. Frequency response of Cascode & Differential Amplifier Stages
UNIT: 3 FEEDBACK AND SINGLE STAGE OPERATIONAL AMPLIFIERS
PART-A

1. What is the effect on output resistance by voltage series feedback? Relate output
resistance with and without feedback? (Jan 2022)
2. Define Effect of loading in Feedback Network
3. Define Some op Amp Design Parameters
4. Write the properties of Negative Circuits
5. What is Gain Boosting? .(Jan 2022)
6. Write the some Application of Feedback
7. Explain Slew Rate & its Significance
8. Define Power Supply Rejection
9. Write the Advantage of one –Stage Op-amp.
10. Write the Advantage of Two–Stage Op-amps
11. What are the factors which limit slew rate in op-amps? (NOV/DEC 2023)
12. State the reasons for the offset current at the input of the operational amplifier.
(NOV/DEC 2023)

PART-B

1. Explain Single Stage Op Amps

2. Explain Noise in Op Amps
3. Explain Properties & types of Negative Circuit
4. Explain the source of noise and its effect in op-amps. Discuss noise hand width of op-
amps circuit. (NOV/DEC 2023)
5. Draw the small signal equivalent circuit of a simple transistor stage with noise sources
and derive the output noise voltage spectral density. (NOV/DEC 2023)
6. Analyze the implementation of two stage cascade op-amp with neat sketch.(Jan 2022)
7. Explain the effect of loading in feedback networks with neat sketch.(Jan 2022)

UNIT: 4 STABILITY, FREQUENCY COMPENSATION

PART-A

1. Define frequency compensation

2. Write about Multipole System
3. Define Phase Margin
4. Define Stability
5. Define Feed forward Compensation
6. Write the need for Compensation in Operational Amplifier
7. What are the slewing methods in Two stage op amps
8. Write any four Compensation Techniques
9. How much is the phase margin adequate with respect to stability? Give the optimum
phase margin value? (JAN 2022)
10. Define pole splitting. Draw the effect of pole splitting in miller compensation. (JAN
2022)
11. State the need for compensation in a feedback amplifier (NOV/DEC 2023)
12. Make a difference between lock range and capture range (NOV/DEC 2023)

PART-B

1. Explain various compensation techniques of op amps.

2. Explain the Compensation of Two Stage op amps.
3. State the need for frequency compensation in op-amp and describe in detail about
frequency compensation of two stage op-amp with neat diagram (Jan 2022)
4. Summarize in detail about slewing in two stage op amplifier and alternative method of
compensation of two stage op-amp with neat diagrams (Jan 2022)
5. Draw and explain the Wilson current source and find the output current and output
resistance. (NOV/DEC 2023)
6. Explain with necessary waveforms of MOS folded and MOS cascade amplifiers.
(NOV/DEC 2023)

UNIT – 5 LOGIC CIRCUIT TESTING

PART-A

1. Define Fault Detection.

2. Define Partial scan.
3. Write types of detection and Testing of Faults.
4. Define Testability
5. Write the various Ad hoc techniques.
6. What are the faults occur in logic circuits.
7. Write any four fault detection methods.

PART-B

1. Explain the Faults in Logic Circuits

2. Briefly explain about Level-Sensitive Scan Design
3. Explain Built-in-Self-Test