Unit-I

EC2003-1: Digital System Design using Verilog

DSDV
 CAD Tools for Digital Design
Unit-I Verilog HDL: An Introduction
Verilog Constructs, Modules and Operators

CAD Tools for Digital Design

To design a logic circuit, a
number of CAD tools are
needed. They are usually
packaged together into a
CAD system, which typically
includes tools for the
following tasks:
1 Design entry,
2 Logic synthesis and
optimization,
3 Simulation,
4 Physical design
Examples: Quartus Prime
from Altera Corporation
(Intel) and the Vivado/ISE
from Xilinx Corporation
DSDV (AMD).

Unit-I
Design Entry
Design entry process involves entering into the CAD system a
description of the circuit being designed.
Schematic Capture
Schematic refers to a
graphical representation
of circuit elements and
their interconnections.
A CAD tool for entering
a designed circuit in this
way is called a schematic
capture tool.
The schematic-capture
method is simple to use,
but becomes awkward
when large circuits are
involved
CAD Tools for Digital Design
Verilog HDL: An Introduction
Verilog Constructs, Modules and Operators
Hardware Descriptive
Language (HDL)
HDL is a programming
language used to
describe hardware.
Design entry of a logic
circuit is done by writing
HDL code where Signals
are represented as
variables, and logic
functions are expressed
by assigning values to
these variables.
DSDV
 CAD Tools for Digital Design
Unit-I Verilog HDL: An Introduction
Verilog Constructs, Modules and Operators

Logic Synthesis & Optimization

Synthesis is the process of generating a logic circuit from an initial
specification that may be given in the form of a schematic diagram
or code.
Synthesis CAD tools generate efficient implementations of
circuits from such specifications.
Compiling is the process of translating an HDL code into a
network of logic gates. The output of compilation is a set of
logic expressions that describe the logic functions needed to
realize the circuit.
One of the important tasks of the synthesis tools is to
manipulate the user’s design to automatically generate an
equivalent, but better circuit.
The performance of a synthesized circuit can be assessed by
physically constructing the circuit and testing it. But its behavior
can also be evaluated by means of simulation.

DSDV
 CAD Tools for Digital Design
Unit-I Verilog HDL: An Introduction
Verilog Constructs, Modules and Operators

Functional Simulation

A circuit represented in the form of logic expressions can be

simulated to verify that it will function as expected. The tool that
performs this task is called a functional simulator.
It uses the logic expressions (often referred to as equations)
generated during synthesis and assumes that these expressions
will be implemented with perfect gates through which signals
propagate instantaneously.
The simulator requires the user to specify valuations of the
circuit’s inputs that should be applied during simulation. For
each valuation, the simulator evaluates the outputs produced
by the expressions.
The results of simulation are usually provided in the form of a
timing diagram which the user can examine to verify that the
circuit operates as required

DSDV
 CAD Tools for Digital Design
Unit-I Verilog HDL: An Introduction
Verilog Constructs, Modules and Operators

Physical Design

After logic synthesis the next step in the design flow is to determine
exactly how to implement the circuit on a given chip. This step is
often called physical design.
The physical design tools map a circuit specified in the form of
logic expressions into a realization that makes use of the
resources available on the target chip.
They determine the placement of specific logic elements,
which are not necessarily simple gates of the type we have
encountered so far.
They also determine the wiring connections that have to be
made between these elements to implement the desired circuit

DSDV
 CAD Tools for Digital Design
Unit-I Verilog HDL: An Introduction
Verilog Constructs, Modules and Operators

Timing Simulation & Implementation

A timing simulator evaluates the expected delays of a designed logic
circuit.
The results can be used to determine if the generated circuit
meets the timing requirements as per the specification.
If the requirements are not met, the designer can ask the
physical design tools to try again by indicating specific timing
constraints that have to be met.
If this does not succeed, then the designer has to try different
optimizations in the synthesis step, or else improve the initial
design that is presented to the synthesis tool
Having ascertained that the designed circuit meets all requirements
of the specification, the circuit is implemented on an actual chip.
If a custom-manufactured chip is created for this design, then
this step is called chip fabrication.
If a programmable hardware device is used, then this step is
called chip configuration or programming.
DSDV
 CAD Tools for Digital Design
Unit-I Verilog HDL: An Introduction
Verilog Constructs, Modules and Operators

Hardware Description Language

Hardware Description Language (HDL) is a specialized
programming language that allows designers to describe the
behavior, structure, and timing of digital circuits and systems.
VHDL (Very High-Speed Integrated Circuit Hardware Description
Language) and Verilog are two commonly used HDLs.
Key features of HDL are:
Abstraction: various levels of abstraction, from high-level
behavioral descriptions to low-level gate-level representations.
Simulatability: HDL models can be simulated to verify the
correctness and functionality of the design before actual
implementation.
Synthesis: HDL code can be synthesized into a netlist, that
can then be used for physical design and fabrication of the
circuit.
Reusability: HDL promotes modular design and component
reusability.
DSDV
 CAD Tools for Digital Design
Unit-I Verilog HDL: An Introduction
Verilog Constructs, Modules and Operators

Verilog HDL
Verilog was designed in early 1984 by Gateway Design Automation
and was initially used as a simulation and verification tool.
Gateway Design Automation and its Verilog-based tools were later
acquired by Cadence Design System.
Verilog became the IEEE standard, IEEE Std. 1364-1995, in 1995
and was updated in 2001, 2005.
The standard was superseeded by IEEE std. 1800-2009 which
included a unified standard for verilog and System-verilog.
Verilog has variety of constructs aimed at providing a functionally
tested and a verified design description for the target FPGA or
ASIC. Therefore, the language has two functions
1 Fulfil the need for design description
2 Fulfil the need for verifying the design for functionality and
timing constraints

DSDV
 CAD Tools for Digital Design
Unit-I Verilog HDL: An Introduction
Verilog Constructs, Modules and Operators

Verilog Design Levels

Circuit Level: Switch is the basic element with which digital
circuits are built. Switches can be combined to form gates. Basic
MOS switches are built into Verilog constructs.
Gate Level/Structural: It is a form of netlist, defining a circuit as
a wired interconnection of subordinate components/modules. They
are easier to debug, easier to analyze, and can be easier to optimize.
Data Flow: In this the module is designed by specifying the data
flow. The specification is comprised of expressions made up of input
signals and assigned to outputs.
Behavioral: Also known as Algorithmic level. Here outputs are
defined as functions of inputs, without describing any circuit
components or modules that might be used in constructing the
circuit. These descriptions are more abstract, higher-level, quicker
and easier to write, easier for others to understand and follow, and
largely self documenting.
DSDV
 Case Generate
always @(*) begin genvar j;
case(Mux) wire [12:0]Output[19:0];
Verilog 2'd0: A = 8'd9;
2'd1, generate
2'd3: A = 8'd103; for(j = 0; j < 20; j = j+1)
S Winberg and J Taylor 2'd2: A = 8'd2; begin: Gen_Modules
default:; MyModule #(13) MyModule_Instance(
endcase Reset, Clk,
end Output[j]
Comments Operators );
// One-liner // These are in order of precedence... always @(*) begin end
/* Multiple // Select casex(Decoded) endgenerate
lines */ A[N] A[N:M] 4'b1xxx: Encoded = 2'd0;
// Reduction 4'b01xx: Encoded = 2'd1;
&A ~&A |A ~|A ^A ~^A 4'b001x: Encoded = 2'd2;
State Machine
Numeric Constants // Compliment 4'b0001: Encoded = 2'd3; reg [1:0]State;
// The 8-bit decimal number 106: !A ~A default: Encoded = 2'd0; localparam Start = 2'b00;
8'b_0110_1010 // Binary // Unary endcase localparam Idle = 2'b01;
8'o_152 // Octal +A -A end localparam Work = 2'b11;
8'd_106 // Decimal // Concatenate localparam Done = 2'b10;
8'h_6A // Hexadecimal {A, ..., B}
"j" // ASCII // Replicate
Synchronous reg tReset;
{N{A}} always @(posedge Clk) begin
78'bZ // 78-bit high-impedance // Arithmetic if(Reset) B <= 0; always @(posedge Clk) begin
A*B A/B A%B else B <= B + 1'b1; tReset <= Reset;
A+B A-B end
Too short constants are padded with zeros if(tReset) begin
// Shift
on the left. Too long constants are A<<B A>>B State <= Start;
truncated from the left. Loop
// Relational
always @(*) begin end else begin
A>B A<B A>=B A<=B
Nets and Variables A==B A!=B
Count = 0; case(State)
wire [3:0]w; // Assign outside always blocks for(j = 0; j < 8; j = j+1) Start: begin
// Bit-wise
reg [1:7]r; // Assign inside always blocks Count = Count + Input[j]; State <= Idle;
A&B
reg [7:0]mem[31:0]; end end
A^B A~^B
A|B Idle: begin
integer j; // Compile-time variable // Logical Function State <= Work;
genvar k; // Generate variable A&&B end
function [6:0]F; Work: begin
A||B input [3:0]A;
// Conditional State <= Done;
Parameters input [2:0]B; end
A ? B : C begin
parameter N = 8; Done: begin
localparam State = 2'd3; F = {A+1'b1, B+2'd2}; State <= Idle;
Module end end
endfunction default:;
Assignments module MyModule
#(parameter N = 8) // Optional parameter endcase
assign Output = A * B;
(input Reset, Clk, end
assign {C, D} = {D[5:2], C[1:9], E};
output [N-1:0]Output); end
// Module implementation
endmodule

Module Instantiation
// Override default parameter: setting N = 13
MyModule #(13) MyModule1(Reset, Clk, Result);
 CAD Tools for Digital Design
Unit-I Verilog HDL: An Introduction
Verilog Constructs, Modules and Operators

General rules
Verilog is case sensitive and has built-in module features like the file
structure, data types, operators, and declarations.
Each Verilog assignment, definition, or declaration is terminated
with a semicolon (;).
Line wraps are allowed and do not signify the end of an
assignment, definition, or declaration. Line wraps can be used
to make Verilog more readable.
Comments in Verilog are supported in two ways.
Line comment is preceded with two slashes (i.e., //).
Everything after the slashes is considered a comment until the
end of the line.
The block comment begins with /* and ends with a */.
Everything between /* and */ is considered a comment. A
block comment can span multiple lines.
All user-defined names must start with an alphabetic letter, not a
number and are not allowed to be the same as any Verilog keyword
DSDV
 CAD Tools for Digital Design
Unit-I Verilog HDL: An Introduction
Verilog Constructs, Modules and Operators

Data types

In Verilog, every signal, constant, variable, and function must be

assigned a data type.
Verilog standard provides a variety of predefined data types, Some
synthesizable, while others are only for modeling abstract behavior.
The major data types are
Net data type: It models an interconnection between
components
Variable data type: These are data types that model storage
Vectors: A vector is a one-dimensional array of elements.
Arrays: An array is a multidimensional array of elements
Verilog supports four basic values that a signal can take on: 0, 1, X,
and Z.

DSDV
 CAD Tools for Digital Design
Unit-I Verilog HDL: An Introduction
Verilog Constructs, Modules and Operators

Data types: Value set

Most of the predefined data types in Verilog supports four basic

values that a signal can take on: 0, 1, X, and Z.
These values also have an associated strength.
The strengths are used to resolve the value of a signal when it is
driven by multiple sources.

DSDV
 CAD Tools for Digital Design
Unit-I Verilog HDL: An Introduction
Verilog Constructs, Modules and Operators

Net Data type

A net data type is one that models an interconnection between
components and can take on the values 0, 1, X, and Z.
A signal with a net data type must be driven at all times and
updates its value when the driver value changes.
The most common synthesizable net data type in Verilog is the
wire.

DSDV
 CAD Tools for Digital Design
Unit-I Verilog HDL: An Introduction
Verilog Constructs, Modules and Operators

Variable Data type

Variable data type models storage.and can take on the values 0, 1,

X, and Z, but does not have an associated strength.
Variable data types will hold the value assigned to them until their
next assignment.

DSDV
 CAD Tools for Digital Design
Unit-I Verilog HDL: An Introduction
Verilog Constructs, Modules and Operators

Vectors

A vector is a one-dimensional array of elements.

All of the net data types, in addition to the variable type reg, can
be used to form vectors.
// Syntax for defining a vector
<type> [<MSB_index>:<LSB_index>] vector_name;

// Examples
wire [7:0] Sum; // This defines an 8-bit vector called "Sum" of
// type wire. MSB index is 7 & LSB index is 0.
reg [15:0] Q; // Defines a 16-bit vector called "Q" of type reg.

Individual bits within the vector can be addressed using their index.
Ex: Sum[5] represents 6th bit of the vector Sum.
Groups of bits can be accessed using an index range. Ex: Q[15:8]
represents the upper 8-bits of the vector Q.

DSDV
 CAD Tools for Digital Design
Unit-I Verilog HDL: An Introduction
Verilog Constructs, Modules and Operators

Arrays

An array can be thought of as a ”vector of vectors.”

Vectors within the array all have the same dimensions.
// Syntax for defining an array
<element_type> [<MSB_index>:<LSB_index>] array_name
[<start_index>: <end_index>];

// Examples
reg [7:0] Mem [0:15]; // Defines an array of 16, 8-bit vectors
// of type reg
integer A [1:100]; // Defines an array of 100 integers.
When accessing an array, the name of the array is given first,
followed by the index of the element and vector index
A[2] // accesses 2nd element of array A.
Mem [2][7] // MSB of 3rd element of array Mem}.

DSDV
 CAD Tools for Digital Design
Unit-I Verilog HDL: An Introduction
Verilog Constructs, Modules and Operators

Expressing Numbers
Verilog supports defining numbers in other bases with optional bit
size and sign.
Without identifying syntax, number is treated as an integer.
Specifying size is optional. If it is omitted, the number will default
to a 32-bit vector with leading zeros added as necessary.
Values of numbers can be entered in either upper or lower case

DSDV
 CAD Tools for Digital Design
Unit-I Verilog HDL: An Introduction
Verilog Constructs, Modules and Operators

Numbers: Examples
When defining the value of arrays, the “ ” can be inserted between
numerals to improve readability.
Examples

Verilog is a loosely typed language (permits assignments between

different data types).
Verilog will automatically truncate or add leading bits as necessary
to make the assignment between different data types work.
DSDV
 CAD Tools for Digital Design
Unit-I Verilog HDL: An Introduction
Verilog Constructs, Modules and Operators

Some more rules

Verilog treats all of its types as just groups of bits and permits
assignments between different data types.
It is therefore said to be a weakly typed (or loosely typed) language.
When assigning between different types, Verilog will automatically
truncate or add leading bits as necessary to make the assignment
work.
Examples:
reg [2:0] ABC_test; // 3-bit vector ABC_test of type reg

ABC_test = 2'b00; // ABC_test will be assigned 3’b000.

// A leading bit is automatically added.
ABC_test = 5; // ABC_test will be assigned 3’b101.
// Integer truncated to 3 bits.
ABC_test = 8; // ABC_test will be assigned 3’b000.
// Integer truncated to 3 bits.

DSDV
 CAD Tools for Digital Design
Unit-I Verilog HDL: An Introduction
Verilog Constructs, Modules and Operators

Verilog Module
A Verilog design describes a single system in a single file.
The file has the extension *.v.
Within the file, the system description is contained within a
module.
A module is a block of verilog code that implements certain
functionality defining the circuit.
The module includes the interface to the system (i.e., the
inputs and outputs) and the description of the behaviour.
Modules can include instantiations of lower-level modules in
order to support hierarchical designs.
The keywords module and endmodule signify the beginning
and end of the system description.

DSDV
 CAD Tools for Digital Design
Unit-I Verilog HDL: An Introduction
Verilog Constructs, Modules and Operators

Verilog Module

module name is the identifier for the module and should best
describe what the system is doing.
It can be composed of letters, digits, dollar sign ($), and
underscore characters ( ) only.
It should start with a letter or “ ”.
No spaces are allowed inside an identifier.
Reserved keywords cannot be used as identifiers.
Examples: Counter BCD, ALU, TwoInputAnd.

DSDV
 CAD Tools for Digital Design
Unit-I Verilog HDL: An Introduction
Verilog Constructs, Modules and Operators

Verilog Module

A module has inputs and outputs, which are referred to as its ports.
Each port needs to have a user-defined name, a direction, and
a type.
The user-defined port names are case sensitive and must begin
an alphabetic character.
The port directions are declared to be one of the three types:
input, output, and inout.
A port can take on any of the previously described data types,
but only wires, registers, and integers are synthesizable.
Port names with the same type and direction can be listed on
the same line separated by commas.
Starting with the Verilog-2001, the port directions and types
could be included alongside the port names within the
parenthesis after the module name.
DSDV
 CAD Tools for Digital Design
Unit-I Verilog HDL: An Introduction
Verilog Constructs, Modules and Operators

Verilog Module
A signal that is used for internal connections within a system is
declared within the module before its first use.
Each signal must be declared by listing its type followed by a
user-defined name.
Signal names of like type can be declared on the same line
separated with a comma.
All of the legal data types can be used for signals; however, only
types net, reg, and integer will synthesize directly.
Verilog supports a hierarchical design approach, thus signal names
can be the same within a subsystem as those at a higher level
without conflict

DSDV
 CAD Tools for Digital Design
Unit-I Verilog HDL: An Introduction
Verilog Constructs, Modules and Operators

Verilog Module
A parameter, or constant, is useful for representing a quantity that
will be used multiple times in the architecture.

The type is optional and can only be integer, time, real, or

realtime.
If a type is provided, the parameter will have the same properties as
a variable of the same type.
If the type is excluded, the parameter will take on the type of the
value assigned to it.

Once declared, the constant name can be used throughout the

module.

DSDV
 CAD Tools for Digital Design
Unit-I Verilog HDL: An Introduction
Verilog Constructs, Modules and Operators

Verilog Module
A compiler directive provides additional information to the
simulation tool on how to interpret the Verilog model.
A compiler directive is placed before the module definition and is
preceded with a backtick (‘)

Example

DSDV
 CAD Tools for Digital Design
Unit-I Verilog HDL: An Introduction
Verilog Constructs, Modules and Operators

There are a variety of predefined operators in the Verilog standard.

Operators are defined to work on specific data types and that not all
operators are synthesizable.
Available operators are
Assignment Operator
Continuous Assignment
Bitwise Logical Operators
Reduction Logic Operators
Boolean Logic Operators
Relational Operators
Conditional Operators
Concatenation Operator
Replication Operator
Numerical Operators

DSDV
 CAD Tools for Digital Design
Unit-I Verilog HDL: An Introduction
Verilog Constructs, Modules and Operators

Assignment Operator and Continuous Assignment

Verilog uses the equal sign (=) to denote an assignment.

The left-hand side (LHS) of the assignment is the target signal.
The right-hand side (RHS) contains the input arguments and
can contain both signals, constants, and operators.

Verilog uses the keyword assign to denote a continuous signal

assignment. A continuous assignment models combinational logic.
The LHS must be a net type.
The RHS can contain nets, regs, constants, and operators.
Any change to the RHS will result in an update to the LHS
target net.

DSDV
 CAD Tools for Digital Design
Unit-I Verilog HDL: An Introduction
Verilog Constructs, Modules and Operators

Continuous Assignment Examples

Each individual assignment will be executed concurrently and
synthesized as separate logic circuits.

When simulated, the following three lines of Verilog will make three
separate signal assignments at the exact same time.
assign X = A;
assign Y = B;
assign Z = C;
In the following example the signal assignments of C to B and B to
A will take place at the same time. Hence during synthesis, the
signal B will be eliminated from the design since this functionality
describes two wires in series.
assign A = B;
assign B = C;

DSDV
 CAD Tools for Digital Design
Unit-I Verilog HDL: An Introduction
Verilog Constructs, Modules and Operators

Logical Operators

Bitwise operators perform logic functions on individual bits. The

inputs to the operation are single bits and the output is a single bit.
In the case where the inputs are vectors, each bit in the first vector
is operated on by the bit in the same position from the second
vector. If the vectors are not the same length, the shorter vector is
padded with leading zeros to make both lengths equal.

DSDV
 CAD Tools for Digital Design
Unit-I Verilog HDL: An Introduction
Verilog Constructs, Modules and Operators

Logical Operators
A reduction operator uses each bit of a vector as individual inputs
into a logic operation and produces a single-bit output.

A Boolean logic operator is one that returns a value of TRUE (1) or

FALSE (0) based on a logic operation of the input operations.
These operations are used in decision statements.

DSDV
 CAD Tools for Digital Design
Unit-I Verilog HDL: An Introduction
Verilog Constructs, Modules and Operators

Logical Operators: Examples

Bitwise Logical Operators

Reduction Logical Operators

Boolean Logical Operators

DSDV
 CAD Tools for Digital Design
Unit-I Verilog HDL: An Introduction
Verilog Constructs, Modules and Operators

Relational Operators
A relational operator is one that returns a value of TRUE (1) or
FALSE (0) based on a comparison of two inputs

Example:

DSDV
 CAD Tools for Digital Design
Unit-I Verilog HDL: An Introduction
Verilog Constructs, Modules and Operators

Conditional Operators
Verilog contains a conditional operator that can be used to model
logic statements. The keyword is ? with the following syntax:

The operator assigns to the target true assignment if Boolean

condition is TRUE, or false assignment if the condition is FALSE.
The values in this assignment can be signals or logic values.
Nested conditional operators can also be implemented by inserting
subsequent conditional operators in place of the false assignment.

DSDV
 CAD Tools for Digital Design
Unit-I Verilog HDL: An Introduction
Verilog Constructs, Modules and Operators

Concatenation and Replication Operator

{} are used to concatenate multiple signals. Target size must be
equal to sum of the sizes of the input arguments.

Replication operator uses double curly brackets (i.e., {{}}) and

allows to concatenate a vector with itself.

DSDV
 CAD Tools for Digital Design
Unit-I Verilog HDL: An Introduction
Verilog Constructs, Modules and Operators

Numerical Operator

Example:

DSDV
 CAD Tools for Digital Design
Unit-I Verilog HDL: An Introduction
Verilog Constructs, Modules and Operators

Numerical Operators

Numerical operators can be used on arguments of different sizes,

types, and signs
Numerical Operator has the following operational rules:
If two vectors are of different sizes, the smaller vector is
expanded to the size of the larger vector.
If the smaller vector is unsigned, it is padded with zeros.
If the smaller vector is signed, it is padded with the sign bit.
If one of the arguments is real, then the arithmetic will take
place using real numbers.
If one of the arguments is unsigned, then all arguments will be
treated as unsigned.

DSDV
 CAD Tools for Digital Design
Unit-I Verilog HDL: An Introduction
Verilog Constructs, Modules and Operators

Operator precedence
Verilog operators have a fixed order of precedence.
If two operators of the same type appear in an expression without
parenthesis to dictate the order of precedence, the precedence will
be determined by executing from the operations from left to right.

DSDV