IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 69, NO.

11, NOVEMBER 2022 6225

Comparison of Commercial Planar and Trench

SiC MOSFETs by Electrical Characterization
of Performance-Degrading
Near-Interface Traps
Mayank Chaturvedi , Sima Dimitrijev , Senior Member, IEEE, Daniel Haasmann,
Hamid Amini Moghadam, Peyush Pande , Member, IEEE,
and Utkarsh Jadli , Student Member, IEEE

Abstract — The suboptimal performance and low channel-
carrier mobility of silicon carbide (SiC) power MOSFETs
are attributed to a high density of oxide traps near the 4H-
SiC/SiO2 interface. In this article, a commercial 1200-V SiC
trench MOSFET has been compared with a planar MOSFET
obtained from the same manufacturer. We employed a newly
developed integrated-charge method to quantify the near-
interface traps (NITs). The results reveal that, at operating
gate voltages, 15% of the total channel electrons were
trapped for longer than 500 ns in the planar MOSFET com-
pared to 9% in the trench MOSFET.
Index Terms — Commercial silicon carbide (SiC) MOSFET,
near-interface traps (NITs), planar, trench.
I. I NTRODUCTION
S ILICON carbide (SiC) MOSFETs have emerged as the
best power switches due to low power losses and fast
switching [1], [2]. Planar SiC MOSFET was commercialized
in 2011 and is still the dominant MOSFET structure [3]. It has
the same cross-sectional structure as the structure of vertical
double-diffused MOSFET (VDMOSFET) in Si technology.
Trench MOSFET is an alternative structure with advantages of
smaller cell pitch resulting in higher packing density and low
ON -resistance [4]. Since the channel of the MOSFET has to be
formed on a vertical plane that is defined by plasma etching,
Manuscript received 9 June 2022; revised 11 August 2022; accepted
8 September 2022. Date of publication 23 September 2022; date of
current version 24 October 2022. The review of this article was arranged
by Editor D. Sheridan. (Corresponding author: Mayank Chaturvedi.)
Mayank Chaturvedi, Sima Dimitrijev, Daniel Haasmann,
Hamid Amini Moghadam, and Utkarsh Jadli are with the Queensland
Micro- and Nanotechnology Centre and the School of Engineering
and Built Environment, Griffith University, Brisbane, QLD 4111,
Australia (e-mail: mayank.chaturvedi@griffithuni.edu.au; s.dimitrijev@
griffith.edu.au; d.haasmann@griffith.edu.au; h.aminimoghadam@
griffith.edu.au; utkarsh.jadli@griffithuni.edu.au).
Peyush Pande is with the Department of Electronics and
Communication Engineering, Graphic Era (Deemed to be University),
Dehradun 248002, India (e-mail: peyushpande.ece@geu.ac.in).
Color versions of one or more figures in this article are available at
https://doi.org/10.1109/TED.2022.3206184.
Digital Object Identifier 10.1109/TED.2022.3206184
the sidewalls can be rough with atomic defects. At high gate
bias voltages, the surface roughness can significantly impact
electron transport in the inversion layer of MOSFETs [5].
Recently, trench MOSFETs have been developed and
commercialized by a small number of companies [3], [6].
Surprisingly, the channel-carrier mobility is higher in the
trench MOSFETs in comparison to planar MOSFETs [7], [8].
The channel-carrier mobility strongly depends on the selected
plane of the crystal [7]. The vertical plane in trench MOSFETs
is (1120), and it is well-known that channel carrier mobility
is higher with this plane orientation [7], [8], [9], [10].
Carrier scattering in SiC MOSFETs has been considered as
a factor that limits channel carrier mobility [11]. Based on Si
MOSFETs, several scattering models have been proposed for
SiC MOSFETs. In Si MOSFETs, Coulomb scattering, phonon
scattering, and surface-roughness scattering are three domi-
nant mechanisms that limit channel-carrier mobility. These
mechanisms strongly depend on temperature and effective
field and are combined according to Matthiessen’s law [12].
Kutsuki et al. [13] fabricated one-cell trench SiC MOSFET
and suggested that optical phonon scattering, derived from
lattice vibrations, must be considered with acoustic phonon
scattering in conventional scattering models. Compared to
surface roughness scattering, Coulomb scattering and optical
phonon scattering had a greater impact on channel-carrier
mobility [14], [15]. Since the evaluation of the trench sidewalls
and their impact on the channel carriers are complex, there is
no coherent scattering mechanism that can explain the channel
mobility in trench MOSFETs [16].
In addition to carrier scattering, the average value of
channel-carrier mobility in SiC is impacted by carrier trapping
at oxide traps near the SiO2 /SiC interface. There are many
studies of these near-interface traps (NITs), but they are mainly
focused on NITs with energy levels below the conduction band
[17], [18], [19]. However, when the MOSFET is biased at the
operating gate voltage, the Fermi level enters the conduction
band due the quantum-confinement effect [20], [21]. Because
of this effect, the electrons trapped by NITs with the energy

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6226 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 69, NO. 11, NOVEMBER 2022

levels below the conduction band appear as fixed negative

charge, and consequently, their main effect is to increase the
threshold voltage. In addition, these trapped electrons cause
some reduction of channel-carrier mobility due to Coulomb
scattering [22], [23], [24], [25]. However, the NITs with energy
levels aligned to the conduction band and around the Fermi
level are active by capturing and releasing channel electrons.
Hall-effect measurements show that, on average, about 80% of
the electrons attracted by the above-threshold gate voltage in
4H-SiC MOSFETs with the planar structure are trapped [26].
Assuming that each electron is trapped for 80% of the time
and free to conduct current for 20% of the time, the average
channel-carrier mobility is 20% of the mobility limited by
the carrier scattering. Therefore, unlike Si MOSFETs, trapping
of channel carriers by NITs is the dominant factor reducing
the average channel carrier mobility in planar SiC MOSFETs
[18], [19]. Trench SiC MOSFETs exhibit higher channel-
carrier mobility, which is usually explained by the higher
carrier mobility along (1120) plane [27]. However, if trapping
by NITs causes a significant reduction in the average channel-
carrier mobility, it should be assumed that the density of
NITs is lower on the plasma-etched vertical (1120) plane.
This assumption is surprising and requires an experimen-
tal confirmation. Trench MOSFETs are not suitable struc-
tures for Hall-effect measurements, but our recently devel- Fig. 1. (a) Schematic cross sections of planar MOSFET and (b) trench
oped integrated-charge technique [28], [29] can be applied MOSFET [30], showing continuous layers of electrons at the SiC surface
of both MOSFETs, which are created by applied above-threshold gate
to trench MOSFETs. Using this technique, we present in voltage. (c) Energy-band diagrams of the p-type SiC and (d) n-type SiC,
this article measurements of the density of performance- showing energy-band similarity at the SiC surface.
degrading NITs in both commercial planar and commercial
trench MOSFETs obtained from the same manufacturer. These
results provide experimental evidence and insight into the of the capacitor is equal to the gate-oxide thickness (tox ).
dominant reason for the observed higher mobility in trench SiC Hence, the measured gate capacitance at VG = 18 V is
MOSFETs. C G = Cox × A G = (εox /tox ) × A G , where εox is the
permittivity of SiO2 .
II. E XPERIMENTAL M ETHOD The gate-oxide thickness can be determined from Fowler–
In this work, we apply the integrated-charge technique Nordheim tunneling by measuring IG –VG characteristics [31].
to characterize NITs in 1200-V commercial SiC power Based on published results, VG−FN = (0.6 V/nm) × tox is the
MOSFETs with planar and trench gate structures obtained onset voltage for the Fowler–Nordheim tunneling [32], [33],
from the same manufacturer. The selection criteria for the [34], [35]. Practically, VG−FN corresponds to Fowler–
MOSFETs used in this investigation were to ensure that their Nordheim current in the range of 1–10 pA. Fig. 2 shows
respective input capacitance (Ciss ) and gate oxide capaci- the IG –VG characteristics for both devices. For the planar
tance (Cox ) are comparable. We will refer to the MOSFET with MOSFET, VG−FN was in the range from 22.8 to 24.8 V for
planar gate structure as planar MOSFET and the MOSFET the current range of 1–10 pA. These values correspond to the
with trench gate structure as trench MOSFET. minimum tox of 38.0 nm and the maximum tox of 41.3 nm.
Fig. 1(a) and (b) shows the cross sections of planar and Analogously, for the trench MOSFET, VG−FN was between
trench MOSFETs, respectively, at the operating gate voltage 25.0 and 27.2 V for the current range of 1–10 pA, which
of VG = 18 V. As the figures illustrate, electron layers appear corresponds to the minimum tox of 41.7 nm and the maximum
at the surface of SiC in both n-type and p-type regions. This tox of 45.3 nm. The average tox of ≈40 nm for planar MOSFET
is because the n-type drift region is accumulated, whereas the and ≈44 nm for trench MOSFET was used to determine A G
p-type body is inverted at the semiconductor surface forming values of these MOSFETs. The relevant parameters for the
the MOSFET channel. Fig. 1(c) and (d) shows that the energy- devices used in this article are given in Table I.
band diagrams at the surface of SiC are similar in both n-type The integrated-charge technique measures the density of
and p-type regions and in both MOSFET structures. However, electrons trapped at and near the SiC/SiO2 interface of the
Fig. 1(a) and (b) shows that the key difference between the two MOSFET. To perform measurements using the integrated-
device structures is the section of the vertical plasma-etched charge technique, the drain and the source of the MOSFET
surface in the case of trench MOSFET. under test were shorted and connected to the ground, while the
Fig. 1(a) and (b) also shows that the active area of the gate was connected in series with an external resistor, REXT .
capacitor is equal to the gate area ( A G ), and the thickness The series connection of REXT and gate capacitance was biased

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CHATURVEDI et al.: COMPARISON OF COMMERCIAL PLANAR AND TRENCH SiC MOSFETs
Fig. 2. Measured IG –VG characteristics.
TABLE I
D EVICE PARAMETERS OF M EASURED SiC MOSFETs
with a dc voltage that was slowly stepped down from 20 to
−20 V. At a particular dc voltage, a superimposed rectangular
waveform (V step ) with the time interval tstep is applied using
a Tektronix AFG1022 function generator. When V step is
applied, the current in the series RC circuit charges the gate
capacitor during tstep = 1/2 f , and when the pulse is removed,
the gate capacitor discharges during the other half of the
cycle. Tektronix P6139B voltage probes with Tektronix DPO
7104 oscilloscope were used to measure the voltage across
REXT to obtain the current flowing in the series RC circuit.
The current was then used to measure the charge q N carriers in
response to V step . Since C G is a function of applied VG , this
charge corresponds to the apparent or electrically active gate
capacitance C G = qN carriers /V step .
In this article, measurements were performed for step
intervals of 500 μs, 50 μs, 5 μs, and 500 ns, using square
pulses of 1 kHz, 10 kHz, 100 kHz, and 1 MHz, respectively.
The selection of REXT depends upon tstep as the gate capac-
itor charges and then discharges within the half periods
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6227
TABLE II
E XTERNAL S ERIES R ESISTANCES U SED IN M EASUREMENTS
Fig. 3. C–V curves for (a) planar MOSFET and (b) trench MOSFET.
(T /2 = tstep ). To ensure that the capacitor charging is at least
99.3%, the value of REXT was selected using the following
criterion:
tstep ≈ 5 × (REXT + RG )Cox (1)
where Cox is the gate oxide capacitance measured at the
manufacturer’s recommended drive voltage of VG = 18 V
(VDS = 0 V), and RG is the internal gate resistance. Table II
shows the external series resistances used for the measure-
ments by the integrated-charge technique. All the measure-
ments were performed at room temperature.
III. R ESULTS
The capacitance–voltage (C–V ) curves for 1200 V com-
mercial SiC Power MOSFETs obtained using the integrated-
charge method are shown in Fig. 3. It is clear from Fig. 3 that,
irrespective of the gate structure, the apparent capacitance is
6228 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 69, NO. 11, NOVEMBER 2022

smaller for the measurements with shorter step intervals. This

happens because the charge with response times longer than
τmin = tstep remains trapped in NITs and does not contribute to
the measured charging and discharging current. Consequently,
the integrated-charge q N carriers for shorter step intervals is
smaller, which results in the reduced apparent capacitance.
Therefore, the number of trapped carriers can be quantified by
subtracting the integrated charge for the shorter step interval
from the integrated charge for the longer step interval. Hence,
the density of carriers trapped per unit area is given by
 
C G−long V step C G−short (τmin )V step
N trapped (τmin ) = −
q AG q AG
(2)
where C G−long is the measured C–V curve with the reference
time step (tstep = 500 μs) and C G−short is the measured
C–V curve with the shorter time steps. The longest step
interval of 500 μs was used as a reference, as the density
of trapped carriers with response time longer than 500 μs
was too small to be detected. The measurements performed
with step intervals of 50 μs, 5 μs, and 500 ns were used to
profile N trapped with responses time shorter than 500 μs and
longer than 50 μs, 5 μs, and 500 ns, respectively. The carriers
trapped at positive gate voltages are electrons, while the Fig. 4. Density of trapped electrons with response times longer than
carriers trapped at negative gate voltages are holes. However, τmin = 50 μs, 5 μs, and 500 ns for (a) planar MOSFET and (b) trench
MOSFET.
only trapped electrons impact the channel current and degrade
the performance of the MOSFET. Hence, the total density of
performance degrading NITs (NNIT ) at a given voltage can be
determined by

VG
NNIT = N trapped (τmin ). (3)
0

NNIT as a function of applied VG for the planar and trench

MOSFETs is shown in Fig. 4(a) and (b), respectively. It can
be observed that NNIT is higher for shorter response times, and
the response time of the traps is as low as 500 ns.
The fraction of electrons that are trapped for a period longer
than τmin , in response to applied voltage step (V step ) at given
gate voltage, can be calculated as
N trapped (τmin )
γ (τmin ) =
Cox V step /q AG
C G−long − C G−short (τmin )
= . (4)
Cox
Fig. 5(a) and (b) shows γ (τmin ) for the planar and trench
MOSFETs, respectively. For the planar MOSFET, there is
no significant change in the fraction of trapped electrons for
VG > VT . However, in the case of trench MOSFET, there is a
slight decrease in the fraction of trapped electrons, particularly Fig. 5. Fraction of electrons trapped for longer than τmin , in response
at the operating gate voltage. This means that, at the operating to applied voltage steps (ΔV step ) at above-threshold gate voltages.
voltage, the performance of the trench MOSFET will be better (a) Planar MOSFET. (b) Trench MOSFET.
in comparison with the planar MOSFET due to the lower
density of NITs. currently available techniques can characterize NITs only at
subthreshold gate voltages (VG < VT ). Consequently, these
IV. D ISCUSSION techniques do not quantify NNIT in the above-threshold region
The commercial SiC power MOSFETs are available with where MOSFETs operate. On the other hand, it is one of the
the operating gate voltages from 15 to 20 V. However, exceptional advantages of the integrated-charge method that it

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CHATURVEDI et al.: COMPARISON OF COMMERCIAL PLANAR AND TRENCH SiC MOSFETs
Fig. 6. Fraction of total density of electrons attracted to the SiC surface
by VG = 18 V and trapped for longer than τmin .
can characterize NITs at the operating gate voltage and with
commercial MOSFETs [28], [29].
Since NNIT is responsible for the degraded performance of
the MOSFET, it is significant to compare the density of NITs
at the operating VG .
The fraction of the total density of electrons attracted to the
SiC surface by VG and trapped for longer than τmin is given by
NNIT (τmin )
γTOT (τmin ) =
Cox (VG − VT )/q AG
V step 
VG
= γ (τmin ). (5)
VG − VT 0
The values of γTOT (τmin ) at VG = 18 V are shown in Fig. 6.
For τmin = 500 ns, 9% of the channel electrons are trapped in
the trench MOSFET compared to 15% in the planar MOSFET.
There are NITs that are located closer to the SiC surface
and have shorter response times than 500 ns, which means
NNIT will be even higher for the time responses shorter than
500 ns. The extrapolation shown in Fig. 6 indicates that, in the
case of trench MOSFET, 60% of the channel electrons will be
trapped for the response time of 10 ns, compared to 80% in
the planar MOSFET.
It is also useful to note that the trench MOSFET has
significantly smaller RDS(on) (105 m) compared to the planar
MOSFET (280 m), whereas Ciss values of both MOSFETs
are similar. This could be due to a combined effect of a higher
channel-carrier mobility and the smaller cell pitch used by the
trench structure.
V. C ONCLUSION
This article compares commercial planar and trench SiC
MOSFETs based on the density of performance-degrading
NITs, measured by a newly developed integrated-charge tech-
nique. The major advantage of the integrated-charge method is
that it can quantify the NITs with response times in the order
of nanoseconds at the operating gate voltages in commercial
MOSFETs. It was found that, at VG = 18 V, 9% and 15% of
the total channel electrons were trapped for longer than 500 ns
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6229
in the trench and planar MOSFETs, respectively. These results
explain the better channel-carrier mobility and hence the better
performance of trench MOSFETs.
ACKNOWLEDGMENT
This work was performed at the Australia National Fab-
rication Facility (ANFF), Queensland node, QLD, Australia,
a company established under the National Collaboration
Research Infrastructure Strategy to provide nano- and micro-
fabrication facilities to Australia’s researchers.
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