Modul 6:

VHDL for LATCH and FLIP-FLOP

MII 2312: Advance Electronics
ELINS – DIKE – FMIPA - UGM

1
SR-Latch
VHDL Code for SR-Latch
library ieee;
use ieee.std_logic_1164.all;

entity srlt is
port(r,s:in std_logic;
q,qbar:buffer std_logic);
end srlt;

architecture srlatch of srlt is

begin
q<= s nand qbar;
qbar<= r nand q;
end srlatch;
SR-Latch TestBench
library ieee;
use ieee.std_logic_1164.all;

entity srlt_tb is
end srlt_tb;

architecture srlt_test of srlt_tb is

component srlt
port(r,s:in std_logic;
q,qbar:buffer std_logic);
end component;
signal s1,r1:std_logic := '0';
signal qp:std_logic := '1';
signal qn:std_logic := '0';
begin
u1: srlt port map (r=>r1, s=>s1, q=>qp, qbar=>qn);
p1 : process
begin
r1<='X';
s1<='X';
wait for 1 ns;

r1<='1';
s1<='1';
wait for 1 ns;

r1<='0';
s1<='1';
wait for 1 ns;
r1<='1';
s1<='1';
wait for 1 ns;

r1<='1';
s1<='0';
wait for 1 ns;

r1<='1';
s1<='1';
wait for 1 ns;

r1<='0';
s1<='1';
wait for 1 ns;
 r1<='0';
s1<='0';
wait for 1 ns;

assert false report "End of Test";

wait;

end process p1;

end srlt_test;
Simulation Waveform
D-Latch
VHDL Code for an D-Latch
library ieee;
use ieee.std_logic_1164.all;
entity dlt is
port(d:in std_logic;
q,qbar:buffer std_logic);
end dlt;
architecture dlatch of dlt is
signal s, r : std_logic;
begin
s <= d;
r <= not d;
q <= r nor qbar;
qbar <= s nor q;
end dlatch;
D-Latch TestBench
library ieee;
use ieee.std_logic_1164.all;
entity dlt_tb is
end dlt_tb;
architecture dlt_test of dlt_tb is

component dlt
port(d:in std_logic;
q,qbar:buffer std_logic);
end component;

signal d1:std_logic := '0';

signal qp:std_logic := '1';
signal qn:std_logic := '0';
begin
u1: dlt port map (d=>d1, q=>qp, qbar=>qn);
p1 : process
begin
d1<='0';
wait for 1 ns;
d1<='1';
wait for 1 ns;
d1<='0';
wait for 1 ns;
d1<='1';
wait for 1 ns;
d1<='1’;
wait for 1 ns;
 d1<='0';
wait for 1 ns;
d1<='0';
wait for 1 ns;
d1<='1';
wait for 1 ns;
assert false report "End of Test";
wait;
end process p1;
end dlt_test;
Simulation Waveform
SR Latch with Clock signal
VHDL Code for an SR Latch with Clock signal

library ieee;
use ieee.std_logic_1164.all;

entity srff is
port(r,s,clk: in std_logic;
q,qbar: buffer std_logic);
end srff;

architecture srflip of srff is

signal s1, r1:std_logic;
begin
s1<=s nand clk;
r1<=r nand clk;
q<= s1 nand qbar;
qbar<= r1 nand q;
end srflip;
SR Latch with Clock signal TestBench
library ieee;
use ieee.std_logic_1164.all;
entity srff_tb is
end srff_tb;

architecture srff_test of srff_tb is

component srff
port(r,s,clk:in std_logic;
q,qbar:buffer std_logic);
end component;

signal s1,r1,cl:std_logic := '0';

signal qp:std_logic := '1';
signal qn:std_logic := '0';
begin

u1: srff port map (r=>r1, s=>s1, clk=>cl, q=>qp, qbar=>qn);

p0 : process
begin
cl <= '1';
wait for 0.5 ns;
cl <= '0';
wait for 0.5 ns;
end process p0;
p1 : process
begin
r1<='X';
s1<='X';
wait for 1 ns;
r1<=‘0';
s1<=‘0';
wait for 1 ns;
r1<='0';
s1<='1';
wait for 1 ns;
r1<=‘0';
s1<=‘0';
wait for 1 ns;
r1<='1';
s1<='0';
wait for 1 ns;
 r1<=‘0';
s1<=‘0';
wait for 1 ns;
r1<=‘1';
s1<=‘0';
wait for 1 ns;
r1<='0';
s1<='0';
wait for 1 ns;
assert false report "End of Test";
wait;

end process p1;

end srff_test;
Simulation Waveform
D Flip-Flop
D Flip-Flop VHDL
library ieee;
use ieee.std_logic_1164.all;
entity dff_enb is
port ( data :in std_logic; -- Data input
clk :in std_logic; -- Clock input
enb :in std_logic; -- Enable input
q :out std_logic -- Q output
);
end entity;
architecture behav of dff_enb is
begin
process (clk,enb)
begin
if(rising_edge(clk) and enb ='1') then
q<= data;
end if;
end process;
end architecture;
TestBench
library ieee;
use ieee.std_logic_1164.all;
entity dff_tb is
end dff_tb;

architecture beh of dff_tb is

component dff_enb
port (
data, clk, enb : in std_logic; -- inputs
q : out std_logic ); -- output
end component;
signal data_s,clk_s,enb_s : std_logic := '0';
signal q_s : std_logic;
begin -- beh
u1 : dff_enb port map (
data => data_s,
clk => clk_s,
enb => enb_s,
q => q_s);
clk_p: process
begin -- process clk_p
clk_s <= '1';
wait for 0.5 ns;
clk_s <= '0';
wait for 0.5 ns;
end process clk_p;
dff: process
begin -- process dff
enb_s <= '1';
data_s <= '0';
wait for 1 ns;

enb_s <= '1';

data_s <= '1';
wait for 1 ns;

enb_s <= '1';

data_s <= '0';
wait for 1 ns;

enb_s <= '0';

data_s <= '0';
wait for 1 ns;
enb_s <= '0';
data_s <= '0';
wait for 1 ns;
enb_s <= '0';
data_s <= '1';
wait for 1 ns;
enb_s <= '1';
data_s <= '0';
wait for 1 ns;
assert false report "Selesai Test";
wait;

end process dff;

end beh;
Simulation Waveform
JK-FF
JK-FF Simulation