CHAPTER 4

Field Effect Transistors

 4.1 INTRODUCTION
• The field-effect transistor (FET) is a three-terminal
device used for a variety of applications that match,
to a large extent, those of the BJT transistor.

• Although there are important differences between

the two types of devices, there are also many
similarities that will be pointed out in the sections
to follow.
Contd…
FETs vs. BJTs

Similarities:
 Amplifiers , Switching devices , Impedance matching circuits
Differences:
 FETs are voltage controlled devices. BJTs are current controlled devices.
 The BJT transistor is a bipolar device, The FET is a unipolar device
 FETs have a higher input impedance because reverse biased of gate
source. BJTs have higher current gains.
 FETs are less sensitive to temperature variations and are more easily integrated
on ICs.
 FETs are generally more static sensitive than BJTs.
 In JFET, there are no junctions as in an ordinary transistor. The conduction is
through an n- type or p-type semi-conductor material. For this reason, noise level in
3
JFET is very small.
Contd…
• In BJT a current level and in the FET an applied
voltage.
• For the FET an electric field is established by the
charges present that will control the conduction path
of the output circuit;
Without the need for direct contact between
the controlling and controlled quantities.
Contd…

BJT and JFET Transistor

Contd…
FET types
• JFET: Junction FET
• MOSFET: Metal–Oxide–Semiconductor FET
 D-MOSFET: Depletion MOSFET
 E-MOSFET: Enhancement MOSFET
N-Channel JFET
Symbol P-Channel JFET
Symbol
 JFET Construction
• The n-channel is more widely used.
• There are three terminals:
• Drain (D) and Source (S) are connected to the
n-channel, Gate (G) is connected to the p-type
material
 JFET Operation: The Basic Idea
• JFET operation can be compared to a
water spigot.
• The source of water pressure is the
accumulation of electrons at the
negative pole of the drain-source
voltage.

• The drain of water is the electron

deficiency (or holes) at the positive
pole of the applied voltage.

• The control of flow of water is the gate

voltage that controls the width of the
n-channel and, therefore, the flow of
charges from source to drain.
Water analogy for the JFET
control mechanism.
 JFET Operation (cont).
 Since the n-channel JFET is a normally-ON device and if VGS is
sufficiently negative enough, the drain-source conductive
channel closes (cut-off) and the drain current reduces to zero.
 For the n-channel JFET, the closing of the conductive channel
between drain and source is caused by the widening of the p-
type depletion region around the gate until it completely
closes the channel. N-type depletion regions close the
channel for a p-channel JFET.
 So by setting the gate-source voltage to some pre-determined
fixed negative value, we can cause the JFET to conduct
current through its channel at a certain value between zero
amperes and IDSS respectively making it an ideal FET current
source.
 Hence, JFET is always operated with the gate-source pn
junction reverse-biased otherwise the JFET will operate ID
beyond its maximum value
 JFET Operating Characteristics
There are three basic operating conditions for
a JFET:
VGS = 0 V, VDS Some Positive Value and
increasing to some value
VGS < 0, VDS at some positive value
Voltage-controlled resistor
Case I: VGS = 0 V, VDS Some Positive Value
Contd…
• If a positive voltage VDS has been applied across the channel and the
gate has been connected directly to the source to establish the
condition VGS =0 V.
• The result is a gate and source terminal at the same potential and a
depletion region in the low end of each p-material similar to the
distribution of the no-bias conditions

JFET in the VGS=0

V and VDS > 0 V.
Contd…
 The instant the voltage VDD ( VDS) is applied, the
electrons will be drawn to the drain terminal,
establishing the conventional current ID
The path of charge flow clearly reveals that the drain and
source currents are equivalent (ID = IS).
 It is important to note that the depletion region is
wider near the top of both p type materials.
 Assuming a uniform resistance in the n-channel, the
resistance of the channel can be broken down to the
divisions appearing in Figure below.
 The current ID will establish the voltage levels through
the channel as indicated on the same figure.
Contd…
The result is that the upper region of the p-type
material will be reverse biased by about 1.5 V,
And the lower region is only reverse-biased by 0.5
V.

Figure: Varying reverse-

bias potentials across
the p-n junction of an n-
channel JFET.
Contd…
• Recall from the discussion of the diode operation
that the greater the applied reverse bias,
 The wider the depletion.
• The fact that the p-n junction is reverse-biased for
the length of the channel; results in a gate current
of zero amperes.
• The fact that IG = 0 A is an important characteristic
of the JFET.
Contd….
Case II: VGS = 0 V and VDS increasing to some
positive value
• Three things happen when VGS = 0 and VDS is increased from
0 to a more positive voltage
1, The depletion region between p-gate and n-channel increases
as electrons from n-channel combine with holes from p-gate.
2, Increasing the depletion region, decreases the size of
the n-channel which increases the resistance of the n-
channel.
3, Even though the n-channel resistance is increasing,
• The current (ID) from source to drain through the
n-channel is increasing.
• This is because VDS is increasing.
Contd…

VGS = 0 V and VDS increasing to some positive value

JFET Operating Characteristics: Pinch Off
• As the voltage VDS is increased from 0 to a few volts;
the current will increase as determined by Ohm’s
law and the plot of ID versus VDS is relatively straight
line
• The relative straightness of the plot reveals that for
the region of low values of VDS; the resistance is
essentially constant.
• As VDS increases and approaches a level referred to as
VP;the depletion regions will widen and causing a
noticeable reduction in the channel width.
Contd…
• The reduced path of conduction causes the
resistance to increase.
• If VDS is increased to a level where; it appears
that the two depletion regions would “touch” a
condition referred to as pinch-off will result.
• The level of VDS that establishes this condition
is referred to as the pinch-off voltage(VP)
• When VDS reaches VP; ID maintains a saturation
level defined as IDSS.
• In reality a very small channel still exists, with a
current of very high density
Contd…
• The fact that ID does not drop off at pinch-off and maintains the
saturation level is verified by the following fact:
• The absence of a drain current would remove the possibility of
different potential levels through the n-channel material; to establish
the varying levels of reverse bias along the p-n junction.
• The result would be a loss of the depletion region distribution that
caused pinch-off in the first place.

Pinch-off (VGS =0 V, VDS =VP).

JFET Operating Characteristics: Saturation
• At the pinch-off point:
• Any further increase in VDS does not produce any increase in ID.
VDS at pinch-off is denoted as Vp. ID is at saturation or maximum.
It is referred to as IDSS. The ohmic value of the channel is
maximum.

ID versus VDS for

VGS = 0 V.
 Plotting the JFET Transfer Curve
• Using IDSS and Vp (VGS(off)) values found in a
specification sheet,
– the transfer curve can be plotted according to these
three steps:
Step 1
2
 VGS 
I D  I DSS 1  
 V 
 GS(Off) 

Solving for VGS = 0V ID = IDSS

Step 2  VGS 
2

I D  I DSS 1   Step 3
 V 
 GS(Off)  2
 VGS 
I D  I DSS 1  
 V 
Solving for VGS = -Vp = VGS(off), ID = 0A  GS(Off) 
Solving for VGS = 0V to Vp
Contd…
• Therefore, once VDS > VP the JFET has the
characteristics of a current source.
• As shown in Figure below, the current is fixed at ID =
IDSS,
• but the voltage VDS (for levels > VP) is determined
by the applied load.

Figure : Current source

equivalent for VGS = 0 V, VDS > VP.
 Case III: VGS < 0, VDS at some positive value
• As VGS becomes more negative, the depletion region
increases.
Application of a negative
voltage to the gate of a
JFET.
As VGS becomes more negative:
The JFET experiences pinch-off at a
lower voltage value of VDS. The
effect of the applied negative-bias
VGS is; to establish depletion
regions similar to those obtained
with VGS = 0 V but at lower levels
of VDS.
Contd…
• Therefore, the result of applying a negative bias
to the gate is to reach the saturation level at a
lower level of VDS
• As VGS is made more and more negative;
The resulting saturation level for ID has been
reduced and in fact will continue to decrease.
• Eventually, when VGS=-VP, It will be sufficiently
negative to establish a IDSS saturation level that is
essentially 0 mA, and for all practical purposes
the device has been “turned off.”
Contd…

Figure: n-Channel JFET characteristics with IDSS = 8 mA

and VP=4 V ( for VGS = 0 V)
Contd…
• At point where ID reaches 0 A. VGS is equal to -Vp
or VGS(off)(Cut-off voltage)
• Also note that at high levels of VDS the JFET
reaches a breakdown situation.
– ID increases uncontrollably if VDS > VDSmax.
• The region to the right of the pinch-off Locus is
the region typically employed in linear
amplifiers. linear amplifiers(amplifiers with
minimum distortion of the applied signal).
 JFET as Voltage-Controlled Resistor
• The region to the left of the pinch-off point is called the
ohmic region.
• The JFET can be used as a variable resistor, where VGS
controls the drain-source resistance (rd).As VGS
becomes more negative, the resistance (rd)
increases.
ro where ro is the resistance with VGS
rd  2 = 0 V, and
 
1  VGS  rd the resistance at a particular
 V 
 GS(Off)  level
of VGS.
 p-Channel JFETS
• The p-channel JFET behaves the same as the n-
channel JFET, except the voltage polarities and
current directions are reversed.

p-Channel JFET.
Contd…
p-Channel JFET Characteristics
• As VGS increases more positively
• The depletion zone increases(I.e resistance increases)
• ID decreases (ID < IDSS)
• Eventually ID = 0 A
• Also note that at high levels of VDS the JFET reaches a
breakdown situation: ID increases uncontrollably if VDS >
VDSmax.
Contd…

p-Channel JFET characteristics with IDSS = 6 mA and

VP=6 V(VGS = 0 V)
 JFET Transfer Characteristics
• The transfer characteristic of input-to-output is not as
straightforward in a JFET as it is in a BJT.
In a BJT,  indicates the relationship between IB (input)
and IC (output).
• In a JFET, the relationship of VGS (input) and ID
(output) is a little more complicated:
2
 
 
 V  Shockley’s
ID  I 1
DSS 
GS 


V 
 equation
 GS(Off) 
 JFET Transfer Characteristics Curve

This graph shows the value of ID for a given

value of VDS.
Example 1.Figure below shows the transfer characteristic curve of a JFET. Write the
equation for drain current.

Solution.
Referring to the transfer characteristic curve
we have,

Example 2. A JFET has the following parameters: IDSS = 32 mA ; VGS (off) = – 8V ;

VGS = – 4.5 V. Find the value of drain current.

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Example 3. A JFET has a drain current of 5 mA. If IDSS = 10 mA and VGS (off) = – 6 V,
find the value of (i) VGS and (ii) VP.

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 Example 4. For the JFET in Figure below VGS (off) = – 4V and IDSS = 12 mA.
Determine the minimum value of VDD required to put the device in the constant-current
region of operation.

Solution.
Since VGS (off) = – 4V, VP = 4V. The minimum
value of VDS for the JFET to be in
constant-current region is
VDS = VP = 4V
In the constant current region with VGS = 0V,
ID = IDSS = 12 mA
Applying Kirchhoff’s voltage law around the drain
circuit, we have,
VDD = VDS +V RD = VDS + ID RD
= 4V + (12 mA) (560Ω) = 4V + 6.72V = 10.72V
This is the value of VDD to make VDS = VP and put
the device in the constant-current region.
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 FET Small-Signal Model
Transconductance: The relationship of a change in ID to the
corresponding change in VGS is called transconductance,
Transconductance is denoted gm and given by:
ΔI D
gm 
ΔV GS

37
Mathematical Definitions of gm and input
impedance

Input impedance: Z i  

1
Output Impedance: Z o  rd 
y os
VDS
where: rd  VGS  constant
I D

yos= admittance parameter listed on FET specification sheets.

38
FET AC Equivalent Circuit

39
 JFET Biasing
For the proper operation of n-channel JFET, gate must be negative w.r.t.
source. This can be achieved either by inserting a battery in the gate circuit
or by a circuit known as biasing circuit.
1. Bias battery. In this method, JFET is biased by a bias battery VGG. This
battery ensures that gate is always negative w.r.t. source during all parts of
the signal.
2. Biasing circuit. The biasing circuit uses supply voltage VDD to provide
the necessary bias. Two most commonly used methods are
(i) self-bias
(ii) (ii) potential divider method.

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 JFET Biasing by Bias Battery
Figure shows the biasing of a n-channel JFET by a bias
battery – VGG.
This method is also called gate bias. The battery voltage
– VGG ensures that gate – source junction remains reverse
biased. Since there is no gate current, there will be no
voltage drop across RG.
 VGS = VGG
We can find the value of drain current ID from the
following relation

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 Self-Bias for JFET
Figure shows the self-bias method for n-channel
JFET. The resistor RS is the bias resistor. The d.c.
component of drain current
flowing through RS produces the desired bias
voltage. Voltage across RS, VS = ID RS
Since gate current is negligibly small, the gate
terminal is at d.c. ground i.e., VG = 0.
VGS = VG − VS = 0 − ID RS
or VGS = − ID RS
Thus bias voltage VGS keeps gate negative w.r.t.
source

VGS = VG – VS = Negative. This means that VG is negative w.r.t. VS. Thus if VG = 2V and VS
= 4V, then VGS = 2 – 4 = – 2V i.e. gate is less positive than the source.

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1/25/2023 Dessie Fentaw 43
Example 5. Find VDS and VGS in Figure, given that ID = 5 mA.

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Example 6. In a self-bias n-channel JFET, the operating point is to be set at ID = 1.5 mA
and VDS =10 V. The JFET parameters are IDSS = 5 mA and VGS (off) = − 2 V. Find the
values of RS and RD. Given that VDD = 20 V.
Solution.

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 JFET with Voltage-Divider Bias

Figure shows potential divider method of biasing a

JFET. This circuit is identical to that used for a
transistor. The resistors R1 and R2 form a voltage
divider across drain supply VDD. The voltage V2 (=
VG)across R2 provides the necessary bias.

The circuit is so designed that ID RS is larger than V2 so

that VGS is negative. This provides correct bias voltage. We
can find the operating point as under :

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Example 7. Determine ID and VGS for the JFET with voltage-divider bias in Figure
given that VD = 7V.

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EX. In an n-channel JFET biased by potential divider method, it is desired to set the
operating point at ID = 2.5 mA and VDS = 8V. If VDD = 30 V, R1 = 1 MΩ and R2 =
500 kΩ, find the value of RS. The parameters of JFET are IDSS = 10 mA and VGS
(off) = – 5 V. For the figure below

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 D.C. and A.C. Equivalent Circuits of JFET

 Like in a transistor amplifier, both d.c. and a.c. conditions prevail in a JFET
amplifier. The d.c. sources set up d.c. currents and voltages whereas the a.c.
source (i.e. signal) produces fluctuations in the JFET currents and voltages
 . Therefore, a simple way to analyse the action of a JFET amplifier is to split
the circuit into two parts viz.
 d.c. equivalent circuit and a.c. equivalent circuit.
 The d.c. equivalent circuit will determine the operating point (d.c. bias
levels) for the circuit while a.c. equivalent circuit determines the output
voltage and hence voltage gain of the circuit.

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 We shall split the JFET amplifier shown in Figure below

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 1. D. C. equivalent circuit.
In the d.c. equivalent circuit of a JFET amplifier, only d.c. conditions are considered

 Reduce all a.c. sources to zero.

 Open all the capacitors.
Applying these two steps to the JFET
amplifier circuit shown above , we get the
d.c. equivalent circuit
shown here. We can easily calculate the
d.c. currents and voltages from this
circuit

The d.c. equivalent circuit of a JFET amplifier

using voltage-divider bias . It is clear that :
VDD = VDS + ID (RD + RS)
or VDS = VDD – ID (RD + RS)

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2. A. C. equivalent circuit.
In the a.c. equivalent circuit of a JFET amplifier, only a.c. conditions are to be considered.
The capacitors are generally used to couple or bypass the a.c. signal. The designer
intentionally selects capacitors that are large enough to appear as short circuits to the a.c.
signal. It follows, therefore, that in order to draw the a.c. equivalent circuit, the following
two steps are applied to the JFET amplifier circuit :
(i) Reduce all d.c. sources to zero (i.e. VDD = 0).
(ii) Short all the capacitors.

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 Calculations
Input impedance:
Zi  RG

Output impedance:

Z o  rd || R D

Zo  R D
rd  10R D

Voltage gain:

A v   g m (rd || R D )

A v  g m R D
rd  10R D

53
 Voltage Gain of JFET Amplifier
(i) for facility of reference. Note that R1 || R2 and can be replaced by a single
resistance RT. Similarly, RD || RL and can be replaced by a single resistance RAC (=
total a.c. drain resistance). The a.c. equivalent circuit can be of

We now find the expression for voltage gain of this amplifier. Referring to Fig. 19.36
(ii), output voltage (vout) is given by ;
vout = id RAC

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 But vout /vin is the voltage gain (Av) of the amplifier.
∴ Voltage gain, Av = gm RAC for loaded amplifier
= gm RD for unloaded amplifier
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 Calculations
Input impedance:

Z i  R1 || R 2

Output impedance:

Z o  rd || R D

Zo  R D
rd  10R D

Voltage gain:
A v   g m (rd || R D )

A v  g m R D
rd  10R D

56
 Example 8. The JFET in the amplifier of Figure given has a transconductance
gm = 1 mA/V. If the source resistance RS is very small as compared to RG,
find the voltage gain of the amplifier.

Transconductance of JFET, gm= 1

mA/V =

The total ac load (i.e. RAC) in the drain circuit consists of the parallel combination of RD
and RL i.e.
Total a.c. load, RAC = RD || RL
= 12 kΩ || 8 kΩ = 4.8 kΩ

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 Metal Oxide Semiconductor FET (MOSFET)
 The main drawback of JFET is that its gate must be reverse biased for proper
operation of the device i.e. it can only have negative gate operation for n-channel
and positive gate operation for p-channel.
 This means that we can only decrease the width of the channel (i.e. decrease the
conductivity of the channel) from its zero-bias size. This type of operation is
referred to as depletion-mode operation.
 Therefore, a JFET can only be operated in the depletion-mode.
 However, there is a field effect transistor (FET) that can be operated to enhance (or
increase) the width of the channel (with consequent increase in conductivity of the
channel) i.e. it can have enhancement-mode operation.
 Such a FET is called MOSFET.

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 Types of MOSFETs

 A field effect transistor (FET) that can be operated in the enhancement-mode is

called a MOSFET.
There are two basic types of MOSFETs
1. Depletion-type MOSFET or D-MOSFET. The D-MOSFET can be operated in
both the depletion- mode and the enhancement-mode. For this reason, a D-
MOSFET is sometimes called depletion/enhancement MOSFET.
2. Enhancement-type MOSFET or E-MOSFET. The E-MOSFET can be operated
only in enhancement- mode.
 The manner in which a MOSFET is constructed determines whether it is D-
MOSFET or EMOSFET.

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1. D-MOSFET. the constructional details of n-channel D-MOSFET shown figure .

It is similar to n-channel JFET except with the following modifications

(i) The n-channel D-MOSFET is a piece of n-type material with a p-type region (called
substrate) on the right and an insulated gate on the left as shown in Fig above. The free
electrons (Q it is n-channel) flowing from source to drain must pass through the narrow
channel between the gate and the p-type region (i.e. substrate).
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(ii) Note carefully the gate construction of D-MOSFET. A thin layer of metal
oxide usually silicon dioxide, SiO2 is deposited over a small portion of the
channel.
A metallic gate is deposited over the oxide layer. As SiO2 is an insulator,
therefore, gate is insulated from the channel. Note that the arrangement forms a
capacitor. One plate of this capacitor is the gate and the other plate is the
channel with SiO2 as the dielectric.
(iii) It is a usual practice to connect the substrate to the source (S) internally so
that a MOSFET has three terminals viz source (S), gate (G) and drain (D).
(iv) Since the gate is insulated from the channel, we can apply either negative
or positive voltage to the gate. Therefore, D-MOSFET can be operated in both
depletion-mode and enhancement-mode.

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 2. E-MOSFET.
The constructional details of n-channel E-MOSFET.

Its gate construction is similar to that of D-MOSFET.

The E-MOSFET has no channel between source and drain unlike the D-MOSFET. Note that
the substrate extends completely to the SiO2 layer so that no channel exists.
The E-MOSFET requires a proper gate voltage to form a channel (called induced channel).
It is reminded that E-MOSFET can be operated only in enhancement mode. In short, the
construction of E-MOSFET is quite similar to that of the D-MOSFET except for the absence
of a channel between the drain and source terminals.
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 MOSFETs
MOSFETs have characteristics similar to JFETs and additional
characteristics that make then very useful
There are 2 types of MOSFET’s:
1. Depletion mode MOSFET (D-MOSFET)
 Operates in Depletion mode the same way as a JFET when VGS  0
 Operates in Enhancement mode like E-MOSFET when VGS > 0
2. Enhancement Mode MOSFET (E-MOSFET)
 Operates in Enhancement mode
 IDSS = 0 until VGS > VT (threshold voltage)

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 D-MOSFET Symbols

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 Depletion Mode MOSFET Construction

The Drain (D) and Source (S) leads connect to the to n-doped regions
These N-doped regions are connected via an n-channel
This n-channel is connected to the Gate (G) via a thin insulating layer of SiO2
The n-doped material lies on a p-doped substrate that may have an additional terminal
connection called SS
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 Basic Operation
A D-MOSFET may be biased to operate in two modes:
the Depletion mode or the Enhancement mode

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 D-MOSFET Depletion Mode Operation

The transfer characteristics are similar to the JFET

In Depletion Mode operation:
When VGS = 0V, ID = IDSS
When VGS < 0V, ID < IDSS
When VGS > 0V, ID > IDSS 2
 VGS 
The formula used to plot the Transfer Curve, is: ID = IDSS  1 - 
 VP 
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 D-MOSFET Enhancement Mode Operation

Enhancement Mode operation

In this mode, the transistor operates with VGS > 0V, and ID increases above IDSS
Shockley’s equation, the formula used to plot the Transfer Curve, still applies but VGS is
positive: 2
 VGS 
ID = IDSS  1 - 
 VP 

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 p-Channel Depletion Mode MOSFET

The p-channel Depletion mode MOSFET is similar to the n-channel except that the
voltage polarities and current directions are reversed

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 Enhancement Mode MOSFET’s

n-Channel E-MOSFET showing channel length L and channel width W

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 Enhancement Mode MOSFET Construction

The Drain (D) and Source (S) connect to the to n-doped regions
These n-doped regions are not connected via an n-channel without an external voltage
The Gate (G) connects to the p-doped substrate via a thin insulating layer of SiO2
The n-doped material lies on a p-doped substrate that may have an additional terminal
connection called SS
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 E-MOSFET Symbols

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 Basic Operation
The Enhancement mode MOSFET only operates in the enhancement mode.

VGS is always positive

IDSS = 0 when VGS < VT
As VGS increases above VT, ID increases
If VGS is kept constant and VDS is increased, then ID saturates (IDSS)
The saturation level, VDSsat is reached.

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 Transfer Curve

ID(on)
To determine ID given VGS: ID = k (VGS - VT) 2 k=
(VGS(ON) - VT)2
where VT = threshold voltage or voltage at which the MOSFET turns on.
k = constant found in the specification sheet
k is based on the geometry of the device:
 W  KP  Cox denoted capacitance per unit gate area
k =   where KP = μNCOX
 L  2 
μ N is the mobility of electrons in the channel
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 p-Channel Enhancement Mode MOSFETs
The p-channel Enhancement mode MOSFET is similar to the n-channel except that the
voltage polarities and current directions are reversed.

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 D-MOSFETs Versus E-MOSFETs

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 Reading Assignments
• Common-Gate Configuration
• Common-Drain(Source-Follower) Configuration
• MOSFET Small-Signal Model

77
 Reading Assignments
• Common-Gate Configuration
• Common-Drain(Source-Follower) Configuration
• MOSFET Small-Signal Model

78
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