1_Analog_Integrated_Circuit_Design_Technology

Analog and Mixed-Signal
Integrated Circuit Design
Prof. Dr.-Ing. Ralf Brederlow

Chair for Circuit Design
With many thanks to my former TI

colleagues…
Lehrstuhl für Schaltungsentwurf, Fakultät für Elektrotechnik und Informationstechnik

Coures content
1. Transistor and Technology: 3. A/D-Converters:
a. IC Device physics and IC processing a. Introduction to switched-capacitor circuits
(discrete time)
b. Device Modeling
b. Introduction to ADC and DACs
c. Component non-idealities
c. ADC basics: Flash, pipeline, SAR, oversampling
d. Basics of manufacturing and circuit modeling
d. DAC basics: String, R2R, oversampling
2. Amplifiers
4. Power Management:
a. Ideal opamps and basic opamp configurations
a. overview of linear, capacitive, inductive and hybrid
b. Amplifier stages and current mirrors
power conversion
c. Basic opamp design
b. charge pumps
d. Frequency compensation
c. buck and boost converter control
e. Amplifier noise analysis
d. integrated power management circuits
f. Advanced gain stages and current mirrors
g. Bandgaps
2
Reference books
• B. Razavi, Design of Analog CMOS Integrated Circuits
• V. Ivanov, I. Filanovsky, Operational Amplifier Speed and Accuracy
Improvement
• P. Gray, R. Meier, et al, Analysis and Design of Analog Integrated
Circuits
3
Analog ICs in a “classical” “digital” world
• Digital
– cost/function decreases ~30%/year (2x scaling rule)
– each process node brings the possibility for more speed
and/or less power with the same architecture
– benefits from supply voltage decreases
– Easily transferable [to other process]
- if circuit design follows strict scaling rules
– Design and layout can be automated
• Analog
– cost/function decreases slower (2x scaling rule)
– decrease of supply degrades performance
– difficult to transfer between technologies
– attempts for automation show only limited success
4
Why analog?
• The world is ANALOG with small signals and large disturbances
– Analog is the interface to the world
– Often the critical path defining performance
• Examples
– Sensors and actuators
– Wireline and wireless communications
– Power management
• Positive benefits for engineers
– Analog experts are in high demand by industry
– Circuits are difficult to replace – leading to more stable markets
5
‘Moore‘s Law‘: the business model
• Historic trend of semiconductor industry cycles:

2x smaller size (and cost!) reduction every 2-3 years.
• Drives exponential growth with exponential device cost reductions
6
Recent cost trends in CMOS manufacturing
• Feature size reduction

does not keep historic
rules of scaling
(2x per node every
2 years)
• Due to technology
challenges in transistor
and interconnect
scaling (energy,
leakage, lithography)
7
Electronics is driving global trends:
e.g. Aging Populations
Clock
and NVM RAM
Power ...
JTAG/Debug
 How to ease the live of elder people, MSP430TM MAB 16
16MHz
 …work against the trend of growing RISC MDB 16
CPU
health care cost, ...
 …and show new opportunities for Digital Analog
Peripheral Peripheral
better heath care
Reference : CATRENE Scientific Committee Report on ‘Smart Systems for Healthcare and Wellness’, http://www.catrene.org/web/about/scientific.php, 2014 8
Electronics is driving global trends:
e.g. Aging Populations
SD
LDO
Internal Supply
Vref
zero-offset
A differential
amplifier
DAC
 How to ease the live of elder people,
 …work against the trend of growing IV-converter
RTD
health care cost,

 …and show new opportunities for
MCU
better heath care
Reference : CATRENE Scientific Committee Report on ‘Smart Systems for Healthcare and Wellness’, http://www.catrene.org/web/about/scientific.php, 2014 9
Medical monitoring system needs
• Sensing and signal aquisition – ‚eyes‘ of the system
• MCU – ‚brain’ of the system
• Support circuits (analog, digital, communication) –
the ‚voice‘ and ‚hands‘ of the system
Medical System Needs:
• Good (sensor) performance
• Easy of use
• Low weight
• Smallest form factor + + ?
• No power, no charging
• Easy data handling
• Robust and failsafe - also in a medical
environment (e.g. X-ray radiation, EMC)
• Respect patient privacy
10
System block diagram
32 kHz
LCD 256kB Real Time
160 Segs + MSP
Flash FG4xxx Clock +
Contrast 16-bit
16kB CPU Batt. Bck.
Control RAM BLE
1 21 323445 56 76 87 8 AM/PM
AM
/PM mg/dL
mg
/dL
SPI or
CR1025 NFC
Power
Basic 16-bit
Mgmt. USB
Timer Timer
Sensor Com-
parator UART
Refe-
rence 12-bit 12-bit
TEMP ADC DAC
12-bit
DAC GPIO
Sensor
Sensor systems need sensors PLUS a computer/microcontroller

(with analog interfaces, communication capabilities, and power supply)
11
System block diagram
32 kHz
LCD 256kB Real Time
160 Segs + MSP
Flash FG4xxx Clock +
Contrast 16-bit
16kB CPU Batt. Bck.
Control RAM BLE
1 21 323445 56 76 87 8 AM/PM
AM
/PM mg/dL
mg
/dL
SPI or
CR1025 NFC
Power
Basic 16-bit
Mgmt. USB
Timer Timer
Sensor Com-
parator UART
Refe-
rence 12-bit 12-bit
TEMP ADC DAC
12-bit
DAC GPIO
Sensor
Sensor systems need sensors PLUS a computer/microcontroller

(with analog interfaces, communication capabilities, and power supply)
12
Enable new applications with new ICs
Body worn, swallowed, or implanted monitoring
devices (Chip + Sensor + Battery + NFC communication as SiP)
• Real time, continuous data acquisition
• Intelligent and secure data processing and transmission
• Easy to wear and use
Impedance
NFC
p(glucose)
pH
Temperature
Patient monitor Wireless portable
patient monitor
Continuous monitoring of physiological data possible
Reference: http://www.everydayupsanddowns.co.uk/2014/09/abbott-freestyle-libre-review-bg.html 13
Course scope: Analog IC Design
Main Focus Secondary focus
• Circuit design from specification • Based on knowledge of
to topology to layout semiconductor physics and
• Circuit fundamentals transistor function
• Structural design
• Transistor-level design
• Precision from DC to mid-
frequencies– lowest offset,
highest linearity, SNR, gain, etc.
14
Semiconductor
Process and Device Basics
Technology, Components, and Circuit Modeling aspects
15
Modern CMOS technology
• Active components - transistors:
– MOS N- and P-channel
– Substrate PNP bipolar and diodes
• Passives
– low sheet-ro poly-Si resistors
– Capacitors: poly-Nwell (high voltco),
metal-metal/MIM (low density)
• Driven by digital technology advances
• Allows integration of digital and analog
• Can be as simple as 12 masks (photo-lithography steps)
• Analog processes – often over 30 masks for precision components
16
Performance analog process extensions
• Double-well – N-channel isolated from substrate
• Lightly doped drain – higher Vds
• Dual gate oxide – higher voltage operation
• Bipolar NPN and PNP – low noise, high transconductrance
• Improved passive components
– Poly-poly or Metal caps – good matching and linearity,
medium density
– Higher sheet resistance poly resistors – area savings
– Thin-film SiCr resistors - low drift, area efficient, very good matching
and stability
17
Passive Integrated Components
Resistors
18
MOS technology resistors
NWELL P+
SILICIDED POLY
19
Resistor non-idealities
• Self-heating – power dissipated at high current densities
• Voltage coefficient
Up to +/- 15% ! Can’t control
– Non-linearity
• Absolute value variation due to process and temperature
– Important for: oscillators, filter time constants,
bias current generators
• Matching – ratio variation 2% or better
– Systematic (metal, contacts, vias…)
– Gradients on the wafer ! Can be improved by 10x
– Random between devices (lithography) or more by large area and
– Important for: Opamp feedback ratios, good layout techniques
Resistive DACs, Voltage References
• In digital CMOS only silicide-poly, n+/p+ or nwell are available
20
Resistors
Type Sheet r Temperature coeff. Notes
Silicided poly-Si ~5-30 W/square -300 to 600 ppm/0C 100kW at 1mm width =
20000 mm length !
N-well 1-4 kW/square Up to -3000 ppm/0C Highly non-linear vs.
voltage, not isolated
P+ or N+ diffusion 30-100 W/square Up to 1500 ppm/0C Can be non-linear, not
isolated, good thermal
dissipation
Silicide-block medium 30-200 W/square -50 to 200 ppm/0C Additional mask
poly-Si
Thin Film SiCr 0.5-2 kW/square +/-10 ppm/0C Highest perf., 2 add.
masks, great matching!
Al metallization 30-50 mW/square Up to 4000 ppm/0C Parasitic or very special

purpose
MOS transistors in >10 kW/square varies Too process variable, used in
MOSFET-C filters, bias start-up
triode mode
21
Resistor non-idealities
Evaluation of short distance (“pair”) mismatch (II)
Frequency
Examples: Systematic mismatch

Improved by: careful layout
(metal, via, force/sense
considerations)
Wafer related distribution
of measured R values of
high ohmic poly-Si resistors:
Resistance [W]
Random mismatch
Frequency
Improved by: more area
and better layout
Wafer related distribution

of measured R values of
high ohmic poly-Si resistors:
Difference R [W]
22
Noise in circuits
Noise free
four-terminal
device
Noise free
two-terminal
 A noisy device can always be treated as an ideal device with

external noise sources
23
Thermal noise in resistors
• Thermal noise arises from the random thermal motion of the carriers in addition
to the drift in the field - even
• The contribution of a carrier to the total noise at a certain location in the device
is proportional to the conductance in that region:
=4 ∆ =4 ∆
24
Noise spectrum of a poly-Si resistor
10-18
Current-noise [A²/Hz]
length x width = 32 x 4 µm²
-19
10 1kW -resistance
10-20
12 25 5
10-21 5m 0m 00m 1V
V V V
10-22
10-23
thermal noise level
-24
10
100 101 102 103 104 105
Frequency [Hz]
• At higher frequencies thermal noise dominates in resistors
• At low frequencies and high currents 1/f-noise is present in practical CMOS
resistor options as well (e.g. due to carrier trapping effects at grain boundaries)
25
Resistor Layout Guidelines
• Always consider current density
• For accuracy and matching - stick with rectangles
• Avoid dog-bone ends and corners
• Use multiples of a unit geometry connected by metal
• Watch for contact resistance
• Inter-digitate, add dummies (next slide)
• Watch for series metal – excessive drift
26
Inter-digitation and Dummies
• Resistor variation caused by process gradients, over-
etch/under-etch and shadows => systematic mismatch
• Inter-digitation and dummy segments reduce these effects
by orders of magnitude
27
MOSFET Basics
STI STI
28
MOS transistors
Conventions
• “n+” and “p+” indicates higher doping level
(NOT charge polarity!), also used: NSD, PSD
• “n-”,”p-” lower doping (n-well and p-well are
usually low-doped)
• Transistor length “L” – Poly-Si gate between
drain and source,
• Transistor width “W” – stretch of
thin oxide under the gate
along source and drain
• VTH – MOS threshold voltage,
L, Leff
also used VT, but: Vt is also
the thermal voltage kT/q!
29
MOS transistor – circuit symbols
and terminals
n-MOS
p-MOS
• basic active component of circuit design

• Gate – the control terminal, high impedance
• Drain, Source – (usually) symmetrical, interchangeable
• don’t forget about the 4th terminal!
30
MOSFET current equation Poly-Si
SiO
2
0 L
( )= ( − − ) Bulk Silicon
Poly-Si Gate Bulk Silicon

= ( )=
µ µ SiO2
= µ ( ) Ef
∫ =∫ µ ( )
Drain
µ y
= ( − − ) L
Source 0
31
MOS I-V curves
Triode (ohmic) region: (VDS < (VGS-VTH)
W  V 
I D   C OX  V GS  V TH  DS V DS
L  2 
Saturation region (above threshold /

weak inversion): (VDS > VGS -VTH)
 C OX W
ID  V GS  V TH 2
2 L
K   C OX - technology dependent
In saturation region the channel is not fully formed and in a small drift /
saturation region carriers are passing at max. speed
32
MOS I-V curves
Triode (ohmic) region: (VDS < (VGS-VTH)
W  V 
I D   C OX  V GS  V TH  DS V DS
L  2 
Saturation region (above threshold /

weak inversion): (VDS > VGS -VTH)
 C OX W
2 L
Fully featured MOS models are highly complex but can be greatly simplified for
hand analysis here
33
MOS I-V curves
Weak inversion (subthreshold):
(VGS < VTH , VDS > 4 VTH )
W V  V GS 
ID  KW exp  TH 
L  nV T 
Strong inversion:
Ef
(VGS > VTH , VDS > VGS -VTH)
 C OX W
ID  V GS  V TH 2 Gate Oxide Substrate
2 L
• Current in weak inversion drift / diffusion limited

• In strong inversion current is limited by drift of free carriers
34
MOS I-V curves
Weak inversion (subthreshold): log(Ids)
(VGS < VTH , VDS > 4 VTH )
W V  V GS 
L  nV T  Strong
inversion
Strong inversion:
(VGS > VTH , VDS > VGS -VTH)
inversion
 C OX W
Weak
2 L
K   C OX - technology dependent Vgs
Vdd
Fully featured MOS models are highly complex but simplified model for hand
analysis can give a lot of insights into circuit sizing and optimization
35
MOS operating regions
Triode (ohmic) region:
• A flat inversion layer forms in the channel – carriers are free to flow from drain to source
• Transistor behaves as a resistor at very low Vds
Saturation region:
• Saturation is entered when pinch-off region appears
– Drain cannot “communicate with source
– Carriers travel through pinch-off region at saturated speed
• In reality: The current increases slightly with Vds – finite output resistance
Weak inversion:
• The current is due to diffusion rather then drift
• Therefore the current gain is exponential near the threshold voltage
• Moderate or weak inversion increasingly common in analog
• Good VTH matching – bad Ids matching
36
MOS transistor basics
Transfer
D characteristic
n-type MOSFET characteristic G
S
• Triode region, linear region for small VDS VTH

• Saturation region Output
characteristic
ideal saturation state: dIds / dVds = 0
saturation drain voltage Vds =Vdsat ≈ VGS –VTH
p-type MOSFET characteristic is similar, but opposite in sign for all voltages
37
MOSFET nonlinear characteristics
Triode region
 1  0  V DS  V GS  V TH
I DS     V GS  V TH (V BS )   V DS   V DS2 
 2 
Saturation region
 2
I DS   V GS  V TH (V BS )  0  V GS  V TH  V DS
2
with the gain factor (or conductance parameter)
W W   W
  K '   n C ox    n 0 ox  Layout parameter!
L L t ox L
38
MOSFET transconductance (gm)
• Transconductance is one of the key small-signal parameters for
transistors in linear circuits
• Measures a change of drain current for a given change of VGS
• Determines the amplification properties (in saturation):
I DS W W 2I DS
gm  VDS const  Cox VGS  VTH   Cox I DS 
VGS L L VGS  VTH
For MOS strong inversion, saturation:
39
MOSFET transconductance (cont.)
• Strong inversion 2 I DS
– increases linear with VGS – VTH and g mFET 
as the square root of IDS Vdsat
– Vdsat >> Vt = nkT/q IC
g mBJT 
Vt
• Sub-threshold
– gm same equation as for a BJT
– exponential current gain
– but low current = low speed
40
MOSFET operating regions and
small signal characteristics
Linear regions of operation
The MOSFET is a nonlinear device, but has operating regimes with
fairly linear characteristics which are often used for circuit design
Linear region
In this part of the triode region with VDS << VGS – VTH , the MOSFET is a
voltage controlled resistor with linear characteristics.
Large signal I     V  V   V  1  V 2  0  V DS  V GS  V TH
DS  GS TH DS
2
DS 

Small signal i D  g m v GS
with gain g   I DS   n C ox
W
V DS    V DS
m
 V GS V DS  const L
V BS  const
41
Saturation region
Ideal: Voltage controlled current source
 2
Large signal I DS   V GS  V TH 
2
Small signal i DS  g m  v GS
with gain β
 I DS W 2 I DSat
g m   n C ox V GS  V TH   2   I Dsat
 V GS V DS  const
V BS  const
L V GS  V TH 
42
Saturation region
with channel length modulation
linearized (Taylor) approximation:
 2
Large signal: I DS   V GS  V TH   (1    V DS )  V DS  1
2
 I DS  2
Small signal: g DS      V GS  V TH    I DS
 V DS 2
To have a large saturation region, MOSFETs in analog circuits are
biased at low overdriveV GS  V TH  V sat ; usually V sat  V TH
43
Output resistance 1/gds in saturation
• Channel length modulation: the
pinch-off region changes the
channel length
• Increasing L reduces the effect:
(Very important for analog
design – GAIN!)
1 W
Id   n C ox V GS  V TH 2 1   V DS 
2 L
  1
L More complex output resistance relations in circuit models
44
Key design analog parameters
• Region: moderate or strong inversion / saturation
– Most common region of operation in analog circuits
– Behaves like transconductor: voltage controlled current source
• Key design parameters
– Large signal
• Current ID → power dissipation
• Minimum VDS → available signal swing
– Small signal
• Transconductance gm → speed / voltage gain
• Capacitances CGS, CGD, … → speed
• Output impedance rds → voltage gain
45
Choice of MOSFET operating points
• To have a large saturation region = large
dynamic range, MOSFETs in analog circuits
are preferably biased at V GS  V TH  V sat
at low overdrive voltageV sat  V TH
• the differential resistance rds should be small
• In analog circuits MOSFETs mostly work in the conduction region above
threshold or sometimes in weak inversion (upper sub-threshold region)
with lower current, but higher dIDS/dVGS , i.e. higher gain per current.
• When used as switches (e.g. in DC-DC converters, class D amplifiers),
the operation is nonlinear, so small signal behavior is not important.
Here Ion should be large and Ioff small (leakage)
46
Basic building blocks for analog circuits
Current and voltage reference generators:
Symbol for Symbol for
Current reference generator Voltage reference generator
Biasing of circuit elements in the required operating point
D D
G W V  V GS  G
S L  nV T  S
Vds ~ ln (Ids) ~ const.
Ids ~ const.
47
Small signal model of MOSFET
• Approximation of large signal I D W
gm    C ox ID
model around the operating point  V GS L
• Simplifies calculations  V ds
r0   1
ds
I D ID
48
Body effect
• Body effect appears when the source is not tied to bulk
– Also called back gate transconductance
• The bulk attracts carriers, thus changing the depletion region
• This effectively changes VTH
• Effect occurs when the source voltage changes with respect to the
substrate/ well potential
• Must be considered for matching
V TH  V TH 0   2 F  V SB  2 F  Ef
2 q  si N sub
 
C ox Gate Oxide Substrate
49
Small signal model of MOSFET
• Approximation of large signal I D W
gm    C ox ID
model around the operating point  V GS L
including the gate to body
 V ds
relationship ... rds   1
ID
I D
• Capacitances are important for C
GB
speed and stability
CGD CDB
1/rDS vout= vDS

CGS gmvGS CSB
vin= vGS gmbvBS
50
Temperature effects
• Both threshold voltage VTH and
mobility µ vary with temperature Nominal Temp
• In saturation and strong inversion:
log(Ids)
 µ ~ 1/T n, n = 1 - 1.5
VTH ~ -T
• In subthreshold there is an
exponential temperature
dependence of the current Ids:
W  V TH  V GS  High Temp
ID  KW exp  
L  nV T  VGS
51
Variability - technology manufacturing window
• In-accuracies in manufacturing process are not avoidable
 U s e m a s k 1 2 6 t o a d ju s t V T
resulting in device performance gradients for all devices
 T h e V T s t a n d d e v i a t io n w a s h ig h e r t h a n S T D p r o c e s s
 If V t k -s h if t 2 s ig m a , t h e p r o c e s s w in d o w w a s n o t e n o u g h b a s e o n
c u rr e n t P C M s p e c .
Nominal Ids-Vgs
log(Ids)
P ro c e s s w in d o w w a s n o t e n o u g h
weak Ids-Vgs
strong Ids-Vgs
STD + 2 s ig m a +4 s ig m a +6 s ig m a STD + 2 s ig m a + 4 s ig m a + 6 s ig m a ULL VT ST D
P o ly c d +1 0 % VGS
52
Local variability in MOS technology
• On top of manufacturing tolerances there are principal
statistical reasons for VTH fluctuation in modern CMOS
devices:
• Mismatch in long channel devices is mainly determined by the

dopant fluctuations and is estimated by the following formula:
1
 Vt  t ox, el  4 N dop 
WL
53
Small signal noise model of MOSFET
 A noisy MOSFET can be treated as a noise free MOSFET with a

noise current source between source and drain
 An equivalent gate voltage referred noise-representation is possible
 For low frequencies we can neglect the gate current noise source
54
Thermal noise of a MOSFET
• The contribution of a carrier to the total noise at a certain location in
the device is proportional to the conductance in that region:
=4 ∆ =4 ( , ) ∆
• The noise magnitude is frequency dependent since the number of

carriers participating at the current transport is a function of time
• In non-linear regimes there is a noise modification factor f(Vgs, Vds)
which is e.g. ~2/3 in saturation region
55
1/f- or flicker-noise in MOSFETs
SiO2 SiO2
- Ef Ef
• Traps at the Si/SiO2 boundary frequently capture and re-

emit free carriers. They modify current transport through
the MOSFET channel both by number and mobility  (VGS , VDS ) N t ( E f )
SVgs  
fluctuations W L Cox
2
f
• Only traps close to the Fermi level significantly contribute
to fluctuations in current of the MOSFET surface channel
56
Random Telegraph Signal (RTS)
Noise amplitude
time
• Voltage over time for a small size device

• The noise is mainly produced by single trap events in
those devices!
57
MOS noise spectrum in frequency domain
10-10
Drain current noise [A/Hz]

Gate referred voltage noise
10 -3 n-MOS 200µm / 0.5µm experimental data

n-MOS, W / L = 25µm / 0.25µm
classical model
V d = 1.0V, V g,eff = 0.5V
10 -4
[VHz ]
10 -5
-1/2
10-11
10 -6 Vgs,eff: 0.20V;
Vds: 0.65V;
10 -7 gds: 0.63mS;
gm: 6.50mS;
gmb: 1.26mS;
10 -8 10-12
100 10 1
10 2
10 3
10 4
10 5
105 106 107 108
Frequency [Hz] Frequency [Hz]
58
Velocity saturation, impact ionization,
hot carrier effect
• Near the drain due to high electric fields
carriers have high energy
• The hot electrons collide with the lattice
(electron/ hole pairs)
– Leads to a substrate current Isub – leakage!
– Can limit gain if not controlled
• At high gate and drain fields this also
results in saturation velocity of carriers vsat
even in the inverted part of the channel
IDS  IDS 0  Isub
• This effects limits the Ids increase at higher   
 
gate voltages in modern CMOS to become
I sub  I DS VDS  Vdsat  e  VDS Vdsat 
linear with Vgs
59
MOFSET hot carrier damage generation
– High electric field in channel
CHC-induced
causes high carrier energy
trapped charge – At low energy levels, carriers
spacer oxide conduct
gate
gate CHC-induced – If carriers have enough
oxide interface states
energy, they can jump into
drain
the oxide
local Vt-shift (± Vt) • This is sometimes noticeable as
+ pA or nA of DC gate current
mobility decrease (m) R D-shift (± R D)
• With time, enough carriers
become trapped in the oxide
60
Negative and positive bias temperature
instability (NBTI / PBTI)
NBTI PBTI
NBTI -V / PBTI +V Under high electric field, PSD Gate Poly
highly-energetic holes
B
PSD Gate Poly bombard the interface and B B
B B B
Containing B-H release hydrogen from weak
PMOS Structure
Complex
Si-H bonds. Free Hydrogen H H
can leave behind an interface H
Gate Oxide Gate
SiO2 state or form a positive oxide Oxide H H
H charge. SiO2 H
H H
H H Under high electric field
SiO2
Si Si Si Si Si B-H complexes break and the
Holes
free hydrogen moves to the

Si
nwell
Si/SiO2 interface creating
interface states and oxide charge
Gnd
61
Reliability depends on region of operation
• Operating points of n-MOS and p-MOSFET in an inverter
62
MOS reliability: critical operating conditions
1. analog operation:
power-down mode with 0  VG 
typical VDD, VD  0, operation in the
2
DRAIN CURRENT
CMOS-inverter depletion or inversion region,

switching curve digital operation:
“ON“ state with VG = VDD,
3 VD = 0
typical analog
operating regime
2. analog operation:
(active mode) power-down mode with 0  VG 
................................... 4
1 ..........................................
..........
VDD, VD  0, operation in the
depletion or accumulation region,
DRAIN VOLTAGE
“ON“ “OFF“ 3: digital operation during switching
4: analog operation active mode
63
MOSFET degradation mechanisms
Effect Occurrence Effect on circuit Specific analog
of stress performance approach required
active power-down active power-down

mode mode mode mode
Channel hot-carrier possible negligible yes no yes

(CHC) stress
Bias temperature negligible possible yes no in part *

(BT) stress
Oxide stress negligible possible yes possible no
64
PMOS vs. NMOS
• PMOS:
– Holes have lower mobility
(lower current drive and transconductance)
– Lower output resistance (lower gain)
– Generally matches better than NMOS and
has often lower flicker (1/f) noise
• PMOS can generally be placed in its own n-well
(eliminate impact ionization and bulk bias effects)
65
MOSFET(s) as a switch
| log(Ids) |
Vin Vout
Vdd - Vin = | VGS |

Vin = | - VGS |
• On-resistance Rout at different Vin depends on VGS

• n-MOS good at low, p-MOS good at high Vin
• For a combination of n- and p-MOSFET the highest on-resistance
is at medium voltages between the rails
66
Device modeling / Simulator
67
BSIM model / circuit simulation
• In a circuit simulator today much more sophisticated model for the
MOSFET operation are used – including all aspects discussed here
• They contain up to several hundret parameters for correct fitting of the
electrical characteristics of a MOSFET for all regions of operation and
geometries and are build such that the system is continuously
differentiable (for convergence in a numerical simulator)
• Details on those models can be found at:
http://bsim.berkeley.edu/models/bsimbulk/
• These models are used in todays circuit simulations tools
(SPICE, PSPICE, ...) for simulation of large electronic circuits
→ See practical courses / projects on integrated circuit design
68
Transistor/component modeling for circuits
For all future circuit blocks discussed during this lecture
• operating points (OP) are determined from the
nonlinear device characteristics
• signal processing function is determined from the small signal
equivalent circuits (linearized in OP), where the characteristics are
linearized in the operation point. This is only possible if the devices are
always in saturation and operating points are fixed.
• Large signal (non-linear) behavior is model as a stepwise linear
operation in time using small enough time steps (often adjusted by the
simulation tool based on accuracy and linearity of the system)
69
How to design more complex circuits with
more sophisticated models I
• First the simulator needs to find a DC ~
operating point of the device using the large
signal equations for a MOSFET
 2
I DS   V GS  V TH (V BS ) 
2
... or a more complex representation of ID
• In a second step a small signal change
(e.g. the supply voltage rejection) can be
added to the simulation to understand circuit
sensitivity with respect to disturbances
70
How to design more complex circuits with
more sophisticated models II
• Using the approximation of large signal model around the
operating point (including parasitic capacitances) reveal a
AC result around the DC operating point
~ I W  V DS
g m  DS  Cox I DS rds   1
 I Ds  I DS
R VGS L
G
rds rds
1/gm
M1 M2
71
Circuit simulation flow
Large signal models and
known node voltages
Iterative solutions
of DC variables
Small signal models Small signal models

at the DC variables at the DC variables
Transient
AC
Solution of the linear Large signal model of (time)
(frequency)
equations the new DC variables response
response
periodic steady state
frequency analysis
72
Passive Integrated Components
Capacitors
73
MOS Gate and Metal-Metal Capacitors
MOS gate
• High capacitance
• Highly non-linear
• Large parasitics
Metal-Metal
• Linear but low density
• Lateral can be comparable to vertical
• Large parasitics
74
Poly-Poly and other analog Caps
• Require additional
masks/process steps
• Very good linearity
• Very good matching
75
Capacitor layout examples
• Same considerations as for resistors

(interdigitate, dummies), plus:
• Bottom-plate parasitic cap
• Shielding, fringe capacitance
76
MOS transistor capacitances
• To predict the AC behavior capacitances need to be taken into account
• Different capacitances: between terminals, oxide capacitance, depletion,
overlap, junction
• Capacitance depends on per region of operation of underlying MOS:
Cpoly CovGD
Cox
triode
Cdep region
saturation
CovDB
77
Parasitic capacitance and resistance
Passivation
Wire
Dielectric
Etch Stop Layer
Via
Global (up to 5) Dielectric Capping Layer
Copper Conductor with

Barrier/Nucleation Layer
Intermediate (up to 8)
Metal 1 Pre Metal Dielectric

Tungsten Contact Plug
Metal 1 Pitch
• Number of metal layer increases with decreasing process min. feature size
• Hierarchy of metal layers becomes more pronounced and material choices different
between different hierarchy levels
• Hierarchy, organization & number choice depend on product needs
78
Capacitors
• High density – opamp compensation, bypass
• High accuracy – feedback, sampling, ADCs, filters
Type Capacitance fF/mm2 Voltage coefficient Notes

poly-Si – Nwell ~3-15 Very large Large Tc
(MOS gate) (depends on Cox)
Metal-Metal 0.05-0.5 (for None or <5ppm/V Consider
special geometries) vertical and lateral!
Poly-Poly or Me-poly 0.5-2 -50 ppm/V Process option
w/ special dielectric
Junction ~1000 Very large Usually parasitic
79
Parasitic effects: cross-talk and wiring
• In an integrated circuit a lot of different signals are propagating across the
chip in order to perform data processing
• These signals can interfere:
• Series resistance: R    L
A
• Stray capacitance: C    A
t
• Capacitive and resistive coupling between different signals occurs

• Interference between different signals (or Vdd, Vss) increases with the
complexity of the (wiring of the) circuit
80
Analog trade-off for power / speed
• Higher performance, but also fast start-up needs more current
for faster charging of capacitances:
2
µ C ox W
I DS    V GS  V TH   (1    V DS )
2L
•  t ~ Ctotal / IDS ~ Ctotal / Cox
• All capacitance of the next gate needs to be recharged

 small caps per current support high speed  small L
• More biasing current ( high VGS) when speed is needed
81
Analog scaling considerations
Supply voltage and noise
101
at minimum area [V]
Vdd
6sV,th matching
12sv,in 1/f-noise
100
10-1
10-2
350 250 180 130 90 65 45 32 25 18
node [nm]
• Devices with higher voltage tolerance have higher signal to noise ratio
• But those devices have area and speed penalty …
82
Scaling scenario for analog devices (ITRS)
Minimum gate lenght (nm) E035.2
130 90 65 45
Minimum Supply Voltage Digital Design (V) 1.5 1.2 1.1 1
Analog Design (V) 3.6 - 1.8 3.6 - 1.8 3.6 - 1.8 3.6 - 1.8
nMOS Analog Speed Device Tox (nm) 3.3 2.9 2.3 2
max. operating voltage 1.5 1.2 1.1 1
gm / gds @ 5·Lmin-digital 100 100 100 100
1/f-noise (µV²·µm² / Hz) 300 200 150 100
s Vth matching (mV·µm) 5 4 3 2.5
nMOS Analog Precision Device Tox (nm) 6.5 6 5.5 5
Analog Vth (V) 0.7 0.7 0.7 0.7
gm / gds @ 10·Lmin-digital 300 300 300 300
1/f Noise (µV²·µm² / Hz) 500 400 350 300
s Vth matching (mV·µm) 15 13 11 10
Analog Capacitor Density (fF/µm²) 1.5 2 2.6 3.5
Voltage linearity (ppm / V²) < 100 < 100 < 100 < 100
Leakage (fA/µm² @ max Vdd) 10 5 3 2
s Matching (%·µm) 1 0.7 0.5 0.3
Analog Resistor Resistance (kOhm/sq.) 2.5 5 10 20
Parasitic capacitance (fF/µm²) 0.02 0.02 0.02 0.02
Temp. linearity (ppm / ºC) 50 40 30 20
1/f-current-noise per current²
> 10-18 > 10-18 > 10-18 > 10-18
(1 / [µm²·Hz])
s Matching (%·µm) 3 2.5 2 1.5
Bipolar Analog Device 1/f-noise (µV²·µm² / Hz) 5 3 2 1.5
beta 5 5 5 5
s current matching (%·µm²) 20 20 20 20
83
Inductors
... even though not used in most analog and digital circuit application
(but often in RF circuits!):
• RF coils in the order of a few nH can be
integrated on-chip
• They tyically suffer from a low quality
factors due to:
– Metal resistance
– Eddy currents in the substrate
• For high speed analog designs the
inductance of bondwires need to be
considered! 84

Bipolar Transistor Basics
85
Bipolar Junction Transistors
• Provide lower noise, higher current (speed) than MOS for equivalent power
• Often used in RF, high-speed design
• Also good for high-precision (good matching and low noise)
• Modern BJTs are often based on SiGe, GaAs, InP
86
The NPN Transistor
• An NPN transistor consists of a P-type base region sandwiched between N-
type emitter and collector regions.
IC
IE VBE VCB
IB
– + – +
• NPN transistors have four regions of operation:

– Cutoff VBE < 0V, VCB > 0V
– Forward active VBE > 0V, VCB > 0V
– Reverse active VBE < 0V, VCB < 0V
– Saturation VBE > 0V, VCB < 0V
87
NPN – Cutoff region
• When an NPN operates in cutoff,

– The base-emitter depletion region is reverse-biased
(VBE < 0V)
– The base-collector depletion region is reverse-biased
(VCB > 0V)
– Each of these junctions behaves as it does in a PN diode.
– Terminal currents IE, IB, and IC are thus all very small.
88
NPN – Forward active region
• When an NPN operates in the forward active region,
– The base-emitter depletion region is forward-biased (VBE > 0V)
– The base-collector depletion region is reverse-biased (VCB > 0V)
– Although each of the two PN junctions acts like a PN diode, they are located so
close to one another that they begin to interact.
• If VBE exceeds 0V, then additional minority carriers flow across the base-emitter junction.
• Most of these additional minority carriers consist of electrons injected from the heavily
doped emitter into the moderately doped base.
• The electrons injected into the base diffuse across this region.
• Some recombine, but the base is so thin that quite a few diffuse all the way to the
collector-base depletion region before they recombine.
• Electrons that reach the collector-base depletion region are drawn into the collector by
the electric field present across this region.
• Electrons flowing into the collector generate a collector terminal current that did not
previously exist.
89
Forward Active Terminal Currents
IC
IE VBE VCB
IB
– + – +
• The emitter current consists of electrons injected from emitter to base, plus
electrons required to support emitter recombination.
• The base current consists of holes injected from base to emitter, plus holes
required to support base recombination.
• The collector current consists of electrons flowing from base to collector.
90
The NPN Transistor
Base Recombination:
• Some electrons injected into the base do not reach the collector; instead they
recombine within the base – base current
• The fraction of carriers that transit the base depends upon two factors:
– Neutral base width
– Base doping V BE
Collector current and : I C  I CS e Vt
IC
 
IB
High-level injection:
• At high collector currents, the excess minority carrier charge becomes
comparable to the base doping.
– This condition is called high-level injection.
– High-level injection causes increased recombination and reduced beta.
91
The Early Effect
An increase in collector-to-emitter voltage VCE appears primarily across the base-collector
junction. If this occurs, then:
– The depletion region across the base-collector junction widens.
– The neutral base width decreases.
– This mechanism is called the Early effect. IC
VBE
Vt  VCE 
I C  I CS e 1  
 VA 
VBE
1 I I
 C  CS e Vt
ro VCE VA
V CE
VA
• The Early voltage VA quantifies the impact of VCE upon gain.
• VA is defined as the horizontal intercept of the ICE-versus VCE-curve.
92
Saturation
• In a saturated transistor, both the emitter-base and the collector-base
depletion regions are forward biased.
– In an NPN transistor, saturation implies VBE > 0 and VCB < 0.
– Current can flow either from the emitter to the collector or vice versa, depending
upon the relative degree of forward bias applied to the two junctions.
• The large minority carrier populations in a saturated device slow its switching.
– In order for current to cease flowing through the transistor, the minority carriers must
all recombine.
– This typically requires 1–2µs, producing a saturation delay of the same duration.
• Saturation can cause failures in junction-isolated ICs.
– A typical integrated NPN transistor is fabricated on a P-type substrate. This
substrate operates at ground potential.
– The collector-substrate junction is thus reverse-biased.
– Saturation injects holes from the base into the collector.
– Some of holes diffuse across into the isolation => current flow
93
Saturation Terminal Currents
IC
IE VBE VCB
IB
– + – +
• The emitter current consists of electrons injected from emitter to base, plus
electrons required to support emitter recombination.
• The base current consists of holes injected from base to emitter, holes injected
from base to collector, and holes required to support base recombination.
• The collector current consists of electrons flowing from base to collector, minus
electrons required to support collector recombination.
94
PNP Transistors
IC
IE VBE < 0 IB VCB < 0
– + – +
• The PNP transistor behaves much like an NPN transistor.

– The PNP uses a P-type emitter, an N-type base, and a P-type collector.
– During forward-active operation, holes injected from the emitter diffuse across the
base to reach the collector.
– The forward-biased PNP exhibits VBE < 0V, VCB < 0V.
• PNP transistors generally do not perform as well as NPN transistors.
– Holes are less mobile than electrons, so PNP transistors tend to switch more
slowly than NPN transistors.
– Most processes optimize the NPN transistor at the expense of the PNP transistor.
95
Bipolar Transistors Layout
96
BJT Small Signal Modeling
IC I
g   C
m
 V BE Vt
Vc kT
a ie Vt 
Vb rb rc q
 V BE 
re rb  
I B gm
Ve
 V BE 
re  
I E gm
97
Bipolar Junction vs. MOS Transistors
MOSFET BJT
Almost infinite DC current gain Finite  = ICE / IBE
Exponential, then quadratic IDS vs. VGS Exponential ICE vs. VBE
Lower gm, depends on IDS High gm=ICE / Vt
Good switch Poor switch, saturation increases base,

substrate currents
High flicker noise Low flicker noise
Poor matching Good matching
Higher parasitic cap Lower parasitics (forward active)
98
MOSFET parasitic bipolar transistors
p-well p-well
p-substrate
99
Manufacturing Issues
– a simple circuit example
100
Technology to design relation
Digital Speed in digital is given by:
Rpar • current driving capabilities of the
Vout
= transistors
Vin Cpar t+t • capacitance (and resistance) of
parasitics and next stage
• these define the delay between
Vdd input and output of a stage
Vin
Vout • all delays can be calculated and
Vss build up the delay of a digital circuit
t+t t
Lehrstuhl für Schaltungsentwurf, Fakultät für Elektrotechnik und Informationstechnik 101

Parasitic effects – circuit impact
vin, before
vin,small parasitic
Vdd
Rpar V vin,large parasitic
in Vout = = vout,small parasitic
Vin,before
Cpar vout,large parasitic
Dt + dt
Vss
t
• The difference (Vout - Vin) increases with decreasing switching time
• For achieving fast or low power circuits any kind of undesired loading
of parasitic capacitances through parasitic resistors must be avoided
• Parasitic reactance must remain comparable to device reactance to
keep performance when scaling
• Increasing speed reduces the manufacturing tolerance
102
Device-to-circuit relation for digital circuits I
• In a digital design the delays will sum up between each clocked register:
T = S (ti) tn
t1 t2
t3
Register
Register
CLK
tn-1 CLK
 This is a simple relationship describing all technology dependent factors in a
digital design
 Individual delay of library elements determine the overall timing of a design
 Even the technology information of large blocks can be described by one
parameter and one timing relation
 Therefore even large blocks can be put together automatically
Lehrstuhl für Schaltungsentwurf, Fakultät für Elektrotechnik und Informationstechnik 103
Device-to-circuit relation for digital circuits II
• In a digital design the delays will sum up between each clocked register:
t1+t1 t2+… tn+…

t3+…
Register
Register
tn-1+…
CLK CLK
• Global process variability: T  T = S (ti + ti)
• Statistical process variability: T  T = S ti +  (ti)²
 Even with statistical process effects this is a simple sum of the timing and
therefore a simple relationship
 individual delay of library elements and their margins determine the overall
margins of a design
104
Design-to-Technology Relation (SPICE model)
L, … Slow fmax Simulation
model result
VTH Ioff
Process spread Parameter spread

Simulation
Fast result
model
• Parametric performance is closely tied to technology

• As a direct consequence the stand-alone design or isolated technology
optimization is complicated
 Design and process are tied by simulation models
 The SPICE model translates technology into circuit parameter
 The RTL to physical approach for digital designs translates all technology spread into
timing spread in the library for digital circuits
105
Parametric Design –
Cross Check with real Silicon for new tech.
fmax Fast simulation fmax max.
result limit?
Ioff Experimental Ioff
Parameter spread
Min.
Parameter spread
Slow
limit?
simulation result
• Correlation between Spec and Models is overruled by silicon results

• However there is still a statistical problem …
 characterization feedback is necessary to prove module functionality over
parametric range – which also means it is necessary to have a good
representative of production spread in the char material
 But characterization results rely on the availability of silicon and the
randomness of semiconductor manufacturing …
106
Digital Design & Manufacturable Spec.
fmax Max.
limit!
Experimental Ioff
Parameter spread
Min. Spec
limit!
• Customers want to buy a chip with guaranteed electrical parameters –

so you have to set the specification of a circuit according to your
experimental design limits
• How to tackle the statistical, economical problem …
 After gaining some experience in a digital design you can trust your
simulation and have a fast turnaround time for future designs
107
Parametric Design – closing the loop
fmax Max. experimental L New slow
result
model
Experimental Ioff Vth
Process spread
Min.
Parameter spread
 New
experimental result
fast model
• Since parametric performance is closely tied to technology
 the feedback loop can be closed now:
Design and process are linked by simulation models
Reuse of the same design now needs less characterization when
module is reused on another device
A digital design approach is now failsafe!
108
Parametric Design – Dimensions of Analog
• More technology optimization parameters for analog performance
L Slow fmax Simulation
model result
Vth Ioff
Process spread Parameter spread

Simulation
Fast gm result Gain
model svthgds PSSR
offset
• One-dimensional slow-fast approach misses lots of problematic cases
• Analog design is a multi-dimensional problem
and continuous in parametric range
• It is hard to cover the parameter space with a finite set of models …
• ... and to have full trust in simulations!
109

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Analog and Mixed-Signal

Integrated Circuit Design

Prof. Dr.-Ing. Ralf Brederlow

With many thanks to my former TI

Lehrstuhl für Schaltungsentwurf, Fakultät für Elektrotechnik und Informationstechnik

• Historic trend of semiconductor industry cycles:

• Feature size reduction

health care cost,

Sensor systems need sensors PLUS a computer/microcontroller

Sensor systems need sensors PLUS a computer/microcontroller

Al metallization 30-50 mW/square Up to 4000 ppm/0C Parasitic or very special

Examples: Systematic mismatch

Wafer related distribution

 A noisy device can always be treated as an ideal device with

• basic active component of circuit design

Poly-Si Gate Bulk Silicon

Saturation region (above threshold /

Saturation region (above threshold /

• Current in weak inversion drift / diffusion limited

• Triode region, linear region for small VDS VTH

Biasing of circuit elements in the required operating point

1/rDS vout= vDS

• Mismatch in long channel devices is mainly determined by the

 A noisy MOSFET can be treated as a noise free MOSFET with a

• The noise magnitude is frequency dependent since the number of

• Traps at the Si/SiO2 boundary frequently capture and re-

• Voltage over time for a small size device

Drain current noise [A/Hz]

10 -3 n-MOS 200µm / 0.5µm experimental data

free hydrogen moves to the

CMOS-inverter depletion or inversion region,

4: analog operation active mode

active power-down active power-down

Channel hot-carrier possible negligible yes no yes

Bias temperature negligible possible yes no in part *

Oxide stress negligible possible yes possible no

Vdd - Vin = | VGS |

• On-resistance Rout at different Vin depends on VGS

Small signal models Small signal models

• Same considerations as for resistors

Copper Conductor with

Metal 1 Pre Metal Dielectric

Type Capacitance fF/mm2 Voltage coefficient Notes

• Capacitive and resistive coupling between different signals occurs

•  t ~ Ctotal / IDS ~ Ctotal / Cox

• All capacitance of the next gate needs to be recharged

Lehrstuhl für Schaltungsentwurf, Fakultät für Elektrotechnik und Informationstechnik

• NPN transistors have four regions of operation:

• When an NPN operates in cutoff,

• The PNP transistor behaves much like an NPN transistor.

Lower gm, depends on IDS High gm=ICE / Vt

Good switch Poor switch, saturation increases base,

Poor matching Good matching

Higher parasitic cap Lower parasitics (forward active)

Lehrstuhl für Schaltungsentwurf, Fakultät für Elektrotechnik und Informationstechnik 101

t1+t1 t2+… tn+…

• Parametric performance is closely tied to technology

• Correlation between Spec and Models is overruled by silicon results

• Customers want to buy a chip with guaranteed electrical parameters –

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